LDMOS device and preparation method thereof

Abstract

The invention relates to an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a preparation method thereof, and the device comprises a P-type substrate which comprises a P-type isolation layer extending along a first direction parallel to the first surface of the P-type substrate, and first regions and second regions which are located on the top surface of the P-type isolation layer and are alternately arranged along the first direction; the second region comprises an N-type drift region and an N-type buried layer which are sequentially stacked along a second direction deviating from the first surface; the N-type drift region comprises N-type wells arranged at intervals in the first direction and first P-type body regions located between the adjacent N-type wells; the size of the first P-type body region in the first direction is smaller than the distance between the N-type wells; the first region comprises a second P-type body region extending into the P-type substrate through the first surface, and a P-type well surrounding the contact surface of the second P-type body region and the P-type substrate. By changing the structure of the device and the injection condition of the N-type drift region, the area of the device can be saved, and the Source / Body can be isolated from the substrate.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to an LDMOS device and a method for preparing the same. Background Art

[0002] The lateral double-diffused MOSFET (LDMOS) device is a double-diffused power device. While inheriting the advantages of traditional MOSFET, it has higher voltage resistance and stronger current driving capability. It is widely used in high voltage and / or high power related fields.

[0003] In the device design process, in order to further improve the voltage resistance performance of LDMOS, the length of the device drift region is usually increased, or its doping concentration is reduced. However, as the length of the device drift region increases, the breakdown voltage of the device is mainly limited by the longitudinal voltage resistance of the body, but the existing methods of isolating the device body from the substrate often require complex processes and a large device area.

[0004] As the demand for high voltage levels, strong current driving capabilities and high integration increases, how to further reduce the size of LDMOS devices while maintaining or improving existing performance has become one of the urgent issues that researchers in this field need to solve. Summary of the invention

[0005] Based on this, it is necessary to provide an LDMOS device and a preparation method thereof to address the technical problems in the prior art, which can at least save device area while ensuring the isolation effect of the device.

[0006] In a first aspect, the present application provides an LDMOS device, comprising: a P-type isolation layer extending in a first direction parallel to a first surface of the P-type substrate in a P-type substrate, and a first region and a second region located on a top surface of the P-type isolation layer and alternately arranged along the first direction;

[0007] The second region includes an N-type drift region and an N-type buried layer stacked in sequence along a second direction away from the first surface; the N-type drift region includes N-type wells arranged at intervals along the first direction, and a first P-type body region located between adjacent N-type wells; the size of the first P-type body region along the first direction is smaller than the spacing between the N-type wells;

[0008] The first region includes a second P-type body region extending into the P-type substrate via the first surface, and a P-type well surrounding a contact surface between the second P-type body region and the P-type substrate.

[0009] In the LDMOS device in the above embodiment, by setting a higher concentration N-type buried layer in the N-type drift region, the depletion region width in the PNP (first P-type body region-N-type buried layer-P-type isolation layer) structure in the first direction is reduced, thereby ensuring the isolation of the first P-type body region from the first-type substrate, avoiding the first P-type body region from being connected to the P-type substrate via the P-type isolation layer, breaking through the potential setting of the traditional LDMOS device, and being able to meet the demand of connecting a higher voltage to the first P-type body region.

[0010] In some embodiments, the P-type substrate further includes a plurality of first isolation structures and second isolation structures extending into the P-type substrate via the first surface;

[0011] A first isolation structure, located at both sides of the first region along a first direction, and partially embedded in the first region and / or the second region;

[0012] The second isolation structures are distributed in the second region at intervals along the first direction and cover a portion of the top surface of the N-type well and the N-type drift region.

[0013] In some embodiments, the first P-type body region extends along the second direction and penetrates the N-type drift region;

[0014] The size of the second P-type body region along the first direction is smaller than the size of the first P-type body region along the first direction;

[0015] The first P-type body region and the second P-type body region are prepared at the same time in the same process step.

[0016] In some embodiments, the doping concentration of the N-type buried layer is greater than the doping concentration of the N-type drift region.

[0017] In some embodiments, a body electrode is located between adjacent first isolation structures;

[0018] A drain electrode is located between the first isolation structure and the second isolation structure;

[0019] A source electrode is located in the first P-type body region, and a top surface is located within the first surface;

[0020] The gates are distributed along the first direction at intervals on the top surface of the P-type substrate in the second region; any gate covers a portion of the top surface of the second isolation structure and extends to the top surface of the source.

[0021] In a second aspect, the present application further provides a method for preparing an LDMOS device, comprising: providing a P-type substrate, wherein the P-type substrate comprises a P-type isolation layer extending along a first direction parallel to a first surface, and a first region and a second region located on a top surface of the P-type isolation layer and alternately arranged along the first direction;

[0022] An N-type drift region, an N-type buried layer, an N-type well, and a first P-type body region located between adjacent N-type wells are formed in the second region; the size of the first P-type body region along the first direction is smaller than the spacing between the N-type wells;

[0023] During and before forming the first P-type body region in the second region, a second P-type body region extending into the P-type substrate through the first surface and a P-type well surrounding the contact surface between the second P-type body region and the P-type substrate are formed in the first region.

[0024] In some embodiments, an N-type drift region, an N-type buried layer, an N-type well, and a first P-type body region located between adjacent N-type wells are formed in the second region and are sequentially stacked along a second direction away from the first surface, including:

[0025] forming a patterned photoresist layer on the top surface of the P-type substrate to expose the top surface of the P-type substrate in the second region;

[0026] Based on the photoresist layer, an N-type buried layer and an N-type drift region are formed in the P-type substrate and are arranged in sequence along a direction away from the P-type substrate;

[0027] A first isolation structure is formed in the P-type substrate, extending from the first surface into the P-type substrate, located at both sides of the first region along the first direction, and partially embedded in the first region and / or the second region, and a second isolation structure is distributed in the second region at intervals along the first direction;

[0028] After forming an N-type well between the first isolation structure and the second isolation structure, a first P-type body region is formed between adjacent N-type wells; the second isolation structure covers the N-type well and a portion of the top surface of the N-type drift region.

[0029] In some embodiments, before and during the process of forming the first P-type body region in the second region, forming a second P-type body region and a P-type well in the first region includes:

[0030] After forming the N-type well, forming a P-type well in the P-type substrate of the first region;

[0031] In the same process step of forming the first P-type body region, a second P-type body region is simultaneously prepared in the P-type well.

[0032] In some embodiments, a gate is formed on the top surface of the P-type substrate in the second region and is spaced apart along the first direction; wherein the gate covers a portion of the top surface of the second isolation structure and extends to the top surface of the first P-type body region;

[0033] Based on the gate, a first P-type body region is formed along the second direction penetrating the N-type drift region; the size of the first P-type body region along the first direction is smaller than the spacing between the N-type wells.

[0034] In some embodiments, the second P-type body region has the same size as the first P-type body region along the second direction.

[0035] In some embodiments, a size of the second P-type body region along the first direction is smaller than a size of the first P-type body region along the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 A schematic cross-sectional view of an LDMOS device provided in the prior art;

[0038] Figure 2 A cross-sectional schematic diagram of another LDMOS device provided in the prior art;

[0039] Figure 3 A schematic diagram of a process for preparing an LDMOS device provided in an embodiment;

[0040] Figure 4 It is a schematic cross-sectional view of a structure obtained after a P-type isolation layer is formed in step S102 in a method for preparing an LDMOS device provided in an embodiment;

[0041] Figure 5 It is a schematic cross-sectional view of a structure obtained after a patterned photoresist layer is formed in step S202 in a method for preparing an LDMOS device provided in an embodiment;

[0042] Figure 6 It is a schematic cross-sectional view of a structure obtained after forming an N-type buried layer in step S204 in the method for preparing an LDMOS device provided in an embodiment;

[0043] Figure 7 for Figure 6 A schematic cross-sectional view of the resulting structure after forming the N-type drift region;

[0044] Figure 8 for Figure 7 A schematic cross-sectional view of the resulting structure after removal of the patterned photoresist layer;

[0045] Fig. 9 It is a schematic cross-sectional view of a structure obtained after forming a second isolation structure in step S206 in a method for preparing an LDMOS device provided in an embodiment;

[0046] Fig.10It is a schematic cross-sectional view of a structure obtained after a P-type well is formed in step S304 in a method for preparing an LDMOS device provided in an embodiment;

[0047] Fig.11 It is a schematic cross-sectional view of a structure obtained after a gate is formed in step S306 in a method for preparing an LDMOS device provided in an embodiment;

[0048] Fig.12 It is a schematic cross-sectional view of a structure obtained after forming the second P-type body region in step S306 in the method for preparing an LDMOS device provided in an embodiment;

[0049] Fig.13 for Fig.12 Schematic diagram of the cross-section of the resulting structure after forming the source, drain, and body electrodes.

[0050] Description of reference numerals:

[0051] 10. P-type substrate; 11. P-type isolation layer; 12. Photoresist layer; 21. N-type buried layer; 22. N-type drift region; 23. N-type well; 24. first P-type body region; 31. first isolation structure; 32. second isolation structure; 41. P-type well; 42. second P-type body region; 51. gate; 52. drain; 53. source; 54. body electrode. DETAILED DESCRIPTION

[0052] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0054] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0055] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0056] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0057] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the present application, so that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present application.

[0058] At present, common LDMOS isolation structures such as Figure 1 and Figure 2 As shown, Figure 1 The LDMOS device shown requires the growth of a P-type epitaxial layer (PEPI), a high-concentration N-type buried layer (BNL), and a deep N-well (HNW) to ensure isolation of the Source / Body region from the substrate; Figure 2 The LDMOS device shown directly uses a deep N-well (HNW) to isolate the source / body region from the substrate. Forming the above LDMOS device often requires a complex process and a large device area.

[0059] Based on this, see Figure 3 The present application provides a method for preparing an LDMOS device, comprising: steps S102 to S106.

[0060] In an embodiment of the present application, the P-type substrate 10 may include a first surface located on the front side, and a back side opposite to the front side, i.e., a second surface. Ignoring the flatness of the first surface and the second surface, a first direction parallel to the first surface is defined, and the direction toward the substrate includes a second direction perpendicular to the first surface of the substrate. For example, the direction parallel to the top surface of the substrate is the first direction, and the direction toward the substrate is the second direction. The first direction and the second direction are perpendicular to each other. In an embodiment of the present application, the first direction is defined as the Y-axis direction, and the second direction is defined as the X-axis direction. At the same time, the first area is defined as area A, and the second area is defined as area B.

[0061] Step S102: providing a P-type substrate 10, wherein the P-type substrate includes a P-type isolation layer extending in a first direction (OY direction) parallel to the first surface, and a first region A and a second region B located on a top surface of the P-type isolation layer and alternately arranged in the first direction.

[0062] For example, the material of the P-type substrate 10 includes but is not limited to semiconductor materials, insulating materials, conductor materials or any combination thereof, and can be a single-layer structure or a multi-layer structure. For example, the substrate may include a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate may also include Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator substrates. Therefore, the type of substrate should not limit the scope of protection of the present disclosure. The substrate may include a word line structure and a capacitor contact structure, etc., which are not closely related to the invention of this scheme, so they are omitted.

[0063] Step S104: forming an N-type drift region, an N-type buried layer, an N-type well, and a first P-type body region located between adjacent N-type wells in the second region B; the size of the first P-type body region along the first direction (OY direction) is smaller than the spacing between the N-type wells.

[0064] The embodiments of the present disclosure do not specifically limit the types of P-type impurity ions. As an example, P-type impurity ions may include, but are not limited to, any one or more of boron (Boron, B) ions, gallium (Magnesium, Mg) ions, or indium (Indium, In) ions, etc. Similarly, the embodiments of the present disclosure do not specifically limit the types of N-type impurity ions. As an example, N-type impurity ions may include, but are not limited to, one or more of phosphorus (Phosphorus, P) ions, arsenic (As) ions, or antimony (Sb) ions.

[0065] Step S106: During and before forming the first P-type body region in the second region A, a second P-type body region extending into the P-type substrate through the first surface and a P-type well surrounding the contact surface between the second P-type body region and the P-type substrate are formed in the first region.

[0066] The above method only introduces an embodiment in which the substrate includes a P-type substrate. Correspondingly, in an embodiment in which the substrate includes an N-type substrate, the above method can be referred to by simply exchanging "P" and "N" in each step of the above method.

[0067] The LDMOS device obtained after steps S102-S106 can be referred to Fig.13 In order to facilitate understanding of this application, Fig.13This is an example of an LDMOS device manufactured by the manufacturing method of the present application. Of course, there may be other suitable examples of LDMOS devices manufactured by the manufacturing method provided by the present application, and the present application does not limit them here.

[0068] It should be understood that although Figure 3 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 3 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0069] The following is a detailed description of the LDMOS device manufacturing method provided by the present application in conjunction with specific embodiments:

[0070] See also Figure 4 In some embodiments, step S102 further includes: forming a deeper P-type isolation layer 11 by performing blanket ion implantation in the P-type substrate 10 .

[0071] Specifically, a sacrificial oxide layer may be formed on the top surface of the P-type substrate 10 to prevent ion implantation from damaging the surface of the P-type substrate 10 and preventing the tunnel effect caused by ion implantation. Based on the sacrificial oxide layer, ion implantation of the P-type isolation layer 11 is performed.

[0072] See also Figure 5-Figure 8 In some embodiments, step S104 further includes:

[0073] Step S202 : forming a patterned photoresist layer 12 on the top surface of the P-type substrate 10 to expose the top surface of the P-type substrate in the second region B.

[0074] See also Figure 5 For example, a photoresist is coated on a P-type substrate 10 to form a photoresist layer 12 , and after steps such as exposure and development, the photoresist layer 12 is formed.

[0075] Step S204: Based on the photoresist layer 12 , an ion implantation process is performed on the P-type substrate 10 to form an N-type buried layer 21 and an N-type drift region 22 arranged in sequence along a direction away from the P-type substrate (XO direction, opposite to the second direction OX direction) in the P-type substrate 10 .

[0076] See also Figure 6-Figure 8 For example, based on the patterned photoresist layer 12, that is, the implantation window, and then based on the same mask, self-aligned ion implantation is performed in sequence using different doses to form Figure 6 The N-type buried 21 layer shown, and Figure 7 As shown in the N-type drift region 22 , it is necessary to ensure that the doping concentration of the N-type buried layer 21 is greater than the doping concentration of the N-type drift region 22 .

[0077] After forming the above structure, Figure 8 The photoresist layer 12 is shown removed.

[0078] See also Fig. 9 , step S206: forming a first isolation structure 31 in the P-type substrate 10, extending through the first surface into the P-type substrate 10, located on both sides of the first region A along the first direction (OY direction), and partially embedded in the first region A and / or the second region B, and a second isolation structure 32 distributed in the second region B at intervals along the first direction (OY direction).

[0079] For example, by combining oxidation process, deposition process, photolithography process and etching process, a P-type substrate 10 is formed as follows: Fig. 9 The shallow trench isolation structure (Shallow Trench Isolation, STI) shown is the first isolation structure 31. For example, an oxide layer is first formed by thermal growth to relieve the stress between the protective layer and the P-type substrate 10, a protective layer is formed on the top surface of the oxide layer by a deposition process, an STI region is photolithographically formed, and a shallow trench is formed in the STI region, and the first isolation structure 31 is formed after the shallow trench is filled. It should be noted that the first isolation structure 31 can be a single-layer structure or a multi-layer structure. For example, in addition to the filled insulating material, it can also include an oxide layer for rounding the corners of the trench, and no specific limitation is made here.

[0080] Subsequently, a local oxidation of silicon (LOCOS) process is performed at a preset position in the second region B to form LOCOS structures distributed at intervals along the first direction (OY direction), ie, the second isolation structure 32 .

[0081] In the above structure, the STI structure has good isolation performance and high integration, and is suitable for use in areas with high requirements for isolation performance and high-density integration. Therefore, the first isolation structure 31 using the STI structure can ensure effective isolation between the first area A and the second area B, as well as other devices; the process of the LOCOS structure is relatively simple, and it has certain advantages in some areas where the requirements for isolation accuracy are not particularly high but are more sensitive to process costs. Therefore, the second isolation structure 32 of the LOCOS structure can provide sufficient isolation in the second area B. At the same time, by optimizing the internal electric field distribution of the device to make it more uniform and avoid electric field concentration, the voltage resistance of the device is effectively improved. The electrical property curve (IDVD) of the LDMOS device based on this structure performs better, and the reliability of the device is further improved. It should be noted that the LDMOS device provided in this application is left-right symmetrical about the center line. In order to simplify the diagram, the figure mark is only displayed on one side.

[0082] See also Figure 10-12 , step S208: after forming the N-type well 23 between the first isolation structure 31 and the second isolation structure 32 , a first P-type body region 24 is formed between adjacent N-type wells 23 ; the second isolation structure 32 covers the N-type well 23 and a portion of the top surface of the N-type drift region 22 .

[0083] In some embodiments, step S208 further includes:

[0084] Step S302 : forming N-type wells 23 arranged at intervals along a first direction (OY direction) between the first isolation structure 31 and the second isolation structure 32 .

[0085] Step S304: After forming the N-type well, forming a P-type well in the P-type substrate of the first region.

[0086] See also Fig.10 For example, the implantation process of the N-type well 23 and the P-type well 41 is similar to that of the N-type buried layer and the N-type drift region, and will not be described in detail here.

[0087] In the above structure, the N-type well 23 and the N-type drift region 22 together constitute the drift region in the LDMOS device. Since the doping concentrations of the N-type well 23 and the N-type drift region 22 are different, a concentration lateral gradient is formed in the OY direction, which equivalently increases the overall doping concentration of the drift region of the LDMOS device, optimizes the electric field distribution, and reduces the specific on-resistance of the device.

[0088] Step S306 : forming gates 51 spaced apart along the first direction (OY direction) on the top surface of the P-type substrate 10 in the second region B; wherein the gates 51 cover a portion of the top surface of the second isolation structure 32 and extend to the top surface of the first P-type body region 24 .

[0089] For example, after performing other conventional processes such as ACT / PL1, Fig.11 As shown, the method for preparing the gate 51 is a technical solution well known to those skilled in the art and will not be described in detail here.

[0090] Step S308 : Based on the gate 51 , a first P-type body region 24 is formed along the second direction (OX direction) penetrating the N-type drift region 22 , and in the same process step of forming the first P-type body region 24 , a second P-type body region 42 is simultaneously prepared in the P-type well 41 .

[0091] See also Fig.12 Specifically, the size of the first P-type body region 24 along the first direction is smaller than the spacing between the N-type wells 23;

[0092] The second P-type body region 42 has the same size as the first P-type body region 24 along the second direction (OX direction);

[0093] The size of the second P-type body region 42 along the first direction (OY direction) is smaller than the size of the first P-type body region 24 along the first direction (OY direction).

[0094] In the above structure, when the first P-type body region 24 is formed by implantation, the ion implantation energy and dose need to be adjusted so that the overlapping area of ​​the N-type drift region 22 and the first P-type body region 24 is P-type, but the N-type buried layer 21 remains unchanged. Due to the presence of the N-type buried layer 21, the first P-type body region is isolated from the P-type substrate 10, so that the body voltage does not need to always maintain zero potential with the substrate, but can be adjusted according to the actual application scenario, thereby expanding the application range of the LDMOS device based on this structure.

[0095] See also Fig.13 In some embodiments, after step S308, the process further includes: performing heavy ion doping on the source, drain, and body electrodes, and completing post-metal wiring and other processes. The final cross-sectional view of the LDMOS device is as follows: Fig.13 shown.

[0096] Specifically, the body electrode 54 is located between adjacent first isolation structures 31;

[0097] The drain 52 is located between the first isolation structure 31 and the second isolation structure 32;

[0098] The source 53 is located in the first P-type body region 24 , and has a top surface located within the first surface.

[0099] See also Fig.13, the present application also provides an LDMOS device, comprising: a P-type substrate 10 including a P-type isolation layer 11 extending in a first direction parallel to a first surface of the P-type substrate 10, and a first region A and a second region B located on a top surface of the P-type isolation layer 11 and alternately arranged along the first direction;

[0100] The second region B includes an N-type drift region 22 and an N-type buried layer 21 stacked in sequence along a second direction away from the first surface; the N-type drift region 22 includes N-type wells 23 arranged at intervals along the first direction, and first P-type body regions 24 located between adjacent N-type wells 23; the size of the first P-type body region 24 along the first direction is smaller than the spacing between the N-type wells 23;

[0101] The first region A includes a second P-type body region 42 extending into the P-type substrate 10 via the first surface, and a P-type well 41 surrounding the contact surface between the second P-type body region 42 and the P-type substrate 10 .

[0102] The LDMOS device and the manufacturing method thereof provided by the present application have the following unexpected technical effects:

[0103] Compared with the common LDMOS vertical isolation structure, this new LDMOS device forms a high-concentration P-type isolation layer and an N-type buried layer by changing the ion implantation conditions, ensuring the isolation of the Source / Body region from the substrate. This structure not only eliminates the process steps of forming BNL / HNW / EPI, but also saves device area, while allowing the source to withstand a larger voltage and more evenly distribute the voltage inside the device, thereby reducing the voltage stress in other areas (such as between the drain and the source), with more flexible circuit design and application range, and prolonging the device life and improving system reliability.

[0104] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0105] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. An LDMOS device, characterized in that: include: A P-type substrate, wherein the P-type substrate includes a P-type isolation layer extending along a first direction parallel to a first surface of the P-type substrate, and a first region and a second region located on a top surface of the P-type isolation layer and alternately arranged along the first direction; The second region includes an N-type drift region and an N-type buried layer stacked in sequence along a second direction away from the first surface; the N-type drift region includes N-type wells arranged at intervals along the first direction, and a first P-type body region located between adjacent N-type wells; a size of the first P-type body region along the first direction is smaller than a spacing between the N-type wells; The first region includes a second P-type body region extending into the P-type substrate via the first surface, and a P-type well surrounding a contact surface between the second P-type body region and the P-type substrate.

2. The LDMOS device according to claim 1, characterized in that: The P-type substrate also includes a plurality of first isolation structures and a second isolation structure extending into the P-type substrate via the first surface; The first isolation structure is located at both sides of the first region along the first direction and is partially embedded in the first region and / or the second region; The second isolation structures are distributed in the second region along the first direction at intervals and cover a portion of the top surface of the N-type well and the N-type drift region.

3. The LDMOS device according to claim 1, characterized in that: The first P-type body region extends along the second direction and penetrates the N-type drift region; The size of the second P-type body region along the first direction is smaller than the size of the first P-type body region along the first direction; The first P-type body region and the second P-type body region are prepared at the same time in the same process step.

4. The LDMOS device according to any one of claims 1 to 3, characterized in that: The doping concentration of the N-type buried layer is greater than the doping concentration of the N-type drift region.

5. The LDMOS device according to any one of claims 1 to 3, characterized in that: Also includes: a body electrode, located between adjacent first isolation structures; a drain electrode, located between the first isolation structure and the second isolation structure; A source electrode, located in the first P-type body region, with a top surface located within the first surface; Gates, spaced apart and distributed along the first direction on the top surface of the P-type substrate in the second region; Any of the gates covers a portion of the top surface of the second isolation structure and extends to the top surface of the source.

6. A method for preparing an LDMOS device, characterized in that: include: Providing a P-type substrate, wherein the P-type substrate includes a P-type isolation layer extending along a first direction parallel to a first surface, and a first region and a second region located on a top surface of the P-type isolation layer and alternately arranged along the first direction; An N-type drift region, an N-type buried layer, an N-type well, and a first P-type body region located between adjacent N-type wells are formed in the second region; the size of the first P-type body region along the first direction is smaller than the spacing between the N-type wells; During and before forming the first P-type body region in the second region, a second P-type body region extending into the P-type substrate through the first surface and a P-type well surrounding the contact surface between the second P-type body region and the P-type substrate are formed in the first region.

7. The preparation method according to claim 6, characterized in that: The N-type drift region, the N-type buried layer, the N-type well, and the first P-type body region located between adjacent N-type wells are formed in the second region and are sequentially stacked along a second direction away from the first surface, including: forming a patterned photoresist layer on the top surface of the P-type substrate to expose the top surface of the P-type substrate in the second region; Based on the photoresist layer, forming the N-type buried layer and the N-type drift region arranged in sequence along a direction away from the P-type substrate in the P-type substrate; A first isolation structure is formed in the P-type substrate, extending from the first surface into the P-type substrate, located at both sides of the first region along the first direction, and partially embedded in the first region and / or the second region, and a second isolation structure is distributed in the second region at intervals along the first direction; After forming the N-type well between the first isolation structure and the second isolation structure, the first P-type body region is formed between adjacent N-type wells; the second isolation structure covers the N-type well and a portion of the top surface of the N-type drift region.

8. The preparation method according to claim 7, characterized in that: During and before forming the first P-type body region in the second region, forming the second P-type body region and the P-type well in the first region, comprising: After forming the N-type well, forming the P-type well in the P-type substrate in the first region; In the same process step of forming the first P-type body region, the second P-type body region is simultaneously prepared in the P-type well.

9. The preparation method according to any one of claims 7-8, characterized in that: Also includes: Forming gates spaced apart along the first direction on the top surface of the P-type substrate in the second region; wherein the gates cover a portion of the top surface of the second isolation structure and extend to the top surface of the first P-type body region; Based on the gate, the first P-type body region penetrating the N-type drift region along the second direction is formed; the size of the first P-type body region along the first direction is smaller than the spacing between the N-type wells.

10. The preparation method according to any one of claims 7-8, characterized in that: Include at least one of the following features: The second P-type body region has the same size as the first P-type body region along the second direction; A size of the second P-type body region along the first direction is smaller than a size of the first P-type body region along the first direction.

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