VDMOS device integrated with Schottky diode and manufacturing method thereof
By integrating Schottky diodes in the conventional process of VDMOS devices, using Schottky contacts to reduce switching losses and improve conversion efficiency, the problems of high loss and low efficiency in the high-frequency switching process of existing VDMOS devices are solved.
Patent Information
- Application Number
- CN202411978995.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-05-06
AI Technical Summary
Existing VDMOS devices have high switching losses during high-frequency switching and are not highly converted.
In the conventional process of VDMOS devices, the Schottky diode is integrated, and a second contact region is formed in the N-type epitaxial layer while forming a first contact region between the P-type base region and the source region, forming a Schottky contact, thereby achieving integration of the Schottky diode.
Effectively reduces switching losses during high-frequency switching, improves conversion efficiency, and realizes the integration of Schottky diodes without adding additional process steps.
Smart Images
Figure CN119947187A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor devices, and in particular to a VDMOS device with an integrated Schottky diode and a manufacturing method thereof. Background Art
[0002] Vertical Double-diffused Metal-Oxide Semiconductor Field-Effect Transistor (VDMOS) is the most widely used type of power device in power semiconductors. As a switching device connected between the power supply and the load, it has the characteristics of easy driving, fast switching speed, integration, and simple process.
[0003] At present, in order to improve the cross-frequency characteristics of the switching device and reduce the loss of the switch, a Schottky diode can be integrated on the power MOS transistor chip. For example, Figure 1 This is a schematic diagram of a DC-DC conversion control circuit using MOS tubes as switching devices. Figure 1 As shown, the upper switch tube M1 and the lower switch tube M2 are both VDMOS devices, which are the core switch devices of the DC-DC conversion control circuit. Under the control of the control chip, DC-DC conversion can be achieved. Among them, the upper switch tube M1 and the lower switch tube M2 themselves have parasitic diodes D1 and D2 (composed of a P-type well region / drain surrounding the source), and in order to effectively reduce the loss of high-frequency switching, Figure 1 In the embodiment, a Schottky diode SBD is designed between the source S and the drain D of the lower switch tube M2. In this way, when the upper switch tube M1 and the lower switch tube M2 are both in the off state in a certain state, in order to ensure that the load is continuously supplied with current, the Schottky diode SBD (with a turn-on voltage of about 0.3V) in parallel with the lower switch tube M2 will be turned on before the body diode D2 (with a turn-on voltage of about 0.7V), effectively reducing the loss caused by the high turn-on voltage drop. In addition, the reverse recovery time of the Schottky diode is shorter, which can more effectively reduce the switching loss during high-frequency switching and further improve the conversion efficiency.
[0004] Based on this application, the present application proposes a VDMOS device with an integrated Schottky diode and a manufacturing method thereof. The integrated Schottky diode can be generated in the conventional process of the VDMOS device without the need for additional process steps. The implementation scheme is simple and easy to implement. Summary of the invention
[0005] The present application provides a field effect transistor with an integrated Schottky diode and a method for manufacturing the same.
[0006] In a first aspect, the present application provides a vertical double diffused metal oxide semiconductor field effect transistor VDMOS device with an integrated Schottky diode, comprising an N+ substrate, an N-type epitaxial layer, a gate region, a P-type body region, a drain region, a source region, a first contact region, a second contact region, a first P-type doped region, and a second P-type doped region;
[0007] The N-type epitaxial layer is located above the N+ substrate, the gate region, the P-type base region, the source region, the first contact region, the second contact region and the P-type doped region are all located on the N-type epitaxial layer, and the drain region is located below the N+ substrate;
[0008] Among them, the P-type base region and the source region are located between the gate region and the source region is located above the P-type base region, the first contact region penetrates downwardly through the source region and terminates within the P-type base region, the first P-type doped region is located directly below the first contact region, the second contact region extends downward from the upper surface of the N-type epitaxial layer into the N-type epitaxial layer, the second P-type doped region is located directly below the second contact region, and the sidewall of the second contact region forms a Schottky contact with the N-type epitaxial layer.
[0009] Optionally, the first P-type doping region and the second P-type doping region both include a first-concentration P-type doping region and a second-concentration P-type doping region connected in contact with each other from top to bottom;
[0010] The first concentration P-type doping region is located below the second concentration P-type doping region, the doping concentration of the first concentration P-type doping region is less than the doping concentration of the P-type base region, and the doping concentration of the second concentration P-type doping region is greater than the doping concentration of the P-type base region.
[0011] Optionally, the first contact region and the second contact region extend downward from the N-type epitaxial layer to the same depth, the junction depth of the first-concentration P-type doped region is greater than the junction depth of the P-type base region, and the junction depth of the second-concentration P-type doped region is less than the junction depth of the P-type base region.
[0012] Optionally, the area size of the first concentration P-type doping region is larger than the area size of the second concentration P-type doping region.
[0013] Optionally, the first P-type doping region and the second P-type doping region are formed simultaneously, and the first contact region and the second contact region are formed simultaneously.
[0014] Optionally, the gate region is a trench gate structure;
[0015] The gate region is formed in a first trench in the N-type epitaxial layer, and the gate region includes a first dielectric layer and a control gate, wherein the first dielectric layer is arranged around the control gate.
[0016] Optionally, the gate region is a shielded trench gate structure;
[0017] The gate region also includes a shielding gate, and the first dielectric layer includes a field oxide layer, a gate spacer layer and a gate oxide layer, wherein the shielding gate is located below the control gate, the spacer oxide layer is located between the control gate and the shielding gate, and the field oxide layer and the gate spacer layer wrap the shielding gate, and the gate oxide layer is located on both sides of the control gate.
[0018] Optionally, the gate region is a planar gate structure;
[0019] Wherein, the gate region is formed above the N-type epitaxial layer.
[0020] In a second aspect, the present application provides a method for manufacturing a VDMOS device with an integrated Schottky diode, comprising:
[0021] Providing an N+ substrate;
[0022] Forming an N-type epitaxial layer on the N+ substrate;
[0023] Forming a gate region, a P-type base region, and a source region in sequence on the N-type epitaxial layer, wherein the P-type base region and the source region are located between the gate region, and the source region is located above the P-type base region;
[0024] A first P-type doping region, a second P-type doping region, a first contact region, and a second contact region are formed on the N-type epitaxial layer, wherein the first contact region extends downward through the source region and terminates within the P-type base region, the first P-type doping region is formed below the first contact region, the second contact region extends downward to be formed in the N-type epitaxial layer, the second P-type doping region is formed below the second contact region, and a sidewall of the second contact region forms a Schottky contact with the N-type epitaxial layer;
[0025] A drain region is formed under the N+ substrate.
[0026] Optionally, forming a first P-type doping region, a second P-type doping region, a first contact region, and a second contact region on the N-type epitaxial layer includes:
[0027] Digging a second deep trench in the source region and digging a third deep trench in the N-type epitaxial layer, wherein the second deep trench penetrates the source region and terminates at the P-type body region;
[0028] Performing P-type ion implantation into the second deep trench to form the first P-type doped region, and simultaneously performing P-type ion implantation into the third deep trench to form the second P-type doped region;
[0029] Metal filling is performed above the first P-type doping region in the second deep trench to form the first contact region, and metal filling is performed above the second P-type doping region in the third deep trench to form the second contact region.
[0030] Optionally, performing P-type ion implantation into the second deep trench to form the first P-type doped region, and simultaneously performing P-type ion implantation into the third deep trench to form the second P-type doped region, comprises:
[0031] Simultaneously performing a first P-type ion implantation into the second deep trench and the third deep trench to form a first concentration P-type doping region respectively;
[0032] Simultaneously performing a second P-type ion implantation on the first-concentration P-type doping region in the second deep trench and the third deep trench to form a second-concentration P-type doping region;
[0033] Among them, the first P-type doping region and the second P-type doping region both include the first-concentration P-type doping region and the second-concentration P-type doping region; the doping concentration of the first-concentration P-type doping region is less than the doping concentration of the P-type base region, and the doping concentration of the second-concentration P-type doping region is greater than the doping concentration of the P-type base region; the junction depth of the first-concentration P-type doping region is greater than the junction depth of the P-type base region, and the junction depth of the second-concentration P-type doping region is less than the junction depth of the P-type base region.
[0034] After the first P-type ion implantation is performed simultaneously in the second deep trench and the third deep trench, the method further includes:
[0035] Annealing and diffusion treatment is performed to make the area size of the formed first concentration P-type doping region larger than the area size of the second concentration P-type doping region.
[0036] Optionally, the gate region is a trench gate structure;
[0037] Forming a gate region on the N-type epitaxial layer, comprising:
[0038] Digging a first deep trench in the N-type epitaxial layer;
[0039] The gate region is formed in the first deep trench, and the gate region includes a first dielectric layer and a control gate, wherein the first dielectric layer is disposed around the control gate.
[0040] Optionally, the gate region is a shielded trench gate structure; and forming the gate region in the first deep trench comprises:
[0041] forming a field oxide layer, a shielding gate and a gate spacer in the first deep trench, wherein the field oxide layer and the gate spacer wrap the shielding gate, and the shielding gate is located below the gate spacer;
[0042] forming a gate oxide layer on the sidewall of the first deep trench, wherein the thickness of the gate oxide layer is less than the thickness of the field oxide layer;
[0043] A control gate is formed in the first deep trench, the gate oxide layer is located on both sides of the control gate, and the control gate is located above the gate spacer layer.
[0044] Optionally, the gate region is a planar gate structure;
[0045] Forming a gate region on the N-type epitaxial layer, comprising:
[0046] Growing a first dielectric layer on the upper surface of the N-type epitaxial layer;
[0047] Polysilicon is deposited on the first dielectric layer, and the polysilicon is etched to form a gate region.
[0048] The present application provides a VDMOS device with an integrated Schottky diode and a manufacturing method thereof. When manufacturing the VDMOS device, a Schottky diode is simultaneously generated. Specifically, after forming a gate region, a P-type base region and a source region, a first contact region can be formed in the P-type base region and the source region, and a second contact region can be formed in the N-type epitaxial layer at the same time. Moreover, a first P-type doped region below the first contact region and a second P-type doped region below the second contact region are also formed simultaneously. The second contact region forms a Schottky contact with the N-type epitaxial layer at the side wall. That is, the first P-type doped region and the second P-type doped region are formed using the same mask, and the first contact region and the second contact region are formed using the same mask. Therefore, the manufacturing method forms a VDMOS device with an integrated Schottky diode without adding additional process steps. BRIEF DESCRIPTION OF THE DRAWINGS
[0049] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.
[0050] Figure 1 It is a schematic diagram of a DC-DC conversion control circuit using MOS tubes as switching devices;
[0051] Figure 2 This is a schematic diagram of the structure of a VDMOS device with an integrated Schottky diode provided in an embodiment of the present application;
[0052] Figure 3is another structural schematic diagram of a VDMOS device with an integrated Schottky diode provided in an embodiment of the present application;
[0053] Figure 4 This is another structural schematic diagram of a VDMOS device with an integrated Schottky diode provided in an embodiment of the present application;
[0054] Figure 5 It is a schematic flow chart of a method for manufacturing a VDMOS device integrated with a Schottky diode provided in an embodiment of the present application;
[0055] Figure 6a to Figure 6m It is a schematic diagram of the process flow of a VDMOS device with an integrated Schottky diode provided in an embodiment of the present application.
[0056] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION
[0057] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0058] The terms "including" and "having" and any variations thereof appearing in the specification, claims and drawings of this application are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or modules is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products or devices.
[0059] In addition, the terms "first", "second" and "third" are used to distinguish different objects, rather than to describe a specific order. The electrical connection of the present application includes direct electrical connection and indirect electrical connection. Indirect electrical connection means that other electronic components, pins, etc. may exist between the two electrically connected components. The XX end mentioned in the present application may be an actual terminal, or it may not be an actual terminal, for example, it is only one end of a component or one end of a wire. The "and / or" mentioned in the present application includes three situations. For example, A and / or B includes three situations: A, B, A and B.
[0060] Vertical Double-diffused Metal Oxide Semiconductor (VDMOS) devices are a type of semiconductor power component, and their working principle is similar to that of general Metal Oxide Semiconductor Field Effect Transistor (MOSFET, MOS tube), that is, the current between the drain and the source is controlled by changing the gate voltage. VDMOS devices have a vertical structure, which means that the connection between its drain, source and gate is vertical, not horizontal, and this structure helps to achieve higher current density and lower on-resistance.
[0061] At present, in order to reduce the power loss of semiconductor power components and increase the switching speed of semiconductor power components, integrating Schottky diodes into semiconductor power components has gradually been widely used. Figure 1 The example shows that in a DC-DC conversion control circuit using a MOS tube as a switching device, a Schottky diode SBD designed between the source S and the drain D of the lower switch tube M2 can be turned on before the body diode D2 when the upper switch tube M1 and the lower switch tube M2 are both in the off state, effectively reducing the loss caused by the high turn-on voltage drop, and the reverse recovery time of the Schottky diode is shorter, further improving the conversion efficiency. That is, the MOS tube integrated with the Schottky diode can improve its application in the bridge circuit (H-bridge) and synchronous rectification.
[0062] The embodiments of the present application provide a VDMOS device with an integrated Schottky diode and a method for manufacturing the same. The integrated Schottky diode can be generated in a conventional process of the VDMOS device without adding additional process steps.
[0063] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.
[0064] For example, Figure 2 1 is a schematic diagram of a structure of a VDMOS device with an integrated Schottky diode provided in an embodiment of the present application. The VDMOS device can be, for example, an N-type MOS, a P-type MOS, etc., and the N-type MOS is used as an example for illustration in the figure. In the application of bridge circuits and synchronous rectification, the VDMOS device can be the lower switch tube of a half-bridge circuit, and the body diode and Schottky diode it has can be used for freewheeling. Figure 2As shown, in this embodiment, the VDMOS device with integrated Schottky diode may include an N+ substrate 10, an N-type epitaxial layer 20, a gate region 30, a P-type body region 40, a source region 50, a drain region 60, a first contact region 71, a second contact region 72, a first P-type doping region 81, and a second P-type doping region 82. The N-type epitaxial layer 20 is located above the N+ substrate 10, the gate region 30, the P-type body region 40, the source region 50, the first contact region 71, the second contact region 72, the first P-type doping region 81, and the second P-type doping region 82 are all located on the N-type epitaxial layer 20, and the drain region 60 is located below the N+ substrate 10.
[0065] Continue to refer to Figure 2 As shown, the P-type base region 40 and the source region 50 are located between the gate region 30 and the source region 50 is located above the P-type base region 40, the first contact region 71 penetrates downward through the source region 50 and terminates within the P-type base region 40, the first P-type doping region 81 is located directly below the first contact region 71, the second contact region 72 extends downward from the upper surface of the N-type epitaxial layer 20 into the N-type epitaxial layer 20, the second P-type doping region 82 is located directly below the second contact region 72, and the sidewall of the second contact region 72 forms a Schottky contact with the N-type epitaxial layer 20.
[0066] In the embodiment of the present application, the VDMOS device is N-type, and the doping concentration of the N+ substrate 10 is greater than the doping concentration of the N-type epitaxial layer 20. The formation region of the VDMOS device may include a MOS formation region 100 and a Schottky diode formation region 200. Among them, the gate region 30, the P-type base region 40, the source region 50 and the first contact region 71 are formed in the MOS formation region 100, the P-type base region 40 is formed in the surface region of the N-type epitaxial layer 20 and has a certain thickness, and the source region 50 is formed in the surface region of the P-type base region 40, which is an N-type heavily doped region, that is, the doping concentration of the source region 50 is greater than the doping concentration of the N-type epitaxial layer 20. The second contact region 72 is formed in the Schottky diode forming region 200. Specifically, the second contact region 72 extends downward from the surface of the N-type epitaxial layer 20 and terminates in the N-type epitaxial layer 20, that is, the P-type body region 40 is not formed in the Schottky diode forming region 200. The second contact region 72 is located in the N-type epitaxial layer 20, and the depth of the second contact region 72 is the same as the depth of the first contact region 71. Optionally, the second contact region 72 and the first contact region 71 are filled with metal to serve as the connection portion between the source of the VDMOS device and the anode of the Schottky diode.
[0067] Optionally, in this embodiment, the P-type base region 40 is connected to the source region 50, and the source region 50 is led out through the first contact region 71, the bottom of the first contact region 71 has a first P-type doping region 81, and the bottom of the second contact region 72 has a second P-type doping region 82. Figure 2As shown, the first P-type doping region 81 and the second P-type doping region 82 both include a first concentration P-type doping region 801 and a second concentration P-type doping region 802 that are in contact with each other. The first concentration P-type doping region 801 is located below the second concentration P-type doping region 802, that is, the second concentration P-type doping region 802 is connected to the first contact region 71 or in contact with the second contact region 72, the doping concentration of the first concentration P-type doping region 801 is less than the doping concentration of the P-type base region 40, and the doping concentration of the second concentration P-type doping region 802 is greater than the doping concentration of the P-type base region 40.
[0068] Optional, see Figure 2 As shown, the first contact region 71 and the second contact region 72 extend downward from the N-type epitaxial layer 20 to the same depth. Therefore, regardless of whether it is the first P-type doping region 81 or the second P-type doping region 82, the junction depth of the first concentration P-type doping region 801 is greater than the junction depth of the P-type base region 40, and the junction depth of the second concentration P-type doping region 802 is less than the junction depth of the P-type base region 40, that is, the depth of the lowest surface of the first concentration P-type doping region 801 is greater than the depth of the P-type base region 40, and the depth of its highest surface is less than the depth of the P-type base region 40.
[0069] For example, refer to Figure 2 As shown, in the MOS formation region 100, the lowest surface of the first concentration P-type doping region 801 is located in the N-type epitaxial layer 20, and its highest surface is located in the P-type matrix region 40, that is, the lowest surface of the first concentration P-type doping region 801 is located in the P-type matrix region 40. Correspondingly, in the Schottky diode formation region 200, the side wall of the second contact region 72 is in contact with the N-type epitaxial layer 20, so that a lateral metal-semiconductor contact is formed on the side wall of the second contact region 72, thereby forming a Schottky contact, and the barrier height of the Schottky contact is less than the barrier height of the PN junction, so that the conduction voltage drop of the formed Schottky diode is less than the conduction voltage drop of the body diode. In this embodiment, the Schottky contact is formed on the side wall of the second contact region 72, the area is large, and the conduction impedance of the Schottky diode is low.
[0070] In this embodiment, the first concentration P-type doping region 801 and the second concentration P-type doping region 802 form a super junction structure in the N-type epitaxial layer, which is beneficial to reducing the on-resistance of the formed VDMOS device on the one hand, and on the other hand can improve the voltage resistance characteristics of the VDMOS device and the Schottky diode.
[0071] Optionally, in an embodiment of the present application, the first P-type doping region 81 and the second P-type doping region 82 are formed simultaneously, and the first contact region 71 and the second contact region 72 are formed simultaneously. That is, the process steps of the first P-type doping region 81 and the second P-type doping region 82 are the same, and the process steps of the first contact region 71 and the second contact region 72 are the same, so that the formation of the VDMOS device with integrated Schottky diode does not add additional process steps compared to the formation of a normal VDMOS device.
[0072] Optionally, when forming the first concentration P-type doping region 801, an annealing diffusion treatment is also performed, so that the area size of the first concentration P-type doping region 801 is larger than the area size of the second concentration P-type doping region 802, further improving the withstand voltage characteristics.
[0073] Optionally, the drain region 60 can be formed by a metal layer formed under the N+ substrate 10. In this embodiment, since the formed Schottky diode is connected in parallel with the VDMOS, the back metal layer forming the drain region 60 also forms the cathode of the Schottky diode. Therefore, the drain region 60 can be led out through a lead to serve as the drain of the VDMOS device and the cathode of the Schottky diode. The first contact region 71 and the second contact region 72 are both led out through the conductive material 51, which are connected to the source of the VDMOS device and the anode of the Schottky diode. At the same time, the gate region 30 can be connected to the gate of the VDMOS device through a lead (not shown).
[0074] In one implementation of the present application, the gate region 30 is a trench gate structure. Figure 2 As shown, the gate region 30 is formed in the first trench in the N-type epitaxial layer 20, and the gate region 30 includes a first dielectric layer 302 and a control gate 301, and the first dielectric layer 302 is arranged around the control gate 301. Optionally, the gate region 30 may also include a gate protection layer (not shown in the figure), which is located above the control gate 301, and the gate protection layer is, for example, SiO2 or other insulating materials.
[0075] In another implementation of the present application, the gate region 30 is a shielded trench gate structure. Figure 3 is another structural schematic diagram of a VDMOS device with an integrated Schottky diode provided in an embodiment of the present application. Figure 3 As shown, in Figure 2 Based on the schematic diagram shown, the gate region 30 further includes a shielding gate 303 , which is located in the first dielectric layer 302 and below the control gate 301 .
[0076] Optionally, the first dielectric layer includes a field oxide layer, a gate spacer layer and a gate oxide layer, the spacer oxide layer is located between the control gate and the shield gate, the field oxide layer is located on both sides of the shield gate 303, and the gate oxide layer is located on both sides of the control gate, that is, the field oxide layer and the gate spacer layer wrap the shield gate, and the gate spacer layer is located between the control gate and the shield gate to insulate the two, wherein the thickness of the gate oxide layer is less than the thickness of the field oxide layer, for example, the thickness of the gate oxide layer is less than half of the thickness of the field oxide layer, for example, the thickness of the gate oxide layer is 1 / 4-1 / 10 of the thickness of the field oxide layer.
[0077] In another implementation of the present application, the gate region 30 is a planar gate structure. Figure 4 is another structural schematic diagram of a VDMOS device with an integrated Schottky diode provided in an embodiment of the present application. Figure 4 As shown in FIG. 1 , the gate region 30 is formed above the N-type epitaxial layer 20 . Figure 2 or Figure 3 Similar to the schematic diagram shown, the gate region 30 includes a first dielectric layer 302 and a control gate 301 , the first dielectric layer 302 is located above the N-type epitaxial layer 20 , the control gate 301 is located above the first dielectric layer 302 , and the first dielectric layer 302 is in contact with the P-type base region 40 .
[0078] In an embodiment of the present application, a VDMOS device with an integrated Schottky diode is proposed, and a Schottky contact can be generated simultaneously when a contact region of a source is formed. Specifically, after forming a gate region, a P-type matrix region, and a source region, when a first contact region is formed in the P-type matrix region and the source region, a second contact region can be formed in an N-type epitaxial layer by the same process step, and a first P-type doped region below the first contact region and a second P-type doped region below the second contact region are also formed at the same time, and the second contact region forms a Schottky contact with the N-type epitaxial layer at the side wall, that is, the first P-type doped region and the second P-type doped region are formed using the same mask, and the first contact region and the second contact region are formed using the same mask, so that the scheme forms a VDMOS device with an integrated Schottky diode without adding additional process steps.
[0079] Optionally, the present application embodiment also provides a method for manufacturing a VDMOS device with an integrated Schottky diode, the manufacturing method is used to generate the above-mentioned N-type VDMOS device, referring to the above Figures 2 to 4 The VDMOS device shown in FIG. Figure 5 is a flow chart of a method for manufacturing a VDMOS device with an integrated Schottky diode provided in an embodiment of the present application, Figure 6a to Figure 6m Schematic diagram of the process of VDMOS device with integrated Schottky diode provided in the embodiment of the present application. Figure 5The manufacturing process is explained and Figure 6a to Figure 6m Explain the VDMOS device process.
[0080] Reference Figure 5 As shown, the manufacturing method includes:
[0081] S501 , providing an N+ substrate.
[0082] Optional, see Figure 6a As shown, firstly, a low-resistance N+ substrate 10 is provided as a base plate.
[0083] S502 , forming an N-type epitaxial layer on the upper portion of the N+ substrate.
[0084] See also Figure 6b As shown, an N-type epitaxial layer 20 with a certain thickness is grown on an N+ substrate 10 , and the doping concentration of the N-type epitaxial layer 20 is less than the doping concentration of the N+ substrate 10 .
[0085] S503, forming a gate region, a P-type base region, and a source region in sequence on the N-type epitaxial layer, wherein the P-type base region and the source region are located between the gate region, and the source region is located above the P-type base region.
[0086] Exemplarily, this embodiment generates Figure 2 The VDMOS device with a trench gate is explained as shown in FIG. A gate region 30 is sequentially formed on the N-type epitaxial layer 20 , and the specific steps are as follows:
[0087] Reference Figure 6c As shown, firstly, a first deep trench 300 is dug in a first area of the N-type epitaxial layer 20 , and the first deep trench 300 extends downward from the upper surface of the N-type epitaxial layer 20 into the N-type epitaxial layer 20 , and the bottom of the first deep trench 300 is located in the N-type epitaxial layer 20 , that is, the first deep trench 300 does not pass through the lower surface of the N-type epitaxial layer 20 .
[0088] Secondly, refer to Figure 6d to Figure 6fAs shown, a gate region 30 is formed in the first deep trench 300. The gate region 30 includes a first dielectric layer 302 and a control gate 301. In this embodiment, a first insulating layer 310 is first formed on the inner surface of the first deep trench 300 and the upper surface of the N-type epitaxial layer 20 by oxidation and / or deposition. The first insulating layer 310 is, for example, SiO2, but the first insulating layer 310 itself does not fill the first deep trench 300. Then, a first conductive material 320 is deposited on the surface of the first insulating layer 310. Subsequently, the first conductive material 320 is etched, and the first conductive material 320 located outside the first deep trench 300 is completely etched away. Part of the first conductive material 320 in the first deep trench 300 is also etched away to form a control gate 301. Then, the first insulating layer 310 is etched, and the first insulating layer 310 located outside the first deep trench 300 is completely etched away. Part of the first insulating layer 310 located inside the first deep trench 300 is etched away to form a first dielectric layer 302. Finally, an oxide layer is grown on the control gate 301 for isolation protection.
[0089] Reference Figure 6g As shown, p-type impurities are doped into the N-type epitaxial layer 20 between the gate regions 30 to form a P-type body region 40 , where the p-type impurities are trivalent elements, such as boron, etc. In this embodiment, the lower surface of the P-type body region 40 is higher than the lower surface of the gate region 30 .
[0090] See also Figure 6h In this embodiment, the upper portion of the P-type base region 40 is doped with n-type impurities, where the n-type impurities are pentavalent elements, such as phosphorus, arsenic, etc., to form a full-layer source region 50.
[0091] S504 , forming a first P-type doping region, a second P-type doping region, a first contact region 71 and a second contact region 72 on the N-type epitaxial layer.
[0092] Among them, the first contact region 71 penetrates downward through the source region 50 and terminates in the P-type base region 40, the first P-type doping region 81 is formed below the first contact region 71, the second contact region 72 extends downward to be formed in the N-type epitaxial layer 20, the second P-type doping region 82 is formed below the second contact region 72, and the side wall of the second contact region 72 forms a Schottky contact with the N-type epitaxial layer 20.
[0093] For example, refer to Figure 6i and Figure 6jAs shown, a second dielectric layer 90 is formed on the upper surfaces of the gate region 30, the source region 50 and the N-type epitaxial layer 20. The second dielectric layer 90 is an insulating layer, for example, the material is SiO2, Si3N4, etc., and then a second deep groove 701 is formed in the second dielectric layer 90 above the source region 50, and a third deep groove 702 is formed in the second dielectric layer 90 above the N-type epitaxial layer 20. That is, the second deep groove 701 can be dug in the source region 50, and the third deep groove 702 can be dug in the N-type epitaxial layer 20 at the same time, wherein the second deep groove 701 extends downward from the surface of the second dielectric layer 90, penetrates the source region 50 and terminates at the P-type base region 40, and the third deep groove 702 extends downward from the surface of the second dielectric layer 90 to the N-type epitaxial layer 20.
[0094] Optionally, in this embodiment, the height of the third deep trench 702 is the same as the height of the second deep trench 701 , so that both can be formed by the same etching without adding additional process steps.
[0095] Optionally, P-type ion implantation is performed into the second deep trench 701 to form a first P-type doping region 81, and P-type ion implantation is performed into the third deep trench 702 to form a second P-type doping region 82. Exemplarily, the first P-type doping region 81 and the second P-type doping region 82 both include a first concentration P-type doping region 801 and a second concentration P-type doping region 802. Figure 6l As shown, a first P-type ion implantation is performed simultaneously into the second deep trench 701 and the third deep trench 702 to form a first concentration P-type doping region 801, respectively. Subsequently, a second P-type ion implantation is performed simultaneously above the first concentration P-type doping region 801 in the second deep trench 701 and the third deep trench 702 to form a second concentration P-type doping region 802.
[0096] Optionally, after the first P-type ion implantation is performed simultaneously in the second deep trench 701 and the third deep trench 702, an annealing diffusion process is further included to make the area size of the formed first concentration P-type doping area 801 larger than the area size of the second concentration P-type doping area 802, for example, Figure 6l As shown, the contact area between the first concentration P-type doping region 801 and the N-type epitaxial layer 20 is increased, and the voltage resistance of the VDMOS device and the Schottky diode is improved.
[0097] For example, refer to Figure 6k As shown, the doping concentration of the first concentration P-type doping region 801 is less than the doping concentration of the P-type base region 40, and the doping concentration of the second concentration P-type doping region 802 is greater than the doping concentration of the P-type base region 40; the junction depth of the first concentration P-type doping region 801 is greater than the junction depth of the P-type base region 40, and the junction depth of the second concentration P-type doping region 802 is less than the junction depth of the P-type base region 40.
[0098] Optional, see Figure 6l As shown, metal filling is performed above the first P-type doped region 81 in the second deep trench 701 to form a first contact region 71, and metal filling is performed above the second P-type doped region 82 in the third deep trench 702 to form a second contact region 72. At this time, the sidewall of the second contact region 72 forms a Schottky contact with the N-type epitaxial layer 20.
[0099] S505 , forming a drain region below the N+ substrate.
[0100] In this embodiment, refer to Figure 6m As shown, a metal layer is deposited below the N+ substrate 10 to form a drain region 60, which also serves as a cathode of the Schottky diode.
[0101] Optional, continue to refer to Figure 6m As shown, conductive materials are deposited on the gate region 30 and then etched to form corresponding gate terminals (not shown in the figure), and conductive material 51 is deposited on the first contact region 71 and the second contact region 72 and then etched to form source terminals and the anode of the Schottky diode, wherein the conductive material is, for example, aluminum, alloy, etc.
[0102] At this point, based on the above steps S501 to S505, combined with the above Figure 6a to Figure 6m A trench gate VDMOS device with a Schottky diode is formed, which not only reduces the switching loss of the VDMOS device in the high-frequency switching process, but also improves the conversion efficiency.
[0103] Exemplarily, in another implementation of the present application, the gate region 30 is a shielded trench gate structure; forming the gate region in the first deep trench includes:
[0104] Firstly, a field oxide layer, a shielding gate and a gate spacer are formed in the first deep trench, wherein the field oxide layer and the gate spacer wrap the shielding gate, and the shielding gate is located below the gate spacer; secondly, a gate oxide layer is formed on the sidewall of the first deep trench, and the thickness of the gate oxide layer is less than that of the field oxide layer; finally, a control gate is formed in the first deep trench, the gate oxide layer is located on both sides of the control gate, and the control gate is located above the gate spacer.
[0105] For example, refer to Figure 3As shown, first, a first insulating layer is formed on the inner surface of the first deep groove and the upper surface of the N-type epitaxial layer 20 by oxidation and / or deposition, but the first insulating layer itself does not fill the first deep groove; secondly, a first conductive material is deposited on the surface of the first insulating layer, and the first conductive material fills the first deep groove. The first conductive material is, for example, N-type polysilicon; the first conductive material is etched again, and the first conductive material outside the first deep groove is completely etched away, and the first conductive material in the first deep groove is also partially etched away to form a shielding gate; finally, a second insulating layer is deposited above the shielding gate in the first deep groove to fill and overflow the first deep groove, and then the second insulating layer and the first insulating layer are etched, and the first insulating layer and the second insulating layer outside the first deep groove are completely etched away, and the first insulating layer and the second insulating layer inside the first deep groove are partially etched away to form a field oxide layer and a gate spacer, and the field oxide layer and the gate spacer wrap the shielding gate.
[0106] Furthermore, in this embodiment, a gate oxide layer is formed on the sidewall of the first deep trench above the shielding gate, and the gate oxide layer itself is relatively thin, for example, the thickness of the gate oxide layer is less than half of the thickness of the field oxide layer.
[0107] Furthermore, a second conductive material is filled in the first deep groove, the second conductive material is, for example, N-type polysilicon, and then the second conductive material is etched to form a control gate. A gate spacer layer is provided between the control gate and the shielding gate to insulate the two, and then a gate protection layer is formed on the control gate, thereby forming a gate region of a shielding trench gate structure.
[0108] Exemplarily, in another implementation of the present application, the gate region 30 is a planar gate structure; that is, referring to Figure 4 As shown, forming the gate region 30 on the N-type epitaxial layer 20 includes: growing a first dielectric layer on the upper surface of the N-type epitaxial layer 20 , depositing polysilicon on the first dielectric layer, and etching the polysilicon to form the gate region 30 .
[0109] It is understandable that for details not described in a certain embodiment of the present application, reference may be made to the records in other implementations or embodiments, and the present application will not elaborate on them.
[0110] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the application disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.
[0111] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.
Claims
1. A vertical double diffused metal oxide semiconductor field effect transistor (VDMOS) device with integrated Schottky diode, characterized in that: It includes an N+ substrate, an N-type epitaxial layer, a gate region, a P-type body region, a drain region, a source region, a first contact region, a second contact region, a first P-type doping region, and a second P-type doping region; The N-type epitaxial layer is located above the N+ substrate, the gate region, the P-type base region, the source region, the first contact region, the second contact region and the P-type doped region are all located on the N-type epitaxial layer, and the drain region is located below the N+ substrate; Among them, the P-type base region and the source region are located between the gate region and the source region is located above the P-type base region, the first contact region penetrates downwardly through the source region and terminates within the P-type base region, the first P-type doped region is located directly below the first contact region, the second contact region extends downward from the upper surface of the N-type epitaxial layer into the N-type epitaxial layer, the second P-type doped region is located directly below the second contact region, and the sidewall of the second contact region forms a Schottky contact with the N-type epitaxial layer.
2. The VDMOS device according to claim 1, characterized in that: The first P-type doping region and the second P-type doping region each include a first-concentration P-type doping region and a second-concentration P-type doping region connected in contact with each other from top to bottom; The first concentration P-type doping region is located below the second concentration P-type doping region, the doping concentration of the first concentration P-type doping region is less than the doping concentration of the P-type base region, and the doping concentration of the second concentration P-type doping region is greater than the doping concentration of the P-type base region.
3. The VDMOS device according to claim 2, characterized in that: The first contact region and the second contact region extend downward from the N-type epitaxial layer to the same depth, the junction depth of the first-concentration P-type doped region is greater than the junction depth of the P-type base region, and the junction depth of the second-concentration P-type doped region is less than the junction depth of the P-type base region.
4. The VDMOS device according to claim 2 or 3, characterized in that: The area size of the first concentration P-type doping region is greater than the area size of the second concentration P-type doping region.
5. The VDMOS device according to any one of claims 1 to 3, characterized in that: The first P-type doping region and the second P-type doping region are formed simultaneously, and the first contact region and the second contact region are formed simultaneously.
6. The VDMOS device according to any one of claims 1 to 3, characterized in that: The gate region is a trench gate structure; The gate region is formed in a first trench in the N-type epitaxial layer, and the gate region includes a first dielectric layer and a control gate, wherein the first dielectric layer is arranged around the control gate.
7. The VDMOS device according to claim 6, characterized in that: The gate region is a shielded trench gate structure; The gate region also includes a shielding gate, and the first dielectric layer includes a field oxide layer, a gate spacer layer and a gate oxide layer, wherein the shielding gate is located below the control gate, the spacer oxide layer is located between the control gate and the shielding gate, and the field oxide layer and the gate spacer layer wrap the shielding gate, and the gate oxide layer is located on both sides of the control gate.
8. The VDMOS device according to any one of claims 1 to 3, characterized in that: The gate region is a planar gate structure; Wherein, the gate region is formed above the N-type epitaxial layer.
9. A method for manufacturing a VDMOS device with an integrated Schottky diode, characterized in that: include: Providing an N+ substrate; Forming an N-type epitaxial layer on the N+ substrate; Forming a gate region, a P-type base region, and a source region in sequence on the N-type epitaxial layer, wherein the P-type base region and the source region are located between the gate region, and the source region is located above the P-type base region; A first P-type doping region, a second P-type doping region, a first contact region and a second contact region are formed on the N-type epitaxial layer, wherein the first contact region extends downward through the source region and terminates within the P-type base region, the first P-type doping region is formed below the first contact region, and the second P-type doping region is formed below the first contact region. The second contact region extends downwardly and is formed in the N-type epitaxial layer, the second P-type doping region is formed below the second contact region, and the sidewall of the second contact region forms a Schottky contact with the N-type epitaxial layer; A drain region is formed under the N+ substrate.
10. The manufacturing method according to claim 9, characterized in that: A first P-type doping region, a second P-type doping region, a first contact region, and a second contact region are formed on the N-type epitaxial layer, including: Digging a second deep trench in the source region and digging a third deep trench in the N-type epitaxial layer, wherein the second deep trench penetrates the source region and terminates at the P-type body region; Performing P-type ion implantation into the second deep trench to form the first P-type doped region, and simultaneously performing P-type ion implantation into the third deep trench to form the second P-type doped region; Metal filling is performed above the first P-type doping region in the second deep trench to form the first contact region, and metal filling is performed above the second P-type doping region in the third deep trench to form the second contact region.
11. The manufacturing method according to claim 10, characterized in that: Performing P-type ion implantation into the second deep trench to form the first P-type doped region, and simultaneously performing P-type ion implantation into the third deep trench to form the second P-type doped region, comprises: Simultaneously performing a first P-type ion implantation into the second deep trench and the third deep trench to form a first concentration P-type doping region respectively; Simultaneously performing a second P-type ion implantation on the first-concentration P-type doping region in the second deep trench and the third deep trench to form a second-concentration P-type doping region; Among them, the first P-type doping region and the second P-type doping region both include the first-concentration P-type doping region and the second-concentration P-type doping region; the doping concentration of the first-concentration P-type doping region is less than the doping concentration of the P-type base region, and the doping concentration of the second-concentration P-type doping region is greater than the doping concentration of the P-type base region; the junction depth of the first-concentration P-type doping region is greater than the junction depth of the P-type base region, and the junction depth of the second-concentration P-type doping region is less than the junction depth of the P-type base region.
12. The manufacturing method according to claim 11, characterized in that: After simultaneously performing a first P-type ion implantation in the second deep trench and the third deep trench, the method further includes: Annealing and diffusion treatment is performed to make the area size of the formed first concentration P-type doping region larger than the area size of the second concentration P-type doping region.
13. The manufacturing method according to any one of claims 9 to 12, characterized in that: The gate region is a trench gate structure; Forming a gate region on the N-type epitaxial layer, comprising: Digging a first deep trench in the N-type epitaxial layer; The gate region is formed in the first deep trench, and the gate region includes a first dielectric layer and a control gate, wherein the first dielectric layer is disposed around the control gate.
14. The manufacturing method according to claim 13, characterized in that: The gate region is a shielded trench gate structure; forming the gate region in the first deep trench comprises: forming a field oxide layer, a shielding gate and a gate spacer in the first deep trench, wherein the field oxide layer and the gate spacer wrap the shielding gate, and the shielding gate is located below the gate spacer; forming a gate oxide layer on the sidewall of the first deep trench, wherein the thickness of the gate oxide layer is less than the thickness of the field oxide layer; A control gate is formed in the first deep trench, the gate oxide layer is located on both sides of the control gate, and the control gate is located above the gate spacer layer.
15. The manufacturing method according to any one of claims 9 to 12, characterized in that: The gate region is a planar gate structure; Forming a gate region on the N-type epitaxial layer, comprising: Growing a first dielectric layer on the upper surface of the N-type epitaxial layer; Polysilicon is deposited on the first dielectric layer, and the polysilicon is etched to form a gate region.