VDMOS device

Abstract

The invention provides a VDMOS device which comprises a cell, and the cell comprises a substrate and a drain electrode arranged on the back side of the substrate. The epitaxial layer is located on the substrate; the two source electrodes are arranged in the epitaxial layer at intervals, and the source electrodes are grounded; the channel region is formed below the source electrode, and the channel region is grounded; the gate dielectric layer is formed on the epitaxial layer, covers the part between the two source electrodes and is partially overlapped with the two source electrodes; the combined gate is formed on the gate dielectric layer, covers the part between the two source electrodes and is partially overlapped with the two source electrodes, and the combined gate comprises a first gate electrode, a combined gate isolation layer and a floating gate which are arranged from top to bottom; the first gate, the combined gate isolation layer and the floating gate form a first capacitor, and the floating gate, the gate dielectric layer and the channel region form a second capacitor; the gate voltage is divided by the first capacitance and the second capacitance such that the potential of the floating gate is lower than the gate voltage. According to the embodiment of the invention, the technical problem that the short-circuit tolerance of a VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) of a traditional SiC substrate is relatively low is solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular, to a VDMOS device. Background Art

[0002] Silicon Carbide (SiC) material is a third-generation wide bandgap semiconductor. Its bandgap width of 3.2eV is much larger than that of traditional silicon material 1.1eV, and its critical breakdown field strength is one order of magnitude higher than that of silicon material. It has the advantages of high temperature and high pressure resistance. At the same time, its saturation drift speed is fast, making it suitable for manufacturing fast-response high-temperature and high-pressure power semiconductor devices, such as VDMOS (Vertical Double-diffused MOSFET) and JFET (Junction Field-Effect Transistor, JFET) and other devices.

[0003] Vertical Double-diffused MOSFET (VDMOS) is a vertical semiconductor device that has the advantages of both bipolar transistors and ordinary MOS devices. The gate and source of VDMOS are located on the surface of the device, and the drain is located on the back of the device. Its working principle is that the gate controls the opening and closing of the channel, so that the current flows from the drain through the body and the inverted channel on the surface of the device to the source, and its conduction channel is on the surface of the device. VDMOS is an ideal power device in both switching applications and linear applications, and is mainly used in electronic switches, adapters, drive belt energy and industrial control.

[0004] Figure 1 This is a schematic diagram of the SiC VDMOS structure of the existing patent application CN116598356A. When a voltage is applied to Poly1-7, the capacitance effect of the metal oxide semiconductor is utilized to attract positive charges near the surface of Pwell 1-3 to form an inversion channel on the surface, thereby realizing conduction from the drain 1-10 to the source 1-9. The current first flows vertically from the drain 1-10 to the interface between the surface of the substrate 1-6 and the epitaxial layer 1-5 above the substrate, and then flows into the source 1-9 through the inversion channel 1-1 on the SiC surface.

[0005] In the field of electronic power, SiC MOSFET has a tendency to gradually replace silicon-based IGBT due to its excellent characteristics such as high withstand voltage, low on-resistance, and low switching loss. Since SiC materials can work under higher field strengths, the gate oxide layer 1-0 of SiCMOSFET will face a more severe working environment. Unclamped inductive switching test and short circuit test are important experiments to characterize the reliability of power devices.

[0006] Due to human factors and machine failures, power devices sometimes work under short-circuit faults. Normally, once a device short circuit is detected, the external protection circuit will trigger the protection mechanism and immediately shut down the circuit.

[0007] However, within the reaction time of triggering the protection circuit, the power device is required to be able to withstand a short circuit for a certain period of time, which is the short-circuit tolerance. Although the short circuit is only in microseconds, a very high-density current will flow through the power device instantly, generating a large amount of heat, and eventually causing thermal failure. There are many factors that cause short circuits, such as device failure in half-bridge circuits, gate false-on signals, and aging of insulation lines. Most of the research at home and abroad explores the short-circuit tolerance of devices from the perspective of failure phenomena and external circuit protection. Improving the short-circuit tolerance of the device itself is also of great significance.

[0008] SiC has a wider bandgap, so the drift region concentration of SiC power devices can be doped higher than that of silicon-based power devices, the SiC chip area is smaller, and the current capacity is stronger. According to experimental tests, the short-circuit tolerance of Si IGBT (a type of power device) can reach more than 10 microseconds. The short-circuit tolerance of SiC MOSFET (another type of power device) is much lower than that of Si IGBT due to the low reliability of the gate oxide layer and the excessive current density causing excessive temperature and thermal failure.

[0009] Mainstream device manufacturers on the market have given the short-circuit withstand time of Si IGBTs, and most IGBT devices can achieve a short-circuit withstand time of 10 microseconds under certain stress. For SiC MOSFET, only Infineon has promised a short-circuit withstand time of 3 microseconds.

[0010] Therefore, the short-circuit tolerance of the conventional existing SiC substrate VDMOS is relatively low, which is a technical problem that those skilled in the art urgently need to solve.

[0011] The above information disclosed in the background section is only for enhancing understanding of the background of the present application and therefore it may contain information that does not form the prior art known to a person of ordinary skill in the art. Summary of the invention

[0012] The embodiment of the present application provides a VDMOS device to solve the technical problem that the short-circuit tolerance of the conventional VDMOS on a SiC substrate is relatively low.

[0013] An embodiment of the present application provides a VDMOS device, including a cell, wherein the cell includes:

[0014] A substrate and a drain electrode disposed on the back side of the substrate;

[0015] an epitaxial layer, located on the substrate;

[0016] Two source electrodes are arranged in the epitaxial layer at intervals, and the source electrodes are grounded;

[0017] A channel region is formed below the source electrode, and the channel region is grounded;

[0018] A gate dielectric layer is formed on the epitaxial layer, covers a portion between the two source electrodes and overlaps with the two source electrodes respectively;

[0019] A combined gate is formed on the gate dielectric layer, covers the portion between the two source electrodes and overlaps with the two source electrodes respectively, and comprises a first gate, a combined gate isolation layer, and a floating gate arranged from top to bottom;

[0020] The combined gate isolation layer isolates the first gate and the floating gate, so that the first gate, the combined gate isolation layer and the floating gate form a first capacitor, and the floating gate, the gate dielectric layer and the channel region form a second capacitor; the external gate voltage is divided by the first capacitor and the second capacitor so that the potential of the floating gate is lower than the gate voltage, and the potential of the floating gate controls the opening and closing of the channel region.

[0021] The embodiment of the present application adopts the above technical solution, which has the following technical effects:

[0022] The gate voltage does not directly control the channel region, but controls the floating gate and then the channel region through electric field coupling. This can improve the protection of the gate (i.e., the combined gate) and enhance the short-circuit tolerance in the case of a short circuit.

[0023] The way to control the floating gate by electric field coupling is as follows:

[0024] The first gate, the combined gate isolation layer, and the floating gate form a first capacitor; the floating gate, the gate dielectric layer, and the channel region form a second capacitor. The first capacitor and the second capacitor form a structure of two capacitors connected in series. The characteristic of the capacitor series structure is that the electric field in the same dielectric is the same, so the electric field between the floating gate and the channel region is controlled by electric field coupling.

[0025] The protection of the gate (i.e., combined gate) is also due to this reason. The electric field on the gate dielectric layer is coupled up, and there is a floating gate in the middle as a transition layer.

[0026] In the combined gate mode, the voltage between the floating gate and the channel region is what really determines the current. When the electric field in the channel region changes, the potential of the floating gate will also change. In the case of high drain voltage, the opening of the channel in the channel region will be reduced, so the on-current will be reduced (that is, the short-circuit current will be reduced). Short-circuit power consumption = short-circuit current * short-circuit voltage, so when the short-circuit power consumption is reduced, the time for the device to reach the failure temperature becomes longer, increasing the short-circuit time.

[0027] When the VDMOS device of the embodiment of the present application works normally:

[0028] The on-resistance of the device is small, and thus the current is large, generally between one hundred and several hundred amperes.

[0029] When the VDMOS device of the embodiment of the present application is in a short-circuit state:

[0030] The on-resistance of the device is large, and the current is small, only a few amperes. The general device can only withstand the large current generated by the short circuit for less than 2μs. However, the VDMOS device of the embodiment of the present application has a combined gate, so that the short-circuit current is small, so that the VDMOS device can withstand the large current for a longer time, that is, the short-circuit tolerance is longer. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0032] Figure 1 This is a schematic diagram of the SiC VDMOS structure of the existing patent application CN116598356A;

[0033] Figure 2 A schematic diagram of a VDMOS device according to an embodiment of the present application;

[0034] Figure 3 A simulation diagram of a VDMOS device according to an embodiment of the present application;

[0035] Figure 4 It is a curve diagram of the drain output voltage Vd and the drain current Id of the VDMOS device of the present application and the SiC VDMOS of CN116598356A in the short-circuit state.

[0036] Reference numerals:

[0037] In the background technology:

[0038] Gate oxide layer 1-0, channel 1-1, N+ region 1-2, P-well 1-3, P+ region 1-4, epitaxial layer 1-5,

[0039] Substrate 1-6, Poly 1-7, source 1-9, drain 1-10;

[0040] In this application:

[0041] first gate 1, combined gate isolation layer 3, floating gate 2, gate dielectric layer 4,

[0042] Channel contact region 11 , epitaxial layer 12 , substrate 13 , channel region 14 , source 15 , source metal 16 . DETAILED DESCRIPTION

[0043] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0044] Embodiment 1

[0045] like Figure 2 As shown, the VDMOS device of the embodiment of the present application includes a cell, and the cell includes:

[0046] A substrate 13 and a drain electrode arranged on the back side of the substrate 13;

[0047] An epitaxial layer 12, located on the substrate 13;

[0048] Two source electrodes 15 are spaced apart and arranged in the epitaxial layer 12, and the source electrodes 15 are grounded;

[0049] A channel region 14 is formed under the source 15 and is grounded;

[0050] A gate dielectric layer 4 is formed on the epitaxial layer 12, covers a portion between the two source electrodes and overlaps with the two source electrodes respectively;

[0051] A combined gate is formed on the gate dielectric layer 4, covers the portion between the two sources and overlaps with the two source portions respectively, and comprises a first gate 1, a combined gate isolation layer 3, and a floating gate 2 arranged from top to bottom;

[0052] The combined gate isolation layer is used to isolate the first gate 1 from the floating gate 2, the first gate is used to connect to an external gate voltage so that the external gate voltage directly controls the first gate 1, the floating gate 2 is not connected to an external voltage so that the potential of the first gate 1 is coupled to the floating gate 2, and the potential of the floating gate 2 controls the opening and closing of the channel region 14. Specifically, the combined gate isolation layer 3 isolates the first gate 1 from the floating gate 2, so that the first gate 1, the combined gate isolation layer 3 and the floating gate 2 form a first capacitor, and the floating gate 2, the gate dielectric layer 4 and the channel region 14 form a second capacitor; the external gate voltage is divided by the first capacitor and the second capacitor so that the potential of the floating gate 2 is lower than the gate voltage, and the potential of the floating gate 2 controls the opening and closing of the channel region 14.

[0053] When the VDMOS device of the embodiment of the present application is working, the source 15 is grounded, the drain voltage of the drain is (usually a high voltage of several hundred volts), and the first gate 1 is connected to the gate voltage (usually a low voltage of several volts), that is, the gate voltage directly controls the first gate 1. Since the floating gate 2 is not connected to an external voltage, the potential of the floating gate 2 is achieved by coupling the potential of the first gate 1 to the floating gate 2.

[0054] The electric potential of the floating gate 2 obtained in this way is obtained by dividing the electric potential at the bottom of the floating gate 2 by the electric potential of the first gate 1. This technical feature is the voltage division technology.

[0055] If two or more capacitors are connected in series and the current is the same, then the voltage U on each capacitor is determined by Q = CU. That is to say, the voltage U across each capacitor is inversely proportional to the capacitance C, U = Q / C. The total voltage is the sum of the voltages across each capacitor, and Q represents the amount of charge carried by the capacitor.

[0056] Correspondingly, the first gate 1, the combined gate isolation layer 3, and the floating gate 2 of the VDMOS device of the present application form a first capacitor; the floating gate 2, the gate dielectric layer 4, and the channel region 14 form a second capacitor. Among them, the channel region 14 is grounded so that the potential of the channel region 14 is zero, and the first gate 1 is connected to the external gate voltage. These two capacitors are connected in series. The potential of the floating gate 2 is the gate voltage divided by the first capacitor and the second capacitor. That is, the potential of the floating gate 2 is lower than the gate voltage.

[0057] In this way, the gate voltage does not directly control the channel region 14, but controls the floating gate 2 and thus the channel region 14 through electric field coupling. This can improve the protection of the gate (ie, the combined gate) and enhance the short circuit tolerance in the short circuit situation.

[0058] The method of controlling the floating gate 2 by electric field coupling is as follows:

[0059] The first gate 1, the combined gate isolation layer 3, and the floating gate 2 form a first capacitor; the floating gate 2, the gate dielectric layer 4, and the channel region 14 form a second capacitor. The first capacitor and the second capacitor form a structure of two capacitors connected in series. The characteristic of the capacitor series structure is that the electric field in the same dielectric is the same, so the electric field between the floating gate 2 and the channel region 14 is controlled by electric field coupling.

[0060] The protection formed on the gate (ie, the combined gate) is also due to this reason. The electric field on the gate dielectric layer 4 is coupled upward, and there is a floating gate 2 in the middle as a transition layer.

[0061] In the combined gate mode, the voltage between the floating gate 2 and the channel region 14 is what really determines the current. When the electric field in the channel region 14 changes, the potential of the floating gate 2 will also change. In the case of high drain voltage, the opening of the channel in the channel region 14 will be reduced, so the on-current will be reduced (that is, the short-circuit current will be reduced). Short-circuit power consumption = short-circuit current * short-circuit voltage, so when the short-circuit power consumption is reduced, the time for the device to reach the failure temperature becomes longer, which increases the short-circuit time.

[0062] When the VDMOS device of the embodiment of the present application works normally:

[0063] The on-resistance of the device is small, and thus the current is large, generally between one hundred and several hundred amperes.

[0064] When the VDMOS device of the embodiment of the present application is in a short-circuit state:

[0065] The on-resistance of the device is large, and the current is small, only a few amperes. The general device can only withstand the large current generated by the short circuit for less than 2μs. However, the VDMOS device of the embodiment of the present application has a combined gate, so that the short-circuit current is small, so that the VDMOS device can withstand the large current for a longer time, that is, the short-circuit tolerance is longer.

[0066] like Figure 2 As shown, the side edge of the combined gate is flush with the side edge of the gate dielectric layer 4 .

[0067] As an optional manner, the side edge of the gate dielectric layer 4 may also protrude beyond the side edge of the combined gate.

[0068] In implementation, the thickness of the floating gate 2 ranges from greater than or equal to 0.05 μm to less than or equal to 1 μm.

[0069] In implementation, such as Figure 2 As shown, the floating gate 2 is a floating gate made of polysilicon material.

[0070] As an optional manner, the floating gate 2 may be a floating gate made of a conductive material such as a metal material; the floating gate 2 may also be a floating gate made of a conductive material such as an alloy material.

[0071] In implementation, such as Figure 2 As shown, the thickness of the combined gate isolation layer 3 ranges from greater than or equal to 10 nm to less than or equal to 1 μm, and the combined gate isolation layer 3 is a combined gate isolation layer made of a high dielectric constant material.

[0072] In implementation, such as Figure 2 As shown, the substrate is a SIC substrate.

[0073] As an option, the substrate may be a substrate of diamond material; the substrate may also be a substrate of GaN material.

[0074] In implementation, such as Figure 2 As shown, the overlap width of the combined gate and the channel region 14 ranges from greater than or equal to 0.1 μm to less than or equal to 1 μm.

[0075] In this way, the control of the combined gate over the channel region 14 can be ensured.

[0076] In implementation, the thickness of the gate dielectric layer 4 is more than twice the thickness of the gate isolation layer 3 .

[0077] In implementation, such as Figure 2 As shown, the VDMOS device also includes:

[0078] Two channel contact regions 11 are respectively connected to opposite sides of the two channel regions 14;

[0079] A grounded source metal 16 is formed on the epitaxial layer and connects the source 15 and the channel contact region 11 .

[0080] In implementation, the channel region 14 includes the channel contact region 11 and the bottom surface, and the bottom surface and side surfaces of the source 15 .

[0081] Figure 3 The VDMOS device of the embodiment of the present application is a simulation diagram. The VDMOS device of the embodiment of the present application adopts a gate dielectric layer 4 (Tox2) of 100A and a combined gate isolation layer 3 (Tox1) of 400A.

[0082] The simulation comparison of the VDMOS device of the present application and the SiC VDMOS of CN116598356A in the short-circuit state is shown in the following table:

[0083]

[0084] In the table, Vth is the threshold voltage, Rsp is the on-resistance, BV is the breakdown voltage, and short-circuit Idsat is the on-current under short-circuit conditions.

[0085] The third row in the table shows the short-circuit state parameters of the VDMOS device of the present application using a gate dielectric layer 4 (Tox2) with a thickness of 100A and a combined gate isolation layer 3 (Tox1) with a thickness of 400A.

[0086] The content of the second row in the table is the short-circuit state parameters of the SiC VDMOS of CN116598356A.

[0087] From the above table, it can be seen that the on-resistance Rsp of the VDMOS device of the present application and the SiC VDMOS of CN116598356A are close, while the short-circuit current (short-circuit Idsat) is reduced by more than half. Therefore, the short-circuit withstand capacity of the VDMOS device of the present application is more than doubled than that of the SiC VDMOS device of CN116598356A.

[0088] Figure 4 It is a curve diagram of the drain output voltage Vd and the drain current Id of the VDMOS device of the present application and the SiC VDMOS of CN116598356A in the short-circuit state.

[0089] Figure 4 In the figure, the horizontal axis is the drain output voltage in volts; the vertical axis is the drain current in amperes. There are four VDMOS devices in the present application. The thickness of the combined gate isolation layer 3 (Tox1) of the four VDMOS devices in the present application is 300A (i.e., angstroms), 400A, 500A, and 600A, respectively, and the thickness of the gate dielectric layer 4 (Tox2) of the four VDMOS devices in the present application is 100A.

[0090] like Figure 4 As shown, the drain current Id and the drain output voltage Vd when the gate voltage Vg is 18V at 400 degrees Celsius under simulation.

[0091] The temperature when simulating device damage is set to 400 degrees Celsius, and it can be seen that the current of the single poly (SiC VDMOS of CN116598356A of the prior art) is 1462 amperes when the drain output voltage Vd is 800 volts.

[0092] The combined gate isolation layer 3 (Tox1 is 400A) of the VDMOS device of the present application is the best simulation structure this time. It can be seen that under 800 volts, the drain current Id is 637 amperes, which means that there is a significant reduction in the saturation region, thereby obtaining a significant reduction in the heat generation power of the device at this time.

[0093] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0094] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0095] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0096] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0097] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0098] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A VDMOS device, characterized in that: Comprising a cell, the cell comprising: A substrate (13) and a drain electrode arranged on the back side of the substrate (13); An epitaxial layer (12) located on the substrate (13); Two source electrodes (15) are arranged at intervals in the epitaxial layer (12), and the source electrodes (15) are grounded; A channel region (14) is formed below the source (15), and the channel region is grounded; A gate dielectric layer (4) is formed on the epitaxial layer (12), covers a portion between the two source electrodes and overlaps with the two source electrodes respectively; A combined gate is formed on the gate dielectric layer (4), covers the portion between the two source electrodes and overlaps with the two source electrodes respectively, and comprises a first gate (1), a combined gate isolation layer (3), and a floating gate (2) arranged from top to bottom; The combined gate isolation layer (3) isolates the first gate (1) from the floating gate (2), so that the first gate (1), the combined gate isolation layer (3) and the floating gate (2) form a first capacitor, and the floating gate (2), the gate dielectric layer (4) and the channel region (14) form a second capacitor; the external gate voltage is divided by the first capacitor and the second capacitor so that the potential of the floating gate (2) is lower than the gate voltage, and the potential of the floating gate (2) controls the opening and closing of the channel region (14).

2. The VDMOS device according to claim 1, characterized in that: The side edge of the combined gate is flush with the side edge of the gate dielectric layer (4); Alternatively, the side edge of the gate dielectric layer (4) protrudes beyond the side edge of the combined gate.

3. The VDMOS device according to claim 1, characterized in that: The thickness of the floating gate (2) has a value range of greater than or equal to 0.05 μm and less than or equal to 1 μm.

4. The VDMOS device according to claim 1, characterized in that: The floating gate (2) is a floating gate made of polysilicon material; or the floating gate (2) is a floating gate made of metal material; or the floating gate (2) is a floating gate made of alloy material.

5. The VDMOS device according to claim 1, characterized in that: The thickness of the combined gate isolation layer (3) is in the range of greater than or equal to 10 nm and less than or equal to 1 μm, and the combined gate isolation layer (3) is a combined gate isolation layer made of a high dielectric constant material.

6. The VDMOS device according to claim 1, characterized in that: The substrate is a SIC substrate; or the substrate is a substrate made of diamond material; or the substrate is a substrate made of GaN material.

7. The VDMOS device according to claim 1, characterized in that: The overlap width of the combined gate and the channel region (14) is in the range of greater than or equal to 0.1 μm and less than or equal to 1 μm.

8. The VDMOS device according to claim 7 requires a short-circuit withstand capability greater than 5us, characterized in that: The thickness of the gate dielectric layer (4) is more than twice the thickness of the gate isolation layer (3).

9. The VDMOS device according to any one of claims 1 to 8, characterized in that: Also includes: Two channel contact regions (11) are respectively connected to opposite sides of the two channel regions (14); A grounded source metal (16) is formed on the epitaxial layer and connects the source (15) and the channel contact region (11).

10. The VDMOS device according to claim 9, characterized in that: The channel region (14) includes the channel contact region (11) and the bottom surface, and the bottom surface and side surfaces of the source (15).

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