Semiconductor device with isolation structure and manufacturing method of isolation structure

Abstract

The invention relates to a semiconductor device with an isolation structure and a manufacturing method of the isolation structure. The semiconductor device comprises a substrate; the first doped region is located on the substrate, and the doping concentration of the first doped region is smaller than that of the substrate; the junction isolation structure comprises a first buried region and a second buried region in direct contact with the first buried region, the first buried region is located on the first doped region, the second buried region is located on the first buried region, and the doping concentration of the second buried region is smaller than that of the first buried region; a second doped region on the second buried region; and the device main body region is located in the second doped region. The hole blocking layer is formed on the interface of the first buried region and the second buried region, so that the hole can be prevented from passing through the hole blocking layer to transit to the substrate to form substrate electric leakage, and the latch-up effect of the device is improved. Due to the arrangement of the first doped region, the width of the effective base region can be wider by utilizing the base region expansion effect, so that parasitic electric leakage flowing into the substrate is effectively reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device with an isolation structure, and also to a method for manufacturing the isolation structure. Background Art

[0002] The exemplary full isolation structure uses an N-type buried layer to isolate the substrate from the internal structure of the device (ie, isolation is performed using junction isolation) to meet diverse circuit applications.

[0003] However, the isolation junction formed by the N-type buried layer will form a parasitic BJT (bipolar junction transistor). In the H-bridge circuit, when the body diode of the semiconductor device is freewheeling during the dead time, the parasitic BJT will be triggered, resulting in substrate leakage. For the low-side device of the half-bridge circuit, the parasitic BJT may even cause latch-up, or even burn the device. Summary of the invention

[0004] Based on this, it is necessary to provide a semiconductor device with an isolation structure that can improve the latch-up effect.

[0005] A semiconductor device with an isolation structure comprises: a substrate having a second conductivity type; a first doped region located on the substrate and having the second conductivity type, wherein the doping concentration of the first doped region is less than the doping concentration of the substrate; a junction isolation structure comprising a first buried region and a second buried region directly in contact with the first buried region, wherein the first buried region is located on the first doped region and has the first conductivity type, and the second buried region is located on the first buried region and has the first conductivity type, wherein the doping concentration of the second buried region is less than the doping concentration of the first buried region; the first conductivity type and the second conductivity type are opposite conductivity types; a second doped region having the second conductivity type, located on the second buried region; wherein the junction isolation structure is used to achieve insulation isolation between the substrate and the second doped region.

[0006] The above-mentioned semiconductor device with an isolation structure, the isolation structure includes a first buried region and a second buried region. Due to the difference in carrier concentration between the first buried region and the second buried region, a built-in electric field is formed at the junction of the first buried region and the second buried region. Due to the existence of the electric field, a carrier blocking layer is formed at the interface. Specifically, for the embodiment in which the first conductivity type is N-type and the second conductivity type is P-type, the carrier blocking layer is a hole blocking layer, which can prevent the holes in the second doped region from passing through the hole blocking layer and crossing to the substrate to form substrate leakage, thereby improving the latch effect of the device. For the embodiment in which the first conductivity type is P-type and the second conductivity type is N-type, the carrier blocking layer is an electron blocking layer, which can prevent the electrons in the second doped region from passing through the electron blocking layer and crossing to the substrate to form substrate leakage, thereby also improving the latch effect of the device. Even if the parasitic transistor formed by the second doped region-junction isolation structure-first doped region and the substrate is turned on, due to the provision of the first doped region of the second conductivity type, the width of the effective base region becomes wider according to the base region expansion effect, thereby effectively reducing the parasitic leakage flowing into the substrate.

[0007] In one embodiment, the first doping region has a doping dose not exceeding 3E14 cm -2 epitaxial layer.

[0008] In one embodiment, the thickness of the first doped region is not less than 10 micrometers.

[0009] In one embodiment, the resistivity of the substrate is less than 0.01 Ω·cm.

[0010] In one of the embodiments, the semiconductor device further includes a device body region, and the device body region is located in the second doped region.

[0011] In one of the embodiments, the semiconductor device further includes a lateral isolation structure surrounding the device body region in a laterally direction, and the lateral isolation structure is located in the second doped region and on the second buried region.

[0012] In one of the embodiments, the lateral isolation structure includes a first conductivity type region.

[0013] In one embodiment, the lateral isolation structure comprises an insulating material.

[0014] In one embodiment, the lateral isolation structure includes an insulating layer arranged on the inner wall of the isolation groove, and a conductive structure electrically connected to the second buried area is also provided in the isolation groove, and the insulating layer insulates and isolates the conductive structure in the laterally direction, and the conductive structure is used to lead the second buried area to the upper surface of the semiconductor device.

[0015] In one embodiment, the bottom of the second buried region is in direct contact with the top of the first buried region.

[0016] In one embodiment, the doping concentration of the first buried region is not less than 1E19 cm -3 , the doping concentration of the second buried region is not higher than 1E17 cm -3 .

[0017] In one embodiment, the thickness of the second buried region is smaller than the thickness of the first buried region.

[0018] In one embodiment, the device body region includes a drift region, and the drift region is separated from the second buried region by the second doped region.

[0019] In one embodiment, the second doped region is an epitaxial layer.

[0020] In one of the embodiments, the drift region has a first conductivity type.

[0021] In one embodiment, the semiconductor device comprises a lateral device.

[0022] In one embodiment, the semiconductor device includes a lateral double diffused metal oxide semiconductor field effect transistor.

[0023] In one embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0024] It is also necessary to provide a method for manufacturing an isolation structure.

[0025] A method for manufacturing an isolation structure, comprising: obtaining a substrate, on which a first doped region is formed; the substrate and the first doped region have a second conductivity type, and the doping concentration of the first doped region is less than the doping concentration of the substrate; forming a first buried region on the first doped region, the first buried region has the first conductivity type; forming a second buried region on the first buried region that is in direct contact with the first buried region, the second buried region has the first conductivity type and the doping concentration is less than the doping concentration of the first buried region; forming a second doped region on the second buried region.

[0026] In the manufacturing method of the isolation structure, there is a difference in carrier concentration between the first buried region and the second buried region of the junction isolation structure, so a built-in electric field is formed at the junction of the first buried region and the second buried region. Due to the existence of the electric field, a hole blocking layer is formed at the interface, which can prevent the holes in the second doping region from passing through the hole blocking layer and crossing to the substrate to form substrate leakage, thereby improving the latch effect of the device. Even if the parasitic triode formed by the second doping region-junction isolation structure-first doping region and substrate is turned on, due to the provision of the first doping region of the second conductivity type, according to the base region expansion effect, the width of the effective base region becomes wider, thereby effectively reducing the parasitic leakage flowing into the substrate.

[0027] In one embodiment, the step of forming a first buried region in the substrate includes: the step of forming a first buried region on the first doped region includes: injecting first conductive type ions into the first doped region and then performing a push-trap, the temperature of the push-trap is above 1000 degrees Celsius and the time is above 100 minutes.

[0028] In one embodiment, the doping concentration of the first buried region is at least 100 times higher than that of the second buried region.

[0029] In one embodiment, after the step of forming the second doped region on the second buried region, the method further includes the step of forming a device body region in the second doped region.

[0030] In one embodiment, the device body region includes a drift region.

[0031] In one of the embodiments, the drift region has a first conductivity type.

[0032] In one embodiment, the step of forming the second doped region on the second buried region is growing an epitaxial layer.

[0033] In one embodiment, the semiconductor device comprises a lateral device.

[0034] In one embodiment, the semiconductor device includes a lateral double diffused metal oxide semiconductor field effect transistor.

[0035] In one embodiment, the first conductivity type is N-type, and the second conductivity type is P-type. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the embodiments and / or examples currently described, and the best modes of these inventions currently understood.

[0037] Figure 1 is a schematic cross-sectional structure diagram of a semiconductor device with an isolation structure in one embodiment of the present application;

[0038] Figure 2 is a schematic diagram of the electric field direction of a junction isolation structure of a semiconductor device with an isolation structure in another embodiment of the present application;

[0039] Figure 3 yes Figure 1 Equivalent circuit diagram of the structure shown;

[0040] Figures 4a to 4c 1 is a schematic diagram of a cross-sectional structure of a device according to three different embodiments of the present application having a lateral isolation structure 150;

[0041] Figure 5 is a flow chart of a method for manufacturing an isolation structure in one embodiment of the present application;

[0042] Figures 6a to 6c is used Figure 5 The schematic diagram of the cross-sectional structure of the junction isolation structure during the process of manufacturing the isolation structure by the method shown is shown. DETAILED DESCRIPTION

[0043] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0045] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0046] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0047] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0048] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0049] The semiconductor field vocabulary used in this article is technical vocabulary commonly used by technical personnel in this field. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0050] The present application provides an isolation structure that can be applied to all semiconductor devices that require junction isolation. Figure 1 1 is a schematic cross-sectional view of a semiconductor device with an isolation structure in an embodiment of the present application, the semiconductor device includes a substrate 110, a first doped region 112, a junction isolation structure (including a first buried region 122 and a second buried region 124) and a second doped region 130. The substrate 110 is a semiconductor substrate, and its material can be undoped single crystal silicon, single crystal silicon doped with impurities, etc., and can also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors. Figure 1 In the illustrated embodiment, the substrate 110 is a single crystal silicon substrate of the second conductivity type. In one embodiment of the present application, the substrate 110 is a heavily doped substrate to obtain a lower resistivity. In one embodiment of the present application, the resistivity of the substrate 110 is less than 0.01Ω·cm. The first doped region 112 is located on the substrate 110 and has the second conductivity type, and the doping concentration of the first doped region 112 is less than the doping concentration of the substrate 110.

[0051] The first buried region 122 is located on the first doped region 112. The second buried region 124 is located on the first buried region 122 and directly contacts the first buried region 122. The first buried region 122 and the second buried region 124 have the first conductivity type, and the doping concentration of the second buried region 124 is less than the doping concentration of the first buried region 122. Figure 1 In the illustrated embodiment, the first conductivity type is N-type and the second conductivity type is P-type. In other embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type. The embodiment in which the first conductivity type is N-type and the second conductivity type is P-type is particularly suitable for the BCD process commonly used in medium and low voltage devices. The junction isolation structure is used to achieve insulation isolation between the substrate 110 and the second doping region 130. The insulation isolation refers to the ability to reduce or even isolate leakage, rather than having the insulation properties of a general non-conductive insulating material.

[0052] The second doped region 130 is located on the second buried region 124 .

[0053] The above-mentioned semiconductor device with an isolation structure, the isolation structure includes a first buried region 122 and a second buried region 124. Since there is a difference in carrier concentration between the first buried region 122 and the second buried region 124, a built-in electric field is formed at the junction of the first buried region 122 and the second buried region 124. Due to the existence of the electric field, a carrier blocking layer is formed at the interface. Specifically, for an embodiment in which the first conductivity type is N-type and the second conductivity type is P-type, the carrier blocking layer is a hole blocking layer, which can prevent holes in the second doping region 130 from passing through the hole blocking layer and crossing to the first doping region 112 and the substrate 110 to form substrate leakage, thereby improving the latch effect of the device. For an embodiment in which the first conductivity type is P-type and the second conductivity type is N-type, the carrier blocking layer is an electron blocking layer, which can prevent electrons in the second doping region 130 from passing through the electron blocking layer and crossing to the first doping region 112 and the substrate 110 to form substrate leakage, thereby also improving the latch effect of the device. Even if the parasitic transistor formed by the second doping region 130-junction isolation structure-first doping region 112 and substrate 110 is turned on, due to the provision of the first doping region 112 of the second conductivity type, the width of the effective base region becomes wider according to the base region extension effect, thereby effectively reducing the parasitic leakage flowing into the substrate. In addition, the first doping region 112 can ensure that the junction isolation structure has a higher withstand voltage level.

[0054] exist Figure 1 In the illustrated embodiment, the semiconductor device with the isolation structure further includes a device body region 140 located in the second doping region 130 .

[0055] It can be understood that in order to achieve the desired isolation effect, the hole blocking layer should be distributed widely enough, so that in the entire region where isolation is required, the bottom surface of the second buried region 124 should be in direct contact with the top surface of the first buried region 122. In one embodiment of the present application, the entire bottom surface of the second buried region 124 is in direct contact with the first buried region 122, and / or the entire top surface of the first buried region 122 is in direct contact with the second buried region 124.

[0056] Since the first buried region 122 and the second buried region 124 serve as junction isolation structures, the back side (i.e. Figure 1 The bottom of the substrate 110 in the middle) cannot be used as an electrode of the device, and the device cannot be a vertical device with an electrode arranged on the back of the substrate 110, such as a vertical double diffused metal oxide semiconductor field effect transistor (VDMOSFET). In one embodiment, the semiconductor device with an isolation structure of the present application includes a lateral device, such as a lateral double diffused metal oxide semiconductor field effect transistor (LDMOSFET). In one embodiment of the present application, the semiconductor device with an isolation structure of the present application is a fully isolated semiconductor device.

[0057] In the embodiment where the first conductivity type is N-type and the second conductivity type is P-type, the first buried region 122 is a high-concentration N-type buried layer BN+, and the second buried region 124 is a low-concentration N-type buried layer BN-. At the junction of the first buried region 122 and the second buried region 124, the concentration difference of carriers will cause ions to diffuse and move, thereby forming a built-in electric field with an electric field strength of Where N E + is the electron concentration of BN+, N E - is the electron concentration of BN-, and the direction of the electric field is from BN+ to BN-, such as Figure 1 As shown. Due to the existence of the built-in electric field, a hole blocking layer is formed at the interface, which can prevent the holes in the second doping region 130 from passing through the hole blocking layer and crossing to the substrate 110 to form substrate leakage. For the embodiment in which the first conductivity type is P type and the second conductivity type is N type, the direction of the electric field is as follows Figure 2 As shown, since the thickness of the first buried region 122 is thick enough and the concentration is high, the resistance value of the first buried region 122 is low, thereby suppressing the damage of the device caused by the latch effect.

[0058] To obtain a better blocking effect on holes, the field strength of the aforementioned built-in electric field should be large enough. In one embodiment of the present application, the doping concentration of the first buried region 122 is at least 100 times higher than that of the second buried region 124. Furthermore, for BN+, a higher doping concentration can provide better recombination ability of minority carriers, thereby further reducing hole crossing. In one embodiment of the present application, the doping concentration of the first buried region 122 is not less than 1E19 cm -3 , the doping concentration of the second buried region is not higher than 1E17 cm -3 It should be noted that a high BN+ doping concentration will affect the breakdown voltage (withstand voltage) of the device, that is, the higher the BN+ doping concentration, the lower the breakdown voltage of the device. Therefore, the BN+ doping concentration must also meet the breakdown voltage requirements of the device.

[0059] In one embodiment of the present application, the thickness of the second buried region 124 is less than the thickness of the first buried region 122, so that the minority carrier recombination effect of the junction isolation structure can be strengthened. For the junction isolation structure, the first buried region 122 plays the main isolation role, and the second buried region 124 is used as a buffer layer (buffer layer) to further strengthen the isolation effect of the first buried region 122, and is used to establish its built-in electric field on the isolation ring through a concentration gradient, and use the built-in electric field to prevent electrons or holes from crossing to the substrate 110, thereby preventing the substrate 110 from leaking or even latching.

[0060] See also Figure 1 In this embodiment, the device body region 140 includes a drift region, and the drift region and the second buried region 124 are separated by the second doped region 130. Figure 1 In the illustrated embodiment, the second doped region 130 is a P-type epitaxial layer, the first doped region 112 is a P-type lightly doped epitaxial layer, and the device body region 140 includes an N-type drift region. Figure 3 yes Figure 1 The equivalent circuit diagram of the structure shown in FIG. 1 includes a parasitic PNP transistor (i.e., P-type epitaxial layer-N-type buried layer-P-type first doped region and P-type substrate) and a parasitic NPN transistor (i.e., N-type drift region-P-type epitaxial layer-N-type buried layer), R P-epi is the equivalent resistance of the P-type epitaxial layer, R BN+ is the equivalent resistance of the first buried region 122 (ie, BN+). When the body diode of the device on the junction isolation structure is freewheeling, Figure 3 The emitter junction of the parasitic PNP transistor and the emitter junction of the parasitic NPN transistor in the equivalent circuit are forward biased, but due to the presence of the aforementioned hole blocking layer, only a very small current will enter the first buried region 122. And because the first buried region 122 has a higher doping concentration, R BN+ The resistance value is very small, R BN+ The voltage drop is also very small, and it is difficult for the parasitic PNP transistor and the parasitic NPN transistor to be turned on at the same time, thereby effectively avoiding the latch effect. In addition, since the doping concentration of the first doping region 112 is very low, a base region extension region (i.e. Figure 1 Even if the parasitic PNP is turned on, the width of the effective base region will become wider due to the base region extension effect, thereby effectively reducing the parasitic leakage flowing into the substrate 110. In one embodiment of the present application, the doping dose of the first doping region 112 does not exceed 3E14cm -2 In one embodiment of the present application, the thickness of the first doping region 112 is not less than 10 micrometers to obtain a sufficient width of the effective base region.

[0061] In one embodiment of the present application, the semiconductor device with an isolation structure is a lateral device, such as an LDMOSFET. In one embodiment of the present application, the semiconductor device with an isolation structure can be applied to circuit structures such as a half-bridge circuit and an H-bridge circuit, for example, as a low-side device of a half-bridge circuit.

[0062] Since the upper transistor and the lower transistor share a substrate in the half-bridge circuit, the connection between the upper tube and the lower tube will parasitize an NPN transistor. However, since the first doping region 112 is provided in the present application, the Psub of the substrate 110 can be made of a heavily doped substrate material (for example, the resistivity of the substrate 110 is less than 0.01Ω·cm), so that in the half-bridge circuit and the H-bridge circuit, the base resistance of the parasitic N-type buried layer-P-type substrate-N-type buried layer transistor between the upper tube and the lower tube is reduced, thereby further improving the latch effect that may exist between the upper tube and the lower tube.

[0063] In one embodiment of the present application, the semiconductor device with the isolation structure further includes a lateral isolation structure 150 that surrounds the device main region 140 in the lateral direction. The lateral isolation structure 150 is located in the second doped region 130 and on the second buried region 124, and thus together with the junction isolation structure, serves as an isolation cover that surrounds the device main region 140, surrounds and electrically isolates the device main region 140 in the lateral direction and at the bottom, thereby reducing leakage current. For embodiments in which the lateral isolation structure 150 is provided, the junction isolation structure only needs to be formed in the area defined by the lateral isolation structure 150, and does not need to occupy the entire first doped region 112 in the horizontal plane. Figure 4a In the illustrated embodiment, the lateral isolation structure 150 includes a first conductivity type region. In an embodiment where the first conductivity type is N-type and the second conductivity type is P-type, the first conductivity type region is an N-well.

[0064] In one embodiment of the present application, the lateral isolation structure 150 is formed by digging a groove and then filling the groove with an isolation material. Figure 4b In the illustrated embodiment, the junction isolation structure (the first buried region 122 and the second buried region 124) is led out to the upper surface of the semiconductor device through a conductive structure 160 (whose material may be metal and / or alloy) filled in a lead-out groove, and the bottom of the lead-out groove extends to the second buried region 124.

[0065] exist Figure 4c In the illustrated embodiment, the lateral isolation structure 150 includes an insulating layer 154 disposed on the inner wall of the isolation groove, and a conductive structure 152 electrically connected to the second buried region 124 is also disposed in the isolation groove, and the insulating layer 154 insulates and isolates the conductive structure 152 in the lateral direction. The conductive structure 152 is used to lead the second buried region 124 to the upper surface of the semiconductor device. The conductive structure 152 can be made of metal and / or alloy.

[0066] The present application accordingly provides a method for manufacturing an isolation structure. Figure 5 : is a flow chart of a method for manufacturing an isolation structure in an embodiment of the present application, comprising the following steps:

[0067] S510, obtaining a substrate, on which a first doping region is formed.

[0068] The substrate 110 is a semiconductor substrate, and its material may be undoped single crystal silicon, single crystal silicon doped with impurities, etc., or at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors. Figure 6a In the illustrated embodiment, the substrate 110 is a single crystal silicon substrate of the second conductivity type. In one embodiment of the present application, the first conductivity type is N-type and the second conductivity type is P-type. In other embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type. In one embodiment of the present application, the substrate 110 is a heavily doped substrate to obtain a lower resistivity. In one embodiment of the present application, the resistivity of the substrate 110 is less than 0.01Ω·cm. The first doped region 112 is located on the substrate 110 and has the second conductivity type, and the doping concentration of the first doped region 112 is less than the doping concentration of the substrate 110.

[0069] In one embodiment of the present application, the first doping region 112 is formed by epitaxy. In one embodiment of the present application, the doping dose of the first doping region 112 does not exceed 3E14 cm -2 In one embodiment of the present application, the thickness of the first doping region 112 is not less than 10 micrometers.

[0070] S520, forming a first buried region on the first doped region.

[0071] In one embodiment of the present application, ions of the first conductivity type are implanted into the first doping region 112 by an ion implantation process to form a first buried region 122. Figure 6b . In one embodiment of the present application, the first buried region 122 is a heavily doped N-type buried layer (BN+), and the concentration of the N-type impurities should be as heavily doped as possible while ensuring the breakdown voltage of the device, because a denser N-type impurity can provide a stronger minority carrier recombination ability and reduce hole crossing. After the injection, a thermal process is used to push the well, so that the junction depth of the first buried region 122 is deeper and the width is larger. In one embodiment of the present application, the temperature of the thermal process is above 1000 degrees Celsius and the time is above 100 minutes.

[0072] S530 , forming a second buried region on the first buried region and directly contacting the first buried region.

[0073] The second buried region 124 has the first conductivity type, and its doping concentration is less than the doping concentration of the first buried region 122. In one embodiment of the present application, after forming the first buried region 122 (i.e., after the well push in step S520), an ion implantation is performed to form the second buried region 124. Figure 6c . In one embodiment of the present application, the second buried region 124 is formed by N-type implantation with a lower impurity concentration and a shallow implantation depth (low implantation energy), forming a second buried region 124 (lightly doped N-type buried layer BN-) whose bottom is directly in contact with the top of the first buried region 122. The concentration difference at the junction of the first buried region 122 and the second buried region 124 will cause the diffusion movement of ions, thereby forming a built-in electric field, and the direction of the electric field is from BN+ to BN-. Due to the existence of this electric field, a hole blocking layer is formed at the junction of BN+ and BN-, which can prevent holes in the body region of the semiconductor device from entering the buried layer and crossing to the substrate 110 to form substrate leakage. At the same time, due to the high concentration of BN+, the resistance value is low, and the aforementioned push-well makes the buried layer deep enough (that is, the depth from the top to the bottom of the buried layer is large), thereby suppressing the damage to the device caused by the latch effect.

[0074] In one embodiment of the present application, the doping concentration of the first buried region 122 is at least 100 times higher than that of the second buried region 124 .

[0075] S540, forming a second doped region on the second buried region.

[0076] In one embodiment of the present application, epitaxy is grown on the structure formed in step S530 to form a second doped region 130 located on the second buried region 124. Figure 1 In one embodiment of the present application, the second doped region 130 is a P-type epitaxial layer.

[0077] The internal manufacturing processes of the device can then be performed on the epitaxial layer.

[0078] The manufacturing method of the isolation structure is to form a hole blocking layer at the interface of the first buried region 122 and the second buried region 124 with a concentration difference by setting the first buried region 122 and the second buried region 124 as a junction isolation structure, and to prevent holes from passing through the buried layer into the substrate 110 to form substrate leakage by using the contact potential difference. Thereby, the junction isolation effect of the semiconductor device is improved, and the latch problem of the fully isolated device is improved. And because the first doped region 112 of the second conductivity type is set, even if the parasitic triode formed by the second doped region 130-junction isolation structure-first doped region 112 and the substrate 110 is turned on, the base region extension effect can be used to make the width of the effective base region wider, thereby effectively reducing the parasitic leakage flowing into the substrate.

[0079] In one embodiment of the present application, the doping concentration of the first buried region 122 is at least 100 times higher than that of the second buried region 124 .

[0080] In one embodiment of the present application, the doping concentration of the first buried region 122 is not less than 1E19 cm -3 , the doping concentration of the second buried region 124 is not higher than 1E17 cm -3 .

[0081] In one embodiment of the present application, after step S540, a step of forming a device body region 140 in the second doping region is also included.

[0082] In one embodiment of the present application, after step S540, a step of forming a lateral isolation structure 150 is further included. The lateral isolation structure 150 is located in the second doped region 130 and on the second buried region 124, and surrounds the device body region 140 in the lateral direction.

[0083] exist Figure 4a In the illustrated embodiment, the lateral isolation structure 150 includes a first conductivity type region. In an embodiment where the first conductivity type is N type and the second conductivity type is P type, the first conductivity type region is an N well formed by ion implantation.

[0084] In one embodiment of the present application, the lateral isolation structure 150 is formed by photolithography on the second doping region 130, etching the second doping region 130 to form an isolation groove, and then filling the groove with an isolation material. Figure 4b .

[0085] exist Figure 4b In the illustrated embodiment, after step S540, the process further includes photolithography on the second doped region 130, etching the second doped region 130 to form an extraction groove, and then filling the extraction groove with a conductive structure. The junction isolation structure (the first buried region 122 and the second buried region 124) is extracted to the upper surface of the semiconductor device through the conductive structure 160 (the material may be metal and / or alloy), and the bottom of the extraction groove extends to the second buried region 124.

[0086] exist Figure 4c In the illustrated embodiment, the lateral isolation structure 150 includes an insulating layer 154 disposed on the inner wall of the isolation groove, and a conductive structure 152 electrically connected to the second buried region 124 is also disposed in the isolation groove, and the insulating layer 154 insulates and isolates the conductive structure 152 in the lateral direction. The conductive structure 152 is used to lead the second buried region 124 to the upper surface of the semiconductor device. The conductive structure 152 can be made of metal and / or alloy.

[0087] In one embodiment of the present application, the device body region includes a drift region.

[0088] In one embodiment of the present application, the drift region has a first conductivity type.

[0089] In one embodiment of the present application, the semiconductor device includes a lateral device.

[0090] In one embodiment of the present application, the semiconductor device includes an LDMOSFET (Lateral Double Diffused Metal Oxide Semiconductor Field Effect Transistor).

[0091] It should be understood that, although the various steps in the flowchart of the present application are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0092] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0093] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0094] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A semiconductor device with an isolation structure, characterized in that: include: a substrate having a second conductivity type; A first doping region, located on the substrate and having a second conductivity type, wherein a doping concentration of the first doping region is less than a doping concentration of the substrate; A junction isolation structure, comprising a first buried region and a second buried region directly contacting the first buried region, wherein the first buried region is located on the first doped region and has a first conductivity type, the second buried region is located on the first buried region and has the first conductivity type, and the doping concentration of the second buried region is less than the doping concentration of the first buried region; the first conductivity type and the second conductivity type are opposite conductivity types; a second doped region, having a second conductivity type, located on the second buried region; Wherein, the junction isolation structure is used to achieve insulation isolation between the substrate and the second doping region.

2. The semiconductor device with an isolation structure according to claim 1, characterized in that: The first doping region has a doping dose not exceeding 3E14cm -2 and / or The thickness of the first doping region is not less than 10 micrometers.

3. The semiconductor device with an isolation structure according to claim 1, characterized in that: The resistivity of the substrate is less than 0.01 Ω·cm.

4. The semiconductor device with an isolation structure according to claim 1, characterized in that: The doping concentration of the first buried region is not less than 1E19 cm -3 , the doping concentration of the second buried region is not higher than 1E17 cm -3 .

5. The semiconductor device with an isolation structure according to claim 1, characterized in that: Also includes: A device body region, located in the second doped region; A lateral isolation structure surrounds the device main region in a lateral direction, and the lateral isolation structure is located in the second doped region and on the second buried region.

6. The semiconductor device with an isolation structure according to claim 5, characterized in that: The lateral isolation structure includes a first conductivity type region; or The lateral isolation structure comprises an insulating material; or The lateral isolation structure includes an insulating layer arranged on the inner wall of the isolation groove, and a conductive structure electrically connected to the second buried area is also provided in the isolation groove. The insulating layer insulates and isolates the conductive structure in the lateral direction, and the conductive structure is used to lead the second buried area to the upper surface of the semiconductor device.

7. The semiconductor device with an isolation structure according to claim 1, characterized in that: The thickness of the second buried region is smaller than the thickness of the first buried region.

8. The semiconductor device with an isolation structure according to any one of claims 1 to 7, characterized in that: The first conductivity type is N type, and the second conductivity type is P type.

9. A method for manufacturing an isolation structure, comprising: Obtaining a substrate, on which a first doping region is formed; The substrate and the first doping region have a second conductivity type, and the doping concentration of the first doping region is less than the doping concentration of the substrate; forming a first buried region on the first doped region, wherein the first buried region has a first conductivity type; forming a second buried region on the first buried region and in direct contact with the first buried region, the second buried region having a first conductivity type and a doping concentration lower than that of the first buried region; A second doped region is formed on the second buried region.

10. The method for manufacturing an isolation structure according to claim 9, characterized in that: The step of forming the first buried region on the first doped region includes: injecting first conductive type ions into the first doped region, and then performing well-driving, the well-driving temperature is above 1000 degrees Celsius, and the time is above 100 minutes.

Images