Power semiconductor device and related method

Abstract

A semiconductor power device includes an active region including a drift region of a first conductivity type; a body region of a second conductivity type, wherein the second conductivity type is opposite to the first conductivity type; a super junction region at least partially disposed between the drift region and the body region, the super junction region including: a first pillar of the first conductivity type, at least a portion of a second pillar of the second conductivity type, the first pillar disposed adjacent to the portion of the second pillar, at least one of: a doping concentration of the first pillar is constant in a direction from the drift region to the body region along the first pillar, and a doping concentration of a portion of the second pillar decreases in a direction from the drift region to the body region along the portion of the second pillar; or a doping concentration of the first pillar increases in a direction from the drift region to the body region along the first pillar, and a doping concentration of a portion of the second pillar is constant in a direction from the drift region to the body region along the portion of the second pillar.

Description

Technical Field

[0001] The present disclosure relates to power semiconductor devices and methods of manufacturing power semiconductor devices. In particular, but not exclusively, the present disclosure relates to super junction (SJ) metal oxide semiconductor field effect transistors (MOSFETs). Background Art

[0002] Power semiconductor devices such as metal oxide semiconductor field effect transistors (MOSFETs) or insulated gate bipolar transistors (IGBTs) require high breakdown voltages. For example, by using multiple thin semiconductor layers in the super junction region to produce charge balance, high breakdown voltage values ​​can be achieved in the active region of the super junction MOSFET. However, when the cell pitch decreases, it may be difficult to improve the quality factor (FOM), which corresponds to the ratio of the breakdown voltage to the specific resistance of the super junction MOSFET. For example, when the cell pitch decreases, the doping concentration in the super junction region of the MOSFET can be increased to reduce the specific resistance. However, this may also result in a reduction in the breakdown voltage, which may be due to the increase in the electric field at the top of the super junction region compared to the electric field at the bottom of the super junction region.

[0003] US 9595596 B2 relates to a power device, US 9024381 B2 relates to a semiconductor device, US 6630698 B1 relates to a high voltage semiconductor component, and US 8283720 B2 relates to a power semiconductor device. Summary of the invention

[0004] Various aspects and preferred features are set out in the appended claims.

[0005] According to a first aspect of the present disclosure, there is provided a semiconductor power device, comprising an active region, wherein the active region comprises:

[0006] a drift region of a first conductivity type;

[0007] a body region of a second conductivity type, wherein the second conductivity type is opposite to the first conductivity type;

[0008] A super junction region, which is at least partially arranged between the drift region and the body region, the super junction region comprising:

[0009] a first pillar of a first conductivity type,

[0010] at least a portion of a second pillar of a second conductivity type, the first pillar being arranged adjacent to the portion of the second pillar, wherein at least one of the following:

[0011] The doping concentration of the first column is constant in a direction from the drift region to the body region along the first column, and the doping concentration of the portion of the second column decreases in a direction from the drift region to the body region along the portion of the second column; or

[0012] A doping concentration of the first column increases in a direction from the drift region to the body region along the first column, and a doping concentration of the portion of the second column is constant in a direction from the drift region to the body region along the portion of the second column.

[0013] By configuring the doping concentration of the first column to be constant in the direction from the drift region to the body region along the first column, and configuring the doping concentration of the portion of the second column to decrease in the direction from the drift region to the body region along the portion of the second column; or, configuring the doping concentration of the first column to increase in the direction from the drift region to the body region along the first column, and configuring the doping concentration of the portion of the second column to be constant in the direction from the drift region to the body region along the portion of the second column, the breakdown voltage of the device can be increased. This in turn can lead to an increase in the ratio of the breakdown voltage to the specific resistance of the device. This ratio can also be referred to as a figure of merit (FOM).

[0014] In addition, the electric field at the top or surface of the active region can be reduced. This can result in a more uniform distribution of the electric field in the active region of the device. The effect of reducing the electric field at the top or surface of the active region can also be referred to as reduced surface field (RESURF).

[0015] In addition, the impact ionization site of the device can be located at the bottom of the super junction region, for example, close to the drift region. This can improve the non-latch-up performance of the device. The improved latch-up performance can in turn lead to a more uniform distribution of the heat generated in the device.

[0016] The doping concentration of the portion of the second column may decrease linearly in a direction from the drift region to the body region along the portion of the second column. Alternatively, the doping concentration of the first column may increase linearly in a direction from the drift region to the body region along the first column.

[0017] The doping concentration of the portion of the second column may gradually decrease in a direction from the drift region to the body region along the portion of the second column. Alternatively, the doping concentration of the first column may gradually increase in a direction from the drift region to the body region along the first column.

[0018] The doping concentration of the portion of the second pillar may decrease in two or more steps. Alternatively, the doping concentration of the first pillar may increase in two or more steps.

[0019] A doping concentration of the first pillar at or near the body region may be greater than, less than, or equal to a doping concentration of the portion of the second pillar at or near the body region.

[0020] The super junction region may include a plurality of first columns and a plurality of second columns. The plurality of first columns and the plurality of second columns may be arranged alternately with each other. The portion of the second column may be a portion of at least one second column in the plurality of second columns or included in at least one second column in the plurality of second columns. Each of the plurality of first columns may be arranged adjacent to at least one of the plurality of second columns. Each of the plurality of first columns may form a pn junction with at least one of the plurality of second columns.

[0021] The semiconductor device may include a metal oxide semiconductor field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT).

[0022] The first column or each of the plurality of first columns may include or define a further drift region.A portion of the second column, the second column or each of the plurality of second columns may include or define a separation region.

[0023] According to a second aspect of the present disclosure, there is provided a method for manufacturing an active region of a semiconductor power device, the method comprising:

[0024] forming a drift region of a first conductivity type on a substrate;

[0025] A super junction region is formed on the drift region, wherein the super junction region comprises:

[0026] a first pillar of a first conductivity type,

[0027] at least a portion of a second pillar of a second conductivity type, the first pillar being arranged adjacent to the portion of the second pillar, wherein at least one of the following:

[0028] The doping concentration of the first column is constant in a direction from the drift region to the body region along the first column, and the doping concentration of the portion of the second column decreases in a direction from the drift region to the body region along the portion of the second column; or

[0029] A doping concentration of the first column increases in a direction from the drift region to the body region along the first column, and a doping concentration of the portion of the second column is constant in a direction from the drift region to the body region along the portion of the second column;

[0030] A body region of a second conductivity type is formed on at least a portion of the super junction region.

[0031] Forming a super junction region may include:

[0032] Perform each of steps (i) to (v) one or more times:

[0033] (i) depositing a semiconductor layer on or over the drift region;

[0034] (ii) forming a first mask on the semiconductor layer, wherein the first mask exposes an upper surface of a first region of the semiconductor layer;

[0035] (iii) selectively doping the first region of the semiconductor layer to form a first region of a first conductivity type;

[0036] (iv) forming a second mask on the semiconductor layer, the second mask exposing an upper surface of a second region of the semiconductor layer, the second region of the semiconductor layer being laterally spaced apart from the first region of the semiconductor layer; and

[0037] (v) selectively doping the second region of the semiconductor layer to form a second region of a second conductivity type.

[0038] In a first iteration, the semiconductor layer may be deposited on the drift region. In one or more subsequent iterations, a subsequent semiconductor layer may be deposited on a previously deposited semiconductor layer.

[0039] When at least one subsequent iteration has been performed, the doping concentration of each first region of the first conductivity type can be the same.When at least one subsequent iteration has been performed, the doping concentration of the second region of the second conductivity type formed in at least one subsequent iteration can be reduced relative to the doping concentration of the second region of the second conductivity type formed in the previous iteration.

[0040] When at least one subsequent iteration has been performed, the doping concentration of each second region of the second conductivity type can be the same.When at least one subsequent iteration has been performed, the doping concentration of the first region of the first conductivity type formed in at least one subsequent iteration can be increased relative to the doping concentration of the first region of the first conductivity type formed in the previous iteration.

[0041] The method may include forming the first pillar, and at least a portion of the second pillar using a diffusion or redistribution process.

[0042] Forming the super junction region may include forming a trench in a semiconductor region of the first conductivity type. The method may include forming a body region before forming the trench. The trench may be formed so that the trench extends through the body region into the semiconductor region. The trench may extend into the semiconductor region in a vertical direction. The trench may be formed so that the trench contacts the body region. The trench may be formed so that the trench contacts the drift region.

[0043] A portion of the semiconductor region adjacent to the trench may form a first pillar. Forming the super junction region may include filling the trench with a semiconductor material of the second conductivity type to form at least a portion of a second pillar.

[0044] According to a third aspect of the present disclosure, there is provided a method of manufacturing a semiconductor power device, comprising manufacturing an active region of the semiconductor power device according to the second aspect.

[0045] The device and manufacturing method of the present disclosure have one or more of the following advantages over prior art devices:

[0046] - the device may have an increased breakdown voltage and an increased quality factor;

[0047] - The electric field distribution in the active area can be improved;

[0048] -Can improve the reduced surface field (RESURF) effect;

[0049] - The non-latching performance of the device can be improved;

[0050] - the distribution of heat generated in the active area of ​​the device can be more uniform;

[0051] - The manufacturing steps may be compatible with existing MOSFET and / or IGBT manufacturing processes and / or may be performed using materials and processing equipment commonly available in MOSFET and / or IGBT manufacturing plants. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Some embodiments of the present disclosure will now be described, by way of example only, and with reference to the accompanying drawings, in which:

[0053] Figure 1 schematically shows a cross section of an active region of a semiconductor device;

[0054] Figure 2 Schematically shows Figure 1 The cross-section of one half of the unit cell of the device;

[0055] Figure 3 (a) to Figure 3 (f) schematically shows a method for forming Figure 1 and Figure 2Different exemplary distributions of dopant doses for a first column and a second column of a device;

[0056] Figure 4 An exemplary semiconductor power device that has been used Figure 3 (a) The distribution of n-type dopant and p-type dopant implantation doses for simulation of effective charge carrier concentrations;

[0057] Figure 5 Shows that it has been targeted Figure 3 (a) to Figure 3 (f) a graph of drain-source current curves versus breakdown voltage for each of the simulated n-type dopant and p-type dopant implant dose profiles;

[0058] Figure 6 Shows Figure 1 and Figure 2 The device has been targeted Figure 3 (a) to Figure 3 (f) a graph of a simulated electric field curve of each of the n-type dopant and p-type dopant implant dose profiles relative to the distance between the drain contact and the source contact;

[0059] Figure 7 Shows that it has been targeted Figure 3 (a) to Figure 3 (f) comparison between the breakdown voltage, specific resistance and quality factor simulated for each of the n-type dopant and p-type dopant implantation dose profiles;

[0060] Figure 8 (a) to Figure 8 (f) shows that Figure 3 (a) to Figure 3 (f) simulation of the impact ionization position of each of the n-type dopant and p-type dopant implantation dose profiles;

[0061] Fig. 9 (a) to (f) of FIG. 9 respectively show the embodiment of the present disclosure. Figure 1 and Figure 2 exemplary n-type dopant concentrations and p-type dopant concentrations of the first column and the second column of the device;

[0062] Fig.10 (a) to Fig.10 (f) respectively show the embodiments according to the present disclosure Figure 1 and Figure 2 exemplary n-type dopant concentrations and p-type dopant concentrations of the first column and the second column of the device;

[0063] Fig.11(a) to Fig.11 (f) shows the steps of a method for manufacturing an active region of a semiconductor power device according to an embodiment of the present disclosure;

[0064] Fig.12 (a) to Fig.12 (k) shows steps of another method for manufacturing an active region of a semiconductor power device according to an embodiment of the present disclosure; and

[0065] Fig.13 Schematically shows the use of Fig.12 (a) to Fig.12 (k) A cross section of a super junction region formed by one or more steps of the method. DETAILED DESCRIPTION

[0066] Figure 1 and Figure 2 A cross section of an active region 105 of a semiconductor device 100 is schematically shown. Figure 1 The active region 105 shown in can be considered as a unit cell, which can be repeated thousands of times in the device 100 . Figure 2 The active region 105 shown can be considered as Figure 1 Half of the unit cell shown. In the examples described herein, the device 100 is a silicon-based superjunction MOSFET. However, it will be understood that the device may include one or more alternative semiconductor materials. For example, the device may alternatively be based on silicon carbide (SiC) or based on gallium nitride (GaN).

[0067] The active region 105 includes a substrate 110 of a first conductivity type. The substrate 110 may include an n-type doped semiconductor material, such as n + The n-type dopant concentration of the substrate 110 may be greater than about 5×10 18 cm -3 The substrate 110 is conductive and serves as a drain region. The thickness of the substrate may be between about 40 μm and about 100 μm.

[0068] The active region 105 includes a drift region 115 disposed on the substrate 110. The drift region 115 includes an n-type doped semiconductor material, such as n-type doped silicon. The n-type dopant concentration of the drift region 115 may be about 5×10 14 cm -3 and 5×10 17 cm -3 between, for example, about 7×10 15 cm -3. Drift region 115 may also be referred to as an n-drift region, an n-type buffer region, or an n-type voltage sustaining region. Drift region 115 is formed on or over semiconductor substrate 110. In this embodiment, drift region 115 includes one or more epitaxial layers and has a thickness of approximately 15 μm. However, it will be understood that in other embodiments, the drift region may have a thickness greater than or less than 15 μm.

[0069] The drain contact 110a may be arranged on the lower side of the substrate 110, for example, on the side of the substrate 110 opposite to the drift region 110. The drain contact 110a may include a conductive material, such as a metal material. The metal material may include a metal alloy, such as titanium nickel silver or other metal alloys.

[0070] The active region 105 includes a body region 120 of a second conductivity type. The second conductivity type is opposite to the first conductivity type. Figure 1 and Figure 2 In the illustrated embodiment, the body region 120 includes a p-type semiconductor material.

[0071] The active region 105 includes a super junction region 125. The super junction region 125 is arranged between the drift region 115 and the body region 120. The super junction region 125 includes a plurality of first columns 125a of a first conductivity type and a plurality of second columns 125b of a second conductivity type. In this embodiment, each first column 125a is an n-type column, and each second column 125b is a p-type column. The first column 125a may define an additional drift region. The second column 125b may define a separation region. The first column 125a and the second column 125b are alternately arranged and contact each other. For example, each first column 125a is arranged between two adjacent second columns 125b. For example, in Figure 1 In the unit cell shown, the super junction region 125 includes two portions of a first pillar 125a and two corresponding second pillars 125b. The first pillar 125a is arranged between the two portions of the second pillar 125b. Figure 2 In the half of the unit cell shown, the super junction region includes a portion of the first column 125a and a portion of the second column 125b. A portion of the first column 125a and a portion of the second column 125b are arranged adjacent to each other. This arrangement results in a parallel pn junction extending in a vertical direction between the drift region 115 and the body region 120. The super junction region 125 may also be referred to as a pn junction region.

[0072] In this embodiment, the width of each of the first pillar 125a and the second pillar 125b can be about 3.5 μm. The height of each of the first pillar 125a and the second pillar 125b can be between about 3 μm and 6 μm. However, it will be understood that the first pillar and the second pillar are not limited to having the exemplary heights and / or widths disclosed herein.

[0073] The active region 105 includes an n-type doped JFET region 130. The JFET region is arranged above the first pillar 125a. The JFET region 130 is arranged to extend from the first pillar to the upper surface of the body region 120. The body region 120 is arranged on either side of the JFET region 130.

[0074] The active region 105 includes a gate conductive region 135. The gate conductive region 135 is located above the JFET region 130 and the body region 120. The gate conductive region 135 is used to control a conductive channel in the active region 105.

[0075] The active region 105 includes a first insulating region 140a. The first insulating region 140a is disposed between the JFET region 130 and the gate conductive region 135. The first insulating region 140a may extend along a side of the gate conductive region 135. The first insulating region may be referred to as a gate oxide region 140a.

[0076] Active region 105 includes second insulating region 140b. Second insulating region 140b is disposed on or over gate conductive region 135 and gate oxide region 140a. Second insulating region may also be referred to as interlayer dielectric layer 140b.

[0077] The device 100 includes a source contact region, in this example an n+ source contact region 145. The n+ source contact region 145 is arranged on either side of the JFET region 130 and below the gate oxide region 140a. During operation, by applying a positive voltage to the gate conductive region 135, a conductive channel is formed between the n+ source contact region 145 and the drift region 115.

[0078] The body region 120 includes contact regions, which in this example include p+ contact regions 150 . The p+ contact regions 150 are formed on either side of the JFET region 130 and are adjacent to corresponding n+ source contact regions 145 .

[0079] The device 100 includes a source contact 155. The source contact 155 may include a conductive material, such as a metal material. The metal material may include aluminum, tungsten, titanium, or a combination thereof. The source contact 155 is located on the upper surface of the device. For example, the source contact 155 may be arranged on or above the interlayer dielectric layer 140b. The source contact 155 may also be arranged to contact the n+ source contact region 145 and the p+ contact region 150.

[0080] exist Figure 1 In the embodiment shown, the lateral extension or width of the unit cells of device 100 is about 7 μm. However, it will be appreciated that in other embodiments, the lateral extension or cell pitch may be greater or less than 7 μm. The lateral extension or width of the unit cells of a device may also be referred to as the cell pitch.

[0081] Figure 3 (a) to Figure 3 (f) schematically shows different exemplary distributions of dopant doses that can be used to form the first pillar 125a and the second pillar 125b. As will be described in more detail below, the first pillar 125a and the second pillar 125b can be formed by implanting n-type dopants and p-type dopants in a plurality of semiconductor layers, respectively. Figure 3 (a) to Figure 3 In (f), the semiconductor layer 157 is indicated by reference numeral 157. The semiconductor layer 157 may also be referred to as an epitaxial layer. Each of the semiconductor layers may have a thickness of about 6 μm. However, it should be understood that in other embodiments, the thickness of each semiconductor layer may be greater or less than 6 μm.

[0082] The n-type dopant dose is indicated by reference numeral 160a, and the p-type dopant dose is indicated by reference numeral 160b. Figure 3 (a) to Figure 3 Only the drift region 115 and the body region 120 are shown in (f).

[0083] exist Figure 3 (a) to Figure 3 In the example shown in (f), the first pillar 125a and the second pillar 125b are formed of six semiconductor layers 157. However, it will be understood that in other embodiments, the first pillar and the second pillar may be formed of more or less than six semiconductor layers.

[0084] exist Figure 3 In the example shown in (a), each of the semiconductor layers 157 is implanted with the same dose of p-type dopant and n-type dopant. For example, the implantation dose of the p-type dopant 160b and the n-type dopant 160a may be about 1.1×10 13 cm -2 .

[0085] In this way, the doping concentration of each of the first column 125a and the second column 125b is constant in a direction along each of the first column 125a and the second column 125b from the drift region 115 to the body region 120. The term "along the direction of the first column / the second column" may be understood to encompass the term "a direction parallel to the longitudinal axis of the first column / the second column". The direction along the first column / the second column may also be referred to as a vertical direction.

[0086] exist Figure 3 In the example shown in (b), the p-type dopant dose 160b of the semiconductor layer 157 adjacent to the drift region 115 is higher than the p-type dopant of the remaining semiconductor layers 157. In this way, a p-type dopant-enriched region 160c is formed in the second column 125b near the drift region 115. For example, the p-type dopant dose of the enriched region 160c may be about 1.2×10 13 cm-2 The p-type dopant dosage of each of the remaining semiconductor layers 157 may be about 1.1×10 13 cm -2 The n-type dopant dose 160a is the same for each semiconductor layer 157. For example, for each semiconductor layer 157, the n-type dopant dose is about 1.1×10 13 cm -2 The doping concentration of the first pillar 125 a is constant in a direction from the drift region 115 to the body region 120 along the first pillar 125 a .

[0087] exist Figure 3 In the example shown in (c), the p-type dopant dose 160b varies across the semiconductor layer 157 in the direction from the drift region 115 to the body region 120. In this example, the p-type dopant dose gradually decreases and then gradually increases in the direction from the drift region 115 to the body region 120. For example, the p-type dopant dose increases from about 1.16×10 13 cm -2 Reduced to about 1.11×10 13 cm -2 , and then from about 1.11×10 13 cm -2 Increased to about 1.16×10 13 cm -2 For each semiconductor layer 157, the n-type dopant dose 160a is the same. For example, for each semiconductor layer 157, the n-type dopant dose 160a is approximately 1.1×10 13 cm -2 .

[0088] exist Figure 3 In the example shown in (d) of FIG. 1 , the p-type dopant dose 160 b varies across the semiconductor layer 157 in a direction from the drift region 115 to the body region 120. In this example, the p-type dopant dose 160 b gradually increases in a direction from the drift region 115 to the body region 120. For example, the p-type dopant dose increases from about 1.07×10 13 cm -2 Increased to about 1.12×10 13 cm -2 For each semiconductor layer 157, the n-type dopant dose 160a is the same. For example, for each semiconductor layer 157, the n-type dopant dose 160a is approximately 1.1×10 13 cm -2 .

[0089] exist Figure 3In the example shown in (e) of FIG. 1 , the n-type dopant dose 160 a and the p-type dopant dose 160 b vary across the semiconductor layer 157 in the direction from the drift region 115 to the body region 120. In this example, the n-type dopant dose 160 a and the p-type dopant dose 160 b simultaneously increase and then decrease in the direction from the drift region 115 to the body region 120. For example, the n-type dopant dose 160 a and the p-type dopant dose 160 b simultaneously increase from approximately 1.1×10 13 cm -2 Increased to about 1.16×10 13 cm -2 , and then reduced to about 1.05×10 13 cm -2 .

[0090] Figure 3 (f) shows n-type dopant and p-type dopant implantation doses 160a, 160b according to an embodiment of the present disclosure. Figure 3 In (f), the p-type dopant dose 160b varies across the semiconductor layer 157 in a direction from the drift region 115 to the body region 120. For example, the p-type dopant dose 160b decreases in a direction from the drift region 115 to the body region 120. The p-type dopant dose 160b may be increased from about 1.16×10 13 cm -2 Reduced to about 1.09×10 13 cm -2 .

[0093] The n-type dopant dose 160a is the same for each semiconductor layer 157. The n-type dopant dose may be approximately 1.1×10 13 cm -2 It will be appreciated that in other embodiments, the n-type dopant dose may vary across the semiconductor layer and the p-type dopant dose may be constant. In such other embodiments, the n-type dopant dose may increase in the direction from the drift region to the body region, for example, from about 1.05×10 13 cm -2 Increased to 1.11×10 13 cm -2 In such other embodiments, the p-type dopant dosage may be the same for each semiconductor layer. For example, the p-type dopant dosage may be approximately 1.1×10 13 cm -2 .

[0094] The implantation energy for implanting the p-type dopant in the above example may be between about 100 KeV and 850 KeV. The implantation energy for implanting the n-type dopant in the above example may be between about 140 KeV and 950 KeV.

[0095] Figure 4 It is shown that the semiconductor power device has been used in an exemplary Figure 3 The distribution of the n-type dopant implantation dose and the p-type dopant implantation dose described in (a) is simulated for the effective charge carrier concentration. In other words, as for Figure 3 As described in (a), the n-type dopant concentration and the p-type dopant concentration of the first pillar and the second pillar are respectively assumed to be constant from the drift region to the body region in the direction along the first pillar and the second pillar.

[0096] Figure 5 A graph of simulated drain-source current curves versus breakdown voltage is shown. Using the parameters of the device 100 described herein, a simulation of Figure 3 (a) to Figure 3 (f) The n-type dopant and p-type dopant implantation dose distributions in each simulation Figure 5 The curve shown in .

[0097] from Figure 5 It can be seen that for Figure 3 The device 100 with the n-type dopant and p-type dopant implantation doses described in (f) has simulated the highest breakdown voltage. In other words, by configuring the device 100 to have a first column 125a having a constant n-type dopant concentration in the direction from the drift region 115 to the body region 120 along the first column 125a and at least a portion of the second column 125b having a p-type dopant concentration that decreases in the direction from the drift region 115 to the body region 120 along the second column 125b, the breakdown voltage of the device 100 can be increased. This in turn leads to an increase in the ratio of the breakdown voltage to the specific resistance of the device 100. This ratio can also be referred to as a figure of merit (FOM).

[0098] In addition, by configuring the device 100 to have a first pillar 125a having a constant n-type dopant concentration in a direction along the first pillar 125a from the drift region 115 to the body region 120 and at least a portion of the second pillar 125b having a p-type dopant concentration that decreases in a direction along the second pillar 125b from the drift region 115 to the body region 120, the electric field at the top of the active region 105 can be reduced, resulting in a more uniform distribution of the electric field in the active region 105 of the device 100. The reduced effect of the electric field at the top of the active region 105 may also be referred to as a reduced surface field (RESURF).

[0099] Figure 6Graph showing the electric field curve versus the distance X between the drain contact and the source contact of the device. Using the parameters of the device 100 described herein, for Figure 3 (a) to Figure 3 Each of the n-type dopant and p-type dopant implantation dose profiles described in (f) simulates Figure 6 The curve shown. Figure 6 It can be seen that Figure 3 (a) to Figure 3 Compared with the simulated electric field curves of the device with n-type dopant and p-type dopant implantation dose distributions described in (e), for the device with Figure 3 In the device 100 with the n-type dopant and p-type dopant implantation doses described in (f), the electric field is more evenly distributed between the source contact 155 and the drain contact 110a. Figure 6 It can be seen that Figure 3 (a) Figure 3 (b) Figure 3 (d) and Figure 3 The simulated electric field curves for the device with n-type dopant and p-type dopant implantation dose profiles described in (e) are compared to those for the device with Figure 3 The device 100 with the n-type dopant and p-type dopant implantation doses described in (f) has a reduced electric field near the source contact 155. Figure 3 The simulated electric field of the device with the n-type dopant and p-type dopant implantation dose profile of (c) is reduced, but with Figure 3 It is even smaller in the rest of the active region compared to the simulated electric field of the device 100 described in (f) with n-type dopant and p-type dopant implant dosages.

[0100] For those with Figure 3 (a) and Figure 3 The simulated electric field curves for the device with the n-type dopant and p-type dopant implantation dose profiles described in (e) are very similar. It can be seen that the simulated electric field for these n-type dopant and p-type dopant implantation dose profiles decreases towards the drain contact. Figure 3 (b) and Figure 3 The simulated electric field curves for the device with the n-type dopant and p-type dopant implantation dose distributions described in (d) are compared with those for the device with the n-type dopant and p-type dopant implantation dose distributions described in (d). Figure 3 (a) and Figure 3 The electric field curves simulated for the device with the n-type dopant and p-type dopant implantation dose profiles described in (e) are similar. Figure 3The simulated electric field curve of the device with the n-type dopant and p-type dopant implant dose profiles described in (b) increases near the drain contact, while the electric field curves for the devices with about Figure 3 The simulated electric field curve of the device with the n-type dopant and p-type dopant implant dose profile described in (d) decreases near the drain contact. Compared with the electric field curves of other devices, the electric field curves for the device with about Figure 3 The simulated electric field curve of the device of (c) for the n-type dopant and p-type dopant implantation dose profiles decreases near the source contact.

[0101] Figure 7 Parameters for using the apparatus disclosed herein are shown for Figure 3 (a) to Figure 3 Comparison of the simulated breakdown voltage, specific resistance and quality factor for each of the n-type dopant and p-type dopant implantation dose profiles described in (f).

[0102] Specific resistance R sp as follows:

[0103]

[0104] Where W pitch is the width of the unit cell, V B is the breakdown voltage, μ is the electron mobility, ε S is the permittivity of silicon, E C is the critical electric field. As mentioned above, the quality factor corresponds to the ratio V B / R sp .

[0105] from Figure 7 It can be seen that the breakdown voltage is changed from the Figure 3 The n-type dopant and p-type dopant implant dose profiles described in (a) are increased from about 543.7 V for devices having the following configurations: Figure 3 The specific resistance of the device is 694V for the n-type dopant and p-type dopant implantation dose distribution described in (f). Figure 3 (a) The n-type dopant and p-type dopant implant dose profiles of the device are 9.6 MΩ·cm 2 Increase to target Figure 3 (f) The n-type dopant and p-type dopant implant dose profiles of the device are 9.9 MΩ·cm 2 However, the quality factor has evolved from targeting Figure 3 56.6 of the device having the n-type dopant and p-type dopant implantation dose profiles described in (a) is increased to for devices having the n-type dopant and p-type dopant implantation dose profiles described in (a) as for Figure 3(f) describes the n-type dopant and p-type dopant implant dose profiles of the device 70.1.

[0106] Figure 8 8(a) to 8(f) show simulations of the impact ionization location 165. Using the parameters of the apparatus 100 described herein, the impact ionization location 165 has been simulated for the impact ionization location 165. Figure 3 (a) to Figure 3 Each of the n-type dopant and p-type dopant implant dose profiles described in (f) is simulated Figure 8 The impact ionization position 165 shown in (a) to (f) of FIG8. The impact ionization position 165 can be considered as the position where the breakdown occurs. Figure 8 (a) Figure 8 (b) Figure 8 (d) and Figure 8 It can be seen from (e) that for Figure 3 (a) Figure 3 (b) Figure 3 (d) and Figure 3 The simulated impact ionization position 165 is located at or near the body region 120. Figure 3 The device with the n-type dopant and p-type dopant implantation dose distribution described in (c) is provided with the impact ionization position 165 being close to the center of the super junction region 125. Figure 3 The device with the n-type dopant and p-type dopant implantation dose profiles described in (f) of FIG. 1 , the impact ionization location 165 is at the bottom of the super junction region 125. For example, for a device having a Figure 3 In the device of the n-type dopant and p-type dopant implantation dose profile described in (f), the impact ionization position 165 is close to the drift region 115. This can result in a device having a Figure 3 The improved non-latch-up performance of the device 100 with the n-type dopant and p-type dopant implant dose profiles described in (f) of FIG. Latch-up can be understood as creating a low impedance path between regions of the device 100, which triggers the conduction of the parasitic npn bipolar transistor structure between the source contact region 145, the body region 120 and the first pillar 125 or the drain region 115. Figure 3 (a) to Figure 3 The improved latch-up performance may in turn result in a more uniform distribution of heat generated in the device 100 compared to a device having the n-type dopant and p-type dopant implant dose profiles described in (e).

[0107] Fig. 9 (a) to Fig. 9(f) shows exemplary n-type dopant concentrations and p-type dopant concentrations of the first pillar 125a and the second pillar 125b, respectively, according to an embodiment of the present disclosure. Fig. 9 In the examples shown in (a) to (f) of FIG9 , the concentration of the n-type dopant of the first pillar 125 a is constant in the direction X from the drift region 115 to the body region 120 along the first pillar 125 a. The concentration of the p-type dopant of the second pillar decreases in the direction X from the drift region 115 to the body region 120 along the second pillar 125 b.

[0108] In some embodiments, Fig. 9 (a) and Fig. 9 As shown in (c), the p-type dopant concentration of the second pillar 125 b at or near the body region 120 is less than the n-type dopant concentration of the first pillar 125 a.

[0109] In some embodiments, Fig. 9 (b) and Fig. 9 As shown in (d), the p-type dopant concentration of the second pillar 125 b at or near the body region 120 is greater than the n-type dopant concentration of the first pillar 125 a.

[0110] In some embodiments, Fig. 9 (e) and Fig. 9 As shown in (f), the p-type dopant concentration of the second pillar 125 b at or near the body region 120 may be the same as the n-type dopant concentration of the first pillar 125 a .

[0111] In some embodiments, Fig. 9 (a) Fig. 9 (b) and Fig. 9 As shown in (e), the p-type dopant concentration of the second pillar 125 b decreases linearly in the direction X from the drift region 115 to the body region 120 along the second pillar 125 b.

[0112] In some embodiments, Fig. 9 (c) Fig. 9 (d) and Fig. 9 As shown in (f), the p-type dopant concentration of the second pillar 125b gradually decreases in the direction X from the drift region 115 to the body region 120 along the second pillar 125b. Fig. 9 (c) Fig. 9 (d) and Fig. 9 In the example shown in (f) of FIG. 1 , the p-type dopant concentration of the second pillar 125 b decreases in three steps in the direction X along the second pillar 125 b from the drift region 115 to the body region 120. However, it will be understood that in other embodiments, the p-type dopant concentration may decrease in more than three steps or at least two steps in the direction along the second pillar from the drift region to the body region.

[0113] Fig.10 (a) to Fig.10 (f) shows exemplary n-type dopant concentrations and p-type dopant concentrations of the first pillar 125a and the second pillar 125b, respectively, according to an embodiment of the present disclosure. Fig.10 (a) to Fig.10 In the example shown in (f), the concentration of the p-type dopant of the second pillar 125b is constant in the direction X from the drift region 115 to the body region 120 along the second pillar 125b. The concentration of the n-type dopant of the first pillar 125a increases in the direction X from the drift region 115 to the body region 120 along the first pillar 125a.

[0114] In some embodiments, Fig.10 (a) and Fig.10 As shown in (c), the p-type dopant concentration of the second pillar 125 b at or near the body region 120 is lower than the n-type dopant concentration of the first pillar 125 a.

[0115] In some embodiments, Fig.10 (b) and Fig.10 As shown in (d), the p-type dopant concentration of the second pillar 125 b at or near the body region 120 is greater than the n-type dopant concentration of the first pillar 125 a.

[0116] In some embodiments, Fig.10 (e) and Fig.10 As shown in (f), the p-type dopant concentration of the second pillar 125 b at or near the body region 120 may be the same as the n-type dopant concentration of the first pillar 125 a .

[0117] In some embodiments, Fig.10 (a) Fig.10 (b) and Fig.10 As shown in (e) of FIG. 1 , the n-type dopant concentration of the first pillar 125 a increases linearly in the direction X from the drift region 115 to the body region 120 along the first pillar 125 a .

[0118] In some embodiments, Fig.10 (c) Fig.10 (d) and Fig.10 As shown in (f) of FIG. 1 , the n-type dopant concentration of the first pillar 125 a gradually increases in the direction X from the drift region 115 to the body region 120 along the first pillar 125 a. Fig.10 (c) Fig.10 (d) and Fig.10In the example shown in (f) of FIG. 1 , the n-type dopant concentration of the first pillar 125 a increases in three steps in the direction X along the first pillar 125 a from the drift region 115 to the body region 120. However, it will be understood that in other embodiments, the n-type dopant concentration may increase in more than three steps or at least two steps in the direction from the drift region to the body region.

[0119] Fig.11 (a) to Fig.11 (f) shows the steps of a method of manufacturing an active region of a semiconductor power device (eg, active region 105 of device 100 described above) according to an embodiment of the present disclosure. Many features are similar to Figure 1 and Figure 2 Those features shown in FIG. 1 are identical and therefore bear the same reference numerals. It should be understood that Fig.11 (a) to Fig.11 The steps shown in (f) may show a subset of all the steps for manufacturing the device, and the method may also include Fig.11 (a) to Fig.11 The additional step may be performed before or after the step (f). Fig.11 (a) to Fig.11 (f) shows the step of manufacturing an active area having one first pillar 125a and two second pillars 125b, but it will be understood that the method can be used to manufacture an active area including more than one first pillar and more than two second pillars.

[0120] In step (a), the method includes forming a drift region 115 on a substrate 110. The drift region 115 may be formed on the substrate 110 using a deposition process.

[0121] In step (b) to step (e), the method includes forming a super junction region 125 on the drift region 115. Step (b) to step (c) may be performed multiple times in sequence. Fig.11 In the example shown, steps (b) and (c) are performed six times. However, it will be appreciated that these steps may be performed more or less than six times.

[0122] In step (b), the method includes depositing a semiconductor layer 157 on or over the drift region 115. The semiconductor layer 157 may be deposited using a deposition process. The method includes forming a first mask 170 on the semiconductor layer 157. The step of forming the first mask 170 on the semiconductor layer 157 may include depositing a layer of a mask material, such as a layer of a resist or photoresist material, on the semiconductor layer 157. The step of forming the first mask 170 on the semiconductor layer 157 may include patterning the layer of the mask material. This may include exposing a portion of the layer of the mask material. The step of forming the first mask 170 on the semiconductor layer 157 may include developing the layer of the mask material. A material removal process, such as an etching process, may be used to remove the exposed portion of the layer of the mask material, thereby forming the first mask 170.

[0123] The first mask 170 exposes the upper surface of the first region of the semiconductor layer 157. The exposed upper surface of the first region of the semiconductor layer 157 may have a width of about 2.6 μm. The exposed upper surface of the first region of the semiconductor layer 157 may also be referred to as an opening of the first mask 170. It should be understood that in other embodiments, the width of the exposed upper surface of the first region of the semiconductor layer may be greater than or less than 2.6 μm.

[0124] The method includes selectively doping the first region of the semiconductor layer 157 by implanting an n-type dopant. The n-type dopant may include phosphorus, arsenic, or other n-type dopants. The n-type dopant dose is Fig.11 Indicated by reference numeral 160a.

[0125] In step (c), the method includes forming a second mask 175 on the semiconductor layer 157. The second mask 175 can be formed in the same manner as the first mask 170. The second mask 175 exposes the upper surface of the second region of the semiconductor layer 157. The second region of the semiconductor layer 157 is laterally spaced from the first region of the semiconductor layer 157. The exposed upper surface of the second region of the semiconductor layer 157 can have a width of about 2.6 μm. The exposed upper surface of the second region of the semiconductor layer 157 can also be referred to as an opening of the second mask 175. It should be understood that in other embodiments, the width of the exposed upper surface of the second region of the semiconductor layer can be greater than or less than 2.6 μm.

[0126] The method includes selectively doping the second region of the semiconductor layer 157 by implanting a p-type dopant. The p-type dopant may include boron, boron difluoride, or other p-type dopants. The p-type dopant dose is Fig.11 Indicated by reference numeral 160b.

[0127] The first and second regions of the semiconductor layer 157 may be implanted using an implantation process such as vapor diffusion or other implantation processes. The implantation energy for implanting the p-type dopant may be between about 100 KeV and 850 KeV. The implantation energy for implanting the n-type dopant in the above example may be between about 140 KeV and 950 KeV. The implantation depth of the n-type dopant and the p-type dopant may be between about 0.5 μm and about 1.7 μm.

[0128] In step (d), the method includes repeating step (b) and step (c). In this example, step (b) and step (c) are repeated six times. The number of repetitions of step (b) and step (c) may depend on the desired or expected breakdown voltage of the device 100. In the embodiment shown herein, the desired or expected breakdown voltage is about 600V. However, it should be understood that in other embodiments, the desired or expected breakdown voltage of the device may be greater than or less than 600V. In such other embodiments, step (b) and step (c) may be repeated more or less than six times.

[0129] Each time step (b) is performed, a subsequent semiconductor layer 157 is deposited on the previously deposited semiconductor layer 157 .

[0130] Each time step (b) is performed, the first mask 170 exposes the same first region of the subsequent semiconductor layer 157 as in one or more previous repetitions of step (b). Each time step (c) is performed, the second mask 175 exposes the same second region of the subsequent semiconductor layer 157 as in one or more previous repetitions of step (c). The order of n-type doping or p-type doping may be changed.

[0131] The semiconductor layer 157 is doped with a p-type dopant dose ranging from about 1.16×10 13 cm -2 Reduced to about 1.09×10 13 cm -2 The n-type dopant dose 160a is the same for each semiconductor layer 157. The n-type dopant dose may be approximately 1.1×10 13 cm -2 It will be appreciated that in other embodiments, the n-type dopant dose may vary across the semiconductor layer and the p-type dopant dose may be constant. In such other embodiments, the n-type dopant dose may increase in the direction from the drift region to the body region, for example, from about 1.05×10 13 cm -2 Increased to 1.11×10 13 cm -2In such other embodiments, the p-type dopant dosage may be the same for each semiconductor layer. For example, the p-type dopant dosage may be approximately 1.1×10 13 cm -2 .

[0132] In step (e), the method may include forming the first column 125a and the second column 125b. For example, the method may include forming the first column 125a and the second column 125b using a diffusion or redistribution process. The diffusion or redistribution process may include a drive-in process to further diffuse or redistribute the dopant, thereby forming the first column 125a and the second column 125b. For example, the diffusion or redistribution process may be used to connect the first column 125a and the second column 125b to each other.

[0133] The diffusion length of n-type dopants and p-type dopants during the initial gas phase diffusion is generally shorter than the diffusion length of n-type dopants and p-type dopants during the drive-in process. Therefore, the drive-in process causes the n-type dopants and p-type dopants to diffuse further into the semiconductor layer 157. During the drive-in process, the temperature of the substrate 110, the drift region 115, and the semiconductor layer 157 increases to, for example, about 1125° C. for about 10 hours. The drive-in process causes the n-type dopants and p-type dopants on the surface of the semiconductor layer 157 to diffuse further into the semiconductor layer 157, thereby forming the first pillar 125 a and the second pillar 125 b. This in turn results in the formation of the super junction region 125.

[0134] In step (e), the method includes depositing another semiconductor layer 180 on the super junction region 125, for example using a deposition process. The other semiconductor layer 180 may have a thickness of about 2 μm. However, it will be understood that in other embodiments, the other semiconductor layer may have a thickness greater than or less than 2 μm. The other semiconductor layer 180 may also be referred to as a cap layer.

[0135] In step (f), the method includes forming a third mask on another semiconductor layer 180. The third mask exposes a region of another semiconductor layer 180 located above the first pillar 125a. The third mask may be formed in the same manner as the first mask 170 and the second mask 175 described above.

[0136] In step (f), the method includes forming a JFET region 130. The JFET region 130 may be formed by doping the exposed region of the further semiconductor layer 180 with an n-type dopant, for example, using the above-described implantation process. The n-type dopant may include one or more of the exemplary n-type dopants described above.

[0137] In step (f), the method further includes forming a gate oxide region 140a over the JFET region 130. The gate oxide region 140a may include a thin oxide layer, such as silicon dioxide, which may be deposited or thermally grown.

[0138] In step (f), the method further includes forming a gate conductive region 135. The method includes, for example, depositing a layer of conductive material on the gate oxide region 140a and over the JFET region 130 using a deposition process. The conductive material may include a doped semiconductor material, such as doped polysilicon. The gate conductive region 135 may be formed using a material removal process such as a dry etching process or a wet etching process. For example, a mask may be used to etch the layer of conductive material so that the layer extends over the JFET region 130 to the source contact region 145.

[0139] In step (f), the method further includes forming a body region 120. For example, a p-type dopant may be implanted on the upper surface of the other semiconductor layer 180 so that the p-type body region 120 is formed on either side of the JFET region 130. The p-type dopant may be implanted using a blank implantation process. After the p-type dopant is implanted, a diffusion or redistribution process including a drive-in process is performed to further diffuse or redistribute the p-type dopant in the body region 120. During the drive-in process, the temperature of the substrate 110, the drift region 115, the super junction region 125, and the other semiconductor layer 180 is increased to, for example, about 1125° C. for about 100 minutes. The drive-in process causes the p-type dopant on the surface of the other semiconductor layer 180 to further diffuse into the other semiconductor layer 180, thereby forming the body region 120.

[0140] In step (f), the method further includes forming source contact regions 145. For example, n-type dopants may be implanted on either side of the body region 120 to form the source contact regions 145. The n-type dopant concentration of each of the source contact regions 145 may be greater than 5×10 18 cm -3 The n-type dopant may include one or more of the above exemplary n-type dopants. The n-type dopant may be implanted using a blank implantation process.

[0141] In step (f), the method further includes forming an interlayer dielectric (ILD) layer 140b. For example, the interlayer dielectric layer 140b can be formed by depositing a layer of insulating material on or above the gate conductive region 135, for example, using a deposition process. The layer of insulating material can include an oxide material, such as TEOS (tetraethyl orthosilicate). The interlayer dielectric layer 140b can also be deposited on or above the gate oxide region 140a.

[0142] In step (f), the method further includes forming p+ contact regions 150. The method includes, for example, forming contact openings or recesses on either side of the gate conductive region 135 using a material removal process. For example, the contact openings or recesses may be formed by etching through the interlayer dielectric layer 140b and the gate oxide region 140a. A p-type dopant may be implanted under each contact opening or recess to form the p+ contact region 150. The p-type dopant concentration of the p+ contact region 150 may be greater than 5×10 18 cm -3 The p-type dopant may include one or more of the exemplary p-type dopants described above. The p-type dopant may be implanted using a blank implantation process.

[0143] In step (f), the method further includes forming source contact 155. For example, source contact 155 may be formed by depositing a layer of conductive material into each contact opening or recess and on or over interlayer dielectric layer 140b, such that source contact 155 contacts source contact region 145 and p+ contact region 150.

[0144] In step (f), the method further includes forming a drain contact 110a. For example, the drain contact 110a may be formed by grinding or planarizing the lower surface of the substrate 110 and depositing a layer of a conductive material thereon. The layer of conductive material may be deposited on the lower surface of the substrate 110 using a deposition process such as an evaporation process.

[0145] Fig.12 (a) to Fig.12 (k) shows the steps of another method of manufacturing an active region of a semiconductor power device (such as the active region 105 of the device 100 described above) according to an embodiment of the present disclosure. Many features are similar to Figure 1 and Figure 2 Those features shown in FIG. 1 are identical and therefore bear the same reference numerals. It should be understood that Fig.12 (a) to Fig.12 The steps shown in (k) may show a subset of all the steps for manufacturing the device, and the method may also include Fig.12 (a) to Fig.12 The additional step before or after the step (k). Fig.12 (a) to Fig.12 (k) shows the step of manufacturing an active area having two first pillars 125a and one second pillar 125b, but it will be understood that the method can be used to manufacture an active area including more than two first pillars and more than one second pillar. Fig.12 (a) to Fig.12(k) shows the formation of half a unit cell of the device 100. However, it will be understood that any of the steps and / or features described below may also be applied to the formation of a unit cell of the device 100 or more than one unit cell of the device 100.

[0146] Below about Fig.12 (a) to Fig.12 (k) One or more steps of the method described above with respect to Fig.11 (a) to Fig.11 One or more steps of the method described in (f) are the same or similar. Fig.11 (a) to Fig.11 One or more features of the method described in (f) may also be applicable to the following description of Fig.12 (a) to Fig.12 (k) describes the method.

[0147] In step (a), the method includes forming a semiconductor region 185. The semiconductor region 185 may be formed using a deposition process. In this embodiment, the semiconductor region 185 includes an n-type doped semiconductor material, such as n-type doped silicon.

[0148] The semiconductor region 185 includes one or more epitaxial layers that have been formed on the substrate 110. The thickness T of the semiconductor region 185 may be approximately 50 μm. The thickness of the semiconductor region 185 may depend on the desired or expected breakdown voltage of the device 100. In the embodiment shown herein, the desired or expected breakdown voltage is approximately 600 V. However, it should be understood that in other embodiments, the desired or expected breakdown voltage of the device may be greater than or less than 600 V. In such other embodiments, the thickness of the semiconductor region may be greater than or less than 50 μm.

[0149] In step (b), the method includes forming a JFET region 130. The step of forming the JFET region 130 may include forming a fourth mask 190 on the semiconductor region 185. The fourth mask exposes the upper surface of the first region of the semiconductor region 185. The fourth mask may be formed in the same manner as the first mask 170 and the second mask 175 described above.

[0150] The JFET region 130 may be formed by doping the first region of the semiconductor region 185 with an n-type dopant, for example, using the above-described implantation process. The n-type dopant may include one or more of the exemplary n-type dopants described above.

[0151] In step (c), the method includes forming a body region 120. The step of forming the body region 120 may include forming a fifth mask on the semiconductor region 185. The fifth mask exposes the upper surface of the second region of the semiconductor region 185. The second region of the semiconductor region 185 is located adjacent to the JFET region 130. The fifth mask may be formed in the same manner as the first mask 170 and the second mask 175 described above.

[0152] The body region 120 may be formed by doping the second region of the semiconductor region 185 with a p-type dopant. The p-type dopant may be implanted using a blank implant process. After the p-type dopant is implanted, a diffusion or redistribution process including a drive-in process is performed to further diffuse or redistribute the p-type dopant in the body region 120. During the drive-in process, the temperature of the substrate 110 and the semiconductor region 185 is raised to, for example, about 1125° C. for about 100 minutes. The drive-in process causes the p-type dopant on the surface of the semiconductor region 185 to further diffuse into the semiconductor region 185, thereby forming the body region 120.

[0153] In step (d), the method includes depositing a layer 195 of mask material on the upper surface of semiconductor region 185 (e.g., above JFET region 130 and body region 120). The layer 195 of mask material includes a stack of a layer 195a of nitride material sandwiched between two layers 195b of oxide material. The nitride material may include silicon nitride, such as Si3N4, etc. The oxide material may include TEOS (tetraethyl orthosilicate), etc. The layer 195 of mask material may be patterned, for example, using a material removal process (e.g., a dry etching process or a wet etching process).

[0154] In step (e), the method includes forming a trench 200 in the semiconductor region 185. The trench 200 is formed so that it extends through the body region 120 into the semiconductor region 185. The trench 200 extends into the semiconductor region 185 in a vertical direction (e.g., a direction perpendicular to the substrate 110). The trench 200 is in contact with the body region 120. The trench 200 may be formed using a material removal process such as a dry etching process. A layer of a patterned mask material may be used as a hard mask or a resist layer to define the trench 200 during the material removal process.

[0155] The trench 200 may include a height H of about 35 μm. The trench 200 may include a width of about 5 μm. Fig.12(e) shows half of a unit cell of the device, so the width of the trench 200 is indicated by the reference numeral W / 2. The sidewalls of the trench 200 may be formed at an angle α relative to the surface of the substrate 110. The angle α may be between about 80 degrees and about 90 degrees, for example about 88 degrees. A portion of the semiconductor region 185 below the trench 200 may define a drift region 115. The trench 200 also contacts the drift region 115. It should be understood that in other embodiments, the height and / or width of the trench may be different from the exemplary height and / or width disclosed herein.

[0156] In step (f), for example, after forming the trench 200, a portion of the layer 195 of the mask material may be removed, for example, using a material removal process such as a wet etching process. In this embodiment, the upper layer of the two layers 195b of oxide material and the layer 195a of nitride material are removed. The lower layer of the two layers 195b of oxide material remains on the upper surface of the semiconductor region 185, for example, on the body region 120 and the JFET region 130.

[0157] In step (f), the method further includes filling the trench 200 with a p-type semiconductor material 205 (e.g., p-type doped silicon). The trench 200 may be filled with the semiconductor material 205 using a deposition process. In this embodiment, the semiconductor material 205 may be doped such that the doping concentration of the semiconductor material 205 in the trench 200 decreases in a direction from the drift region 115 to the body region 120 along the trench 200. For example, the p-type doping concentration of the semiconductor material 205 in the trench 200 may decrease in a direction from the drift region 115 to the body region 120 along the trench 200. 15 cm -3 Reduced to 6.9×10 15 cm -3 The direction along the trench 200 may also be understood as a vertical direction, for example, a direction parallel to the longitudinal axis of the trench 200. In this embodiment, the trench 200 forms a second column 125b. The portion of the semiconductor region 185 located adjacent to the trench 200 forms a first column 125a. The doping concentration of the first column 125a is constant in a direction from the drift region 115 to the body region 120 along the first column. For example, the n-type doping concentration of the first column 125a may be approximately 7×10 15 cm -3 However, it will be understood that in other embodiments, the doping concentration of the first column may increase in a direction from the drift region to the body region along the first column, and the doping concentration of the second column or a portion thereof may be constant in a direction from the drift region to the body region along the second column. In such other embodiments, the p-type doping concentration of the second column or a portion thereof may be approximately 7×10 15 cm -3The n-type doping concentration of the first pillar may be increased from about 6.65×10 15 cm -3 Increased to about 7.2×10 15 cm -3 .

[0158] In this embodiment, the body region 120 is located on a portion of the super junction region 125 , for example, on at least a portion of the first pillar 125 a . In this way, it can be considered that the super junction region 125 is at least partially disposed between the drift region 115 and the body region 120 .

[0159] In step (f), the method further comprises removing portions of the semiconductor material 205 extending beyond the body region 120 and the JFET region 130 using, for example, a material removal process such as a dry etching process or a chemical mechanical polishing process.

[0160] In step (g), the method includes removing the remaining portion of the layer 195 of the mask material, such as the lower layer of the two layers 195b of oxide material. The remaining portion of the layer 195 of the mask material can be removed using a material removal process such as a wet etching process. A sacrificial layer of oxide material can be deposited on the JFET region 130, the body region 120, and the second pillar 125b. The sacrificial layer of oxide material can then be removed.

[0161] In step (h), the method includes depositing a layer 210 of oxide material, such as silicon dioxide, over the JFET region 130, the body region 120, and the second pillar 125b.

[0162] In step (h), the method further includes forming a gate conductive region 135. The method includes depositing a layer of conductive material on the layer 210 of oxide material. The conductive material may include a doped semiconductor material, such as doped polysilicon. A material removal process such as a dry etching or wet etching process may be used to form the gate conductive region 135. For example, a mask may be used to etch the layer of conductive material so that the layer extends over the JFET region 130 and the body region 120. A portion of the layer 210 of oxide material located above the second pillar 125b is exposed.

[0163] In step (i), the method includes partially removing the exposed portion of the layer 210 of oxide material using a material removal process (eg, a dry etching or a wet etching process).

[0164] In step (i), the method further includes forming a source contact region 145. For example, an n-type dopant is implanted in a region of the second pillar 125b adjacent to the body region 120 to form the source contact region 145. The region of the second pillar 125b implanted with the n-type dopant is located below the layer 210 of the oxide material and extends from the exposed portion of the layer 210 of the oxide material to the gate conductive region 135. The sixth mask exposes the region to be implanted of the second pillar 125b.

[0165] The n-type dopant concentration of the source contact region 145 may be greater than 5×10 18 cm -3 . The n-type dopant may include one or more of the exemplary n-type dopants described above. The n-type dopant may be implanted using a blank implant process. After the n-type dopant is implanted, a diffusion or redistribution process including a drive-in process is performed to further diffuse or redistribute the n-type dopant in the region of the second pillar 125b. During the drive-in process, the temperature of at least the second pillar 125b is increased, for example, to about 1000°C for about 30 minutes. The drive-in process causes the n-type dopant on the surface of the region of the second pillar 125b to diffuse further into the region, thereby forming a source contact region 145.

[0166] In step (j), the method includes forming an interlayer dielectric layer 140b. For example, the interlayer dielectric layer 140b can be formed by depositing a layer of insulating material on or over the exposed portion of the gate conductive region 135 and the layer 210 of the oxide material, for example, using a deposition process. The layer of insulating material can include an oxide material, such as TEOS (tetraethyl orthosilicate).

[0167] In step (k), the method further includes forming a p+ contact region 150. The method includes, for example, forming an opening or recess using a material removal process. The opening or recess is laterally spaced from the gate conductive region 135. The contact opening or recess may be formed by etching through the interlayer dielectric layer 140B and the layer 210 of oxide material. The remaining portion of the layer 210 of oxide material forms the gate oxide region 140a.

[0168] P-type dopants may be implanted under the contact opening or recess to form a p+ contact region 150. The p-type dopant concentration of the p+ contact region 150 may be greater than 5×10 18 cm -3 The p-type dopant may include one or more of the exemplary p-type dopants described above. The p-type dopant may be implanted using a blank implantation process.

[0169] In step (k), the method further includes forming source contact 155. For example, source contact 155 may be formed by depositing a layer of conductive material into the contact opening or recess and on or over interlayer dielectric layer 140b, such that source contact 155 contacts source contact region 145 and p+ contact region 150.

[0170] In step (k), the method further includes forming a drain contact 110a. For example, the drain contact 110a may be formed by grinding or planarizing the lower surface of the substrate 110 and depositing a layer of a conductive material thereon. The layer of conductive material may be deposited on the lower surface of the substrate 110 using a deposition process such as an evaporation process.

[0171] Fig.13 Schematically illustrates the use of Fig.12 (a) to Fig.12 (k) is a cross-section of a super junction region 125 formed by one or more steps of the method described. Fig.13 In the illustrated embodiment, the super junction region 125 includes a second pillar 125b disposed between two portions of two first pillars 125a. However, it will be understood that the device 100 may have more than one second pillar 125b and more than two first pillars 125a as mentioned above.

[0172] The above deposition process may include a chemical vapor deposition process, a sputtering process or other deposition processes.

[0173] The dry etching process may include a reactive ion etching process or other dry etching processes.

[0174] It should be understood that the term "constant" as used herein encompasses the term "substantially constant".

[0175] It should be understood that the term "same" as used herein encompasses the term "substantially the same".

[0176] It should be understood that the term "width" as used herein encompasses the width of a component or feature in a lateral direction (e.g., parallel to Figure 4 The dimension, size, or extension of a component in the direction of the y-axis.

[0177] It should be understood that the terms "thickness" or "height" as used herein encompass the thickness of a component or feature in the longitudinal or vertical direction (e.g., parallel to the Figure 4 The dimension, size or extension in the direction of the x-axis in the image and / or in the direction perpendicular to the lateral direction).

[0178] Those skilled in the art will appreciate that in the foregoing description and the appended claims, positional terms such as "above," "overlapping," "below," lateral, etc. are made with reference to conceptual illustrations of the device (such as those showing standard cross-sectional perspectives and those shown in the accompanying drawings). These terms are used for ease of reference and are not intended to be limiting. Therefore, these terms should be understood to refer to the device when in the orientation shown in the drawings.

[0179] It should be understood that all of the above-mentioned doping polarities can be reversed and the resulting device is still in accordance with an embodiment of the present invention.

[0180] Although the above description relates to a device comprising a MOSFET, it will be appreciated that in other embodiments, the device may comprise an insulated gate bipolar transistor (IGBT). Any of the above features may also be applied to the IGBT. In such other embodiments, the term "drain region" may be replaced with the term "collector region", and the term "source" as used above may be replaced with the term "emitter".

[0181] In this document, dimensions are provided as indicative examples only and are not intended to be limiting.

[0182] It should be understood that Figures 1 to 3 (f), Fig.11 (a) to Fig.11 (f), Fig.12 (a) to Fig.12 (k) and Fig.13 are schematic diagrams of some embodiments of the present disclosure and may not be drawn to scale.

[0183] Although specific embodiments are described above, the claims are not limited to these embodiments. Those skilled in the art will be able to make modifications and substitutions in view of the present disclosure, and these modifications and substitutions are considered to fall within the scope of the appended claims. Each feature disclosed may be incorporated into any described embodiment alone or in an appropriate combination with other features disclosed herein.

[0184] Reference numerals

[0185] 100 Installations

[0186] 105 Active Area

[0187] 110 Substrate

[0188] 110a Drain contact

[0189] 115 Drift Zone

[0190] 120 Body Area

[0191] 125 Superjunction

[0192] 125a First Column

[0193] 125b Second Column

[0194] 130JFET area

[0195] 135 Gate conductive region

[0196] 140a Gate oxide region

[0197] 140b Interlayer dielectric layer

[0198] 145n+ source contact area

[0199] 150p+contact area 150

[0200] 155 Source contact

[0201] 155 Source contact

[0202] 157Semiconductor layer

[0203] 160a n-type dopant dose

[0204] 160b p-type dopant dose

[0205] 160c enriched area

[0206] 165 Impact ionization position

[0207] 170 First Mask

[0208] 175 Second Mask

[0209] 180 Another semiconductor layer

[0210] 185 Semiconductor Zone

[0211] 190 The Fourth Mask

[0212] 195 Layer of mask material

[0213] 195a Layer of nitride material

[0214] 195b Layer of oxide material

[0215] 200 Grooves

[0216] 205 p-type semiconductor materials

[0217] 210 Layer of oxide material

[0218] H Groove height

[0219] W Groove width

[0220] α Angle of the sidewall of the trench

[0221] T is the thickness of the semiconductor region.

Claims

1. A semiconductor power device, comprising an active region, wherein the active region comprises: a drift region of a first conductivity type; a body region of a second conductivity type, wherein the second conductivity type is opposite to the first conductivity type; A super junction region, which is at least partially arranged between the drift region and the body region, the super junction region comprising: the first column of the first conductivity type, at least a portion of a second pillar of the second conductivity type, the first pillar being arranged adjacent to the portion of the second pillar, wherein at least one of the following: The doping concentration of the first column is constant in a direction from the drift region to the body region along the first column, and the doping concentration of the portion of the second column decreases in a direction from the drift region to the body region along the portion of the second column; or A doping concentration of the first column increases in a direction from the drift region to the body region along the first column, and a doping concentration of the portion of the second column is constant in a direction from the drift region to the body region along the portion of the second column.

2. The semiconductor power device according to claim 1, wherein at least one of the following: The doping concentration of the portion of the second column decreases linearly in a direction from the drift region to the body region along the portion of the second column; or The doping concentration of the first column increases linearly in a direction from the drift region to the body region along the first column.

3. The semiconductor power device according to claim 1, wherein at least one of the following: The doping concentration of the portion of the second column gradually decreases in a direction from the drift region to the body region along the portion of the second column; or The doping concentration of the first column increases stepwise in a direction from the drift region to the body region along the first column.

4. The semiconductor power device according to claim 3, wherein: At least one of the following: The doping concentration of the portion of the second pillar decreases in two or more steps; or The doping concentration of the first pillar increases in two or more steps.

5. A semiconductor power device according to any preceding claim, wherein a doping concentration of the first pillar at or near the body region is greater than, less than or equal to a doping concentration of the portion of the second pillar at or near the body region. 6 . The semiconductor power device according to claim 1 , wherein the super junction region comprises a plurality of first pillars and a plurality of second pillars arranged alternately with each other. 7 . The semiconductor power device of claim 6 , wherein each of the plurality of first pillars is arranged adjacent to at least one of the plurality of second pillars.

8. A semiconductor power device according to any preceding claim, wherein the semiconductor power device comprises a metal oxide semiconductor field effect transistor or an insulated gate bipolar transistor.

9. A method for manufacturing an active region of a semiconductor power device, the method comprising: forming a drift region of a first conductivity type on a substrate; A super junction region is formed on the drift region, wherein the super junction region comprises: the first column of the first conductivity type, at least a portion of a second pillar of a second conductivity type, the first pillar being arranged adjacent to the portion of the second pillar, wherein at least one of the following: The doping concentration of the first column is constant in a direction from the drift region to the body region along the first column, and the doping concentration of the portion of the second column decreases in a direction from the drift region to the body region along the portion of the second column; or A doping concentration of the first column increases in a direction from the drift region to the body region along the first column, and a doping concentration of the portion of the second column is constant in a direction from the drift region to the body region along the portion of the second column; A body region of a second conductivity type is formed on at least a portion of the super junction region.

10. The method of claim 9, wherein forming the super junction region comprises: Perform each of steps (i) to (v) one or more times: (i) depositing a semiconductor layer on or over the drift region; (ii) forming a first mask on the semiconductor layer, wherein the first mask exposes an upper surface of a first region of the semiconductor layer; (iii) selectively doping the first region of the semiconductor layer to form a first region of a first conductivity type; (iv) forming a second mask on the semiconductor layer, the second mask exposing an upper surface of a second region of the semiconductor layer, the second region of the semiconductor layer being laterally spaced apart from the first region of the semiconductor layer; as well as (v) selectively doping the second region of the semiconductor layer to form a second region of a second conductivity type. 11 . The method of claim 10 , wherein in a first iteration the semiconductor layer is deposited on the drift region, and wherein in one or more subsequent iterations a subsequent semiconductor layer is deposited on a previously deposited semiconductor layer.

12. The method of claim 11, wherein when at least one subsequent iteration has been performed: The doping concentration of each first region of the first conductivity type is the same; and The doping concentration of the second region of the second conductivity type formed in at least one subsequent iteration is reduced relative to the doping concentration of the second region of the second conductivity type formed in the previous iteration.

13. The method of claim 11, wherein when at least one subsequent iteration has been performed: The doping concentration of each second region of the second conductivity type is the same; and The doping concentration of the first region of the first conductivity type formed in at least one subsequent iteration is increased relative to the doping concentration of the first region of the first conductivity type formed in the previous iteration.

14. A method according to any one of claims 9 to 13, comprising forming at least a portion of the first and second pillars using a diffusion or redistribution process.

15. The method of claim 9, wherein forming the super junction region comprises: forming a trench in a semiconductor region of a first conductivity type, wherein a portion of the semiconductor region adjacent to the trench forms the first pillar; as well as The trench is filled with a semiconductor material of a second conductivity type to form the at least a portion of the second pillar.

16. A method of manufacturing a semiconductor power device, comprising: A method for manufacturing an active region of a semiconductor power device according to any one of claims 9 to 15.

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