Device with isolation structure

Abstract

The invention relates to a semiconductor structure, and more particularly relates to a device with an isolation structure and a manufacturing method. The structure comprises a semiconductor material stack; a semiconductor substrate underlying the stack of semiconductor materials; a trench filled with an insulator material; and a damaged region of the stack of semiconductor materials extending at least from the bottom of the insulator material to the semiconductor substrate.

Description

Technical Field

[0001] The present disclosure relates to semiconductor structures, and more particularly to devices and fabrication methods having isolation structures. Background Art

[0002] A high electron mobility transistor (HEMT) is a field effect transistor that includes a junction between two materials with different band gaps as the channel, rather than a doped region (as is usually the case with MOSFETs). A common material combination is GaAs with AlGaAs, although there are other material variations depending on the application of the device. For example, HEMTs that include gallium nitride offer high power performance.

[0003] HEMTs are capable of operating at higher frequencies (up to millimeter-wave frequencies) than ordinary transistors. Therefore, HEMTs are used in high-frequency products such as cellular phones, satellite receivers, voltage converters, and radar equipment. HEMTs can also be used in low-power applications such as low-power amplifiers. However, HEMTs can exhibit high gate-to-drain capacitance (Cgd), which varies with the application of different voltages. Summary of the invention

[0004] In one aspect of the present disclosure, a structure includes: a semiconductor material stack; a semiconductor substrate located below the semiconductor material stack; a trench located in the semiconductor material stack and filled with an insulator material; and a damaged area of ​​the semiconductor material stack extending at least from the bottom of the insulator material to the semiconductor substrate.

[0005] In one aspect of the present disclosure, a structure includes: a wide bandgap semiconductor layer of a semiconductor substrate; a device located above the wide bandgap semiconductor layer; a trench located in the wide bandgap semiconductor layer, which is filled with an insulator material surrounding the device; and a damaged region of the wide bandgap semiconductor layer, which extends from at least the bottom of the trench to the semiconductor substrate and surrounds the device.

[0006] In one aspect of the present disclosure, a method includes: forming a semiconductor material stack on a semiconductor substrate; partially forming a trench in the semiconductor material stack; damaging a region of the semiconductor material stack extending at least from a bottom of the trench to the semiconductor substrate; and filling the trench with an insulator material. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In the following detailed description, the present disclosure is described by way of non-limiting examples of exemplary embodiments of the present disclosure with reference to the several accompanying drawings mentioned.

[0008] Figure 1 The structure and corresponding manufacturing process according to some aspects of the present disclosure are shown.

[0009] Figure 2 Structures according to additional aspects of the present disclosure are shown.

[0010] Figure 3 Structures according to additional aspects of the present disclosure are shown.

[0011] Figure 4 Structures according to additional aspects of the present disclosure are shown.

[0012] Figure 5A and 5B Top views of different structures according to some aspects of the present disclosure are shown.

[0013] Figures 6A-6C A method for manufacturing a Figure 1 The corresponding manufacturing process of the structure. DETAILED DESCRIPTION

[0014] The present disclosure relates to semiconductor structures, and more particularly to devices and manufacturing methods having isolation structures. More specifically, the device may be a high electron mobility transistor, and the isolation structure may be a damaged substrate region surrounding the device to form a sealed structure. Advantageously, these structures achieve improved electrical and physical isolation by preventing leakage current and moisture ingress.

[0015] In a more specific embodiment, the present disclosure relates to a high electron mobility transistor (HEMT) comprising a wide bandgap semiconductor layer (e.g., AlGaN) located above a substrate (e.g., a Si substrate), and an isolation region located in the wide bandgap semiconductor layer and surrounding a portion of the wide bandgap semiconductor layer. In a more specific embodiment, the isolation region surrounds the HEMT. The isolation region may include a trench filled with an insulator material and a high-density crystal dislocation region surrounding the insulator material and extending to an underlying substrate. For example, the high-density crystal dislocation region may be arranged along the bottom surface of the trench, and in an embodiment, along the sidewalls of the trench. The high-density crystal dislocation region may include a damaged portion of the wide bandgap semiconductor layer having a higher resistivity than the wide bandgap semiconductor layer and the underlying substrate.

[0016] The structures disclosed herein can be manufactured in a variety of ways using a variety of different tools. However, in general, methods and tools are used to form structures with micrometer and nanometer dimensions. Methods (i.e., techniques) for manufacturing the structures disclosed herein have been adopted based on integrated circuit (IC) technology. For example, these structures are built on a wafer and implemented in a material film patterned on top of the wafer by means of a photolithographic process. Specifically, the manufacture of the structure uses three basic building blocks: (i) depositing a thin film of material on a substrate; (ii) applying a patterned mask on top of the film by photolithographic imaging; and (iii) selectively etching the film to the mask. In addition, as is known in the art, a pre-cleaning process can be used to clean any contaminants on the etched surface. In addition, as is known in the art, a rapid thermal annealing process can be used to drive in dopants or material layers when necessary.

[0017] Figure 1 The structure and corresponding manufacturing process according to some aspects of the present disclosure are shown. More specifically, Figure 1 The structure 10 includes a high-density crystal dislocation region (e.g., a damaged region) 12 that extends through the wide bandgap semiconductor layer 14 and, in an embodiment, extends onto the surface of or within the underlying semiconductor substrate 16. The high-density crystal dislocation region 12 can be formed through the trench before the trench is filled with the dielectric material 18. In this way, the high-density crystal dislocation region 12 can surround the dielectric material 18, and more specifically, can surround the trench filled with the dielectric material 18. The high-density crystal dislocation region 12 also physically and electrically isolates the device 20. Therefore, the high-density crystal dislocation region 12 will improve electrical and physical isolation by preventing leakage current and moisture ingress from reaching the device 20, thereby improving electrical performance and reliability.

[0018] In a more specific embodiment, Figure 1 The structure 10 includes a wide bandgap semiconductor layer 14 located above an underlying semiconductor substrate 16. The wide bandgap semiconductor layer 14 can be, for example, an AlGaN material stack known in the art. For example, as a non-limiting illustrative example, the wide bandgap semiconductor layer 14 can include a seed layer (e.g., AlN), a buffer layer (e.g., AlGaN), and a channel layer (e.g., GaN) located on the underlying semiconductor substrate 16 in a layered stack of semiconductor materials. In an embodiment, a device 20 (e.g., a p-doped GaN gate structure) can be disposed above the channel layer. The semiconductor material stack can be formed by conventional epitaxial growth processes or other known deposition methods (e.g., chemical vapor deposition (CVD)).

[0019] Semiconductor substrate 16 may include a semiconductor processing substrate material containing Si; although other suitable materials are also contemplated herein, including but not limited to SiGe, SiGeC, SiC, GaAs, InAs, InP and other III / V or II / VI compound semiconductors. In a preferred embodiment, the semiconductor material substrate may include a suitable crystal orientation, such as (111).

[0020] The semiconductor substrate 16 may also include a semiconductor-on-insulator substrate used in semiconductor-on-insulator technology. The semiconductor-on-insulator technology includes a processing substrate, a buried insulator layer (i.e., substrate), and a top semiconductor layer (semiconductor-on-insulator substrate) from bottom to top. The processing substrate and the top semiconductor layer may include semiconductor materials such as Si, Ge, SiGe, SiC, SiGeC, III-V compound semiconductors, II-VI compound semiconductors, or any combination thereof. The buried insulator layer may, for example, include oxides, silicon dioxide, silicon nitride, silicon oxynitride, boron nitride, or a combination thereof. In an embodiment, the buried insulator layer may be formed by a deposition process such as CVD, plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or may be formed by an oxygen injection process or a thermal growth process known in the art, and therefore, no further explanation is required to fully understand the present disclosure. The top semiconductor layer may be formed by a deposition process (e.g., CVD or PECVD), or may be formed using a smart cut process known in the art.

[0021] Still reference Figure 1 , the device (e.g., gate structure) 20 can be disposed between the source region 17 and the drain region 19 (e.g., active region) of the channel layer. The device 20 can be a HEMT, which includes a semiconductor material formed (e.g., deposited and patterned) on a semiconductor material stack (e.g., a wide bandgap semiconductor layer 14). In an embodiment, the semiconductor material of the device 20 includes, for example, p-doped GaN (e-mode device) or metal (d-mode device). As is known in the art, the semiconductor material can be epitaxially grown by in-situ doping (e.g., p-type doping). A metal stack 22 (e.g., TiN, TiAl, and / or TaN) can be disposed on top of the semiconductor material of the device 20 and in contact with the semiconductor material. A metal field plate 24 (e.g., TiN, TiAl, and / or TaN) is connected to the source region 17. The metal stack 20 and the field plate can be deposited by conventional deposition methods (e.g., CVD) and then conventional photolithography and etching (e.g., patterning) processes are performed.

[0022] The structure also includes an isolation structure. The isolation structure includes a high-density crystal dislocation region 12, which is arranged at the outer edge of the drain region and the source region 17, more specifically, around the device 20, whether the device 20 is an active device or a passive device. The high-density crystal dislocation region 12 can be formed by Figure 6B The ion implantation process is described. In an embodiment, the high density crystal dislocation region 12 may have a tapered sidewall profile (or a straight sidewall profile as further described herein) extending from the top surface to the bottom surface of the wide bandgap semiconductor layer 14 .

[0023] In a preferred embodiment, the high-density crystal dislocation region 12 may extend completely or partially through the wide bandgap semiconductor layer 14 above the underlying semiconductor substrate 16. In addition, the high-density crystal dislocation region 12 may extend onto the surface of the underlying semiconductor substrate 16 or into the underlying semiconductor substrate 16. In this way, the high-density crystal dislocation region 12 will completely isolate the device 20, both electrically isolating and preventing moisture from entering. The isolation region also includes a dielectric material 18 deposited in the trench. The high-density crystal dislocation region 12 may surround the dielectric material 18. The dielectric material 18 may be an oxide material or other low-k dielectric material known in the art. The dielectric material 18 may also extend above the top surface of the wide bandgap semiconductor layer 14. In an embodiment, the high-density crystal dislocation region 12 and the dielectric material 18 may have tapered sidewalls.

[0024] An interlayer dielectric material 26 may be disposed over the entire structure, including around metal plate 24, metal stack 22, and device 20. Interlayer dielectric material 26 may be SiO2 or nitride or a combination thereof in a stacked configuration.

[0025] Figure 2 A structure 10a is shown according to additional aspects of the present disclosure. Figure 2 In the embodiment of the present invention, the structure 10a includes a liner 28 located on the surface of the trench filled with the dielectric material 18. In this way, the liner 28 is disposed on the sidewalls and the bottom surface of the dielectric material 18. The liner 28 may also be located between the dielectric material 18 and the high density crystal dislocation region 12 and in direct contact with both. The liner 28 may be a nitride or other insulator material 28 different from the dielectric material 18. Figure 2 The remaining features of structure 10a are similar to Figure 1 Structure 10.

[0026] Figure 3 Another structure 10b according to aspects of the present disclosure is shown. Figure 3 In the embodiment, for example, the dielectric material 18 includes upright vertical sidewalls. This is because the trench filled with the dielectric material 18 also has upright vertical sidewalls. In addition, the high-density crystal dislocation region 12 is disposed below the dielectric material 18, extending from the bottom surface of the dielectric material 18 to the top of the underlying semiconductor substrate 16 or extending into the underlying semiconductor substrate 16. In this embodiment, the high-density crystal dislocation region 12 may also have upright vertical sidewalls directly below the dielectric material 18. Figure 3 The remaining features of structure 10b are similar to Figure 1 Structure 10.

[0027] Figure 4 Another structure 10c according to some aspects of the present disclosure is shown. In this structure, a liner 28 is disposed on the surface of the trench filled with dielectric material 18. Figure 3 Similarly, in the structure 10b, since the trench is formed to have upright vertical sidewalls, the dielectric material 18 also includes such upright vertical sidewalls. Figure 3 Similarly, in the structure 10b of FIG. 1 , the high-density crystal dislocation region 12 is disposed below the dielectric material 18, extending from the bottom surface of the dielectric material 18 to the top of the underlying semiconductor substrate 16 or extending into the underlying semiconductor substrate 16. In this embodiment, the high-density crystal dislocation region 12 may also have upright vertical sidewalls directly below the dielectric material 18. Figure 4 The remaining features of structure 10c are similar to Figure 1 Structure 10.

[0028] Figure 5A A top view of a structure according to some aspects of the present disclosure is shown. In this view, high density crystal dislocation regions 12 and dielectric material 18 (e.g., isolation structures) are shown surrounding individual devices 20. In addition, high density crystal dislocation regions 12 and dielectric material 18 (e.g., isolation structures) surround several devices 20. It should be understood that although Figure 5A Four devices are shown in FIG, but any number of devices is contemplated herein. Figure 5B In FIG. 4 , a single high density crystal dislocation region 12 and dielectric material 18 (eg, isolation structure) surround several devices 20 .

[0029] Figures 6A-6C A method for manufacturing a Figure 1 The corresponding manufacturing process of the structure. Fig. 6A As shown, for example, trench 15 is formed in optional insulator material (eg, oxide material) 30 and partially passes through wide bandgap semiconductor layer 14. In an embodiment, trench 15 may have sloped sidewalls and may not extend completely through wide bandgap semiconductor layer 14.

[0030] The grooves 15 may be formed by conventional photolithography, etching, and deposition methods known to those skilled in the art. For example, a resist formed on top of the insulator material 30 is exposed to energy (light) and the exposed resist layer is developed using a conventional resist developer to form a pattern (opening). An etching process with selective chemistry, such as reactive ion etching (RIE), will be used to transfer the pattern through the openings in the resist into the insulator material 30 and the wide bandgap semiconductor layer 14. The resist may be removed by conventional oxygen ashing processes or other known strippers.

[0031] exist Figure 6B In the embodiment, dopants are implanted into the wide bandgap semiconductor layer 14 through the trench 15. The dopants may be, for example, B, C, N, P, Ar, Ge, As or Xe. In an embodiment, the insulator material 30 may be used as an implantation mask, the thickness and stopping power of which are sufficient to block the masked area from receiving a certain dose of implanted ions.

[0032] The implantation process will damage the wide bandgap semiconductor layer 14, resulting in a high-density crystalline dislocation region 12. In an embodiment, due to the tapered sidewalls of the trench 15, the high-density crystalline dislocation region 12 will extend into the wide bandgap semiconductor layer 14 at the sidewalls of the trench 15. The high-density crystalline dislocation region 12 may also have tapered sidewalls and extend from the top surface of the wide bandgap semiconductor layer 14 to the surface of the underlying semiconductor substrate 16 or within the underlying semiconductor substrate 16. The depth of the high-density crystalline dislocation region 12 may be adjusted based on the concentration and energy of the ion implantation process and the depth of the trench 15. For example, nitrogen may be implanted at 3000 KeV.

[0033] In an alternative embodiment, when the sidewalls of the trench 15 are upright and the ion implantation process is straight down, the high density crystalline dislocation region 12 will extend from the bottom of the trench 15 of the underlying semiconductor substrate 16 (not through the sidewalls). In another alternative embodiment, using an angled ion implantation process, the high density crystalline dislocation region 12 can extend through the sidewalls of the trench 15 into the wide bandgap semiconductor layer 14, regardless of whether the sidewalls are tapered or upright.

[0034] exist Figure 6C In the embodiment, the insulator material 18 can be deposited in the trench 15 by a conventional deposition process (such as CVD). The insulator material 18 on the top of the structure can also be planarized by a conventional chemical mechanical planarization (CMP) process. Figure 2 and Figure 4 As shown, before depositing the insulator material, the trench 15 may be lined with a lining material. In this embodiment, the lining material may be N. Thereafter, the trench 15 may be lined with a lining material such as Figure 1 The fabricated device 20 is shown.

[0035] These structures can be used in system-on-chip (SOC) technology. A SoC is an integrated circuit (also called a "chip") that integrates all the components of an electronic system on a single chip or substrate. Because the components are integrated on a single substrate, an SoC consumes much less power and occupies much less area than a multi-chip design with equivalent functionality. As a result, SoCs are becoming a dominant force in the mobile computing (for example, in smartphones) and edge computing markets. SoCs are also used in embedded systems and the Internet of Things.

[0036] The above method is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in the form of a single chip package (e.g., a plastic carrier whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier with surface interconnects and / or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0037] The description of various embodiments of the present disclosure has been given for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the various embodiments, practical applications, or technical improvements to technologies found in the marketplace, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A structure comprising: Semiconductor material stacking; a semiconductor substrate located below the semiconductor material stack; a trench located in the semiconductor material stack and filled with an insulator material; as well as The damaged region of the semiconductor material stack extends at least from the bottom of the insulator material to the semiconductor substrate.

2. The structure according to claim 1, wherein: The semiconductor material stack includes a wide bandgap semiconductor material.

3. The structure according to claim 2, wherein: The damaged region includes a high density of crystal dislocation regions of the semiconductor material stack.

4. The structure according to claim 3, wherein: The damaged region and the insulator material include tapered sidewalls.

5. The structure according to claim 4, wherein: The tapered sidewalls and bottom surface of the insulator material include a liner material.

6. The structure according to claim 3, wherein: The damaged region extends completely through the semiconductor material stack and into the semiconductor substrate.

7. The structure according to claim 3, wherein: The damaged area surrounds the active device.

8. The structure according to claim 7, wherein: The damaged area includes a plurality of damaged areas, at least one of which surrounds a plurality of active devices.

9. The structure according to claim 3, wherein: The damaged region extends partially through the semiconductor material stack and into the semiconductor substrate.

10. The structure according to claim 1, wherein: The insulator material and the damaged region include upstanding vertical sidewalls.

11. The structure according to claim 10, wherein: The upstanding vertical sidewalls and bottom surface of the insulator material are lined with a lining material.

12. A structure comprising: a wide bandgap semiconductor layer of a semiconductor substrate; a device located above the wide bandgap semiconductor layer; a trench in the wide bandgap semiconductor layer filled with an insulator material surrounding the device; as well as The damaged region of the wide bandgap semiconductor layer at least extends from the bottom of the trench to the semiconductor substrate and surrounds the device.

13. The structure according to claim 12, wherein: The trench includes tapered sidewalls.

14. The structure according to claim 12, wherein: The trench is lined with an insulator liner.

15. The structure according to claim 12, wherein: The trench extends partially within the wide bandgap semiconductor layer.

16. The structure of claim 12, wherein: The damaged region extends into the semiconductor substrate.

17. The structure of claim 12, wherein: The damaged region includes a high density crystal dislocation region.

18. The structure of claim 12, wherein: The damaged region extends from a top surface of the wide bandgap semiconductor to a bottom surface of the wide bandgap semiconductor.

19. The structure of claim 12, wherein: The damaged area includes a plurality of damaged areas, each of which surrounds a single device, and one of which surrounds a plurality of devices.

20. A method comprising: forming a semiconductor material stack on a semiconductor substrate; partially forming a trench in the semiconductor material stack; The damage extends at least from the bottom of the trench to a region of the semiconductor material stack of the semiconductor substrate; as well as The trench is filled with an insulator material.

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