Level shifter and semiconductor device

Abstract

According to the level shifter and the semiconductor device provided by the invention, the buried doping region is arranged in the epitaxial layer, close to the drain region, of the field effect transistor, so that the ion doping concentration in the drift region of the transistor is improved, and the resistance of the drift region is reduced, so that the current discharge capability of the level shifter after breakdown is improved, and the reliability of the level shifter is improved. The purpose of improving the self-protection performance of the device is achieved. In addition, the positions of the buried buried doped regions in the transverse direction and the longitudinal direction are limited, so that the arrangement of the buried doped regions does not reduce the voltage resistance between the source region and the drain region of the field effect transistor and between the drain region and the substrate; and the voltage withstanding performance of other regions, except the transistor region, of the device is not influenced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] High-voltage power gate driver chips are usually implemented using compatible processes for high-voltage circuits and low-voltage circuits. A level shifter is used between the high-voltage side circuit and the low-voltage side circuit to convert the control signal from the low-voltage side circuit into a control signal for the high-voltage side circuit, which is then transmitted to the high-voltage side circuit to control the high-voltage side circuit, thereby realizing the level conversion between the high-voltage side circuit and the low-voltage side circuit. An isolation area is provided on the periphery of the level shifter to isolate the high-voltage side circuit and the level shifter to prevent leakage from affecting the functions between the devices.

[0003] In addition to the functions described above, the level shifter also needs to play the role of discharging current after breakdown (that is, the role of self-protection ESD) when facing surge current in circuit applications, so as to avoid being burned out.

[0004] Usually, the level shifter of high-voltage LDMOS (Laterally Diffused Metal Oxide Semiconductor) needs to bear higher voltage, the width of its drift region needs to be designed to be wider, and the ion doping needs to be lower. Although such a design ensures high withstand voltage, it will cause the on-resistance of LDMOS to be larger, which reduces the ability to discharge current and affects the application scope of the level shifter.

[0005] Therefore, how to ensure the voltage resistance performance of the level shifter while improving its ability to discharge current after breakdown is an important research topic in this field. Summary of the invention

[0006] The object of the present invention is to provide a level shifter and a semiconductor device, so as to improve the capability of the level shifter to discharge current after being broken down.

[0007] In order to solve the above problems, the present invention provides a level shifter, comprising: A substrate, the substrate comprising a base of a second doping type and an epitaxial layer of a first doping type stacked in sequence from bottom to top; A field effect transistor, the field effect transistor comprising a drain region of a first doping type, a source region of a first doping type, a gate structure and a field oxide layer, the drain region and the source region are formed in the epitaxial layer, the gate structure is formed on the epitaxial layer and is located between the source region and the drain region, the field oxide layer is formed on a surface of the epitaxial layer, and the gate structure is isolated from the drain region by the field oxide layer; an isolation doping region of a second doping type, the isolation doping region being disposed in the epitaxial layer and extending along the periphery of the field effect transistor; and A buried doped region of a first doping type is arranged in the epitaxial layer between the gate structure and the drain region, the buried doped region is closer to the drain region relative to the gate structure, and the distance between the buried doped region and the substrate is greater than or equal to a set threshold.

[0008] Optionally, in the level shifter, the set threshold is 2 / 3 of the thickness of the epitaxial layer.

[0009] Optionally, in the level shifter, the field effect transistor further comprises a field oxide layer, the field oxide layer is formed on the surface of the epitaxial layer, and the gate structure and the drain region are isolated by the field oxide layer; The buried doped region extends downward from the lower surface of the field oxide layer, or there is a gap between the upper surface of the buried doped region and the lower surface of the field oxide layer.

[0010] Optionally, in the level shifter, the buried doped region is a continuously extending doped region, or the buried doped region includes a plurality of sub-doped regions arranged at intervals.

[0011] Optionally, in the level shifter, the isolation structure includes at least two isolation doping regions arranged in sequence from bottom to top and connected to each other, wherein the isolation doping region located at the bottom layer extends upward from the substrate into the epitaxial layer.

[0012] Optionally, in the level shifter, at least two of the isolation doped regions include a first shallow well region of a second doping type extending inwardly from the top surface of the epitaxial layer into the epitaxial layer; and The level shifter also includes a second shallow well region of a second doping type extending inward from the top surface of the epitaxial layer to the epitaxial layer, the second shallow well region is located on a side of the gate structure close to the source region, the source region is formed in the second shallow well region, and the first shallow well region extends from the outside of the drain region around the field effect transistor to the second shallow well region to be connected to the second shallow well region.

[0013] Optionally, in the level shifter, at least two of the isolation doped regions further include a first deep well region of the second doping type and a first buried region of the second doping type that are located below the first shallow well region and are sequentially connected from top to bottom; and The level shifter also includes a second deep well region of a second doping type and a second buried region of a second doping type located below the second shallow well region and connected in sequence from top to bottom, the first deep well region extending from the outside of the drain region around the field effect transistor to the second deep well region to be connected to the second deep well region, and the first buried region extending from the outside of the drain region around the field effect transistor to the second buried region to be connected to the second buried region.

[0014] Optionally, in the level shifter, the level shifter comprises a third well region of the first doping type, the third well region extends downward from the surface of the epitaxial layer, and the drain region is formed in the third well region; The buried doped region is located between the third well region and the gate structure.

[0015] Optionally, in the level shifter, the level shifter includes a third buried region of the second doping type, the third buried region is located between the source region and the drain region, and the third buried region extends upward from the substrate into the epitaxial layer; The buried doped region is located between the third buried region and the drain region.

[0016] The present invention further provides a semiconductor device, comprising the level shifter as described above and a high-voltage side circuit, wherein the high-voltage side circuit is located on a side of the isolation doping region away from the field effect transistor.

[0017] In summary, the level shifter provided by the present invention increases the ion doping concentration in the drift region of the transistor by setting a buried doping region in the epitaxial layer near the drain region of the field effect transistor, thereby reducing the resistance of the drift region, which is conducive to improving the ability of the level shifter to discharge current after being broken down, and achieving the purpose of improving the overall self-protection performance of the device. In addition, by limiting the position of the buried doping region in the horizontal and vertical directions, the setting of the buried doping region will not reduce the withstand voltage performance between the source region and the drain region of the field effect transistor and between the drain region and the substrate, and will not affect the withstand voltage performance of other regions of the device except the transistor region. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 FIG. 4 is a schematic structural diagram of a semiconductor device with a level shifter in an embodiment of the present invention.

[0019] Figure 2FIG. 4 is a schematic diagram of a semiconductor device with a level shifter in an embodiment of the present invention, showing an interconnection structure.

[0020] Figure 3-Figure 11 FIG. 4 is a schematic structural diagram of a semiconductor device with a level shifter during its preparation process in an embodiment of the present invention.

[0021] Fig.12 A schematic diagram of a simulation comparing the surface current concentration of the drift region of an LDMOS tube provided by an embodiment of the present invention and a conventional LDMOS tube.

[0022] Fig.13 A schematic diagram of a simulation comparing the breakdown voltages of an LDMOS provided by an embodiment of the present invention and a conventional LDMOS.

[0023] The reference numerals are as follows: 100-substrate; 110P-base; 120N-epitaxial layer; 200-field effect transistor; 200S-source region; 200D-drain region; 200G-gate structure; 200B-first contact region; 210-second isolation oxide layer; 220-field oxide layer; 300-isolation structure; 310-first isolation oxide layer; 400N-buried doped region; 510 / 520 / 530 / 540 / 550 / 560 / 570-mask layer; 610-interlayer dielectric layer; 620-conductive plug; 630-electrode conductive layer; PBL1-first buried region; PBL2-second buried region; PBL3-third buried region; NBL-fourth buried region; DPW1-first deep well region; DPW2-second deep well region; PW1-first shallow well region; PW2-second shallow well region; NW1-third well region; NW2-fourth well region. DETAILED DESCRIPTION

[0024] The level shifter and semiconductor device proposed in the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are all in non-precise proportions, which are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis required to be shown in each drawing is different, and sometimes different proportions are used. It should be recognized that relative terms such as "above", "below", "top", "bottom", "above" and "below" shown in the drawings can be used to describe the relationship between various elements. These relative terms are intended to cover different orientations of elements other than the orientations depicted in the drawings. For example, if the device is inverted relative to the view in the drawings, for example, an element described as "above" another element will now be below the element. It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third" and the like in the specification are only used to distinguish between various components, elements, steps, etc. in the specification, rather than to represent the logical relationship or sequential relationship between various components, elements, steps, etc.

[0025] Figure 1 FIG. 1 is a schematic diagram of a level shifter in an embodiment of the present invention. Figure 1 As shown, the level shift device includes: a substrate 100 , a field effect transistor 200 formed on the substrate 100 , and an isolation structure 300 formed outside the field effect transistor 200 .

[0026] The substrate 100 includes a base 110P and an epitaxial layer 120N formed on the base 110P. The base 110P is specifically a base of the second doping type, and the epitaxial layer 120N is specifically an epitaxial layer of the first doping type.

[0027] It should be noted that the first doping type and the second doping type are opposite doping types, for example, if the first doping type is N-type, the second doping type is P-type; or, if the first doping type is P-type, the second doping type is N-type. In this embodiment, the first doping type is N-type and the second doping type is P-type as an example for explanation.

[0028] Further, the field effect transistor 200 specifically includes a drain region 200D of a first doping type, a source region 200S of a first doping type, and a gate structure 200G, wherein the drain region 200D and the source region 200S are specifically formed in the epitaxial layer 120N of the substrate 100, and the gate structure 200G is specifically formed on the substrate 100 and is located between the source region 200S and the drain region 200D. It should be understood that the gate structure 200G is located between the source region 200S and the drain region 200D, which means that it is located between the source region 200S and the drain region 200D in the horizontal direction, and the horizontal direction here refers to the direction parallel to the substrate. In this embodiment, the field effect transistor 200 is, for example, an LDMOS tube, wherein the epitaxial layer 120N located in the transistor region can be used to form the drift region of the LDMOS tube.

[0029] Continue to refer Figure 1 As shown, an isolation structure 300 is provided on the outside of the field effect transistor 200, and the isolation structure 300 is used to isolate the high-voltage side circuit and the field effect transistor 200 to prevent leakage from affecting the functions between devices. In one example, the isolation structure 300 can surround the transistor region from the high-voltage side of the transistor region (i.e., the side close to the drain region 200D) to the low-voltage side of the transistor region (i.e., the side close to the source region 200S).

[0030] Among them, the isolation structure 300 includes at least one isolation doping region of the second doping type, and the isolation doping region of the second doping type (for example, a P-type isolation region) is specifically formed in the epitaxial layer 120N to achieve device isolation using PN junction isolation technology. By performing PN reverse bias on the PN junction isolation, the depletion layer of the PN junction isolation structure can be expanded to improve the device's anti-punchdown performance.

[0031] In a specific example, the isolation structure 300 is formed on the epitaxial layer 120N and penetrates the epitaxial layer 120N to reach the substrate 110P. Further, the isolation structure 300 includes at least two isolation doping regions arranged in sequence from bottom to top and interconnected, thereby penetrating the epitaxial layer 120N in the height direction, wherein the isolation doping region located at the bottom extends upward from the substrate 110P to the epitaxial layer 120N. In this embodiment, the isolation structure 300 includes three isolation doping regions, including a first buried region PBL1 of a second doping type, a first deep well region DPW1 of a second doping type, and a first shallow well region PW1 of a second doping type, which are arranged in sequence from bottom to top and interconnected, and the first shallow well region PW1 described here is a well region with a doping depth shallower than that of the first deep well region DPW1, and the first deep well region DPW1 is a well region with a doping depth deeper than that of the first shallow well region PW1. Specifically, the first shallow well region PW1 extends inward from the top surface of the substrate 100, and partially overlaps with the first deep well region DPW1 therebelow in the height direction. The first deep well region DPW1 partially overlaps with the first buried region PBL1 therebelow in the height direction. The first buried region PBL1 spans the interface between the epitaxial layer 120N and the base 110P, so that the first shallow well region PW1, the first deep well region DPW1 and the first buried region PBL1 are connected up and down and penetrate the epitaxial layer 120N.

[0032] It should be recognized that the isolation structure 300 in this embodiment includes three isolation doping regions, while in other examples, the isolation structure 300 may include two isolation doping regions or more than three isolation doping regions, as long as the isolation doping regions within the isolation structure 300 can be interconnected and penetrate the epitaxial layer 120N.

[0033] In addition, the isolation structure 300 may further include a first isolation oxide layer 310, which is formed on the top surface of the substrate 100 and is located above the isolation doping region. The first isolation oxide layer 310 may be formed, for example, by a local oxidation isolation process (Local Oxidation of Silicon, LOCOS). When the substrate 100 is a silicon substrate, the first isolation oxide layer 310 may be a silicon oxide layer.

[0034] In this embodiment, the field effect transistor 200 also includes a buried doped region 400N of a first doping type, and the buried doped region 400N is arranged in the epitaxial layer 120N, specifically in the drift region between the drain region 200D and the gate structure 200G, and the buried doped region 400N is closer to the drain region 200D relative to the gate structure 200G, and the distance between the buried doped region 400N and the substrate 110P is greater than or equal to a set threshold.

[0035] By burying the buried doping region 400N, the ion doping concentration of the drift region between the source region 200S and the drain region 200D (i.e., in the transistor region) can be increased, thereby reducing the resistance of the region, which is beneficial to improving the ability of the level shifter to discharge current after breakdown, thereby achieving the purpose of improving the self-protection performance of the device. Wherein the epitaxial layer 120N is, for example, N-type doped, then the buried doping region 400N is correspondingly N-type doped, and the concentration of the N-type doping ions in the buried doping region 400N is greater than the depth of the N-type doping ions in the epitaxial layer 120N. Wherein, the N-type doping ions in the buried doping region 400N may, for example, include antimony (Sb) doping, or may also be other N-type doping ions, such as phosphorus ions, arsenic ions, etc. Preferably, the set threshold is 2 / 3 of the thickness of the epitaxial layer 120N, that is, the buried depth of the buried doped region 400N in the epitaxial layer 120N is relatively shallow, so as to achieve the purpose of balancing the on-resistance and the breakdown voltage, so that while reducing the on-resistance, the voltage resistance performance of the level shifter between the drain region 200D and the substrate 110P in the vertical direction can be guaranteed.

[0036] As mentioned above, the level shifter needs to withstand a higher voltage, and the width of its drift region needs to be designed to be wider. Generally, the width of the drift region is much larger than the width between the drain region and the isolation structure. If a shallower buried doped region 400N is buried between the drain region 200D and the isolation structure 300, it will easily cause the surface of the region to be easily broken down prematurely. However, when a shallower buried doped region 400N is buried between the drain region 200D and the gate structure 200G, it will not cause the surface of the region to be easily broken down prematurely.

[0037] Optionally, the buried doping region 400N is a continuously extended doping region, or the buried doping region 400N includes a plurality of sub-doping regions arranged at intervals. By designing the buried doping region 400N as a plurality of small-sized sub-doping regions, the ion concentration of the second doping type in the region can be effectively avoided from being too high. In this embodiment, a field oxide layer 220 is further formed on the surface of the substrate 100, and the gate structure 200G and the drain region 200D are isolated by the field oxide layer 220. The gate structure 200G further extends to cover the field oxide layer 220 to form a field plate structure. The field oxide layer 220 can be formed, for example, by a local oxidation isolation process (Local Oxidation of Silicon, LOCOS). When the substrate 100 is a silicon substrate, the field oxide layer 220 can be a silicon oxide layer accordingly. In this embodiment, the drain region 200D is formed between the field oxide layer 220 and the first isolation oxide layer 310. Furthermore, the field oxide layer 220 , the first isolation oxide layer 310 , and the second isolation oxide layer 210 may be formed simultaneously in the same process step by using a local oxidation isolation process.

[0038] Further, the buried doped region 400N is specifically disposed below the field oxide layer 220. Optionally, the buried doped region 400N extends downward from the lower surface of the field oxide layer 220, or there is a gap between the upper surface of the buried doped region 400N and the lower surface of the field oxide layer 220.

[0039] In this embodiment, a second shallow well region PW2 of a second doping type is also formed in the substrate 100, the second shallow well region PW2 extends downward from the top surface of the substrate 100 to the inside of the substrate, and the second shallow well region PW2 is formed on the low-voltage side of the transistor region (i.e., formed on the side of the gate structure 200G close to the source region 200S), and the source region 200S can be formed in the second shallow well region PW2. In addition, the portion of the gate structure 200G close to the source region 200S also covers the second shallow well region PW2. When a turn-on voltage is applied to the gate structure 200G of the field effect transistor 200, a conductive channel is inverted in the second shallow well region PW2 covered by the gate structure 200G to achieve current flow between the source region 200S, the conductive channel, the drift region and the drain region 200D, that is, the second shallow well region PW2 is used to form a body region of the field effect transistor 200 with a channel inversion.

[0040] A first contact region 200B (specifically, a body contact region Bulk) of a second doping type is also formed in the second shallow well region PW2, and the ion doping concentration of the first contact region 200B is greater than the ion doping concentration of the second shallow well region PW2, so as to electrically lead out the second shallow well region PW2 through the first contact region 200B. In this embodiment, the first contact region 200B is formed on a side of the source region 200S away from the gate structure 200G, and a second isolation oxide layer 210 is further provided between the first contact region 200B and the source region 200S.

[0041] In a specific example, the second shallow well region PW2 can have the same doping depth and doping concentration as the first shallow well region PW1 in the isolation structure 300. Specifically, the second shallow well region PW2 and the first shallow well region PW1 can be formed simultaneously in the same ion implantation process, so that the second shallow well region PW2 and the first shallow well region PW1 have the same parameters. In particular, the first shallow well region PW1 of the isolation structure 300 can be horizontally extended from the outside of the drain region 200D around the field effect transistor 200 to the low-voltage side of the transistor region, so that the first shallow well region PW1 is connected to the second shallow well region PW2 in the horizontal direction, so that the first shallow well region PW1 and the second shallow well region PW2 connected to each other surround the field effect transistor 200.

[0042] In this embodiment, a second deep well region DPW2 of a second doping type and a second buried region PBL2 of a second doping type are also formed in the substrate 100. The second deep well region DPW2 and the second buried region PBL2 are sequentially formed below the second shallow well region PW2 and are connected to each other. The second deep well region DPW2 may have the same doping depth and doping concentration as the first deep well region DPW1 in the isolation structure 300, and the second buried region PBL2 may have the same doping depth and doping concentration as the first buried region PBL1 in the isolation structure 300. Specifically, the second deep well region DPW2 and the first deep well region DPW1 may be formed simultaneously in the same ion implantation process, and the second buried region PBL2 and the first buried region PBL1 may also be formed simultaneously in the same ion implantation process. That is, the second shallow well region PW2 extends inward from the top surface of the substrate 100, and partially overlaps with the second deep well region DPW2 therebelow in the height direction, the second deep well region DPW2 partially overlaps with the second buried region PBL2 therebelow in the height direction, and the second buried region PBL2 extends downward from the epitaxial layer 120N to the base 110P, so that the second shallow well region PW2, the second deep well region DPW2 and the second buried region PBL2 are connected up and down and pass through the epitaxial layer 120N.

[0043] Similarly, the first buried area PBL1 and the first deep well area DPW1 in the isolation structure 300 can also be made to surround the field effect transistor 200 from the outside of the drain area 200D and extend horizontally to the low-voltage side of the transistor area (i.e., the side close to the source area 200S), so that the first deep well area DPW1 is connected to the second deep well area DPW2 in the horizontal direction, and the first buried area PBL1 is connected to the second buried area PBL2 in the horizontal direction, thereby making the interconnected first deep well area DPW1 and the second deep well area DPW2, and the interconnected first buried area PBL1 and the second buried area PBL2 surround the field effect transistor 200.

[0044] It can be considered that, on the low voltage side of the transistor region (i.e., the side close to the source region 200S), the second shallow well region PW2, the second deep well region DPW2, and the second buried region PBL2 connected up and down are also used to achieve isolation, and are horizontally connected to the isolation structure 300 to isolate the field effect transistor 200. That is, the first shallow well region PW1, the first deep well region DPW1, and the first buried region PBL1 in the isolation structure 300 are connected to the second shallow well region PW2, the second deep well region DPW2, and the second buried region PBL2 one by one, thereby forming an isolation ring surrounding the field effect transistor 200.

[0045] That is to say, the isolation doping region of the isolation structure 300 in this embodiment can be adjusted accordingly according to the doping conditions of the low voltage side. For example, on the low voltage side (i.e., the side close to the source region 200S), the depth of the second shallow well region PW2 designed to meet the performance requirements of the field effect transistor 200 is relatively small. At this time, the second deep well region DPW2 can be additionally provided so that the second shallow well region PW2, the second deep well region DPW2 and the second buried region PBL2 connected up and down can reach the substrate 110P to achieve isolation. At this time, the isolation structure 300 can be provided with the first shallow well region PW1, the first deep well region DPW1 and the first buried region PBL1; on the contrary, when the depth of the designed second shallow well region PW2 is relatively large and can be connected up and down with the second buried region PBL2 below, the second deep well region DPW2 can be omitted. At this time, the first deep well region DPW1 can be omitted in the isolation structure 300, and only the first shallow well region PW1 and the first buried region PBL1 are provided.

[0046] Continue to refer Figure 1As shown, a third well region NW1 of the first doping type is also formed in the substrate 100, and the third well region NW1 is located on the high-voltage side of the transistor region (i.e., located on the side of the gate structure 200G close to the drain region 200D), and the drain region 200D is formed in the third well region NW1. On this basis, further, the buried doping region 400N is formed between the gate structure 200G and the third well region NW1. The ion doping concentration of the third well region NW1 may be between the ion doping concentration of the drain region 200D and the ion doping concentration of the epitaxial layer 120N, so that the third well region NW1 can be used to form a buffer to avoid a large change in ion doping concentration when the drain region 200D is directly connected to the epitaxial layer 120N.

[0047] Continue to refer Figure 1 As shown, in one example, a third buried region PBL3 is further formed in the substrate 100, and the third buried region PBL3 is arranged in the transistor region, specifically arranged between the source region 200S and the drain region 200D, and more specifically arranged below the gate structure 200G and the field oxide layer 220. Furthermore, the third buried region PBL3 extends downward from the epitaxial layer 120N to the substrate 110P (or it can also be considered that the third buried region PBL3 extends upward from the substrate 110P to the epitaxial layer 120N), and the third buried region PBL3 is provided to further increase the degree of depletion of the drift region of the field effect transistor 200 below the field oxide layer 220 (in the epitaxial layer 120N). Furthermore, preferably, the third buried region PBL3 includes a plurality of sub-buried regions with small widths arranged side by side (the widths may be, for example, smaller than the widths of the first buried region PBL1), which can effectively prevent the ion concentration of the second doping type in the region from being too high.

[0048] On this basis, further, the buried doped region 400N is formed between the third buried region PBL3 and the third well region NW1. It can be understood that the buried doped region 400N is formed between the third buried region PBL3 and the third well region NW1, and the buried doped region 400N is formed between the gate structure 200G and the third well region NW1, both of which refer to one of them being located between the other two in the horizontal direction parallel to the surface of the substrate 100 shown in the figure. The buried doped region 400N is formed between the third buried region PBL3 and the third well region NW1, which can ensure the withstand voltage performance between the drain region 200D and the source region 200S.

[0049] As can be seen from the foregoing, in this embodiment, the position of the buried doped region 400N in the horizontal and vertical directions is restricted. The specific restrictions are: the spacing between the buried doped region 400N and the substrate 110P is greater than or equal to 2 / 3 of the thickness of the epitaxial layer, and the buried doped region 400N is located between the third buried region PBL3 and the third well region NW1 in the horizontal direction. In this way, the setting of the buried doped region 400N will not reduce the voltage resistance performance between the source region 200S and the drain region 200D of the field effect transistor and between the drain region 200D and the substrate 110P, and will not affect the voltage resistance performance of other regions of the device except the transistor region.

[0050] In addition, in the semiconductor device having the level shifter as described above, the semiconductor device further includes a high-voltage side circuit, which is arranged on the high-voltage side of the level shifter (i.e., the side close to the drain region 200D) and located on the side of the isolation structure 300 away from the field effect transistor 200. The high-voltage side circuit includes a fourth well region NW2 of the first doping type, and a second contact region of the first doping type is also formed in the fourth well region NW2 for achieving electrical connection with the outside. In addition, the high-voltage side circuit further includes a fourth buried region NBL of the first doping type, and the fourth buried region NBL extends upward from the substrate 110P to the epitaxial layer 120N.

[0051] In addition, the semiconductor device may further include an interconnect structure. Figure 2 As shown, the interconnect structure includes: an interlayer dielectric layer 610 formed on a substrate 100, a plurality of conductive plugs 620 formed in the interlayer dielectric layer 610, and a plurality of electrode conductive layers 630 formed on the interlayer dielectric layer 610. The interlayer dielectric layer 610 covers the semiconductor device on the substrate 100, and the plurality of conductive plugs 620 include a plug electrically connected to a source region 200S of a field effect transistor, a plug electrically connected to a drain region 200D of the field effect transistor, a plug electrically connected to a gate structure 200G of the field effect transistor, a plug electrically connected to a first contact region 200B in a second shallow well region PW2, and a plug electrically connected to a second contact region in a fourth well region NW2; and the plurality of electrode conductive layers 630 cover the corresponding conductive plugs 620 one by one, so as to electrically connect the source region 200S, the drain region 200D, the gate structure 200G, etc. to the corresponding signal ports.

[0052] Specifically, during the operation of the semiconductor device, the body contact region Bulk (i.e., the first contact region 200B) and the source region 200S can be connected to a low potential port, the gate structure 200G can be connected to an operating voltage (e.g., 25V), and the drain region 200D and the high-voltage side circuit (e.g., the second contact region in the fourth well region NW2) can be connected to a high potential port (wherein, for example, 600V is applied to the drain region 200D, and for example, 615V is applied to the high-voltage side circuit). In this process, the isolation structure 300 can be used to achieve mutual isolation between the drain region 200D and the high-voltage side circuit.

[0053] With respect to the level shifter described above, the preparation method thereof is described in detail below. Figure 1 As shown, the manufacturing method of the level shifter in this embodiment specifically includes: forming a field effect transistor 200 on a substrate 100, the field effect transistor 200 includes a drain region 200D of a first doping type, a source region 200S of a first doping type and a gate structure 200G, the drain region 200D and the source region 200S are formed in the substrate 100, and the gate structure 200G is formed on the substrate 100 and is located between the source region 200S and the drain region 200D. In addition, the manufacturing method further includes: forming an isolation structure 300 on the periphery of the field effect transistor 200, the isolation structure 300 includes at least one isolation doping region of a second doping type, and at least one buried doping region 400N of a first doping type is formed on a side of the isolation doping region close to the field effect transistor 200, the buried doping region 400N is formed in the doping layer and maintains a predetermined distance from the top surface of the doping layer.

[0054] The substrate 100 has a doped layer of the first doping type. In this embodiment, the substrate 100 includes a base 110P and an epitaxial layer 120N formed on the base 110P, and the base 110P is specifically a base of the second doping type, and the epitaxial layer 120N is specifically an epitaxial layer of the first doping type, so the epitaxial layer 120N constitutes the doped layer of the first doping type of the substrate 100.

[0055] Furthermore, the method for preparing the isolation structure 300 may include: sequentially forming at least two isolation doping regions of the second doping type (for example, P-type isolation doping regions) in the substrate 100, the at least two isolation doping regions are sequentially arranged from bottom to top and interconnected, and the isolation doping region at the bottom extends downward from the epitaxial layer 120N to the base 110P (it can also be considered that the isolation doping region at the bottom extends upward from the base 110P to the epitaxial layer 120N). In a specific example, the isolation doping region can also extend from the high-voltage side of the transistor region to the low-voltage side of the transistor region around the transistor region. In this embodiment, the isolation structure 300 specifically includes: a first buried region PBL1 of the second doping type, a first deep well region DPW1 of the second doping type, and a first shallow well region PW1 of the second doping type, which are sequentially connected to each other from bottom to top.

[0056] In an optional solution, the preparation method of the isolation structure 300 can refer to Figure 4-Figure 6 , Figure 8 Shown: First refer to Figure 4 As shown, a substrate 110P is provided, and before forming the epitaxial layer 120N, a patterned mask layer 520 is formed on the substrate 110P; an ion implantation process of a second doping type (for example, a P-type ion implantation process) is performed on the substrate 110P under the mask of the mask layer 520 to form a first buried region PBL1; then, referring to Figure 5 As shown, an epitaxial process is performed to form an epitaxial layer 120N on the substrate 110P, and during the process of epitaxially forming the epitaxial layer 120N, the ions in the first buried region PBL1 can also diffuse upward into the epitaxial layer 120N; then, referring to Figure 6 and Figure 8 As shown, the epitaxial layer 120N is subjected to two second doping type ion implantation processes (eg, P-type ion implantation processes) in sequence to form a first deep well region DPW1 and a first shallow well region PW1 in sequence.

[0057] In addition, while preparing the first buried area PBL1, the first deep well area DPW1 and the first shallow well area PW1 of the isolation structure 300, the second buried area PBL2, the second deep well area DPW2 and the second shallow well area PW2 are correspondingly formed on the low-voltage side, wherein the first buried area PBL1 and the second buried area PBL2 are interconnected to form a ring structure, the first deep well area DPW1 and the second deep well area DPW2 are interconnected to form a ring structure, and the first shallow well area PW1 and the second shallow well area PW2 are interconnected to form a ring structure, thereby forming a ring-shaped isolation ring.

[0058] In one example, the method for preparing the isolation structure 300 further includes: preparing a first isolation oxide layer 310, for details, see Figure 7As shown, the first isolation oxide layer 310 may be formed by using a local oxidation isolation process (LOCOS). In this embodiment, the second isolation oxide layer 210 and the field oxide layer 220 are formed while the first isolation oxide layer 310 is being prepared.

[0059] For details, please refer to Fig. 9 As shown, the preparation method of the buried doped region 400N includes: forming a patterned mask layer 570 on the epitaxial layer 120N, and performing a first doping type ion implantation process (for example, an N-type ion implantation process) on the epitaxial layer 120N under the mask of the mask layer 570 to form a buried doped region 400N.

[0060] The following combination Figure 3-Figure 11 A specific method for preparing a semiconductor device with a level shifter is described in detail, which includes a preparation process of the level shifter and a preparation process of other circuits (eg, a high-voltage side circuit).

[0061] First reference Figure 3 As shown, a substrate 110P is provided, and the substrate 110P is a substrate of the second doping type. In this embodiment, the substrate 110P is a P-type substrate, which can be doped with boron ions (B), and the ion concentration is, for example, 1E13cm -3 -1.5E20cm -3 Next, a mask layer 510 is formed on the substrate 110P, and a first doping type ion implantation process (eg, N-type ion implantation process) is performed under the mask of the mask layer 510 to form a fourth buried region NBL in the high-voltage side circuit region. Afterwards, the mask layer 510 may be removed.

[0062] Next reference Figure 4 As shown, a mask layer 520 is formed on the substrate 110P, and the mask layer 520 defines the pattern of the first buried area PBL1 and the pattern of the second buried area PBL2. The pattern of the first buried area PBL1 is located in the isolation area, and the pattern of the second buried area PBL2 is located on the low-voltage side of the transistor area, wherein the first buried area PBL1 surrounds the periphery of the transistor area and connects the second buried area PBL2; thereafter, a second doping type ion implantation process (for example, a P-type ion implantation process) can be performed under the mask of the mask layer 520 to form the first buried area PBL1 and the second buried area PBL2 in the substrate 110P. In this embodiment, a pattern of the third buried area PBL3 is also defined in the mask layer 520, and the pattern of the third buried area PBL3 is located in the transistor area, so that when the second doping type ion implantation process (for example, a P-type ion implantation process) is performed, the third buried area PBL3 can be simultaneously formed in the transistor area.

[0063] Next reference Figure 5 As shown, an epitaxial layer 120N is epitaxially formed on the substrate 110P. The epitaxial layer 120N is specifically an epitaxial layer of the first doping type; and the epitaxial layer 120N is, for example, phosphorus-doped, and its doping concentration is, for example, 1E14 cm -3 -1.6E20 cm -3 .

[0064] Continue to refer Figure 5 As shown, a mask layer 530 is formed on the epitaxial layer 120N, and the mask layer 530 defines the pattern of the third well region, and a first doping type ion implantation process (for example, an N-type ion implantation process) can be performed under the mask of the mask layer 540 to form a third well region NW1 in the epitaxial layer 120N. In this embodiment, a pattern of a fourth well region NW2 is also defined in the mask layer 530, and the pattern of the fourth well region NW2 is located in the region of the high-voltage side circuit, so that when the first doping type ion implantation process (for example, an N-type ion implantation process) is performed, the fourth well region NW2 can be simultaneously formed in the region of the high-voltage side circuit. Afterwards, the mask layer 530 can be removed.

[0065] Next reference Figure 6 As shown, a mask layer 540 is formed on the epitaxial layer 120N, and the mask layer 540 defines the pattern of the first deep well region DPW1 and the pattern of the second deep well region DPW2, wherein the first deep well region DPW1 surrounds the periphery of the transistor region and is connected to the second deep well region DPW2; thereafter, an ion implantation process of a second doping type (e.g., a P-type ion implantation process) can be performed under the mask of the mask layer 540 to form the first deep well region DPW1 and the second deep well region DPW2 in the epitaxial layer 120N. The bottom of the first deep well region DPW1 is connected to the first buried region PBL1 thereunder, and the bottom of the second deep well region DPW2 is connected to the second buried region PBL2 thereunder.

[0066] Next reference Figure 7 As shown, a first isolation oxide layer 310 is formed on the surface of the epitaxial layer 120N. The first isolation oxide layer 310 is formed above the isolation doping region to form an isolation structure 300 and enhance the isolation performance of the isolation structure 300. The first isolation oxide layer 310 can be formed, for example, by a local oxidation isolation process (Local Oxidation of Silicon, LOCOS), specifically comprising: forming a mask layer 550 on the epitaxial layer 120N, then performing an oxidation process to form the first isolation oxide layer 310, and then removing the mask layer 550. In this embodiment, while forming the first isolation oxide layer 310, a field oxide layer 220 and a second isolation oxide layer 210 are also formed.

[0067] Next reference Figure 8 As shown, a mask layer 560 is formed on the epitaxial layer 120N, and the mask layer 560 defines the pattern of the first shallow well region PW1 and the pattern of the second shallow well region PW2, wherein the first shallow well region PW1 surrounds the periphery of the transistor region and is connected to the second shallow well region PW2; thereafter, an ion implantation process of a second doping type (e.g., a P-type ion implantation process) can be performed under the mask of the mask layer 560 to form the first shallow well region PW1 and the second shallow well region PW2 in the epitaxial layer 120N. In addition, the bottom of the first shallow well region PW1 is connected to the first deep well region DPW1 below it, and the bottom of the second shallow well region PW2 is connected to the second deep well region DPW2 below it. In this way, an isolation ring can be formed on the periphery of the transistor region, and the second shallow well region PW2 is also used to form the body region of the channel inversion of the field effect transistor.

[0068] Next reference Fig. 9 As shown, a mask layer 570 is formed on the epitaxial layer 120N, and the mask layer 570 exposes the area of ​​the buried doped region 400N to be formed. Then, an ion implantation process of the first doping type (for example, an N-type ion implantation process) can be performed under the mask of the mask layer 530 to form the buried doped region 400N in the epitaxial layer 120N. In this embodiment, the buried doped region 400N is, for example, an Sb doped region, and the ion doping concentration of the Sb doped region is, for example, 1E14 cm -3 -1E20cm -3 The implantation energy is determined according to the target implantation depth so that the distance between the buried doped region 400N and the substrate 110P is greater than or equal to 2 / 3 of the thickness of the epitaxial layer.

[0069] Next reference Fig.10 As shown, an oxidation process is performed to form a gate oxide layer on the epitaxial layer 120N, and then a gate structure 200G is formed on the epitaxial layer 120N, and the gate structure 200G covers a portion of the second shallow well region PW2. In this embodiment, the gate structure 20G also extends to cover the field oxide layer 220 to form a field plate structure to improve the voltage resistance performance of the device.

[0070] In a further solution, a sidewall (not shown in the figure) may be formed on the sidewall of the gate structure 200G. The method for preparing the sidewall specifically includes: depositing a sidewall material, the sidewall material covers the top surface and sidewall of the gate structure 200G, and also covers the substrate surface outside the gate structure; then, performing an etch-back process to remove the sidewall material on the top surface of the gate structure, and remove the sidewall material on the top surface of the substrate, and retain the sidewall material on the sidewall of the gate structure 200G to form the sidewall.

[0071] Next reference Fig.11 As shown, a first doping type ion implantation process (e.g., N-type ion implantation process) is performed to form a source region 200S and a drain region 200D, wherein the source region 200S is formed in the second shallow well region PW2, and the drain region 200D is formed in the third well region NW1. In this embodiment, a first doping type second contact region may also be formed in the fourth well region NW2 at the same time.

[0072] Continue to refer Fig.11 As shown, a second doping type ion implantation process (eg, a P-type ion implantation process) is performed to form a first contact region 200B, wherein the first contact region 200B is formed in the second shallow well region PW2, and the ion doping concentration of the first contact region 200B is higher than the ion doping concentration of the second shallow well region PW2.

[0073] In a further embodiment, an interconnection structure is formed on the substrate 100, wherein the interconnection structure electrically connects the devices on the substrate 100. Figure 2 As shown, the preparation method of the interconnect structure includes: forming an interlayer dielectric layer 610 on a substrate 100, wherein the interlayer dielectric layer 610 covers the semiconductor devices on the substrate 100; then, forming a plurality of conductive plugs 620 in the interlayer dielectric layer 610, wherein the plurality of conductive plugs 620 include a plug electrically connected to a source region 200S of a field effect transistor, a plug electrically connected to a drain region 200D of the field effect transistor, a plug electrically connected to a gate structure 200G of the field effect transistor, a plug electrically connected to a first contact region 200B in a second shallow well region PW2, and a plug electrically connected to a second contact region in a fourth well region NW2; thereafter, forming a plurality of electrode conductive layers 630 on the interlayer dielectric layer 610, wherein the plurality of electrode conductive layers 630 cover corresponding conductive plugs 620 one by one, so as to electrically connect the source region 200S, the drain region 200D, the gate structure 200G, etc. to corresponding signal ports.

[0074] It should be noted that in Figure 2~Figure 11 The method for preparing the semiconductor device shown specifically includes the preparation process of the level shifter and the preparation process of the high-voltage side circuit. However, in other examples, when preparing the semiconductor device, the preparation process of the level shifter therein is not limited to the above method (that is, it can be formed without the above method), as long as the structure of the level shifter as described above can be prepared, and on this basis, the preparation process of other circuits (for example, the high-voltage side circuit) is combined. That is, in other examples, the method for preparing the semiconductor device includes processing on a substrate having the level shifter as described above to prepare the semiconductor device, which still falls within the scope of protection of the technical solution of the present invention.

[0075] Fig.12 A schematic diagram of a simulation comparing the surface current concentration of the drift region of the LDMOS tube provided in this embodiment and the conventional LDMOS tube. Fig.12 In FIG. 4 , the curve L1 represents the LDMOS tube provided by the present embodiment, and the curve L2 represents a conventional LDMOS tube, in which the drift region of the conventional LDMOS tube is not buried in the buried doping region 400N. Fig.12 It can be seen from the figure that after the buried doping region 400N is provided, the surface current concentration of the drift region of the LDMOS tube provided in this embodiment is significantly improved.

[0076] Fig.13 A schematic diagram of a simulation comparing the breakdown voltage of the LDMOS provided in this embodiment with that of a conventional LDMOS. Fig.13 In FIG. 4 , the curve L3 represents the LDMOS provided by the present embodiment, and the curve L4 represents the conventional LDMOS, in which the drift region of the conventional LDMOS is not buried in the buried doping region 400N. Fig.13 It can be seen from the figure that the breakdown voltage of the LDMOS provided in this embodiment is not significantly reduced after the buried doping region 400N is provided.

[0077] It can be seen that, in the LDMOS provided in this embodiment, the setting of the buried doped region 400N can significantly increase the surface current concentration of the drift region, but will not significantly reduce the breakdown voltage. Furthermore, it can be verified that the setting of the buried doped region 400N can significantly improve the ability of the level shifter to discharge current after breakdown, for example, the human body model (HBM) discharge capacity can be increased from 2KV to 2.5KV.

[0078] Although the present invention has been disclosed as above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. A level shifter, characterized in that: include: A substrate, the substrate comprising a base of a second doping type and an epitaxial layer of a first doping type stacked in sequence from bottom to top; A field effect transistor, the field effect transistor comprising a drain region of a first doping type, a source region of a first doping type, and a gate structure, the drain region and the source region are formed in the epitaxial layer, and the gate structure is formed on the epitaxial layer and is located between the source region and the drain region; an isolation doping region of a second doping type, the isolation doping region being disposed in the epitaxial layer and extending along the periphery of the field effect transistor; and A buried doped region of a first doping type is arranged in the epitaxial layer between the gate structure and the drain region, the buried doped region is closer to the drain region relative to the gate structure, and the distance between the buried doped region and the substrate is greater than or equal to a set threshold.

2. The level shifter according to claim 1, wherein: The set threshold is 2 / 3 of the thickness of the epitaxial layer.

3. The level shifter according to claim 1, wherein: The field effect transistor further comprises a field oxide layer, wherein the field oxide layer is formed on the surface of the epitaxial layer, and the gate structure and the drain region are isolated by the field oxide layer; The buried doped region extends downward from the lower surface of the field oxide layer, or there is a gap between the upper surface of the buried doped region and the lower surface of the field oxide layer.

4. The level shifter according to claim 1, wherein: The buried doping region is a continuously extending doping region, or the buried doping region includes a plurality of sub-doping regions arranged at intervals.

5. The level shifter according to claim 1, wherein: The isolation structure comprises at least two isolation doping regions which are arranged in sequence from bottom to top and are interconnected, wherein the isolation doping region located at the bottommost layer is extended upward from the substrate into the epitaxial layer.

6. The level shifter according to claim 5, wherein: At least two of the isolation doped regions include a first shallow well region of a second doping type extending inwardly from the top surface of the epitaxial layer into the epitaxial layer; as well as, The level shifter also includes a second shallow well region of a second doping type extending inward from the top surface of the epitaxial layer to the epitaxial layer, the second shallow well region is located on a side of the gate structure close to the source region, the source region is formed in the second shallow well region, and the first shallow well region extends from the outside of the drain region around the field effect transistor to the second shallow well region to be connected to the second shallow well region.

7. The level shifter according to claim 6, wherein: At least two of the isolation doped regions further include a first deep well region of the second doping type and a first buried region of the second doping type that are located below the first shallow well region and are sequentially connected from top to bottom; as well as, The level shifter also includes a second deep well region of a second doping type and a second buried region of a second doping type located below the second shallow well region and connected in sequence from top to bottom, the first deep well region extending from the outside of the drain region around the field effect transistor to the second deep well region to be connected to the second deep well region, and the first buried region extending from the outside of the drain region around the field effect transistor to the second buried region to be connected to the second buried region.

8. The level shifter according to claim 1, wherein: The level shifter comprises a third well region of a first doping type, the third well region extending downward from a surface of the epitaxial layer, and the drain region is formed in the third well region; The buried doped region is located between the third well region and the gate structure.

9. The level shifter according to claim 1, wherein: The level shifter comprises a third buried region of a second doping type, the third buried region is located between the source region and the drain region, and the third buried region extends upward from the substrate into the epitaxial layer; The buried doped region is located between the third buried region and the drain region.

10. A semiconductor device, characterized in that: The semiconductor device comprises the level shifter according to any one of claims 1 to 9 and a high-voltage side circuit, wherein the high-voltage side circuit is located on a side of the isolation doped region away from the field effect transistor.

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