Method for manufacturing gate oxide layer in high-voltage integration process

Abstract

The invention discloses a method for manufacturing a gate oxide layer in a high-voltage integration process, and the method comprises the following steps: 1, forming a first low-voltage gate oxide layer of a first low-voltage device, the first low-voltage device being one of low-voltage devices; step 2, forming a first hard mask layer, and removing the first hard mask layer in the medium voltage area; and 3, growing a medium-voltage gate oxide layer. And 4, removing the medium-voltage gate oxide layer on the surface of the first hard mask layer outside the medium-voltage region. And step 5, removing the first hard mask layer. And 6, removing the first low-voltage gate oxide layer outside the formation region of the first low-voltage device, wherein the first low-voltage gate oxide layer is only reserved in the formation region of the first low-voltage device. And 7, completing a forming process of a low-voltage gate oxide layer of the low-voltage device outside the forming region of the first low-voltage device. The method can reduce the loss of the oxide layer in the low-voltage region, reduce the electric leakage of the device, and improve the uniformity of the performance of the device.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and in particular to a method for manufacturing a gate oxide layer in a high voltage (HV) integration process. Background Art

[0002] The 28nm high-voltage (28HV) process is mainly used in organic light-emitting diode (OLED) screen driver chips, which are an important part of the screens of mobile phones, tablets, etc. The 28HV integration process includes three types of devices: low voltage, medium voltage, and high voltage. The main operating voltages include 0.9V, 1.2V, 8V, and 32V, and four different thicknesses of gate oxide or gate oxide layers are required.

[0003] In some applications, low-voltage devices of 0.9V are used for logic operations; low-voltage devices of 1.2V are used for MIPI modules, which is a serial interface; medium-voltage devices of 8V are used for OLED source drivers; and high-voltage devices of 32V are used for OLED gate drivers.

[0004] Multiple gate oxide processes will introduce multiple pickling steps, which will cause the step height of the device to be low, resulting in poor leakage of the device, especially small-sized devices. At the same time, the step height will also affect the uniformity of the device. Compared with the devices of the normal 28HK process, the same 0.9V device, the device in the 28HV integration process has multiple picklings, especially the gate oxide removal of the 8V device will introduce a large amount of pickling, which will lead to a low step height, thereby causing a special distribution of the device and affecting the uniformity of the device.

[0005] like Figures 1A to 1K As shown, it is a schematic diagram of the device structure in each step of the manufacturing method of the gate oxide layer in the existing high-voltage integration process; in the manufacturing method of the gate oxide layer in the existing high-voltage integration process, high-voltage devices, medium-voltage devices and various types of low-voltage devices are integrated on the semiconductor substrate 102 at the same time, and two types of low-voltage devices are used as examples for explanation below. The medium-voltage gate oxide layer 108 of the medium-voltage device and the low-voltage gate oxide layers of various low-voltage devices are formed by the following steps:

[0006] Step 1: Figure 1A As shown, a semiconductor substrate 102 is provided in which a high voltage gate oxide layer 104 has been formed in a high voltage region 101a.

[0007] A field oxide layer 103 is formed in the semiconductor substrate 102, and an active region is defined by the field oxide layer 103. The field oxide layer 103 includes shallow trench isolation, Figure 1A In the present invention, shallow trench isolation is also represented by STI.

[0008] like Figure 1A As shown, before step 1, a first pad oxide layer 105 is formed on the surface of the active area outside the high voltage area 101a.

[0009] Figure 1A The high pressure area is indicated by 101a, the medium pressure area is indicated by 101b, and the two low pressure areas are indicated by 101c and 101d respectively. Figure 1A The 32V shown in the figure is the operating voltage of the high-voltage device, 8V is the operating voltage of the medium-voltage device, 1.2V is the operating voltage of one low-voltage device, and 0.9V is the operating voltage of another low-voltage device. The corresponding areas are high-voltage area 101a, medium-voltage area 101b, low-voltage area 101c and low-voltage area 101d.

[0010] Step 2: Figure 1B As shown, the first pad oxide layer 105 is removed.

[0011] Step 3: Figure 1C As shown, a new second pad oxide layer 106 is grown.

[0012] Step 4: Figure 1D As shown, a first hard mask layer 107 is formed. Typically, the material of the first hard mask layer 107 includes silicon nitride. Figure 1D The first hard mask layer 107 is also represented by SiN.

[0013] Step 5: Figure 1E As shown, photolithography and etching are performed to remove the first hard mask layer 107 of the medium voltage region 101 b.

[0014] After removing the first hard mask layer 107, the etching process further includes lowering the top surface of the exposed active area from the first position to the second position to meet the requirements of subsequent Figure 1G As shown, after the growth of the intermediate voltage gate oxide layer 108 is completed, the top surface of the intermediate voltage gate oxide layer 108 is flush with the first position.

[0015] Step 6: Figure 1F As shown, the first hard mask layer 107 is removed.

[0016] Step 7: Figure 1G As shown, a medium voltage gate oxide layer 108 is grown. The medium voltage gate oxide layer 108 is formed on the surface of the active region and the field oxide layer 103 exposed in the medium voltage region 101 b and extends outside the medium voltage region 101 b.

[0017] Typically, the steps of growing the intermediate voltage gate oxide layer 108 include:

[0018] The bottom portion of the gate oxide layer 108 is grown by an ISSG process first.

[0019] The HTO process is then performed to complete the growth of the top portion of the intermediate voltage gate oxide layer 108 .

[0020] Step 8: Figure 1H As shown, the medium voltage gate oxide layer 108 outside the medium voltage region 101b is removed. The process includes the following steps:

[0021] The photoresist 109 is patterned by a photolithography process to cover the medium voltage area 101 b and leave other areas open.

[0022] Then, etching is performed to remove the medium voltage gate oxide layer 108 outside the medium voltage region 101b. When the medium voltage gate oxide layer 108 is removed, the field oxide layer 103 will be greatly lost, resulting in a step-down phenomenon at the position indicated by the arrow line 110 , which will affect the uniformity of the device and have an adverse effect on the performance of the device.

[0023] Step 9: Fig. 1I As shown, a low-voltage gate oxide layer 111 corresponding to the low-voltage device corresponding to the low-voltage region 101c is formed.

[0024] Step 9: Figure 1J As shown, a photolithography process is first used to form a pattern of a photoresist 112 to open the low-voltage area 101d outside the low-voltage area 101c.

[0025] Afterwards, etching is performed using the photoresist 109 as a mask to remove the low voltage gate oxide layer 111 in the open area.

[0026] Step 10: Figure 1K As shown, a low voltage gate oxide layer 113 is formed in the low voltage region 101d. Summary of the invention

[0027] The technical problem to be solved by the present invention is to provide a method for manufacturing a gate oxide layer in a high-voltage integrated process, which can ensure that when there are multiple types of low-voltage devices, the loss of the oxide layer in the low-voltage area, especially the field oxide layer, is reduced, thereby reducing the leakage of the device and improving the uniformity of the device performance.

[0028] In order to solve the above technical problems, in the method for manufacturing a gate oxide layer in a high-voltage integration process provided by the present invention, a high-voltage device, a medium-voltage device and various types of low-voltage devices are integrated on a semiconductor substrate at the same time, and the types of the low-voltage devices are distinguished according to the operating voltage; the medium-voltage gate oxide layer of the medium-voltage device and the low-voltage gate oxide layers of the various low-voltage devices are formed by the following steps:

[0029] Step 1: A first low-voltage gate oxide layer is formed on the surfaces of the active areas of the medium-voltage area and each low-voltage area on the semiconductor substrate, wherein the first low-voltage gate oxide layer is a gate oxide layer of a first low-voltage device, and the first low-voltage device is one of the low-voltage devices; the active area is isolated by a field oxide layer, the medium-voltage area is a formation area of ​​the medium-voltage device, and the low-voltage area is a formation area of ​​the low-voltage device.

[0030] Step 2: forming a first hard mask layer, and performing photolithography and etching to remove the first hard mask layer in the medium voltage area.

[0031] Step three: growing a medium voltage gate oxide layer, wherein the medium voltage gate oxide layer is formed on the surfaces of the active area and the field oxide layer exposed in the medium voltage region and extends to the surface of the first hard mask layer outside the medium voltage region.

[0032] Step 4: removing the medium voltage gate oxide layer on the surface of the first hard mask layer outside the medium voltage region.

[0033] Step five: removing the first hard mask layer.

[0034] Step six: removing the first low-voltage gate oxide layer outside the formation area of ​​the first low-voltage device, and the first low-voltage gate oxide layer is retained only in the formation area of ​​the first low-voltage device.

[0035] Step seven: completing a process for forming a low-voltage gate oxide layer of the low-voltage device outside a formation region of the first low-voltage device.

[0036] A further improvement is that, before step 1, a high voltage gate oxide layer has been formed in the high voltage region, and the thickness of the high voltage gate oxide layer is greater than the thickness of the medium voltage gate oxide layer.

[0037] A further improvement is that the semiconductor substrate comprises a silicon substrate.

[0038] A further improvement is that the field oxide layer includes shallow trench isolation.

[0039] A further improvement is that before step one, a first pad oxide layer is formed on the surface of the active area outside the high voltage area; and before forming the first low voltage gate oxide layer in step one, a step of removing the first pad oxide layer is also included.

[0040] A further improvement is that in step 2, the material of the first hard mask layer includes silicon nitride.

[0041] A further improvement is that in step two, after removing the first hard mask layer, the etching process also includes lowering the top surface of the exposed active area from a first position to a second position, so as to ensure that the top surface of the medium voltage gate oxide layer is flush with the first position after the subsequent growth of the medium voltage gate oxide layer is completed.

[0042] A further improvement is that in step three, the sub-step of growing the medium voltage gate oxide layer includes:

[0043] An in-situ steam oxidation (ISSG) process is first performed to grow the bottom portion of the medium voltage gate oxide layer.

[0044] A high temperature oxidation (HTO) process is then performed to complete the growth of the top portion of the medium voltage gate oxide layer.

[0045] A further improvement is that the first low-voltage device is the low-voltage device with the largest operating voltage among the various low-voltage devices.

[0046] A further improvement is that the low-voltage components include at least two types.

[0047] A further improvement is that the operating voltage of the first low-voltage device is 1.2V, and the operating voltage of the other low-voltage device is 0.9V.

[0048] A further improvement is that the operating voltage of the medium voltage device is 8V.

[0049] The operating voltage of the high voltage device is 32V.

[0050] A further improvement is that, in step four, the medium voltage gate oxide layer on the surface of the first hard mask layer outside the medium voltage area is removed by using a photolithography and etching process.

[0051] The present invention forms a first low-voltage gate oxide layer of a low-voltage device, i.e., a first low-voltage gate oxide layer of a first low-voltage device, on the surface of the active area of ​​each area before growing the first hard mask layer for defining the formation area of ​​the medium-voltage gate oxide layer. After the growth of the medium-voltage gate oxide layer is completed, the protective effect of the first hard mask layer is utilized. When the medium-voltage gate oxide layer outside the medium-voltage area is removed, the field oxide layer at the bottom of the first hard mask layer is not affected. Therefore, the consumption of excessive oxide layer, especially the field oxide layer, in the low-voltage area when removing the medium-voltage gate oxide layer in the existing method is eliminated. Therefore, the present invention can ensure that when there are multiple types of low-voltage devices, the loss of oxide layer, especially the field oxide layer, in the low-voltage area is reduced, thereby reducing the leakage of the device and improving the uniformity of the device performance.

[0052] In the present invention, the photomask used when removing the medium-voltage gate oxide layer outside the medium-voltage region is the same as the photomask of the existing method. The present invention does not add an additional photomask layer, and only needs to change the process flow to achieve it, so the present invention does not increase the process cost. In addition, when removing the medium-voltage gate oxide layer outside the medium-voltage region, the present invention can also use the self-alignment definition effect of the first hard mask layer to remove the medium-voltage gate oxide layer outside the medium-voltage region, so the present invention can also save a layer of photomask, which can further reduce the process cost.

[0053] In addition, in the present invention, since the first low-voltage gate oxide layer is formed before the medium-voltage gate oxide layer, the first low-voltage gate oxide layer can be used to replace the pad oxide layer formed before the medium-voltage gate oxide layer in the existing method, and after removing the first hard mask layer, there is no need to remove the first low-voltage gate oxide layer outside the medium-voltage area, while in the existing method, a step of removing the pad oxide layer outside the medium-voltage area is required. Therefore, the present invention can eliminate the adverse effects caused by removing the pad oxide layer outside the medium-voltage area, such as the adverse effects on the medium-voltage gate oxide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments:

[0055] Figure 1A-Figure 1K It is a schematic diagram of the device structure in each step of the manufacturing method of the gate oxide layer in the existing high-voltage integration process;

[0056] Figure 2 is a flow chart of a method for manufacturing a gate oxide layer in a high voltage integration process according to an embodiment of the present invention;

[0057] Figure 3A-Figure 3I It is a schematic diagram of the device structure in each step of the method for manufacturing a gate oxide layer in a high voltage integration process according to an embodiment of the present invention. DETAILED DESCRIPTION

[0058] like Figure 2 As shown, it is a flow chart of a method for manufacturing a gate oxide layer in a high voltage integration process according to an embodiment of the present invention; FIG. 3A to FIG. 3I As shown, it is a schematic diagram of the device structure in each step of the method for manufacturing a gate oxide layer in a high-voltage integration process in an embodiment of the present invention; in the method for manufacturing a gate oxide layer in a high-voltage integration process in an embodiment of the present invention, a high-voltage device, a medium-voltage device and various types of low-voltage devices are integrated on a semiconductor substrate 202 at the same time, and the types of the low-voltage devices are distinguished according to the operating voltage; the medium-voltage gate oxide layer 208 of the medium-voltage device and the low-voltage gate oxide layers of the various low-voltage devices are formed by the following steps:

[0059] Step 1: Figure 3BAs shown, a first low-voltage gate oxide layer 206 is formed on the surfaces of the active regions of the medium-voltage region 201 b and each low-voltage region 201 c on the semiconductor substrate 202 .

[0060] The first low-voltage gate oxide layer 206 is the gate oxide layer of the first low-voltage device, and the first low-voltage device is one of the low-voltage devices; the active area is isolated by the field oxide layer 203, the medium-voltage area 201b is the formation area of ​​the medium-voltage device, and the low-voltage area 201c is the formation area of ​​the low-voltage device.

[0061] In the embodiment of the present invention, before step one, a high voltage gate oxide layer 204 has been formed in the high voltage region 201 a , and the thickness of the high voltage gate oxide layer 204 is greater than the thickness of the medium voltage gate oxide layer 208 .

[0062] In some embodiments, the semiconductor substrate 202 includes a silicon substrate.

[0063] The field oxide layer 203 includes shallow trench isolation, Figure 3A In the present invention, shallow trench isolation is also represented by STI.

[0064] like Figure 3A As shown, before step one, a first liner oxide layer 205 is formed on the surface of the active area outside the high voltage area 201a; before forming the first low voltage gate oxide layer 206 in step one, a step of removing the first liner oxide layer 205 is also included.

[0065] In the embodiment of the present invention, the low-voltage components include at least two types.

[0066] Figure 3A Two types of low-voltage devices are shown in FIG. 1 , and the corresponding low-voltage regions are respectively denoted as low-voltage regions 201c1 and 201c2. The low-voltage region 201c1 is a formation region of the first low-voltage device, and the low-voltage region 201c2 is a formation region of another type of low-voltage device.

[0067] In some embodiments, the operating voltage of the first low-voltage device is 1.2V, and the operating voltage of another low-voltage device is 0.9V. The operating voltage of the medium-voltage device is 8V. The operating voltage of the high-voltage device is 32V, and Figure 3A The corresponding operating voltages are shown in the corresponding active regions, namely 0.9 V, 1.2 V, 8 V and 32 V. In other embodiments, the operating voltages of the devices may be different from 0.9 V, 1.2 V, 8 V and 32 V. When the operating voltages are different, the specific thickness of the corresponding gate oxide layer needs to be adjusted accordingly according to the actual process.

[0068] Step 2: Figure 3C As shown, a first hard mask layer 207 is formed.

[0069] like Figure 3D As shown, photolithography and etching are performed to remove the first hard mask layer 207 of the medium voltage area 201 b.

[0070] In the embodiment of the present invention, the material of the first hard mask layer 207 includes silicon nitride. In other embodiments, other alternative materials can also be used, as long as they can achieve selective etching with the oxide layer.

[0071] After removing the first hard mask layer 207, the etching process further includes lowering the top surface of the exposed active area from a first position to a second position to meet the requirements of subsequent Figure 3E As shown, after the growth of the medium voltage gate oxide layer 208 is completed, the top surface of the medium voltage gate oxide layer 208 is flush with the first position.

[0072] Step 3: Figure 3E As shown, a medium voltage gate oxide layer 208 is grown, and the medium voltage gate oxide layer 208 is formed on the surface of the active area and the field oxide layer 203 exposed in the medium voltage region 201b and extends to the surface of the first hard mask layer 207 outside the medium voltage region 201b.

[0073] In the embodiment of the present invention, the steps of growing the medium voltage gate oxide layer 208 include:

[0074] The bottom portion of the intermediate voltage gate oxide layer 208 is first grown by an ISSG process.

[0075] The HTO process is then performed to complete the growth of the top portion of the intermediate voltage gate oxide layer 208 .

[0076] Step 4: Figure 3F As shown, the medium voltage gate oxide layer 208 on the surface of the first hard mask layer 207 outside the medium voltage region 201 b is removed.

[0077] In the embodiment of the present invention, the medium voltage gate oxide layer 208 on the surface of the first hard mask layer 207 outside the medium voltage region 201 b is removed by using a photolithography and etching process.

[0078] In other embodiments, the photolithography process can also be omitted. A layer of material can be filled in the opening of the first hard mask layer 207 to protect the bottom medium voltage gate oxide layer 208, and then the surface of the first hard mask layer 207 outside the medium voltage area 201b including the top surface and the side of the medium voltage gate oxide layer 208 can be removed.

[0079] Step 5: Figure 3G As shown, the first hard mask layer 207 is removed.

[0080] In the embodiment of the present invention, a wet process is used to remove the first hard mask layer 207, and phosphoric acid is used as an etching solution.

[0081] Step 6: Figure 3H As shown, the first low-voltage gate oxide layer 206 outside the formation area of ​​the first low-voltage device is removed, and the first low-voltage gate oxide layer 206 is retained only in the formation area of ​​the first low-voltage device.

[0082] like Figure 3H As shown, step six includes the following sub-steps:

[0083] First, a photoresist 209 pattern is formed by a photolithography process to open a low-voltage area outside the formation area of ​​the first low-voltage device. Figure 3H Since the low-voltage region outside the formation area of ​​the first low-voltage device includes only one low-voltage region 201c2, only the low-voltage region 201c2 needs to be opened.

[0084] Afterwards, etching is performed using the photoresist 209 as a mask to remove the first low-voltage gate oxide layer 206 in the open area.

[0085] Step 7: Fig. 3I As shown, the process of forming the low-voltage gate oxide layer 210 of the low-voltage device outside the formation area of ​​the first low-voltage device is completed.

[0086] Fig. 3I In the embodiment, since there is only one low-voltage region 201c2 outside the low-voltage region 201c1, only one low-voltage gate oxide layer 210 needs to be formed. In other embodiments, when there are more than three low-voltage devices, the step of removing the low-voltage gate oxide layer of the low-voltage region corresponding to step 6 and the step of forming a new low-voltage gate oxide layer corresponding to step 7 need to be repeated, which will not be repeated here.

[0087] In the embodiment of the present invention, the first low-voltage device is the low-voltage device with the largest working voltage among the various low-voltage devices. Thus, the first low-voltage gate oxide layer 206 is the thickest layer among all low-voltage gate oxide layers. In other embodiments, the first low-voltage device can also be selected as the low-voltage device of other working electrical instruments.

[0088] Before growing the first hard mask layer 207 for defining the formation area of ​​the medium voltage gate oxide layer 208, the embodiment of the present invention first forms a first low voltage gate oxide layer 206 of a low voltage device, i.e., a first low voltage device, on the surface of the active area of ​​each area. After the growth of the medium voltage gate oxide layer 208 is completed, the protective effect of the first hard mask layer 207 is utilized. When the medium voltage gate oxide layer 208 outside the medium voltage area 201b is removed, the field oxide layer 203 at the bottom of the first hard mask layer 207 is not affected. Therefore, the consumption of excessive oxide layer, especially the field oxide layer 203, in the low voltage area 201c when removing the medium voltage gate oxide layer 208 in the existing method is eliminated. Therefore, the embodiment of the present invention can ensure that when there are multiple types of low voltage devices, the loss of the oxide layer, especially the field oxide layer 203, in the low voltage area 201c is reduced, thereby reducing the leakage of the device and improving the uniformity of the device performance.

[0089] In the embodiment of the present invention, the photomask used when removing the medium-voltage gate oxide layer 208 outside the medium-voltage region 201b is the same as the photomask of the existing method. The embodiment of the present invention does not add an additional photomask layer, and only needs to change the process flow to achieve it. Therefore, the embodiment of the present invention does not increase the process cost. In addition, when removing the medium-voltage gate oxide layer 208 outside the medium-voltage region 201b, the embodiment of the present invention can also use the self-alignment definition effect of the first hard mask layer 207 to remove the medium-voltage gate oxide layer 208 outside the medium-voltage region 201b. In this way, the embodiment of the present invention can also save a layer of photomask, which can further reduce the process cost.

[0090] In addition, in the embodiment of the present invention, since the first low-voltage gate oxide layer 206 is formed before the medium-voltage gate oxide layer 208, the first low-voltage gate oxide layer 206 can be used to replace the pad oxide layer formed before the medium-voltage gate oxide layer 208 in the existing method, and after removing the first hard mask layer 207, there is no need to remove the first low-voltage gate oxide layer 206 outside the medium-voltage area 201b, while the existing method requires a step of removing the pad oxide layer outside the medium-voltage area 201b. Therefore, the embodiment of the present invention can eliminate the adverse effects caused by removing the pad oxide layer outside the medium-voltage area 201b, such as the adverse effects on the medium-voltage gate oxide layer 208.

[0091] The embodiment of the present invention can reduce the low voltage device caused by multiple acid washes without adding a photomask through process optimization, thereby optimizing the leakage and uniformity degradation of the device. For example, without adding a photomask, it can avoid the large amount of acid wash (wet) introduced by the 8V gate oxide removal in the existing process, and can avoid the device leakage and uniformity degradation caused by the low STI of 0.9V and 1.2V devices.

[0092] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A method for manufacturing a gate oxide layer in a high voltage integrated process, characterized in that: A high-voltage device, a medium-voltage device and various types of low-voltage devices are integrated on a semiconductor substrate at the same time, and the types of the low-voltage devices are differentiated according to the operating voltage; a medium-voltage gate oxide layer of the medium-voltage device and low-voltage gate oxide layers of the various low-voltage devices are formed by the following steps: Step 1: forming a first low-voltage gate oxide layer on the surface of the active area of ​​the medium-voltage area and each low-voltage area on the semiconductor substrate, wherein the first low-voltage gate oxide layer is a gate oxide layer of a first low-voltage device, and the first low-voltage device is one of the low-voltage devices; the active area is isolated by a field oxide layer, the medium-voltage area is a formation area of ​​the medium-voltage device, and the low-voltage area is a formation area of ​​the low-voltage device; Step 2: forming a first hard mask layer, and performing photolithography and etching to remove the first hard mask layer in the medium voltage area; Step 3: growing a medium voltage gate oxide layer, wherein the medium voltage gate oxide layer is formed on the surface of the active area and the field oxide layer exposed in the medium voltage region and extends to the surface of the first hard mask layer outside the medium voltage region; Step 4, removing the medium voltage gate oxide layer on the surface of the first hard mask layer outside the medium voltage area; Step 5: removing the first hard mask layer; Step 6: removing the first low-voltage gate oxide layer outside the formation area of ​​the first low-voltage device, and the first low-voltage gate oxide layer is retained only in the formation area of ​​the first low-voltage device; Step seven: completing a process for forming a low-voltage gate oxide layer of the low-voltage device outside a formation region of the first low-voltage device.

2. The method for manufacturing a gate oxide layer in a high voltage integrated process according to claim 1, characterized in that: Before step 1, a high voltage gate oxide layer has been formed in the high voltage region, and the thickness of the high voltage gate oxide layer is greater than the thickness of the medium voltage gate oxide layer.

3. The method for manufacturing a gate oxide layer in a high voltage integrated process according to claim 1, characterized in that: The semiconductor substrate includes a silicon substrate.

4. The method for manufacturing a gate oxide layer in a high voltage integrated process according to claim 1, characterized in that: The field oxide layer includes shallow trench isolation.

5. The method for manufacturing a gate oxide layer in a high voltage integrated process according to claim 2, characterized in that: Before step one, a first pad oxide layer is formed on the surface of the active area outside the high voltage area; before forming the first low voltage gate oxide layer in step one, a step of removing the first pad oxide layer is also included.

6. The method for manufacturing a gate oxide layer in a high voltage integrated process according to claim 1, characterized in that: In step 2, the material of the first hard mask layer includes silicon nitride.

7. The method for manufacturing a gate oxide layer in a high voltage integrated process according to claim 1, characterized in that: In step 2, after removing the first hard mask layer, the etching process also includes lowering the top surface of the exposed active area from a first position to a second position to ensure that the top surface of the intermediate voltage gate oxide layer is flush with the first position after the subsequent growth of the intermediate voltage gate oxide layer is completed.

8. The method for manufacturing a gate oxide layer in a high voltage integrated process according to claim 1, characterized in that: In step three, the sub-steps of growing the medium voltage gate oxide layer include: Firstly, an ISSG process is performed to grow the bottom portion of the intermediate voltage gate oxide layer; Then, a HTO process is performed to complete the growth of the top portion of the medium voltage gate oxide layer.

9. The method for manufacturing a gate oxide layer in a high voltage integrated process according to claim 1, characterized in that: The first low-voltage device is the low-voltage device with the largest operating voltage among the various low-voltage devices.

10. The method for manufacturing a gate oxide layer in a high voltage integrated process according to claim 1, characterized in that: The low-voltage components include at least two types.

11. The method for manufacturing a gate oxide layer in a high voltage integrated process according to claim 10, characterized in that: The operating voltage of the first low-voltage device is 1.2V, and the operating voltage of the other low-voltage device is 0.9V.

12. The method for manufacturing a gate oxide layer in a high voltage integrated process according to claim 11, characterized in that: The working voltage of the medium voltage device is 8V; The operating voltage of the high voltage device is 32V.

13. The method for manufacturing a gate oxide layer in a high voltage integrated process according to claim 1, characterized in that: In step 4, the medium voltage gate oxide layer on the surface of the first hard mask layer outside the medium voltage region is removed by using a photolithography and etching process.

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