Forming method of multistage field plate structure

Abstract

The invention provides a method for forming a multistage field plate structure, which comprises the following steps of: providing a semiconductor structure, and depositing and forming an ONO layer on the semiconductor structure, the ONO layer comprising an upper oxide layer, a middle nitride layer and a lower oxide layer; coating photoresist on the ONO layer, and sequentially performing wet etching on the upper oxide layer, the middle nitride layer and the lower oxide layer according to the patterned photomask; and depositing a metal layer and etching to form a multi-stage field plate structure. Through one-step photoetching and one-step wet etching, the multi-stage field plate structure is formed by utilizing the wet etching selection ratio of SiO2 and SIN, so that the photoetching and etching steps are greatly reduced, the process flow is simplified, and the cost is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuits, in particular to a diffusion oxidation process, and specifically to a method for forming a multi-level field plate structure. Background Art

[0002] Usually, the structure of high-voltage power devices can be divided into a cell area and a terminal protection area. In the blocking state, as the anode pressure increases, the electric field strength inside the device increases accordingly. When the maximum electric field reaches the strongest electric field that the device can withstand, the current increases sharply and cannot withstand the pressure. It is believed that the device fails due to avalanche breakdown, thus limiting the maximum operating voltage of the device. The place where the maximum electric field appears may be inside the device, such as the bottom of the groove, or it may be at the edge of the device. At the edge of the cell area, due to the large potential difference between the outermost tube and the substrate, avalanche breakdown often occurs at the device terminal in post-tapeline testing. Therefore, the design of the terminal structure needs to be considered when designing the chip to ensure the voltage resistance characteristics of the device.

[0003] For the terminal of high-voltage power devices, field plate structures are very common, and the types of field plate structures are also very diverse. Multi-level field plates are widely used in ultra-high voltage power devices and GaN power devices, but they usually require complex process flows to achieve, such as multiple lithography and multiple etching steps to form a graded field plate. Summary of the invention

[0004] In view of this, the present invention provides a method for forming a multi-level field plate structure, which is used to optimize semiconductor technology, reduce photolithography and etching steps, and reduce costs.

[0005] The present invention provides a method for forming a multi-level field plate structure, comprising the following steps:

[0006] Step 1, providing a semiconductor structure, and depositing an ONO layer on the semiconductor structure, wherein the ONO layer includes an upper oxide layer, a middle nitride layer, and a lower oxide layer;

[0007] Step 2: coating the ONO layer with photoresist, and sequentially wet-etching the upper silicon oxide layer, the middle nitride layer and the lower silicon oxide layer according to a patterned photomask;

[0008] Step 3: depositing a metal layer and etching to form a multi-level field plate structure.

[0009] Preferably, the semiconductor structure in step 1 is a substrate or an AlGaN / GaN heterojunction epitaxial layer.

[0010] Preferably, the ONO layer in step 1 is formed by a chemical vapor deposition method.

[0011] Preferably, the material of the upper oxide layer and the lower oxide layer in step 1 is silicon dioxide.

[0012] Preferably, the material of the intermediate nitride layer in step one is silicon nitride.

[0013] Preferably, in step 2, the ONO layer is wet-etched using a wet etching selectivity ratio of silicon dioxide and silicon nitride.

[0014] Preferably, in step 2, an undercut is formed at the notch after etching the upper oxide layer.

[0015] Preferably, in step 2, after etching the intermediate nitride layer, a nitride layer slope with a very small angle is formed on the bottom surface of the groove.

[0016] Preferably, in step 2, after etching the lower oxide layer, a stepped groove side surface is formed.

[0017] Preferably, after step 2 and before step 3, a step of removing the photoresist is also included.

[0018] The present invention etches the ONO layer by one-step photolithography and one-step wet etching, utilizing the wet etching selection ratio of SiO2 and SIN. During etching, the uppermost oxide layer SiO2 is etched first, at which time the etching rate is relatively fast. After etching SiO2, the nitride layer SIN begins to be etched and a SIN slope with a very small angle is generated. After etching SIN, the lower oxide layer SiO2 continues to be etched to form a graded field plate structure, thereby reducing the photolithography and etching steps, simplifying the process flow and being conducive to reducing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0020] Figure 1 A flowchart showing a method for forming a multi-level field plate structure according to an embodiment of the present invention;

[0021] Figure 2 It is a schematic diagram showing the structure after the deposition of an ONO layer according to an embodiment of the present invention;

[0022] Figure 3 Shown is a schematic diagram of the structure after photolithography of the photoresist coating according to an embodiment of the present invention;

[0023] Figure 4 It is a schematic diagram of the structure after the upper silicon oxide layer is etched according to an embodiment of the present invention;

[0024] Figure 5It is a schematic diagram showing the structure after the middle nitride layer is etched according to an embodiment of the present invention;

[0025] Figure 6 Display as Figure 5 An enlarged schematic diagram of

[0026] Figure 7 It is a schematic diagram of the structure after the lower silicon oxide layer is etched according to an embodiment of the present invention;

[0027] Figure 8 Display as Figure 7 SEM schematic diagram of the structure shown;

[0028] Fig. 9 Shown is a schematic diagram of a multi-level field plate structure according to an embodiment of the present invention;

[0029] Fig.10 and Fig.11 FIG. 4 is a schematic diagram showing another multi-level field plate structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the detailed description of the present invention below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present invention without the description of these details. In order to avoid confusing the essence of the present invention, known methods, processes, flows, components and circuits are not described in detail.

[0031] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.

[0032] Unless the context clearly requires otherwise, the words "include", "comprising" and similar words throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, the meaning is "including but not limited to".

[0033] In the description of the present invention, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0034] Figure 1 The flowchart of the method for forming a multi-level field plate structure according to an embodiment of the present invention is shown. Figure 1 As shown, the following steps are included:

[0035] Step 1: Provide a semiconductor structure, and deposit an ONO layer on the semiconductor structure. The ONO layer includes an upper oxide layer, a middle nitride layer, and a lower oxide layer.

[0036] In the embodiment of the present invention, the semiconductor structure is a substrate or an AlGaN / GaN heterojunction epitaxial layer. Figure 2 As shown, the semiconductor structure is a substrate (sub); Fig.10 As shown, the semiconductor structure includes a substrate, a buffer layer, a GaN channel layer, an AlN insertion layer, and an AlGaN barrier layer from bottom to top. The material of the substrate can be Si, SiC, SiGe, GeAs, InAs, InP or other III-V or II-VI compound semiconductors. Furthermore, the material of the substrate is silicon, and the buffer layer is a GaN buffer layer.

[0037] Taking semiconductor structure as substrate as an example, Figure 2 As shown, an ONO layer is deposited on the semiconductor structure. Preferably, the ONO layer is formed by a chemical vapor deposition method. Of course, other suitable methods can also be used. The ONO layer is an oxide layer / nitride layer / oxide layer sandwich structure, including an upper oxide layer, a middle nitride layer, and a lower oxide layer. Preferably, the material of the upper oxide layer and the lower oxide layer is silicon dioxide, and the material of the middle nitride layer is silicon nitride.

[0038] Step 2: coating photoresist on the ONO layer, and wet-etching the upper silicon oxide layer, the middle nitride layer and the lower silicon oxide layer in sequence according to the patterned mask.

[0039] like Figure 3 As shown, a photoresist (PR) is coated on the ONO layer, and photolithography is performed according to the patterned mask to form a patterned photoresist. In the embodiment of the present invention, the ONO layer is wet-etched using the wet etching selectivity of silicon dioxide SiO2 and silicon nitride SIN. Specifically, as Figure 4 As shown in FIG. 1 , the upper silicon oxide layer is wet etched, and the etching rate is relatively fast at this time, forming an undercut at the notch. Figure 5 As shown in FIG. 1 , after etching the upper oxide layer, the middle nitride layer begins to be etched, forming a nitride layer slope on the bottom surface of the groove, and the slope angle is very small, as shown in FIG. Figure 6 As shown in Figure 1, it is an enlarged schematic diagram of the slope. Figure 7 As shown, after the middle nitride layer is etched, the lower oxide layer is etched continuously, and after the etching is completed, a stepped groove side surface is formed.

[0040] Figure 8 Display as Figure 7 SEM diagram of the Figure 8 As shown, the ONO layer is etched so that the side surface is stepped.

[0041] Step 3: depositing a metal layer and etching to form a multi-level field plate structure.

[0042] like Fig. 9 As shown, after the wet etching is completed, a metal layer is deposited and etched to form a multi-level field plate on the surface of the ONO layer with a stepped side.

[0043] The embodiment of the present invention etches the ONO layer by one-step photolithography and one-step wet etching, using the wet etching selectivity of SiO2 and SIN. During etching, the uppermost oxide layer SiO2 is etched first, and the etching rate is relatively fast at this time. After etching SiO2, the nitride layer SIN begins to be etched and a SIN slope with a very small angle is generated. After etching SIN, the lower oxide layer SiO2 continues to be etched to form a graded field plate structure, which reduces the photolithography and etching steps, simplifies the process flow and helps reduce costs.

[0044] Moreover, through experiments, from the simulation data of BV and electric field distribution curve, compared with the prior art, the multi-level field plate structure formed by wet etching in the embodiment of the present invention has a higher BV and a more uniform electric field distribution.

[0045] Fig.10 and Fig.11 It is a schematic diagram of another multi-level field plate structure according to an embodiment of the present invention. Fig.10 and Fig.11 As shown, a multi-level field plate structure of an embodiment of the present invention is formed on the AlGaN / GaN heterojunction epitaxial layer. The specific method is similar to the above, and will not be repeated here. Of course, the subsequent process also includes etching and then filling the source and drain electrode metal to form the source and drain electrode (S / D).

[0046] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for forming a multi-level field plate structure, characterized in that: The following steps are involved: Step 1, providing a semiconductor structure, and depositing an ONO layer on the semiconductor structure, wherein the ONO layer includes an upper oxide layer, a middle nitride layer, and a lower oxide layer; Step 2, coating the ONO layer with photoresist, and sequentially wet-etching the upper oxide layer, the middle nitride layer and the lower oxide layer according to a patterned mask; Step 3: depositing a metal layer and etching to form a multi-level field plate structure.

2. The method for forming a multi-level field plate structure according to claim 1, characterized in that: The semiconductor structure in step 1 is a substrate or an AlGaN / GaN heterojunction epitaxial layer.

3. The method for forming a multi-level field plate structure according to claim 1, characterized in that: In step 1, the ONO layer is formed by a chemical vapor deposition method.

4. The method for forming a multi-level field plate structure according to claim 1, characterized in that: The material of the upper oxide layer and the lower oxide layer in step 1 is silicon dioxide.

5. The method for forming a multi-level field plate structure according to claim 1, characterized in that: The material of the intermediate nitride layer in step 1 is silicon nitride.

6. The method for forming a multi-level field plate structure according to claim 1, characterized in that: In step 2, the ONO layer is wet-etched using a wet etching selectivity ratio of silicon dioxide and silicon nitride.

7. The method for forming a multi-level field plate structure according to claim 1, characterized in that: In step 2, an undercut is formed at the notch after etching the upper oxide layer.

8. The method for forming a multi-level field plate structure according to claim 1, characterized in that: In step 2, after the intermediate nitride layer is etched, a nitride layer slope with a very small angle is formed on the surface of the groove bottom.

9. The method for forming a multi-level field plate structure according to claim 1, characterized in that: In step 2, after the lower oxide layer is etched, a stepped groove side surface is formed.

10. The method for forming a multi-level field plate structure according to claim 1, characterized in that: After step 2 and before step 3, a step of removing the photoresist is also included.

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