Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a manufacturing method thereof. The top corner of a device isolation structure adjacent to an active region where a gate oxide layer is to be formed is etched to remove, a first recess is formed to expose the top corner surface (including the top surface and the sidewall) of the active region where the gate oxide layer is to be formed, the top corner of the active region and the device isolation structure at the first recess are further etched to round the top corner of the active region and expand the first recess into a second recess, space required for growth of the gate oxide layer is provided, stress pressing the active region is reduced, the top corner of the active region is effectively kept rounded, then an oxide film for keeping the top corner of the active region rounded is formed on the exposed surface of the active region including the top corner surface, in the subsequent process of forming the gate oxide layer, the oxide film is used to improve the growth rate uniformization and thickness uniformity of the gate oxide layer and keep the top corner of the active region rounded, thereby improving the device reliability and the yield of products, and the process is simple.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] For micron-level high voltage devices, such as Figure 1 As shown, when in-situ growing gate oxide (which is thicker than the gate oxide of low-voltage and atmospheric-voltage devices) on the surface of the active region AA using furnace tube technology, a long oxidation process is required. The sharp corners at both ends of the active region AA (such as...) Figure 1 (The dashed circle in the image) Due to lattice defects, slow sidewall growth rates, and differences in oxidation rates at different locations, the sharp corners at both ends of the active region AA surface protrude upwards after in-situ growth of the gate oxide, resulting in a sharp corner problem. Figure 2 As shown in the figure. This phenomenon can cause the gate oxide thickness at sharp corners to be below the required range, resulting in a breakdown voltage that does not meet actual requirements, thus affecting the reliability of high-voltage devices and product yield.

[0003] Therefore, ensuring the rounded corners of the active region AA during in-situ growth of gate oxide on the surface of the active region AA is one of the technical problems that urgently need to be solved in this field. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and its manufacturing method that can maintain the rounded corners of the active region after the gate oxide layer is generated, thereby improving device reliability and product yield.

[0005] To achieve the above objectives, the present invention provides a method for manufacturing a semiconductor device, comprising:

[0006] A substrate having a device isolation structure is provided, and a patterned mask layer is formed on the substrate, wherein the device isolation structure defines an active region in the substrate for which a gate oxide layer is to be formed, and the patterned mask layer exposes at least the apex corners of the active region and the device isolation structure that are adjacent to each other;

[0007] Using the patterned mask layer as a mask, the exposed corners of the device isolation structure are etched away to form a first groove that exposes the corners of the active region;

[0008] The active region and the device isolation structure at the first groove are etched, the top corner of the active region is rounded, and the first groove is expanded into a second groove;

[0009] An oxide film is formed on the surface of the active region, including the apex corner surface, to maintain the apex corner rounding of the active region;

[0010] The required gate oxide layer is formed on the active region, and during the formation of the gate oxide layer, the apex corners of the active region remain rounded under the constraint of the oxide film.

[0011] Optionally, using the patterned mask layer as a mask, wet etching is used to remove the exposed corners of the device isolation structure to form the first groove; and / or, using the patterned mask layer as a mask, isotropic etching is used to etch the active region and the device isolation structure out of the first groove, rounding the corners of the active region, and simultaneously expanding the first groove into a second groove.

[0012] Optionally, the patterned mask layer exposes the entire top surface of the active region and the top corner of the device isolation structure adjacent to the active region; using the patterned mask layer as a mask, the active region and the device isolation structure at the first groove are etched to round the top corner of the active region, and while expanding the first groove into a second groove, the top surface of the active region is also etched to flatten the top surface of the active region.

[0013] Optionally, the oxide film is formed in situ on the apex surface of the active region by a rapid annealing process or a rapid thermal oxidation process.

[0014] Optionally, ozone or a mixture of ozone and oxygen gas may be used to form the oxide film and / or the gate oxide layer.

[0015] Optionally, the step of forming the gate oxide layer includes: continuing to oxidize the top of the active region covered by the oxide film using a furnace tube oxidation process to form a first gate oxide layer, the gate oxide layer including the first gate oxide layer.

[0016] Optionally, after forming the first gate oxide layer, a second gate oxide layer is deposited on the inner surface of the second groove, the gate oxide layer comprising the first gate oxide layer and the second gate oxide layer.

[0017] Optionally, before depositing the second gate oxide layer, the inner surface of the second groove and the oxide film are further subjected to wet etching to provide a smooth process surface for the deposition of the second gate oxide layer.

[0018] Optionally, the patterned mask layer may be removed before or after forming the first gate oxide layer using a furnace tube oxidation process, and before depositing the second gate oxide layer; or, the patterned mask layer may be removed after forming the first groove, and before or after forming the oxide film.

[0019] Optionally, the manufacturing method includes at least one of the following parameters:

[0020] (1) The longitudinal depth of the second groove is

[0021] (2) The thickness of the oxide film is

[0022] (3) The thickness of the first gate oxide layer is

[0023] (4) The depth of the second groove differs from the thickness of the oxide stack on the active region after the formation of the first gate oxide layer by ±5% to ±15%.

[0024] Based on the same inventive concept, the present invention also provides a semiconductor device comprising:

[0025] A substrate having a device isolation structure is provided, wherein the device isolation structure defines an active region in the substrate into which a gate oxide layer is to be formed, the apex corner of the active region is rounded, and the apex corner of the device isolation structure adjacent to the active region is removed to form a second groove, the second groove exposing the apex corner of the active region;

[0026] An oxide film is formed on the apex surface of the active region or on the top surface of the active region including the apex surface, and is used to maintain the apex rounded corners of the active region;

[0027] A first gate oxide layer is formed on the top surface of the active region and together with the oxide film serves as part or all of the required gate oxide layer on the active region.

[0028] Optionally, the gate oxide layer further includes a second gate oxide layer located on the surface of the first gate oxide layer.

[0029] Optionally, the semiconductor device includes at least one of the following parameters:

[0030] (1) The longitudinal depth of the second groove is

[0031] (2) The thickness of the oxide film is

[0032] (3) The thickness of the first gate oxide layer is

[0033] (4) The depth of the second groove differs from the thickness of the oxide stack on the active region after the formation of the first gate oxide layer by ±5% to ±15%.

[0034] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0035] 1. The corner of the device isolation structure adjacent to the active region where the gate oxide layer is to be formed is etched away to form a first groove that exposes the corner surface of the active region (including the top surface and sidewall of the corner) where the gate oxide layer is to be formed. The corner of the active region and the device isolation structure at the first groove are further etched to round the corner of the active region and expand the first groove into a second groove, providing the space required for the growth of the gate oxide layer and reducing stress compression of the active region, thereby effectively maintaining the rounded corner of the active region. Then, an oxide film is formed on the exposed surface of the active region, including the corner surface, to maintain the rounded corner of the active region. In the subsequent gate oxide layer formation process, the oxide film can be used to improve the uniformity of the growth rate and the uniformity of the generated thickness of the gate oxide layer, further maintaining the rounded corner of the active region, thereby improving device reliability and product yield. The process is simple.

[0036] 2. When forming oxide thin films through rapid annealing or rapid thermal oxidation processes, lattice defects in the active region caused by previous threshold voltage ion implantation and other processes can also be improved.

[0037] 3. When using wet etching to remove the top corner of the device isolation structure to form the first groove, the wet etching can also remove residual oxides and impurities on the surface of the active area.

[0038] 4. When selecting the isotropic etching method to etch the active region apex and device isolation structure, rounding the active region apex and expanding the first groove into the second groove, the isotropic etching method can also be used to etch the top surface of the active region, making the top surface of the active region flattened, so as to repair problems such as crystal lattice damage in the active region caused by previous processes. Attached Figure Description

[0039] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0040] Figure 1 This is a schematic diagram of the sharp corner positions at both ends of the active region AA of an existing high-voltage device.

[0041] Figure 2 This is a scanning electron microscope (SEM) schematic diagram showing the upward-pointing sharp corners at both ends of the surface of the active region AA after in-situ growth of gate oxide using existing technology.

[0042] Figure 3 This is a schematic diagram of a semiconductor device manufacturing method according to a specific embodiment of the present invention.

[0043] Figure 4 This is a schematic cross-sectional view of the device structure in the manufacturing method of the semiconductor device according to a specific embodiment of the present invention. Detailed Implementation

[0044] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" other elements, it may be directly connected to other elements, or there may be intervening elements. Conversely, when an element is referred to as "directly connected to" other elements, there are no intervening elements. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0045] The technical solution proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0046] Please refer to Figure 3 An embodiment of the present invention provides a method for manufacturing a semiconductor device, which includes the following steps:

[0047] S1, a substrate having a device isolation structure is provided, and a patterned mask layer is formed on the substrate, wherein the device isolation structure defines an active region in the substrate from which a gate oxide layer is to be formed, and the patterned mask layer exposes at least the apex corners of the active region and the device isolation structure that are adjacent to each other;

[0048] S2, using the patterned mask layer as a mask, etch away the exposed corners of the device isolation structure to form a first groove that exposes the corners of the active region;

[0049] S3, etch the active region and the device isolation structure at the first groove, round the top corner of the active region, and expand the first groove into a second groove;

[0050] S4, an oxide film is formed on the surface of the active region, including the apex corner surface, to maintain the apex corner rounding of the active region;

[0051] S5, forming the required gate oxide layer on the active region, and during the formation of the gate oxide layer, the apex corners of the active region remain rounded under the constraint of the oxide film.

[0052] In step S1, please refer to Figure 4 In step (A), firstly, the provided substrate 100 can be any suitable semiconductor substrate material, such as pure silicon, silicon germanium (SiGe), silicon carbide (SiC), or silicon-on-insulator (SOI). Then, a device isolation structure 101 is formed in the substrate 100. This device isolation structure 101 can be a shallow trench isolation structure (STI) or a local field oxide isolation structure. This device isolation structure is used to define the active region AA to be formed in the substrate 100, as well as other active regions.

[0053] Please refer to Figure 4 In (A), taking a shallow trench isolation structure as an example, the specific steps for forming the device isolation structure 101 in the substrate 100 include:

[0054] (1) A pad oxide layer (PAD OX, not shown) is formed on the substrate 100 by any suitable process such as thermal oxidation, atomic layer deposition or plasma-enhanced chemical vapor deposition, and a hard mask layer such as silicon nitride (not shown) is further deposited on the pad oxide layer by chemical vapor deposition, and the hard mask layer is etched by photolithography and etching processes to form a patterned hard mask layer (not shown) for defining the shallow trench formation area.

[0055] (2) Using the patterned hard mask layer described above as a mask, the pad oxide layer and the substrate 100 are etched to form shallow trenches (not shown) in the substrate 100.

[0056] (3) A linear oxide layer (not shown) is formed on the inner surface of the shallow trench by thermal oxidation, atomic layer deposition or plasma-enhanced chemical vapor deposition, and then an insulating dielectric material (not shown) is deposited by a high aspect ratio filling process or a high density plasma deposition process to fill the shallow trench.

[0057] (4) The top of the insulating dielectric material is planarized to the patterned hard mask layer by chemical mechanical polishing process, thereby removing excess insulating dielectric material, thus forming a shallow trench isolation structure STI filled in the shallow trench and with a flat top surface, which serves as the device isolation structure 101, defining an active region AA in the substrate 100 (the active region can be the active region of a high voltage device).

[0058] (5) The patterned hard mask layer is removed by a wet etching process, and the top of the final device isolation structure 101 can be flush with or higher than the top of the substrate 100.

[0059] Optionally, before or after forming the shallow trench in the etched substrate 100 for fabricating the device isolation structure 101, the substrate 100 may be subjected to corresponding ion implantation, such as P-type ion implantation (e.g., boron) to form a P-well region (not shown) or N-type ion implantation (e.g., arsenic or phosphorus) to form an N-well region (not shown), or threshold voltage ion implantation to adjust the threshold voltage of the device.

[0060] In step S1, please refer to Figure 4 In step (A), after forming the device isolation structure 101, a new hard mask layer is formed by redepositing a hard mask material such as silicon nitride on the substrate surface including the active region AA and the device isolation structure 101 through processes such as chemical vapor deposition. Then, the new hard mask layer is photolithographically etched to form a patterned mask layer 102. The patterned mask layer 102 can be a single-layer film structure such as silicon nitride, or a multilayer film composite structure formed by alternating layers of silicon oxide and silicon nitride. In this embodiment, the patterned mask layer 102 exposes the top surface of the active region AA to be formed into the gate oxide layer, the vertex corner of the active region AA to be formed into the gate oxide layer adjacent to the device isolation structure 101, and the vertex corner of the active region AA to be formed into the gate oxide layer adjacent to the device isolation structure 101. For ease of description, the active region AA to be formed into the gate oxide layer will be referred to as "the active region AA" or "the active region AA" in the following text.

[0061] Please refer to Figure 4 In step (B) of the above, in step S2, under the masking effect of the patterned mask layer 102, an etchant with a high etch selectivity ratio relative to the active region AA is selected for wet etching of the device isolation structure 101. This wet etching mainly removes and sides-cuts the apex corner of the device isolation structure 101 adjacent to the active region AA, thereby forming a first groove (i.e., a small notch) 101a on the side of the device isolation structure 101 adjacent to the active region AA. The bottom of the first groove 101a is lower than the top of the active region AA, and it can expose the apex corner sidewall of the active region AA. At this time, the apex corner of the active region AA is a sharp corner 100a.

[0062] As an example, the patterned mask layer 102 also exposes the top surface of the active region AA. The wet etching in step S2 uses any suitable etching solution such as HF acid solution, SPM (a mixture of H2SO4, H2O2, and H2O) or SCI (a mixture of NH4OH, H2O2, and H2O). While etching and removing the top corner of the device isolation structure 101 adjacent to the active region AA, the wet etching also removes the residual oxides and impurities on the surface of the active region AA.

[0063] Please refer to Figure 4 In steps (B) and (C), in step S3, under the masking effect of the patterned mask layer 102 (i.e., using the patterned mask layer 102 as a mask), isotropic etching processes such as wet etching or isotropic dry etching are used to etch the apex corner of the active region AA exposed by the first groove 101a, thereby rounding the apex corner of the active region AA. At the same time, the device isolation structure 101 isotropically etched along the first groove 101a, increasing both the lateral width and longitudinal depth of the first groove 101a, ultimately expanding it into the second groove 101b (i.e., a large notch). At this time, the apex corner of the active region AA exposed by the second groove 101b is a rounded corner 100b, and the bottom surface of the second groove 101b is lower than the top surface of the active region AA.

[0064] It is worth noting that, on the one hand, the depth h1 of the second groove 101b must be greater than or equal to the stacked thickness of the oxide film and the first gate oxide layer that need to be formed on the active region AA later, so as to leave enough space for the subsequent growth of the first gate oxide layer and avoid the problem of the active region AA being squeezed due to the insufficient space of the second groove 101b during the subsequent formation of the first gate oxide layer. For example, the longitudinal depth h1 of the second groove 101b is On the other hand, the lateral width of the second groove 101b needs to be reasonably controlled to provide a sufficiently wide alignment window for the subsequent formation of the first gate oxide layer. This also prevents the remaining device isolation structure 101 from being too thin laterally, thus avoiding the "bird's beak" problem caused by oxygen molecules laterally diffusing into the active region AA outside the patterned mask layer 102 covering the side of the device isolation structure 101 during the subsequent formation of the first gate oxide layer. Furthermore, the dimensions of the second groove 101b must also meet the requirements of minimum spacing between the gate and source contact plugs of high-voltage devices, which is beneficial for the subsequent self-aligned formation of the first gate oxide layer and avoids affecting device reliability.

[0065] As an example, the lateral width of the second groove 101b is at least 10% to 20% of the lateral width of the device isolation structure 101 in which it is located, but does not exceed 50% of the lateral width of the device isolation structure 101.

[0066] Optionally, during the process of etching the apex corner of the active region AA and its adjacent device isolation structure 101 using an isotropic etching process under the masking effect of the patterned mask layer 102 (i.e., using the patterned mask layer 102 as a mask), the etching selectivity ratio between the active region AA and the device isolation structure 101 is controlled and adjusted so that the lateral distance and longitudinal distance between the rounded corner tip of the active region AA and the device isolation structure 101 are both greater than or equal to the stacking thickness of the oxide film and the first gate oxide layer to be formed subsequently.

[0067] Optionally, under the masking effect of the patterned mask layer 102 (i.e., using the patterned mask layer 102 as a mask), while using an isotropic etching process to etch the apex corner of the active region AA and its adjacent device isolation structure 101, the top surface of the active region AA is also etched using the same isotropic etching process to flatten the top surface of the active region AA and repair the crystal lattice damage in the active region AA caused by the previous process.

[0068] Please refer to Figure 4 In step (D), in step S4, under the masking effect of the patterned mask layer 102 (i.e., using the patterned mask layer 102 as a mask), any suitable process such as rapid annealing, rapid thermal oxidation (e.g., in-situ vapor generation ISSG process), or atomic layer deposition can be used to form a highly dense oxide film 103 on the exposed surface of the active region AA (i.e., the apex surface of the active region AA and the top surface of other areas of the active region AA). At this time, the oxide film 103 covers the apex surface of the active region AA and the top surface of other areas of the active region AA, and after the oxide film 103 is formed, the apex of the active region AA covered by the oxide film 103 still maintains a rounded corner of 100c. The oxide film 103 has higher density than the oxide formed by conventional thermal oxidation processes, and its thickness does not need to be too thick, as long as it can achieve the effect of maintaining the rounded corner of the active region AA in this step and subsequent processes. For example, the thickness of the oxide film 103 is...

[0069] As an example, a highly dense oxide film 103 is formed on the exposed surface of the active region AA using a rapid annealing process. This oxide film 103 can maintain the rounded corners of the active region AA in the subsequent step S5. The oxide film 103 is relatively thin, and its formation consumes very little of the thickness of the active region AA. After the oxide film 103 is formed, the corners of the active region AA below the oxide film 103 remain rounded at 100°. This rapid annealing process can form the required oxide film 103 and also repair the interface lattice damage to the active region AA caused by previous threshold voltage ion implantation and other processes.

[0070] As an example, the reaction gas used in the process of forming oxide film 103 includes ozone or a mixture of ozone and oxygen, thereby increasing the density of the formed oxide film 103. Moreover, the highly dense oxide film 103 can suppress the amount and rate of oxygen entry during the subsequent growth of the gate oxide layer, thereby controlling the uniformity of the growth rate and thickness of oxides at different positions on the surface of the active region AA exposed by the patterned mask layer 102. At the same time, it can improve the lattice defects caused by processes such as threshold voltage ion implantation in the active region AA.

[0071] Please refer to Figure 4 In step S5, under the masking effect of the patterned mask layer 102 (i.e., using the patterned mask layer 102 as a mask), the first gate oxide layer 104 can be formed by any suitable thermal oxidation process such as furnace tube thermal oxidation, wherein the reaction gas includes ozone or a mixture of ozone and oxygen.

[0072] As an example, based on the thickness requirements of the high-voltage gate oxide layer of the high-voltage device, a corresponding thermal oxidation process recipe is set. According to this process recipe, under the masking effect of the patterned mask layer 102, the required first gate oxide layer on the surface of the active region AA is formed by a furnace tube thermal oxidation process. At this time, during the furnace tube thermal oxidation process, oxygen molecules pass through the oxide film 103 and react with silicon and other materials in the active region AA below, thereby consuming a certain thickness of the top of the active region AA. As a result, the new oxide formed by the oxidation of the active region AA is fused together with the oxide film 103 to form the required first gate oxide layer 104.

[0073] During the growth of the first gate oxide layer 104b, because the space in the second groove 101b is sufficient, the active region AA will not be subjected to stress from the device isolation structure 101 during the growth of the first gate oxide layer 104b, thereby effectively maintaining the rounded corners. That is, after the formation of the first gate oxide layer, the corners of the active region AA are rounded to 100d. After the formation of the first gate oxide layer 104b, the gate oxide layer may or may not completely fill the second groove 101b.

[0074] It should be understood that, in Figure 4 In (E) and (F), the dashed lines indicate that the oxide film 103 is fused into the first gate oxide layer 104, and also indicate that the oxide film 103 can maintain the apex corner of the active region as a rounded corner during the growth of the first gate oxide layer 104.

[0075] Optionally, during the formation of the first gate oxide layer 104, a certain proportion of ozone can be used to replace oxygen in the reactant gas to improve the density of the gate oxide. Moreover, the highly dense oxide film 103 can suppress the amount and rate of oxygen entry during the growth of the first gate oxide layer 104, thereby controlling the uniformity of the growth rate and thickness of the first gate oxide layer 104. At the same time, it can improve the lattice defects caused by processes such as threshold voltage ion implantation of high voltage devices.

[0076] Optionally, the depth h1 of the second groove 101b differs from the thickness h3 of the first gate oxide layer 104 (i.e., the stacked thickness of the newly grown oxide and the original oxide film 103) by ±5% to ±15%, for example, about ±10%, in order to reduce the tip problem of the active region AA caused by the stress of the device isolation structure 101 during the formation of the first gate oxide layer 104.

[0077] As an example, the h3 of the first gate oxide layer 104 is

[0078] Alternatively, please refer to Figure 4 In step (F), after the first gate oxide layer 104 is formed, the patterned mask layer 102 is removed by any suitable process such as wet etching (an acidic etchant can be used), thereby preparing for subsequent processes such as gate manufacturing process and contact hole process.

[0079] Alternatively, after removing the patterned mask layer 102, the device surface is wet-cleaned, and a second gate oxide layer 104 (not shown) is deposited on the surface of the first gate oxide layer 104 by any suitable deposition process such as chemical vapor deposition. Thus, the gate oxide layer required on the surface of the active region AA includes the first gate oxide layer 104 and the second gate oxide layer from bottom to top, and the gate oxide layer formed on the surface of the active region AA has a better interface with the top of the device isolation structure.

[0080] In summary, the semiconductor device manufacturing method of this embodiment involves etching away the apex corner of the device isolation structure adjacent to the active region where the gate oxide layer is to be formed, creating a first groove that exposes the apex corner surface of the active region (including the top surface and sidewall of the apex corner). Further etching of the apex corner of the active region and the device isolation structure at the first groove rounds the apex corner and expands the first groove into a second groove, providing the space required for gate oxide layer growth and reducing stress compression of the active region, thereby effectively maintaining the rounded apex corner of the active region. Subsequently, an oxide film is formed on the exposed surface of the active region, including the apex corner surface, to maintain the rounded apex corner of the active region. This oxide film can be used in the subsequent gate oxide layer formation process to improve the uniformity of the gate oxide layer growth rate and the uniformity of the generated thickness, further maintaining the rounded apex corner of the active region, thereby improving device reliability and product yield. The process is simple.

[0081] It is worth noting that in this embodiment, the patterned mask layer 102 needs to be used as a mask in subsequent steps S2 to S5, and ensures that the oxide film formed in subsequent step S4 covers the top corner surface of the active region and the top surface of other regions. Therefore, the patterned mask layer 102 exposes the top surface and top corner of the active region AA to be formed with the gate oxide layer, as well as the top corner of the device isolation structure 101 adjacent to the active region, and masks the surfaces of the active regions and the device isolation structure 101 in other regions. However, the technical solution of the present invention is not limited to this.

[0082] In another embodiment of the invention, please further refer to Figure 4 The patterned mask layer 102 formed in step S1 can also serve as a mask only in steps S2 to S4. Therefore, it can only expose the top of the boundary region between the active region AA and the device isolation structure 101, that is, expose the top corner of the device isolation structure 101 adjacent to the active region and the top corner of the active region adjacent to the device isolation structure 101. Thus, under the masking effect of the patterned mask layer 102, the top side of the device isolation structure 101 is hollowed out in step S2, the groove is enlarged and the top corner of the active region is rounded in step S3, and the oxide film 103 is formed in step S4. In this case, the oxide film 102 formed in step S4 only covers the top corner surface of the active region where the gate oxide layer is to be formed. In step S5, the first gate oxide layer 104 can be formed together on the surfaces of the active region where the gate oxide layer is to be formed and other active regions.

[0083] In another embodiment of the invention, please further combine Figure 4The patterned mask layer 102 formed in step S1 can also serve as a mask only in step S2. Therefore, it can only expose the top of the boundary region between the active region AA and the device isolation structure 101, that is, expose the top corner of the device isolation structure 101 adjacent to the active region and the top corner of the active region adjacent to the device isolation structure 101. Thus, under the masking effect of the patterned mask layer 102, after the top side of the device isolation structure 101 is hollowed out in step S2, the patterned mask layer is removed. In step S3, without the masking effect of the patterned mask layer 102, the groove is enlarged and the top corner of the active region is rounded. In step S4, an oxide film is formed together on the surface of the active region where the gate oxide layer is to be formed and the other active regions. In step S5, the first gate oxide layer 104 can be formed together on the surface of the active region where the gate oxide layer is to be formed and the other active regions, or a new patterned mask layer can be formed to restrict the first gate oxide layer 104 to be formed only on the active region where the gate oxide layer is to be formed.

[0084] In yet another embodiment of the invention, please further combine Figure 4 The patterned mask layer 102 formed in step S1 can also serve as a mask only in steps S2 and S3. Therefore, it can only expose the top of the boundary region between the active region AA and the device isolation structure 101, that is, expose the top corner of the device isolation structure 101 adjacent to the active region and the top corner of the active region adjacent to the device isolation structure 101. Thus, under the masking effect of the patterned mask layer 102, the top side of the device isolation structure 101 is hollowed out in step S2, and the groove is enlarged and the top corner of the active region is rounded in step S3. After removing the patterned mask layer, an oxide film is formed together on the surface of the active region where the gate oxide layer is to be formed and the other active regions in step S4. In step S5, the first gate oxide layer 104 can be formed together on the surface of the active region where the gate oxide layer is to be formed and the other active regions, or a new patterned mask layer can be formed to restrict the first gate oxide layer 104 to be formed only on the active region where the gate oxide layer is to be formed.

[0085] Based on the above embodiments, the patterned mask layer formed in step S1 needs to expose at least the active region of the gate oxide layer to be formed and the adjacent apex corner of the device isolation structure. That is, the patterned mask layer formed in step S1 needs to expose at least the top of the boundary region of a certain width between the active region and the device isolation structure, thereby exposing the top of a certain width of the device isolation structure adjacent to the active region and the apex corner of the active region adjacent to the device isolation structure.

[0086] Based on the same inventive concept, please refer to Figure 4An embodiment of the present invention also provides a semiconductor device that can be formed using the semiconductor device manufacturing method of the present invention, the semiconductor device comprising:

[0087] A substrate 100 having a device isolation structure 101 is formed thereon, the device isolation structure 101 defining an active region AA in the substrate to be formed with a gate oxide layer, the apex corner of the active region AA being rounded, and the apex corner of the device isolation structure 101 adjacent to the active region AA being removed to form a second groove 101b, the second groove 101b exposing the apex corner surface of the active region AA.

[0088] An oxide film 103 is formed on the apex surface of the active region AA or on the top surface of the active region AA including the apex surface, and is used to keep the apex of the active region AA rounded.

[0089] A first gate oxide layer 104 is formed on the top surface of the active region and together with the oxide film 103 serves as part or all of the required gate oxide layer on the active region.

[0090] Optionally, the semiconductor device further includes a second gate oxide layer (not shown) located above the top surface of the active region and above the first gate oxide layer 104. The second gate oxide layer and the first gate oxide layer 104 are stacked to form the active region AA, constituting the desired gate oxide layer on the surface of the active region AA.

[0091] In this process, the corner rounding of the second groove 101b and the active region AA is achieved simultaneously. The first gate oxide layer 104 can be formed by fusing the new oxide formed by the thermal oxidation process with the oxide film 103. The second gate oxide layer can be formed on the first gate oxide layer 104 by the deposition process.

[0092] Optionally, the semiconductor device includes at least one of the following parameters:

[0093] (1) The longitudinal depth h1 of the second groove 101b is

[0094] (2) The thickness of the oxide film 103 is

[0095] (3) The thickness of the first gate oxide layer is

[0096] (4) The depth of the second groove h1 differs from the thickness h3 of the first gate oxide layer 104 by ±5% to ±15%.

[0097] The structure and material selection of each film layer in the semiconductor device of this embodiment can be referred to the corresponding content in the semiconductor device manufacturing method above, and will not be repeated here.

[0098] In this embodiment, the active region of the semiconductor device is rounded at the top corner, and the gate oxide layer at the top of the active region has a uniform thickness, which ensures the reliability of the device and the yield of the product.

[0099] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A substrate having a device isolation structure is provided, and a patterned mask layer is formed on the substrate, wherein the device isolation structure defines an active region in the substrate for which a gate oxide layer is to be formed, and the patterned mask layer exposes at least the apex corners of the active region and the device isolation structure that are adjacent to each other; Using the patterned mask layer as a mask, the exposed corners of the device isolation structure are etched away to form a first groove that exposes the corners of the active region; The active region and the device isolation structure at the first groove are etched, the top corner of the active region is rounded, and the first groove is expanded into a second groove; A highly dense oxide film is formed on the surface exposed in the active region, including the apex corner surface; The process of forming the gate oxide layer on the active region includes: using a furnace tube oxidation process to continue oxidizing the top of the active region covered by the oxide film to form a first gate oxide layer, the gate oxide layer including the first gate oxide layer; Wherein, the depth of the second groove is greater than or equal to the stacked thickness of the oxide film and the first gate oxide layer, the density of the oxide film is higher than that of the first gate oxide layer, and the oxide film inhibits the amount and rate of oxygen entry during the growth of the first gate oxide layer, so that the apex of the active region remains rounded under the constraint of the oxide film.

2. The manufacturing method as described in claim 1, characterized in that, Using the patterned mask layer as a mask, wet etching is used to remove the exposed corners of the device isolation structure to form the first groove; And / or, using the patterned mask layer as a mask, an isotropic etching process is used to etch the active region and the device isolation structure at the first groove, rounding the top corners of the active region, and simultaneously expanding the first groove into a second groove.

3. The manufacturing method as described in claim 1, characterized in that, The patterned mask layer exposes the entire top surface of the active region and the top corner of the device isolation structure adjacent to the active region; Using the patterned mask layer as a mask, the active area and the device isolation structure at the first groove are etched, the top corner of the active area is rounded, and while the first groove is expanded into a second groove, the top surface of the active area is also etched to make the top surface of the active area flattened.

4. The manufacturing method as described in claim 1, characterized in that, The oxide film is formed in situ on the apex surface of the active region by a rapid annealing process or a rapid thermal oxidation process.

5. The manufacturing method as described in claim 1, characterized in that, The oxide film and / or the gate oxide layer are formed using ozone or a mixture of ozone and oxygen.

6. The manufacturing method as described in claim 1, characterized in that, After forming the first gate oxide layer, the method further includes depositing a second gate oxide layer on the surface of the first gate oxide layer, wherein the gate oxide layer includes the first gate oxide layer and the second gate oxide layer.

7. The manufacturing method as described in claim 6, characterized in that, Before depositing the second gate oxide layer, the inner surface of the second groove and the first gate oxide layer are wet-etched to provide a smooth process surface for the deposition of the second gate oxide layer.

8. The manufacturing method according to any one of claims 6-7, characterized in that, The patterned mask layer is removed before or after forming the first gate oxide layer using a furnace tube oxidation process, and before depositing the second gate oxide layer; or, the patterned mask layer is removed after forming the first groove, and before or after forming the oxide film.

9. The manufacturing method as described in claim 1, characterized in that, Includes at least one of the following parameters: (1) The longitudinal depth of the second groove is 800 Å to 1000 Å; (2) The thickness of the oxide film is 40 Å ~ 50 Å; (3) The thickness of the first gate oxide layer is 1050 Å ~ 1150 Å; (4) The depth of the second groove differs from the thickness of the oxide stack on the active region after the formation of the first gate oxide layer by ±5% to ±15%.

10. A semiconductor device, characterized in that, include: A substrate having a device isolation structure is provided, wherein the device isolation structure defines an active region in the substrate into which a gate oxide layer is to be formed, the apex corner of the active region is rounded, and the apex corner of the device isolation structure adjacent to the active region is removed to form a second groove, the second groove exposing the apex corner of the active region; A highly dense oxide film is formed on the apex surface of the active region or on the top surface of the active region, including the apex surface. The first gate oxide layer is formed on the top surface of the active region by further oxidizing the top of the active region covered by the oxide film through a furnace tube oxidation process, and together with the oxide film, it serves as part or all of the required gate oxide layer on the active region. Wherein, the depth of the second groove is greater than or equal to the stacked thickness of the oxide film and the first gate oxide layer, the density of the oxide film is higher than that of the first gate oxide layer, and the oxide film suppresses the amount and rate of oxygen entry during the growth of the first gate oxide layer, so that the apex of the active region remains rounded under the constraint of the oxide film.

11. The semiconductor device as claimed in claim 10, characterized in that, The gate oxide layer further includes a second gate oxide layer located on the surface of the first gate oxide layer.

12. The semiconductor device as claimed in claim 11, characterized in that, Includes at least one of the following parameters: (1) The longitudinal depth of the second groove is 800 Å to 1000 Å; (2) The thickness of the oxide film is 40 Å ~ 50 Å; (3) The thickness of the first gate oxide layer is 1050 Å ~ 1150 Å; (4) The depth of the second groove differs from the thickness of the oxide stack on the active region after the formation of the first gate oxide layer by ±5% to ±15%.

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