Nanostructured field effect transistor devices and methods of forming same

Abstract

The invention discloses a nanostructured field effect transistor device and a method of forming the same. A method of forming a semiconductor device includes forming a gate structure over a fin protruding over a substrate; forming an interlayer dielectric (ILD) layer around the gate structure over the fin; forming a first dielectric plug and a second dielectric plug on opposite sides of the fin in the gate structure to cut the gate structure into a plurality of discrete segments; forming a patterned mask layer over the ILD layer, where an opening of the patterned mask layer exposes a segment of the gate structure interposed between the first dielectric plug and the second dielectric plug; etching the segment of the gate structure using the patterned mask layer as an etch mask to form a recess in the gate structure; extending the recess into the fin by performing an anisotropic etch process to deepen the recess; and after extending the recess, filling the recess with a dielectric material.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor devices, and more particularly to a nanostructure field effect transistor device and a method for forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by depositing insulating or dielectric layers, conductive layers, and semiconducting layers of material over a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be solved. Summary of the invention

[0004] According to a first aspect of the present disclosure, a method for forming a semiconductor device is provided, the method comprising: forming a first fin, a second fin, and a third fin protruding above a substrate and extending parallel to each other, wherein the third fin is between the first fin and the second fin; forming a gate structure above the first fin, the second fin, and the third fin; forming a gate spacer along opposite sidewalls of the gate structure; forming an interlayer dielectric (ILD) layer above the first fin, the second fin, and the third fin and around the gate structure; forming a first dielectric plug and a second dielectric plug in the gate structure, the first dielectric plug and the second dielectric plug dividing the gate structure into a plurality of segments, wherein the first dielectric plug is formed between the first fin and the third fin, and the gate structure is formed between the first fin and the third fin; forming a gate spacer along opposite sidewalls of the gate structure; forming an interlayer dielectric (ILD) layer above the first fin, the second fin, and the third fin and around the gate structure; forming a first dielectric plug and a second dielectric plug in the gate structure, the first dielectric plug and the second dielectric plug dividing the gate structure into a plurality of segments, The invention relates to a method for forming a dielectric layer on the ILD layer, wherein the dielectric layer forms a second dielectric plug between the third fin and the second fin; forming a patterned mask layer on the ILD layer, wherein a first opening of the patterned mask layer exposes a first segment of the gate structure disposed between the first dielectric plug and the second dielectric plug; performing a first etching process using the patterned mask layer as an etching mask, wherein the first etching process recesses the first segment of the gate structure and forms a recess between the gate spacers; after performing the first etching process, performing a second etching process different from the first etching process to deepen the recess, wherein after completing the second etching process, the recess extends into the substrate; and after performing the second etching process, forming a dielectric structure in the recess.

[0005] According to a second aspect of the present disclosure, a method for forming a semiconductor device is provided, the method comprising: forming a gate structure on a fin protruding above a substrate; forming an interlayer dielectric (ILD) layer around the gate structure on the fin; forming a first dielectric plug and a second dielectric plug in the gate structure on opposite sides of the fin, wherein the first dielectric plug and the second dielectric plug cut the gate structure into a plurality of segments separated from each other; forming a patterned mask layer on the ILD layer, wherein an opening of the patterned mask layer exposes a segment of the gate structure inserted between the first dielectric plug and the second dielectric plug; using the patterned mask layer as an etching mask, etching the segment of the gate structure to form a recess in the gate structure; extending the recess into the fin, wherein extending the recess comprises performing an anisotropic etching process to deepen the recess; and after extending the recess, filling the recess with a dielectric material.

[0006] According to a third aspect of the present disclosure, a method for forming a semiconductor device is provided, the method comprising: forming a gate structure on a fin protruding above a substrate; forming an interlayer dielectric (ILD) layer on the fin and around the gate structure; forming a first dielectric plug and a second dielectric plug on opposite sides of the fin in the gate structure, wherein the first dielectric plug and the second dielectric plug cut the gate structure into a plurality of discrete segments; forming a patterned mask layer on the ILD layer, wherein an opening of the patterned mask layer allows the first dielectric plug and the second dielectric plug to be formed. The gate structure is exposed by a patterned mask layer, wherein the opening of the patterned mask layer is formed to be laterally shifted a predetermined distance relative to the segment of the gate structure, and wherein, in a top view, there is a lateral offset between a longitudinal center axis of the gate structure and a center axis of the opening; using the patterned mask layer as an etching mask, etching the segment of the gate structure to form a recess in the gate structure; extending the recess into the fin, wherein extending the recess includes performing an anisotropic etching process to deepen the recess; and filling the recess with a dielectric material after extending the recess. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present disclosure may be best understood through the following detailed description. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the size of various features may be arbitrarily increased or reduced.

[0008] Figure 1 An example of a nanostructure field effect transistor (NSFET) device according to some embodiments is shown in a three-dimensional view.

[0009] Figure 2 , Figure 3A , Figure 3B , Figure 4A , Figure 4B , FIG. 5A to FIG. 5C , FIG. 6A to FIG. 6C , 7A to 7C , Fig. 8A , Figure 8B , Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , FIG. 13A to FIG. 13C , FIG. 14A to FIG. 14C , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig.19A , Fig.19B , Fig. 20A , Fig. 20B , Fig.21A , Fig.21B , FIG. 22A to FIG. 22C , Fig.23A , Fig. 23B , Fig.24A , Fig. 24B , Fig.25A , Fig.25B , Fig.26A and 26B are various views of a nanostructure field effect transistor (NSFET) device at various stages of fabrication in accordance with an embodiment.

[0010] FIG. 27A to FIG. 27C The photoresist stripping problem during patterning of the mask layer is shown.

[0011] Fig.28A and Fig.28B Patterning of a mask layer in some embodiments is shown.

[0012] Fig.29A , Fig.29B , Fig. 30A , Fig. 30B , Fig.31A , Fig.31B , Fig.32A , Fig.32B , Fig.33A , Fig.33B , Fig.34A , Fig.34B , Fig.35A , Fig.35B , FIG. 36A to FIG. 36C , Fig.37A and 37B are various views of a nanostructure field effect transistor (NSFET) device at various stages of fabrication according to another embodiment.

[0013] Fig.38A and Fig.38B Bowing during the etching process is shown.

[0014] Fig.39A and Fig.39B Together, flowcharts of methods of forming a semiconductor device in some embodiments are shown. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact.

[0016] In addition, spatially relative terms (e.g., "below," "lower," "above," "higher," etc.) may be used herein to facilitate description of the relationship of one element or feature shown in a figure relative to another (one or more) elements or (one or more) features. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other directions (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Throughout the discussion herein, unless otherwise described, the same or similar figure numbers in different figures represent the same or similar components formed by the same or similar formation processes and using (one or more) the same or similar materials. In addition, figures with the same numbers but different letters (e.g., FIG. 5A to FIG. 5C ) show different views of the device at the same processing stage.

[0017] Embodiments of the present disclosure are discussed in the context of forming nanostructure field effect transistor (NSFET) devices (eg, nanowire devices, nanosheet devices). The principles of the present disclosure can be applied to other types of devices, such as fin field effect transistor (FinFET) devices.

[0018] According to some embodiments, in order to avoid photoresist stripping problems in a continuous metal on diffusion edge (CMODE) process or a continuous polysilicon on diffusion edge (CPODE) process, the position of a cutting pattern in a photoresist layer is intentionally moved away from the central axis of the gate structure. However, moving the position of the cutting pattern may cause a bow problem of an opening formed under the cutting pattern between gate spacers of the gate structure. The present disclosure solves the bow problem by forming the opening using an anisotropic etching process with a lower etch selectivity. The low etch selectivity reduces scattered ions / radicals during etching to reduce asymmetric etching effects, thereby avoiding the bow problem. Since the bow condition may interfere with the formation of a backside via subsequently formed for connecting to a backside power rail, the disclosed embodiments reduce device failures and improve yields.

[0019] Figure 1 An example of a nanostructure field effect transistor (NSFET) device 30 according to some embodiments is shown in a three-dimensional view. The NSFET device 30 includes a semiconductor fin 90 (also referred to as a fin) protruding above a substrate 50. A gate electrode 122 (e.g., a metal gate) is disposed over the fin, and a source / drain region 112 is formed on opposite sides of the gate electrode 122. A plurality of nanostructures 54 (e.g., nanowires or nanosheets) are formed over the fin 90 and between the source / drain regions 112. An isolation region 96 is formed on opposite sides of the fin 90. A gate dielectric layer 120 is formed around the nanostructures 54. The gate electrode 122 is over and around the gate dielectric layer 120.

[0020] Figure 1 Reference cross sections used in subsequent figures are also shown. Cross section AA is along the longitudinal axis of the gate electrode 122 and in a direction, for example, perpendicular to the direction of current flow between the source / drain regions 112 of the NSFET device 30. Cross section BB is perpendicular to cross section AA and along the longitudinal axis of the fin 90 and in a direction, for example, of current flow between the source / drain regions 112 of the NSFET device. Cross section CC is parallel to cross section BB and between two adjacent fins 90. Cross section DD is parallel to cross section AA and extends through the source / drain regions 112 of the NSFET device. For clarity, subsequent figures may refer to these reference cross sections.

[0021] Figure 2 , Figure 3A , Figure 3B , Figure 4A , Figure 4B , FIG. 5A to FIG. 5C , FIG. 6A to FIG. 6C , 7A to 7C , Fig. 8A , Figure 8B , Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , FIG. 13A to FIG. 13C , FIG. 14A to FIG. 14C , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig.19A , Fig.19B , Fig. 20A , Fig. 20B , Fig.21A , Fig.21B , FIG. 22A to FIG. 22C , Fig.23A , Fig. 23B , Fig.24A , Fig. 24B , Fig.25A , Fig.25B , Fig.26A and 26B 1 are various views (eg, cross-sectional views, top views) of a nanostructure field effect transistor (NSFET) device 100 at various stages of fabrication in accordance with an embodiment.

[0022] exist Figure 2 In the embodiment, a substrate 50 is provided. Figure 2 In the example of , substrate 50 includes a lower substrate 49A and an upper substrate 49B, with an etch stop layer 51 sandwiched therebetween. In some embodiments, lower substrate 49A and upper substrate 49B are formed of the same or similar materials, and therefore may be collectively referred to as substrate 49 in the discussion herein. Substrate 49 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, or the like, which may be doped (i.e., doped with a p-type dopant or an n-type dopant) or undoped. Substrate 49 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer or a silicon oxide layer, or the like. An insulator layer is provided on a substrate, typically a silicon substrate or a glass substrate. Other substrates, such as a multilayer substrate or a gradient substrate, may also be used. In some embodiments, the semiconductor material of substrate 49 includes silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations of the foregoing.

[0023] In some embodiments, the etch stop layer 51 is used to control the stop point in the subsequent backside chemical mechanical planarization (CMP) process for thinning the substrate 50, and therefore may also be referred to as a CMP stop layer 51. The etch stop layer 51 is formed of a material different from the substrate 49 to provide etching selectivity. For example, the substrate 49 (e.g., 49A and 49B) may be formed of silicon, and the etch stop layer 51 may be formed of silicon oxide, silicon nitride, etc. As an example, the etch stop layer 51 may be formed by, for example, ion implantation into the substrate 49. As another example, the substrate 49A may be formed by a suitable formation method (e.g., chemical vapor deposition (CVD), physical vapor deposition (CVD), etc.), and then the etch stop layer 51 may be formed on the substrate 49A (e.g., using CVD, PVD, etc.). After the etch stop layer 51 is formed, the upper substrate 49B is formed on the etch stop layer 51 using any suitable formation method. In other embodiments, the etch stop layer 51 is omitted.

[0024] A multilayer stack 64 is formed on the substrate 50. The multilayer stack 64 includes alternating layers of a first semiconductor material 52 and a second semiconductor material 54. Figure 2 , the layers formed by the first semiconductor material 52 are labeled 52A, 52B, and 52C, and the layers formed by the second semiconductor material 54 are labeled 54A, 54B, and 54C. Figure 2 The number of layers formed by the first and second semiconductor materials shown is merely a non-limiting example. Other numbers of layers are possible and are fully intended to be included within the scope of the present disclosure.

[0025] In some embodiments, the first semiconductor material 52 is an epitaxial material suitable for forming a channel region of a p-type FET, such as silicon germanium (Si x Ge 1-x , where x can be in the range of 0 to 1), and the second semiconductor material 54 is an epitaxial material suitable for forming a channel region of an n-type FET, such as silicon. The multilayer stack 64 (which may also be referred to as an epitaxial material stack) will be patterned to form a channel region of the NSFET in subsequent processing. Specifically, the multilayer stack 64 will be patterned and etched to form horizontal nanostructures (e.g., nanosheets or nanowires), and the channel region of the resulting NSFET includes a plurality of horizontal nanostructures.

[0026] The multilayer stack 64 can be formed by an epitaxial growth process, which can be performed in a growth chamber. In some embodiments, during the epitaxial growth process, the growth chamber is cyclically exposed to a first set of precursors for selectively growing the first semiconductor material 52, and then exposed to a second set of precursors for selectively growing the second semiconductor material 54. The first set of precursors includes precursors for a first semiconductor material (e.g., silicon germanium), and the second set of precursors includes precursors for a second semiconductor material (e.g., silicon). In some embodiments, the first set of precursors includes a silicon precursor (e.g., silane) and a germanium precursor (e.g., germanium), and the second set of precursors includes a silicon precursor, but omits the germanium precursor. Thus, the epitaxial growth process can include enabling a silicon precursor to flow continuously to the growth chamber, and then cyclically performing the following operations: (1) enabling a germanium precursor to flow to the growth chamber while growing the first semiconductor material 52; and (2) prohibiting a germanium precursor from flowing to the growth chamber while growing the second semiconductor material 54. The cyclic exposure can be repeated until a target number of layers are formed. Although semiconductor materials (e.g., silicon, silicon germanium) are used in the above examples to form the layer stack 64, the above examples are illustrative and not limiting. For example, in embodiments where the layer labeled 52 is subsequently removed to release the second semiconductor material 54 to form a nanostructure (e.g., a nanosheet or a nanowire), the layer labeled 52 may be referred to as an interposer layer and may be formed of a suitable material (e.g., silicon oxide).

[0027] Figure 3A , Figure 3B , Figure 4A , Figure 4B , FIG. 5A to FIG. 5C , FIG. 6A to FIG. 6C , 7A to 7C , Fig. 8A , Figure 8B , Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , FIG. 13A to FIG. 13C , FIG. 14A to FIG. 14C , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig.19A , Fig.19B , Fig. 20A , Fig. 20B , Fig.21A , Fig.21B , FIG. 22A to FIG. 22C , Fig.23A , Fig. 23B , Fig.24A , Fig. 24B , Fig.25A , Fig.25B , Fig.26A and 26B are various views (eg, cross-sectional views, top views) of NSFET device 100 at subsequent fabrication stages according to an embodiment. Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19A , Fig. 20A , Fig.21A , Fig.22A , Fig.23A , Fig.24A , Fig.25A and Fig.26A is along Figure 1 Cross-sectional view of cross section BB. Figure 3B , Figure 4B , Figure 5C , Figure 6C , Figure 7C , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.19B , Fig. 20B , Fig.21B , Fig. 22B , Fig. 23B , Fig. 24B , Fig.25B and Fig.26B is along Figure 1 Cross-sectional view of cross section AA in FIG. Figure 5B , Figure 6B and Figure 7B is along Figure 1 Cross-sectional view of the cross section DD in. Fig. 13C , Fig. 14C23C is a top view (eg, plan view) of NSFET device 100. The number of fins and the number of gate structures shown in the figures are merely non-limiting examples, and it should be understood that other numbers of fins and other numbers of gate structures may also be formed.

[0028] exist Figure 3A and Figure 3B In the embodiment, a fin structure 91 protruding above the substrate 50 is formed. Each fin structure 91 includes a semiconductor fin 90 (also referred to as a fin) and a stack 92 overlying the semiconductor fin 90. The stack 92 and the semiconductor fin 90 can be formed by etching trenches in the multilayer stack 64 and the substrate 50, respectively. The stack 92 and the semiconductor fin 90 can be formed by the same etching process.

[0029] The fin structure 91 can be patterned by any suitable method. For example, the fin structure 91 can be patterned using one or more photolithography processes (including a double patterning process or a multi-patterning process). Typically, the double patterning process or the multi-patterning process combines a photolithography process and a self-alignment process, thereby allowing the generation of patterns with, for example, a pitch smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on top of a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern, for example, the fin structure 91.

[0030] In some embodiments, the remaining spacers are used to pattern the mask 94, and then the mask 94 is used to pattern the fin structure 91. Mask 94 can be a single-layer mask, or can be a multi-layer mask, such as a multi-layer mask including a first mask layer 94A and a second mask layer 94B. The first mask layer 94A and the second mask layer 94B can each be formed of a dielectric material (e.g., silicon oxide, silicon nitride, a combination thereof, etc.), and can be deposited or thermally grown according to a suitable technique. The first mask layer 94A and the second mask layer 94B are different materials with high etching selectivity. For example, the first mask layer 94A can be silicon oxide, and the second mask layer 94B can be silicon nitride. Mask 94 can be formed by patterning the first mask layer 94A and the second mask layer 94B using any acceptable etching process. Then, the mask 94 can be used as an etching mask to etch the substrate 50 and the multilayer stack 64. The etching can be any acceptable etching process, for example, reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. In some embodiments, the etching is an anisotropic etching process. After the etching process, the patterned multilayer stack 64 forms a stack 92, and the patterned portion of the substrate 50 forms a fin 90, such as Figure 3A and Figure 3B The remaining (eg, unpatterned) portion of the substrate 50 is Figure 3Aand Figure 3B and in subsequent figures is referred to as substrate 50. Thus, in the illustrated embodiment, layer stack 92 also includes alternating layers of first semiconductor material 52 and second semiconductor material 54. Fin 90 is formed of the same material(s) as substrate 50. Figure 2 In the illustrated embodiment, fin 90 includes etch stop layer 51 , upper substrate 49B, and lower substrate 49A. For simplicity, etch stop layer 51 may not be shown in all subsequent figures, and it should be understood that etch stop layer 51 may be formed in fin 90 .

[0031] Next, in Figure 4A and Figure 4B In the embodiment, a shallow trench isolation (STI) region 96 is formed over the substrate 50 and on the opposite side of the fin structure 91. As an example of forming the STI region 96, an insulating material can be formed over the substrate 50. The insulating material can be an oxide (e.g., silicon oxide), a nitride, etc., or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system and post-curing to convert it into another material (e.g., oxide)), etc., or a combination of the foregoing. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. After forming the insulating material, an annealing process can be performed.

[0032] In some embodiments, the insulating material is formed such that excess insulating material covers fin structure 91. In some embodiments, a liner is first formed along the surfaces of substrate 50 and fin structure 91, and a filler material, such as those discussed above, is formed on the liner. In some embodiments, the liner is omitted.

[0033] Next, a removal process is applied to the insulating material to remove excess insulating material above the fin structure 91. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch back process, or a combination thereof may be used. The planarization process exposes the layer stack 92 so that after the planarization process is completed, the top surface of the layer stack 92 and the top surface of the insulating material are level. Next, the insulating material is recessed to form an STI region 96. The insulating material is recessed so that the layer stack 92 protrudes from between adjacent STI regions 96. The top of the semiconductor fin 90 may also protrude from between adjacent STI regions 96. In addition, the top surface of the STI region 96 may have a flat surface (as shown), a convex surface, a concave surface (e.g., a dish), or a combination thereof. The top surface of the STI region 96 may be formed to be flat, convex, and / or concave by appropriate etching. The STI region 96 may be recessed using an acceptable etching process, for example, an etching process that is selective to the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than etching the material of the fin 90 and the layer stack 92). For example, chemical oxide removal with a suitable etchant such as dilute hydrofluoric acid (dHF) may be used.

[0034] Still reference Figure 4A and Figure 4B , a dummy dielectric layer 97 is formed over the layer stack 92 and over the STI region 96. The dummy dielectric layer 97 may be, for example, silicon oxide, silicon nitride, or a combination thereof, and the dummy dielectric layer 97 may be deposited or thermally grown according to an acceptable technique. In an embodiment, a silicon layer is conformally formed over the layer stack 92 and over the upper surface of the STI region 96, and a thermal oxidation process is performed to convert the deposited silicon layer into an oxide layer as the dummy dielectric layer 97.

[0035] Next, in FIG. 5A to FIG. 5C In the embodiment of the present invention, a dummy gate 102 is formed on the fin structure 91. In order to form the dummy gate 102, a dummy gate layer can be formed on the dummy dielectric layer 97. The dummy gate layer can be deposited on the dummy dielectric layer 97 and then planarized, for example, by CMP. The dummy gate layer can be a conductive material and can be selected from a group including amorphous silicon, polysilicon, polycrystalline silicon germanium (poly-SiGe), etc. The dummy gate layer can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known and used in the art. The dummy gate layer can be made of other materials with high etching selectivity to the STI region 96.

[0036] A mask 104 is then formed over the dummy gate electrode layer. The mask 104 may be formed of silicon nitride, silicon oxynitride, combinations thereof, and the like, and may be patterned using acceptable photolithography and etching techniques. In the illustrated embodiment, the mask 104 includes a first mask layer 104A (e.g., a silicon oxide layer) and a second mask layer 104B (e.g., a silicon nitride layer). The pattern of the mask 104 is then transferred to the dummy gate electrode layer by an acceptable etching technique to form a dummy gate electrode 102, and then transferred to the dummy dielectric layer by an acceptable etching technique to form a dummy gate dielectric 97. The dummy gate 102 covers the corresponding channel region of the layer stack 92. The pattern of the mask 104 may be used to physically separate each dummy gate 102 from an adjacent dummy gate. The dummy gate 102 may also have a length direction substantially perpendicular to the length direction of the fin structure 91. In some embodiments, the dummy gate 102 and the dummy gate dielectric 97 are collectively referred to as a dummy gate structure.

[0037] Next, a gate spacer layer 108 is formed by conformally depositing an insulating material over the layer stack 92, the STI region 96, and the dummy gate 102. The insulating material may be silicon oxide, silicon nitride, silicon carbonitride, a combination thereof, or the like. In some embodiments, the gate spacer layer 108 includes a plurality of sub-layers. For example, a first sub-layer (sometimes referred to as a gate sealing spacer layer) may be formed by thermal oxidation or deposition, and a second sub-layer (sometimes referred to as a main gate spacer layer) may be conformally deposited on the first sub-layer.

[0038] Figure 5B and Figure 5C They are shown respectively Figure 5A The NSFET device 100 is Figure 5A The cross-sectional view of the cross sections EE and FF in FIG. The cross sections EE and FF correspond to Figure 1 Cross sections DD and AA.

[0039] Next, in FIG. 6A to FIG. 6C , the gate spacer layer 108 is etched by an anisotropic etching process to form the gate spacer 108. The anisotropic etching process can remove horizontal portions of the gate spacer layer 108 (e.g., portions above the STI region 96 and the dummy gate 102), while the remaining vertical portions of the gate spacer layer 108 (e.g., portions along the sidewalls of the dummy gate 102 and the dummy gate dielectric 97) form the gate spacer 108.

[0040] After forming the gate spacers 108, implantation of lightly doped source / drain (LDD) regions (not shown) may be performed. Appropriate type (e.g., p-type or n-type) impurities may be implanted into the exposed layer stack 92 and / or semiconductor fins 90. The n-type impurities may be any suitable n-type impurities, such as phosphorus, arsenic, antimony, etc., and the p-type impurities may be any suitable p-type impurities, such as boron, BF2, indium, etc. The lightly doped source / drain regions may have a density from about 10 15 cm -3 to about 10 16 cm -3 The annealing process can be used to activate the implanted impurities.

[0041] Next, an opening 110 (also referred to as a recess) is formed in the layer stack 92. The opening 110 may extend through the layer stack 92 and into the fin 90. The opening 110 may be formed by an anisotropic etching process, for example, using the dummy gate 102 and the gate spacer 108 as an etching mask.

[0042] After the opening 110 is formed, a selective etching process is performed to recess the end of the first semiconductor material 52 exposed through the opening 110 without substantially corroding the second semiconductor material 54. After the selective etching process, a recess (also referred to as a sidewall recess) is formed in the first semiconductor material 52 at the location where the removed end was located.

[0043] Next, an internal spacer layer is formed (e.g., conformally) in the opening 110. The internal spacer layer also fills the sidewall recesses of the first semiconductor material 52 formed by the previous selective etching process. The internal spacer layer can be a suitable dielectric material, such as silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), etc., formed by a suitable deposition method such as PVD, CVD, atomic layer deposition (ALD), etc. Next, an etching process such as an anisotropic etching process is performed to remove the portion of the internal spacer layer disposed outside the sidewall recesses of the first semiconductor material 52. The remaining portion of the internal spacer layer (e.g., the portion disposed within the sidewall recesses of the first semiconductor material 52) forms an internal spacer layer 55. As shown in FIG. Fig. 6A As shown, the opening 110 exposes the sidewalls of the second semiconductor material 54 and exposes the upper surface 90U of the fin 90 .

[0044] Figure 6B and Figure 6C They are shown respectively Fig. 6A FIG. 1 is a cross-sectional view of the NSFET device 100 along cross sections EE and FF. Figure 6BIn the embodiment, portions of the gate spacer layer 108 disposed on the upper surface of the STI region 96 between adjacent fins 90 are completely removed by the anisotropic etching process used to form the gate spacer 108. In some embodiments, portions of the gate spacer layer 108 are left (e.g., remain) on the upper surface of the STI region 96 between adjacent fins 90. Since a small distance between adjacent fins 90 reduces the efficiency of the anisotropic etching process, the anisotropic etching process discussed above may not completely remove the gate spacer layer 108 disposed between adjacent fins 90, and those portions of the gate spacer layer 108 may be left as a result.

[0045] Next, in 7A to 7C In the discussion herein, source / drain regions 112 are formed in the openings 110. In the discussion herein, (one or more) source / drain regions may refer to a source or a drain, individually or collectively depending on the context. In the illustrated embodiment, the source / drain regions 112 are formed of (one or more) epitaxial materials and may therefore also be referred to as epitaxial source / drain regions 112. In some embodiments, the epitaxial source / drain regions 112 are formed in the openings 110 to apply pressure in the corresponding channel regions of the formed NSFET device to improve performance. In some embodiments, the epitaxial source / drain regions 112 are formed so that the dummy gates 102 are disposed between corresponding adjacent pairs of the epitaxial source / drain regions 112. In some embodiments, the gate spacers 108 are used to separate the epitaxial source / drain regions 112 from the dummy gates 102 by an appropriate lateral distance so that the epitaxial source / drain regions 112 do not short-circuit a subsequently formed gate of the resulting NSFET device.

[0046] Epitaxial source / drain regions 112 are epitaxially grown in openings 110. Epitaxial source / drain regions 112 may include any acceptable material, such as a material suitable for an n-type or p-type device. For example, when forming an n-type device, epitaxial source / drain regions 112 may include a material that applies tensile stress in the channel region, such as silicon, SiC, SiCP, SiP, etc. Similarly, when forming a p-type device, epitaxial source / drain regions 112 may include a material that applies compressive stress in the channel region, such as SiGe, SiGeB, Ge, GeSn, etc. The epitaxial source / drain regions 112 may have a surface that protrudes from a corresponding surface of the fin 90 and may have a facet.

[0047] The epitaxial source / drain regions 112 and / or fins 90 may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions, followed by annealing. The source / drain regions may have a dopant density of about 10 19 cm -3 and about 1021 cm -3 The n-type and / or p-type impurities used for the source / drain regions may be any of the impurities discussed above. In some embodiments, the epitaxial source / drain regions 112 may be doped in-situ during growth.

[0048] As a result of the epitaxial process used to form the epitaxial source / drain regions 112, the upper surfaces of the epitaxial source / drain regions have facets that extend laterally outward beyond the sidewalls of the fins 90. In the illustrated embodiment, adjacent epitaxial source / drain regions 112 remain separated after the epitaxial process is completed (see FIG. Figure 7B ). In other embodiments, the facets result in merging of adjacent epitaxial source / drain regions 112 of the same NSFET.

[0049] Next, a contact etch stop layer (CESL) 116 is formed over the source / drain regions 112 and over the dummy gate 102 (e.g., conformally), and then a first interlayer dielectric (ILD) 114 is deposited over the CESL 116. The CESL 116 is formed of a material having a different etch rate than the first ILD 114, and may be formed of silicon nitride using PECVD, but other dielectric materials such as silicon oxide, silicon oxynitride, combinations thereof, and the like, as well as alternative techniques for forming the CESL 116 such as low pressure CVD (LPCVD), PVD, and the like may be used instead.

[0050] The first ILD 114 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material for the first ILD 114 may include silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. Figure 7B and Figure 7C They are shown respectively Fig. 7A The NSFET device 100 but along Fig. 7A Cross-sectional view of cross sections EE and FF.

[0051] Fig. 8A , Figure 8B , Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A and Fig. 12BA replacement gate process is shown in which the dummy gate structures (eg, 102 and 97 ) are removed and replaced with replacement gate structures 123 (eg, metal gate structures).

[0052] Next, in Fig. 8A and Figure 8B In order to remove the dummy gate 102, a planarization process such as CMP is performed to make the top surfaces of the first ILD 114 and the CESL 116 flush with the top surfaces of the dummy gate 102 and the gate spacer 108. The planarization process can also remove the mask 104 on the dummy gate 102 (see Fig. 7A ), and portions of the gate spacers 108 along the sidewalls of the mask 104. After the planarization process, the top surfaces of the dummy gate 102, the gate spacers 108, the CESL 116, and the first ILD 114 are flush. Therefore, the top surface of the dummy gate 102 is exposed through the first ILD 114.

[0053] Next, the dummy gate 102 is removed in (one or more) etching steps, thereby forming the recess 103. In some embodiments, the dummy gate 102 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using (one or more) reactive gases that selectively etches the dummy gate 102 without etching the first ILD 114 or the gate spacer 108. During the removal of the dummy gate 102, the dummy gate dielectric 97 may be used as an etch stop layer when etching the dummy gate 102. The dummy gate dielectric 97 may then be removed after the dummy gate 102 is removed. Figure 8B Shows Fig. 8A A cross-sectional view of the NSFET device 100 along cross section FF.

[0054] Next, in Fig. 9A and 9B In the embodiment, the dummy gate dielectric 97 in the recess 103 is removed. An etching process such as an isotropic etching process may be performed to remove the dummy gate dielectric 97. In one embodiment, an isotropic etching process using an etching gas including HF and NH3 is performed to remove the dummy gate dielectric 97. Fig. 9A and Fig. 9B As shown, each recess 103 exposes a channel region of the NSFET. Each channel region is disposed between adjacent pairs of epitaxial source / drain regions 112.

[0055] Next, in Fig. 10A and Fig. 10BIn the embodiment of the present invention, the first semiconductor material 52 (e.g., the portion exposed by the recess 103) is removed to release the second semiconductor material 54. After removing the first semiconductor material 52, the second semiconductor material 54 (e.g., the portion below the dummy gate 102 before removing the dummy gate 102) forms a plurality of nanostructures 54 extending horizontally (e.g., parallel to the main upper surface of the substrate 50). The nanostructures 54 may be collectively referred to as the channel region 93 or channel layer 93 of the formed NSFET device 100. Fig. 10A As shown, gaps 53 (eg, empty spaces) are formed between nanostructures 54 by removing first semiconductor material 52. In some embodiments, nanostructures 54 are nanosheets or nanowires, depending on, for example, the dimensions of nanostructures 54 (eg, size and / or aspect ratio).

[0056] In some embodiments, the first semiconductor material 52 is removed by a selective etching process using an etchant that is selective to (e.g., has a higher etching rate for) the first semiconductor material 52, so that the first semiconductor material 52 is removed without substantially attacking the second semiconductor material 54. In some embodiments, an isotropic etching process is performed to remove the first semiconductor material 52. In some embodiments, the isotropic etching process is performed using an etching gas and an optional carrier gas, wherein the etching gas includes F2 and HF, and the carrier gas can be an inert gas, such as Ar, He, N2, a combination of the foregoing, and the like.

[0057] Fig. 10A A cross-sectional view of the NSFET device 100 along the longitudinal axis of the fin (eg, along the direction of current flow in the fin) is shown, and Fig. 10B A cross-sectional view of NSFET device 100 along cross-section FF is shown, which is a cross-section along a direction perpendicular to the longitudinal axis of the fin and through the middle of nanostructure 54 .

[0058] like Fig. 10A As shown, each nanostructure 54 has a rectangular cross-section along the longitudinal axis of the fin. Fig. 10B In FIG. 5 , each nanostructure 54 has a rectangular cross-section in a cross-section along a direction perpendicular to the longitudinal axis of the fin and passing through the middle of the nanostructure 54 .

[0059] Next, in Fig.11A and Fig. 11BIn some embodiments, nanostructure 54 is reshaped by a nanostructure reshaping process (e.g., an isotropic etching process). In some embodiments, nanostructure 54 is reshaped by a selective etching process using an etchant that is selective to the material of nanostructure 54 (e.g., second semiconductor material 54), so that nanostructure 54 is etched without substantially attacking other materials in NSFET device 100, such as oxide, silicon nitride, and low-K dielectric material.

[0060] In some implementations, an isotropic etching process (e.g., a selective etching process) is performed using an etching gas and an optional carrier gas to reshape the nanostructure 54, wherein the etching gas includes F2 and NH3, and the carrier gas can be an inert gas such as Ar, He, N2, a combination of the foregoing, etc.

[0061] In addition to using a mixture of F2 and NH3 as an etching gas, other suitable etching gases (e.g., ClF3, or a mixture of NF3 and NH3) may also be used alternatively as an etching gas to reshape the nanostructure 54. For example, an isotropic etching process (e.g., an isotropic plasma etching process) using an etching gas including NF3 and NH3 may be performed to reshape the nanostructure 54.

[0062] The nanostructure reshaping process thins the middle portion of each nanostructure 54, while the ends of the nanostructure 54 remain substantially unchanged, thereby producing Fig.11A In addition, the nanostructure reshaping process removes the sharp edges of the nanostructure 54 (see, for example, Fig. 10B ), thereby producing a rounded edge of each nanostructure 54 (see Fig. 11B ), as described in more detail below.

[0063] like Fig.11A As shown, after the nanostructure reshaping process, each nanostructure 54 has a dumbbell shape in a cross section along the longitudinal axis of the fin, wherein the thickness (along the cross section) of the end portion (e.g., the portion physically contacting the source / drain region 112) of the nanostructure 54 is Fig.11A In some embodiments, the difference in thickness between the ends of the nanostructure 54 and the middle of the nanostructure 54 is between about 0 nm and about 3 nm. Fig.11AIn the example of FIG. 5 , the upper and lower surfaces of the middle portion of each nanostructure 54 are shown as flush surfaces (e.g., flat surfaces). Of course, this is merely a non-limiting example. In some embodiments, the upper and lower surfaces of the middle portion of each nanostructure 54 are curved, for example, curved toward the horizontal center axis of the nanostructure 54. In addition, Fig. 11B In the cross section of , each nanostructure 54 has a stadium shape (which may also be referred to as a racetrack shape, a disc rectangular shape, an oblong shape, or a sausage shape). Fig. 11B In a cross section of , the corners of each nanostructure 54 are rounded (e.g., curved). In some embodiments, the thickness T (also referred to as the sheet thickness) of the nanostructure 54 (e.g., nanosheet) is between about 6.3 nm and about 8.2 nm, with an average value (e.g., mean) of about 7.1 nm. In some embodiments, the spacing C (also referred to as the sheet-to-sheet distance) between adjacent nanostructures 54 is between about 4.5 nm and about 5.9 nm, with an average value of about 5.2 nm. In some embodiments, the width O (also referred to as the sheet width) of the nanostructure 54 is between about 94.9 nm and about 97.5 nm, with an average value of about 96.2 nm.

[0064] As feature sizes continue to shrink in advanced process nodes, the distance between adjacent nanostructures 54 may become so small that it may be difficult to form layers (e.g., gate dielectric layers, work function layers) around the nanostructures 54 in subsequent processing. By reshaping the nanostructures 54, such as by thinning the middle of the nanostructures 54, the distance between adjacent nanostructures 54 is increased, thereby making it easier to form, for example, a gate dielectric layer 120 around the nanostructures 54 (see Fig. 12A and Fig. 12B In addition, since the thickness T of the nanostructure 54 forming the channel region 93 of the NSFET device 100 is reduced by the nanostructure reshaping process, it is easier to control (e.g., turn on or off) the NSFET device 100 by applying a gate control voltage to a metal gate formed in a subsequent process.

[0065] In some embodiments, the Fig.11A and Fig. 11B In subsequent figures, the channel region 93 of the NSFET device 100 is shown as having Fig.11A and Fig. 11B It should be understood that the channel region 93 may have a cross section of Fig. 10A and Fig. 10B cross-section (e.g., when the nanostructure reshaping process is omitted).

[0066] Next, in Fig. 12A and Fig. 12B, a gate dielectric layer 120 and a gate electrode 122 are formed to form a replacement gate. The gate dielectric layer 120 is conformally deposited in the recess 103 (e.g., on the top surface and sidewalls of the semiconductor fin 90 and on the sidewalls of the gate spacer 108). The gate dielectric layer 120 may also be formed on the top surface of the first ILD 114. It is noteworthy that the gate dielectric layer 120 is formed to surround the nanostructure 54. According to some embodiments, the gate dielectric layer 120 includes silicon oxide, silicon nitride, or a multilayer thereof. In some embodiments, the gate dielectric layer 120 is formed of a high-k dielectric material, and in these embodiments, the gate dielectric layer 120 may have a k value greater than about 7.0 and may include a metal oxide or silicate of Hf, Al, Zr, La, Mg, Ba, Ti, or Pb or a combination of the foregoing. The formation method of the gate dielectric layer 120 may include molecular beam deposition (MBD), ALD, and PECVD, etc.

[0067] Next, a gate electrode 122 is deposited over and around the gate dielectric layer 120, and the gate electrode 122 fills the remaining portion of the recess 103. The gate electrode 122 may include a metal-containing material, such as TiN, TiO, TaN, TaC, Co, Ru, Al, W, a combination of the foregoing, or multiple layers of the foregoing. For example, although a single layer gate electrode 122 is shown, the gate electrode 122 may include any number of liner layers (e.g., barrier layers), any number of work function tuning layers, and fill materials. After filling the gate electrode 122, a planarization process such as CMP may be performed to remove excess portions of the gate dielectric layer 120 and the gate electrode 122 material that are above the top surface of the first ILD 114. Thus, the gate electrode 122 and the remaining portion of the gate dielectric layer 120 material form a replacement gate for the resulting NSFET device 100. Each gate electrode 122 and the corresponding gate dielectric layer 120 may be collectively referred to as a gate stack 123 , a replacement gate structure 123 , a metal gate structure 123 , or a gate structure 123 . Each gate structure 123 extends around a corresponding nanostructure 54 .

[0068] Next, the formation process continues with the cutting of the gate structure 123 and the cutting (e.g., removal) of some of the nanostructures 54 to form isolated transistors. The cutting of the gate structure 123 is referred to as a cut metal gate (CMG) process. The cutting of the nanostructures 54 (and their corresponding portions of the fins 90 below) is referred to as a continuous metal on diffusion edge (CMODE) process, or sometimes referred to as a cut metal on diffusion edge (CMODE) process. It should be noted that in the illustrated CMODE process, the cutting of the nanostructures 54 and their corresponding underlying fins 90 is performed after the replacement gate stack 123 is formed. In the illustrated CMG process and CMODE process, some examples of cutting locations are shown, such as Fig. 13C and Fig. 22C It can be understood that the cutting process can be performed at different locations and with different sizes, depending on the design of the transistor.

[0069] exist Fig. 12A and Fig. 12B , two fins 90 and two gate structures 123 are shown. Of course, this is a non-limiting example. The number of fins 90 and the number of gate structures 123 in the NSFET device 100 can be any suitable number. FIG. 13A to FIG. 26B ), in order to facilitate the discussion of the CMG process and the CMODE process, three fins 90 (labeled as 90A, 90B and 90C) and four gate structures 123 (labeled as 123A, 123B, 123C and 123D) are shown.

[0070] Next reference FIG. 13A to FIG. 13C , a dielectric plug 125 is formed to cut the gate structure 123B into a plurality of separate segments. Fig. 13C 1 shows a top view (eg, plan view) of the NSFET device 100 after forming the dielectric plug 125. For simplicity, Fig. 13C Not all features of NSFET device 100 are shown. For example, Fig. 13C Only fins 90A, 90B, 90C (collectively referred to as fins 90 ), gate structures 123A, 123B, 123C, and 123D (collectively referred to as gate structures 123 ), gate spacers 108 surrounding sidewalls of the gate structures 123 , and dielectric plugs 125 are shown.

[0071] In some embodiments, the dielectric plug 125 is formed by forming an opening in the gate structure 123B and the first ILD 114 (e.g., using photolithography and etching techniques), and filling the opening with a dielectric material (e.g., silicon nitride, silicon oxide, a combination thereof, etc.). Next, a planarization process (e.g., CMP) may be performed to remove excess portions of the dielectric material from the upper surface of the first ILD 114, and the remaining portion of the dielectric material in the opening forms the dielectric plug 125.

[0072] In the example shown, dielectric plugs 125 are formed on opposite sides of fin 90B. Fig. 13C In the embodiment shown, one dielectric plug 125 is formed between the fins 90A and 90B, and another dielectric plug 125 is formed between the fins 90B and 90C. In the illustrated embodiment, the dimension WDP of the dielectric plug 125 measured along the direction of the cross section BB is greater than the dimension WMG of the gate structure 123B to ensure that the dielectric plug 125 cuts the gate structure 123B into separate segments that are electrically isolated from each other. Fig. 13B As shown, dielectric plug 125 extends through gate structure 123 and into STI region 96 to ensure separation of different segments of gate structure 123B. In some embodiments, dielectric plug 125 is used to remove segment 123BM of gate structure 123 in a subsequent step (see Fig. 13C ) during the etching process to protect the gate structure 123 of the segment not to be removed. It should be noted that the dielectric plug 125 is not Fig. 13C In the cross section BB, therefore Fig.13A In some embodiments, the dielectric plug 125 is omitted because the gate structure 123B is removed by removing the segment 123BM (see Fig. 13C ) is anisotropic and therefore is unlikely to damage other segments of the gate structure 123B.

[0073] Next, in Fig.14A and Fig. 14B In the embodiment of the present invention, a hard mask layer 131 (also referred to as a mask layer 131) is formed over the first ILD 114 and the gate structure 123. The hard mask layer 131 may be a single-layer hard mask formed of, for example, silicon nitride, silicon oxynitride, etc. using a suitable formation method such as CVD. In some embodiments, the hard mask layer 131 has a multi-layer structure. For example, the hard mask layer 131 may include a silicon layer sandwiched between two silicon nitride layers.

[0074] Next, an etching mask 136 is formed over the hard mask layer 131. The etching mask 136 may have a single-layer structure (may be a photoresist layer) or a double-layer structure including a bottom anti-reflective coating (BARC) layer and a photoresist layer. Fig.14A and Fig. 14B In the example of , the etching mask 136 has a three-layer structure including a bottom layer 135 (eg, a carbon-based BARC layer), a middle layer 137 (eg, a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer), and a photoresist layer 139.

[0075] Next, openings 138 are formed in the photoresist layer 139 of the etch mask 136. As will be discussed below, the openings 138 are transferred to the hard mask layer 131 and thus define the openings 132 (see FIG. Fig.15A and Fig. 15B ) in the hard mask layer 131. The opening 132 in the hard mask layer 131 allows the gate structure 123B to be disposed at Fig. 13C The dielectric plug 125 between the segments 123BM (see Fig. 13C ) is exposed. Although it can be intuitively seen that the best position of the opening 138 should be directly above and overlapped with the segment 123BM of the gate structure 123B (e.g., completely overlapped in the top view), the opening 138 in the present disclosure is intentionally (e.g., intentionally) formed to be moved away from this seemingly optimal position. Fig.14A In the example of FIG. 1 , the opening 138 has a lateral offset OVS between a central axis 138X of the opening 138 and a central axis 123BX of the gate structure 123B. Fig. 14C A top view of a NEFET device 100 in an embodiment is shown. For clarity, Fig. 14C Only the boundaries of the opening 138 (shown as a rectangle), the central axis 138X of the opening 138, the boundaries of the segment 123BM of the gate structure 123B (shown as a dashed rectangle), and the central axis 123BX of the gate structure 123B are shown. In addition to the lateral shift, Fig. 14C The dotted rectangle and the rectangle in FIG. 1 are identical. The lateral offset OVS between the center axis 1138X and the center axis 123B is Fig. 14C Since the opening 138 is transferred to the hard mask layer 131 as the opening 132, in some embodiments, the rectangle of the opening 138 also shows the opening 132 in the hard mask layer 131. Fig. 14C As shown, the opening 138 (or the opening 132 ) is formed to be laterally displaced a predetermined distance (eg, laterally offset OVS) relative to the segment 123BM of the gate structure 123B. As discussed below, the lateral offset OVS is used to reduce or avoid photoresist stripping problems.

[0076] refer to Fig.14A In some embodiments, the width of the opening 138 is denoted as WO, and the lateral offset OVS may be between about 5% and about 33% of the width WO of the opening 138 , for example between about 10% and about 33%, or between about 20% and about 30%. Fig.14A Also shown is a width WG of the gate structure 123B measured between the gate spacers 108 on opposite sides of the gate structure 123B. The width WO of the opening 138 may be the same as or similar to the width WG of the gate structure 123B.

[0077] In some embodiments, the opening 138 is intentionally (eg, purposely) formed with a lateral offset OVS to avoid photoresist stripping issues, as described below with reference to FIG. 27A to FIG. 27C as well as FIG. 28A to FIG. 28B discussed.

[0078] Temporary reference Fig.27A and Fig.27B , which respectively show the corresponding Fig.14A and 14B 1 and 13. Top view and cross-sectional view of the three-layer etch mask 136 and hard mask layer 131 of the etch mask 136 and hard mask layer 131 in FIG. Fig.27B Shown along Fig.27A A cross-sectional view of the cross section GG in FIG. It should be noted that Fig.27A Three openings 138A, 138B, and 138C (collectively referred to as openings 138) in photoresist layer 139 are shown to illustrate the reasons and advantages of having a laterally offset OVS. Fig.14A and Fig. 14B In other related figures of the illustrated embodiment, only one opening 138 is shown for simplicity, and it should be understood that a plurality of openings 138 may be formed in the photoresist layer 139, such as Fig.28A The openings shown in FIG. 1 may be the same or similar to the openings 138 shown in FIG. 1 . For example, Fig.28A The opening 138A in may correspond to Fig.14A The opening 138 in the.

[0079] exist Fig.27B In the example of FIG. 1 , the photoresist layer 139 includes two thin fin-shaped sections 139A and 139B disposed between the openings 138A and 138C. Fig.27B In FIG. 1 , the width of the fin slices 139A and 139B is represented as width S (also referred to as the spacing of the openings), the width of the opening 138 is represented as width W (also referred to as the adjacent critical dimension (CD) of the openings), and the spacing between adjacent openings 138 is represented as spacing P. In the semiconductor manufacturing process, the feature size continues to shrink. Currently, in advanced process nodes, the feature size is on the order of nanometers. Due to their size (e.g., small width S and / or high aspect ratio), the fin slices 139A and 139B may collapse. Fig.27CFIG. 1 shows an example of a fin-shaped slice 139B of the photoresist layer 139 collapsing, which is known as a photoresist stripping problem. The photoresist stripping problem tends to occur when the width W is much larger than the width S (e.g., W>>S). Therefore, if the opening 138A is moved to Fig.27B and the opening 138C is moved to the left side Fig.27B , while the position of opening 138B remains unchanged, the width S of fin slices 139A and 139B increases, and the possibility of photoresist stripping problems is reduced. Generally, if the width W is less than or equal to half of the pitch size P (e.g. ), the photoresist stripping problem can be avoided. This condition can be met by moving the positions of openings 138A and 138C as discussed above.

[0080] Fig.28A and Fig.28B The effect of moving the positions of openings 138A and 138C as discussed above is shown. Fig.28A The position of 138B remains the same as Fig.27A The same as in FIG. 1 , but the positions of openings 138A and 138C are the same as in FIG. Fig.27A The positions of the openings 138A and 138C in FIG. 1 are respectively moved to the left and right sides. For comparison, Fig.27A The openings 138A and 138C are located at Fig.28A It is shown with dashed lines (eg, dashed rectangles).

[0081] like Fig.28A As shown, in Fig.28A The central axis 138AX2 of the opening 138A and Fig.27A There is a lateral offset OVS between the central axis 138AX1 of the opening 138A in Fig.28A In some embodiments, the Fig.27A The opening 138A in Fig.28A The dashed rectangle in Fig. 13C The boundary of the segment 123BM of the gate structure 123B in FIG. 1 corresponds to (eg, completely overlaps) the boundary of the segment 123BM of the gate structure 123B in FIG. 1 , and the central axis 138AX1 corresponds to (eg, completely overlaps) the boundary of the segment 123BM of the gate structure 123B in FIG. 1 . Fig. 13C The longitudinal center axis of the gate structure 123B in FIG. 1 corresponds to the longitudinal center axis of the gate structure 123B shown in FIG. Fig. 13C The line of cross section AA in is the same. Fig.28B The width S' of the fin-shaped slices 139A and 139B and the pitch P' of the openings 138 are shown. It should be noted that the width W of the openings 138 is maintained at Fig.27B The width is the same as in. Fig.28B As shown, due to the lateral movement of the openings 138A and 138C, the width S′ of the fin-shaped slices 139A and 139B is greater than Fig.27B The width S in the opening 138 is greater than Fig.27B The spacing P in the etch process is as follows. Therefore, the photoresist stripping problem is avoided or reduced.

[0082] Next, refer to Fig.15A and Fig. 15B , using a suitable method (e.g., one or more anisotropic etching processes), the opening 138 of the photoresist layer 139 extends through the middle layer 137 and the bottom layer 135, and is transferred to the hard mask layer 131 as the opening 132. For simplicity, it is assumed that after (one or more) anisotropic etching processes, the openings 138 and 132 overlap (e.g., are the same) in the top view. Next, the etching mask 136 is removed by a suitable process (e.g., etching, grinding, a combination thereof, etc.).

[0083] Fig.15A and Fig. 15B NSFET device 100 is shown after removal of etch mask 136. Fig.15A and Fig. 15B As shown, the opening 138 is transferred to the hard mask layer 131 as an opening 132 in the hard mask layer 131. The opening 132 allows the segment 123BM (see FIG. 1 ) of the gate structure 123B disposed between the dielectric plugs 125 to be Fig. 13C ) is exposed so that the exposed segment 123BM can be removed in subsequent processing and replaced by an isolation structure, the details of which will be discussed below. In the top view, the shape of the opening 132 (e.g., rectangular) is the same as the shape defined by the boundary (e.g., sidewall) of the segment 123BM of the gate structure 123B, but has a lateral offset OVS between the central axis 132X of the opening 132 and the central axis 123BX of the gate structure 123B, as shown in FIG. Fig.28A and Fig.15A In some embodiments, the lateral offset OVS is controlled within a range such that the sidewall 132S of the opening 132 does not extend beyond the corresponding sidewall of the CESL 116 away from the gate structure 123B. In other words, the opening 132 does not expose the first ILD 114 to avoid damaging the first ILD 114 in a subsequent etching process.

[0084] Next, in Fig.16A and Fig. 16BIn the embodiment shown, an etching process is performed to recess the exposed segment of the gate structure 123B. In the embodiment shown, the etching recesses (e.g., removes) the upper portion of the gate structure 123B and exposes the uppermost nanostructure 54 below the gate structure 123B. Thus, the opening 132 extends into the gate structure 123B. In some embodiments, the etching process is an anisotropic etching process (e.g., a plasma etching process) performed using a gas source including Cl2, BCl3, or a combination thereof. The gas source may also include O2. In the example shown, due to the lateral offset OVS (see FIG. 2 ) between the central axis of the opening 132 and the longitudinal central axis of the gate structure 123B, the gate structure 123B is exposed. Fig.15A ) and due to the anisotropy of the etching process, a portion 123R of the gate structure 123B may remain along the sidewalls of the gate spacer 108. For simplicity, the portion 123R of the gate structure 123B is shown as a single layer, it should be understood that the portion 123R may include multiple layers of materials of the gate structure 123B, such as the gate dielectric layer 120 and one or more sub-layers of the gate electrode 122 (e.g., barrier layers, (one or more) work function layers, and gate electrode materials (e.g., fill metal)). In some embodiments, a wet etching process performed using, for example, piranha solution (e.g., a mixture of sulfuric acid (H2SO4), hydrogen peroxide (H2O2), and water (H2O)) is used to recess the exposed segments of the gate structure 123B.

[0085] In some embodiments, the above-described etching process for recessing the gate structure 123B may be performed using an etchant that is selective to the material of the gate structure 123B so as to selectively remove the exposed segment 123BM of the gate structure 123B without substantially attacking other layers / materials of the NSFET device 100. The hard mask layer 131, the gate spacer 108, and the dielectric plug 125 may help avoid (e.g., prevent) other areas of the NSFET device 100 from being affected by the etching process and limit the effect of the etching process to the area defined by the opening 132. The etching process may have a high etching selectivity greater than, for example, about 10, such as between about 10 and about 100. In the discussion herein, the etching selectivity may be calculated as a ratio between a first etching rate for target material(s) (e.g., material(s) intended to be removed by the etching process) and a second etching rate for non-target material(s) (e.g., material(s) exposed to the etching process but not intended to be removed). In some embodiments, the first etching rate or the second etching rate may be an average etching rate for the corresponding material. In the etching process discussed above for recessing the gate structure 123B, the etching selectivity can be calculated as the ratio between the etching rate of the material(s) of the gate structure 123B (e.g., Cu) and the etching rate of the material(s) of the gate spacer 108 (e.g., SiO). In other embodiments, an etching process with a low etching selectivity is used to recess the gate structure 123B. For example, the anisotropic plasma etching process 143 discussed below (see, e.g., Fig.18A ) to recess the gate structure 123B.

[0086] Next, in Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig.19A , Fig.19B , Fig. 20A and Fig. 20BIn the embodiment of the present invention, an etching process is performed to deepen the opening 132 so as to cut the nanostructure 54 exposed through the opening 132 (e.g., below) and cut the lower portion of the gate structure 123B. In some embodiments, the etching process for deepening the opening 132 includes a plurality of etching cycles, wherein each etching cycle of the plurality of etching cycles includes the following three sequential processing steps: 1) a deposition step, wherein a passivation layer 133 is formed on the hard mask layer 131 and along the sidewalls and bottom of the opening 132; 2) a punch-through step, wherein a punch-through etching step is performed to remove the passivation layer 133 from the etching front (e.g., the bottom of the opening 132); and 3) an etching step, wherein an anisotropic plasma etching process 143 with low etching selectivity is performed to remove the nanostructure 54 below the opening 132. Details of the etching process are discussed below.

[0087] Fig.17A and Fig. 17B A deposition step is shown, wherein, in order to protect the hard mask layer 131 and maintain the size of the opening 132 during subsequent etching steps (e.g., punch-through steps and etching steps), a passivation layer 133 is formed over the upper surface of the hard mask layer 131 and along the sidewalls and bottom of the opening 132 (e.g., conformally). The passivation layer 133 may also be formed over the surface of the nanostructure 54. In some embodiments, the passivation layer 133 is a SiO-based passivation layer formed by injecting a silicon-containing gas (e.g., SiCl4) and an oxygen-containing gas (e.g., O2, CO2) into a plasma etching tool for deepening the opening 132 and removing the nanostructure 54. A carrier gas such as Ar or N2 may be used to carry, for example, SiCl4 and O2 into the plasma etching tool. The SiO-based passivation layer may be formed by the following chemical reaction:

[0088] SiCl4+O2->SiO2+Cl2

[0089] In some embodiments, additive chemicals (one or more) such as HBr are injected into the plasma etch tool chamber along with SiCl4 to promote the dissociation of SiCl4 in the SiO-based passivation layer formation process.

[0090] Chemical reactions such as SiCl4+HBr->SiCl3+HCl+Br

[0091] The dissociation of SiCl 4 and the formation of the SiO-based passivation layer may be accelerated. Bromine (Br) generated by the above chemical reaction may further react with SiO 2 to form SiBrO. Therefore, the composition of the SiO-based passivation layer 133 may include SiBrO.

[0092] In some embodiments, the passivation layer 133 is a SiON layer formed by a deposition process performed using a silicon-containing precursor (e.g., di(tert-butylamino)silane (BTBAS)) and O2 plasma. In some embodiments, the passivation layer 133 is a SiN layer formed by a deposition process performed using a silicon-containing precursor (e.g., BTBAS) and Ar plasma.

[0093] After forming the passivation layer 133, a punch-through step is performed to punch through the passivation layer 133 at the etching front end (e.g., removing the passivation layer 133 from the bottom of the opening 132), so that an etching step (e.g., an anisotropic plasma etching process 143) can be performed next to remove the nanostructure 54. In some embodiments, the punch-through step is an anisotropic etching process (e.g., a plasma etching process) performed using a gas source including CF4, CHF3, C4F6, Cl2, BCl3, or a combination of the foregoing.

[0094] Next, in Fig.18A and Fig.18B In the embodiment shown, an etching step is performed to deepen the opening 132 toward the substrate 50. In the illustrated embodiment, the etching step is an anisotropic plasma etching process 143, which may also be referred to as a plasma dry etching process 143. The anisotropic plasma etching process 143 may be performed using a gas source including HBr, Cl2, or a combination thereof. The gas source may optionally include BCl3. In addition, during the anisotropic plasma etching process 143, other gases (e.g., O2, CO2, or a combination thereof) may be added to the gas source to adjust various aspects of the anisotropic plasma etching process, such as etching rate, etching selectivity, and / or etching profile. The three-step etching cycle discussed above is optional. In some embodiments, the deposition step and the punch-through step are omitted, and the plasma dry etching process 143 is used alone to remove the nanostructure 54 and deepen the opening 132.

[0095] During the anisotropic plasma etching process 143, the gas source is ignited into plasma by the plasma etching tool. The plasma etching tool can use an inductively coupled dipole antenna coil to generate plasma. In some embodiments, the RF power generator of the plasma etching tool generates a 13.6MHz RF power source (e.g., RF signal). The plasma etching tool chamber can operate at a pressure between about 3mTorr and about 150mTorr and at a temperature between about 20 degrees Celsius and about 150 degrees Celsius. The power of the RF power source can be between about 0W and about 2500W. In some embodiments, the plasma dry etching process uses pulsed plasma etching, wherein the duty cycle of the RF power source is in the range of about 10% to 100%. In some embodiments, the amplitude of the bias voltage of the plasma etching tool for the anisotropic plasma etching process 143 is between about 500 volts and about 1200 volts to ensure high anisotropy (also referred to as high directivity).

[0096] It is noteworthy that the anisotropic plasma etching process 143 has a low etching selectivity in a range between about 0.2 and about 5, for example, between about 4 and about 5. Conventional CMODE processes may use (one or more) etching processes with high etching selectivities (e.g., between 10 and 100) to first selectively remove the gate structure (e.g., 123B) and then selectively remove the nanostructure 54. In contrast, the present disclosure uses an anisotropic plasma etching process 143 with low etching selectivity to cut the nanostructure 54. As an example, the etching selectivity of the anisotropic plasma etching process 143 can be calculated as a ratio between an etching rate for a material (e.g., Si) of the nanostructure 54 (or substrate 50) and an etching rate for (one or more) materials (e.g., SiO) of the gate spacer 108 (or STI region 96). The advantages of using an anisotropic etching process 143 with low etching selectivity are discussed below.

[0097] In some embodiments, the low etching selectivity of the anisotropic plasma etching process 143 is achieved by selecting an etchant (e.g., Cl2) that removes both the target material (e.g., Si) and (one or more) non-target materials (e.g., SiO). In some embodiments, the low etching selectivity is achieved by adjusting the mixing ratio between the gases used in the anisotropic plasma etching process 143. For example, in an embodiment where BCl3 is used in the etching gas, increasing the volume percentage of BCl3 in the etching gas can reduce the etching selectivity. In some embodiments, the etching gas can be a mixture of HBr, BCl3, Cl2, and O2, wherein the percentage (e.g., volume percentage) of HBr in the etching gas is between 0% and 80%, the percentage of BCl3 in the etching gas is between 5% and 80%, the percentage of Cl2 in the etching gas is between 0% and 80%, and the percentage of O2 in the etching gas is between 0% and 50%.

[0098] In some embodiments, the anisotropic plasma etching process 143 has high anisotropy (e.g., highly directional vertical etching). The high anisotropy of the anisotropic plasma etching process 143 can be achieved by having a high bias voltage (e.g., an AC bias voltage) for the anisotropic plasma etching process 143. For example, the magnitude of the bias voltage of the plasma etching tool used for the anisotropic plasma etching process 143 can be higher than 500 volts (V), such as between about 500 V and about 1200 V, while the magnitude of the bias voltage used by conventional anisotropic plasma etching processes can be less than 500 V, such as between about 100 V and about 500 V. The advantages of the high anisotropy of the anisotropic plasma etching process 143 are discussed below. Fig.18A and Fig.18B As shown, after the etching step (e.g., anisotropic plasma etching process 143) is completed, the opening 132 is deepened and cut into the nanostructure 54. Due to the low etching selectivity of the anisotropic plasma etching process 143, the passivation layer 133 is etched away by the anisotropic plasma etching process 143, and the portion 123R of the gate structure 123B along the sidewall of the gate spacer 108 is thinned by the anisotropic plasma etching process 143. It should be noted that in some embodiments, in order to avoid complete depletion of the hard mask layer 131 during the etching process, a high anisotropic etching with a high bias voltage can be applied to some steps or some cycles in the etching process. In some embodiments, the bias voltage can be pulsed (e.g., with a duty cycle of less than 100%) during the anisotropic plasma etching process 143 to ensure the retention of the hard mask layer 131.

[0099] Additional etch cycles may be performed. Fig.19A , Fig.19B, Fig. 20A and Fig. 20B A subsequent etching cycle (eg, the last etching cycle) of the etching process is shown. Fig.19A and Fig.19B In the embodiment, a passivation layer 133 is formed on the mask layer 131 and along the sidewalls and bottom of the opening 132. Next, a punch-through step is performed to remove the passivation layer 133 from the bottom of the opening 132. Next, in Fig. 20A and Fig. 20B In the embodiment of the present invention, an anisotropic plasma etching process 143 is performed. The details of the etching cycle are the same or similar to those discussed above and thus will not be repeated.

[0100] like Fig. 20A and Fig. 20B As shown, after the final etch cycle of the etch process is completed, the opening 132 extends through the nanostructure 54, through the fin 90B, and into the substrate 50. Fig. 20A In the embodiment, the upper portion of the opening 132 between the gate spacers 108 has a substantially uniform width, and the lower portion of the opening 132 below the upper portion has a triangular shape, wherein opposite sidewalls 132S1 and 132S2 of the lower portion of the opening 132 have linear profiles and intersect each other to form a V-shape. In some embodiments, the sidewalls 132S1 and 132S2 are Fig. 20A The angle θ1 between the horizontal direction of the side wall 132S2 and the side wall 132S2 is between about 88 degrees and about 90 degrees. Fig. 20A The angle θ2 between the horizontal direction is between about 88 degrees and about 90 degrees. Fig. 20A In the example shown in FIG. 1 , the cross-sectional shape of the lower portion of the opening 132 (eg, the portion disposed below the gate spacer 108 ) is an acute triangle (eg, having three acute angles).

[0101] like Fig. 20B As shown, due to the low etching selectivity of the anisotropic plasma etching process 143, in addition to the nanostructure 54 and the gate structure 123B, the fin 90B and the portion of the STI region 96 below the opening 132 are also removed. Fig. 20B As shown, opening 132 extends through STI region 96 and into substrate 50. Therefore, upper surface 50U1 (e.g., a flat upper surface) of the portion of substrate 50 below opening 132 is lower (e.g., more recessed) than upper surface 50U2 of other (unetched) portions of substrate 50. Fig. 20B In the embodiment, the opening 132 includes two protruding portions 132P (also referred to as protrusions 132P or recesses 132P) at the bottom corners of the opening 132. Fig. 20B, the protrusion 132P extends below the upper surface 50U1 of the substrate 50. The protrusion 132P may be formed due to a faster etching rate achieved at or along the edge of the nanostructure 54 by the anisotropic plasma etching process 143.

[0102] like Fig. 20A and Fig. 20B As shown, after the nanostructure 54 is removed, the opening 132 (which may also be referred to as the recess 132) exposes the sidewall of the dielectric plug 125 facing the nanostructure 54, and exposes the inner sidewall of the gate spacer 108 facing the opening 132. In other words, in the top view, the opening 132 is defined by the opposite sidewalls of the dielectric plug 125 along the first direction (e.g., along the direction of the cross section AA), and by the opposite sidewalls of the gate spacer 108 along the second direction (e.g., along the direction of the cross section BB). Since the opening 132 is subsequently filled with a dielectric material to form the isolation structure 141, Fig. 22C The position of isolation structure 141 in the top view of FIG. 1 also shows the position of opening 132 before it is filled.

[0103] The low etch selectivity of the anisotropic plasma etch process 143 ensures that the opening 132 has a linear sidewall profile and there is no “bow” in the opening 132 . Fig.38B An example of a bow in the opening 132 is shown. Bowing occurs when a portion of the opening 132 has a width greater than an adjacent portion of the opening 132. For example, if the opening 132 has a bow condition at a certain portion, the portion of the opening 132 may appear convex compared to other adjacent portions of the opening 132.

[0104] The opening 132 is then filled with (one or more) dielectric materials to form the isolation structure 141. In subsequent processing, a through hole 165 is formed on the back side of the substrate 50 (see, for example, Fig.25A ) to connect the backside power rail 169 to the source / drain region 112. If there is a bow in the opening 132, the subsequently formed isolation structure 141 may have a protrusion protruding toward the path of the through hole 165 and may hinder the formation of the through hole 165, thereby causing device failure. The method of the present disclosure prevents the occurrence of the bow condition, thereby improving device reliability and yield.

[0105] In order to understand the advantages of the disclosed method, the mechanism by which bow conditions occur and how the disclosed method avoids bow conditions is discussed below. Fig.38A and Fig.38B, which shows that a bow is formed in the opening 132 when an anisotropic etching process with a high etching selectivity is used to deepen the opening 132. The ions and / or radicals of the plasma used in the anisotropic etching process are Fig.38A and 38B are labeled as ions / radicals 142. Fig.38A and Fig.38B The dashed arrow line in FIG shows the trajectory of the ion / radical 142. It should be noted that Fig.38A and Fig.38B The sidewalls of the gate spacers 108 on the right side of the opening 132 are not exposed and are covered by the portion 123R of the gate structure 123B (as in the embodiment method for forming the NSFET device 100) or by the portion 102R of the dummy gate 102 (e.g., polysilicon) (as in the embodiment method for forming the NSFET device 100A discussed below). The portion 123R or 102R is generated due to the shifting of the opening 132 to avoid the photoresist stripping problem.

[0106] Fig.38A Etching caused by non-scattered ions / radicals 142 is shown, which refers to ions / radicals 142 that hit the surfaces of various materials and stop in these materials. In other words, non-scattered ions / radicals 142 do not bounce off the surface (e.g., are not reflected by the surface) and do not continue to travel toward the bottom of the opening 132. Due to the high etching selectivity, the non-scattered ions / radicals 142 react with and remove certain materials (e.g., Si of the nanostructures 54), and do not react with other materials (e.g., SiO) such as the gate spacers 108, the internal spacers 55, etc. Fig.38A The "x" marks in the figure show areas / regions that non-scattered ions / radicals 142 impact but do not react with (thus removing little or no material). The etching effect of non-scattered ions / radicals 142 on the lower portion of opening 132 (e.g., the portion below nanostructure 54) is symmetrical, so non-scattered ions / radicals 142 are not believed to be the cause of the bow condition.

[0107] Fig.38BEtching caused by scattered ions / radicals 142 is shown, which refers to ions / radicals 142 that strike the surface of various materials and bounce off the surface and continue to travel (e.g., toward the bottom of the opening 132). For example, these ions / radicals 142 can be highly reactive with the material of the nanostructures 54 (e.g., Si), but not with the material of the gate spacer 108 (e.g., SiO). Therefore, the ions / radicals 142 can bounce off the sidewalls of the gate spacer 108 disposed on the left side of the opening 132 and travel to the lower portion of the opening 132 and react with the material of the fin 90B (or substrate 50) (e.g., Si) to remove those materials. It should be noted that the sidewalls of the gate spacer 108 on the right side of the opening 132 are not exposed and are covered by a portion 123R of the gate structure 123B, or by a portion 102R of the dummy gate 102 (e.g., polysilicon). The ions / radicals 142 striking the portion 123R or 102R may react with the material(s) of the portion 123R or 102R (and thus not be reflected by the portion 123R or 102R), or may be reflected less than the ions / radicals 142 striking the sidewall of the gate spacer 108 disposed on the left side of the opening 132. Thus, the etching effect of the scattered ions / radicals 142 is asymmetric, which causes one side of the lower portion of the opening 132 to bulge, resulting in a bow condition. Fig.38B In the example shown, the lower portion of the opening 132 has a width W1 that is greater than a width W2 of an adjacent portion of the opening 132. In the example shown, the cross section of the opening 132 having the bow shape is not symmetrical. Specifically, one side (e.g., the right side) of the opening 132 is more protruding than the other side, and the side having the protrusion is on the same side of the gate spacer 108 whose sidewall is covered by the portion 123R or 102R.

[0108] By using an anisotropic etching process 143 with low etching selectivity, the present disclosure ensures that there is no bow caused by scattered ions / radicals 142. This is because, due to the low etching selectivity, the ions / radicals 142 react with different materials in the same or similar manner, thereby avoiding the asymmetric etching effect of the scattered ions / radicals. For example, the ions / radicals 142 can react with both the material of the gate spacer 108 and the material of the portion 123R or 102R, and therefore there are few or no scattered ions / radicals in the anisotropic etching process 143. Therefore, the deepening of the opening 132 is mainly caused by non-scattered ions / radicals with a symmetric etching effect. It should be noted that the formation of the V-shape (see, for example Fig. 20A ) is a feature of the disclosed embodiments. If the scattered ions / radicals contribute significantly to the deepening of the opening 132, the lower portion of the opening 132 will have a rounded (eg, curved) bottom and / or sidewalls.

[0109] However, it may be difficult for non-scattered ions / radicals to reach the deep end of the opening 132. As discussed above, the disclosed embodiments alleviate this problem by using a high bias voltage for the anisotropic plasma etching process 143. The high bias voltage increases the anisotropy of the etching process and allows for better directional etching (e.g., vertically downward) to achieve a deeper depth of the opening 132. In contrast, if a conventional anisotropic plasma etching process using a low bias voltage (thus low anisotropy) and a high etching selectivity (thus more scattered ions / radicals) is used to deepen the opening 132, the low anisotropy means that the non-scattered ions / radicals may not be able to reach the deep end of the opening 132. However, the more scattered ions / radicals compensate for the effect of the low anisotropy because the scattered ions / radicals can travel deeper into the opening 132 (which may cause bowing problems). The lower portion of the opening 132 produced by a conventional anisotropic plasma etching process tends to have a curved bottom surface due to the etching of scattered ions / radicals, unlike the V-shaped bottom of the opening 132 produced by the methods disclosed herein.

[0110] The lower etch selectivity of the anisotropic plasma etch process 143 (if used alone) may damage the hard mask layer 131 during etching and cause enlargement (e.g., widening) of the opening 132. The disclosed embodiments alleviate this problem by using a passivation layer 133 to protect the hard mask layer 131 and other exposed materials during etching. The punch-through step in each etching cycle removes the passivation layer 133 from the bottom of the opening 132 so that the opening 132 can be deepened with each etching cycle.

[0111] By using the passivation layer 133, an anisotropic etching process 143 with low etch selectivity, and highly directional etching (e.g., using a high bias voltage), and other disclosed features in combination, the disclosed embodiments form the opening 132 without bowing issues while achieving excellent control over feature size and achieving a target depth of the opening 132. If the passivation layer 133 and an anisotropic etching process 143 with low etch selectivity are used without a highly directional etch, the depth of the opening 132 may be limited. If an anisotropic etching process 143 with low etch selectivity and a highly directional etch are used without a passivation layer 133, the mask layer 131 may be greatly lost, which results in a loss of control over the size of the features formed.

[0112] Reference now Fig.21A and Fig.21B , which shows Fig. 20A and Fig. 20B After the processing of. Fig.21A and Fig.21BAs shown, a dielectric material 141 is formed in the opening 132 and over the hard mask layer 131. The dielectric material 141 may be, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbon nitride, a combination of the foregoing, or a multilayer of the foregoing. Suitable formation methods (e.g., CVD, PECVD, ALD, etc.) may be used to form the dielectric material 141. The dielectric material 141 may fill the recess 132P to form a protrusion 141P. In some embodiments, the dielectric material 141 includes multiple layers of different dielectric materials. In some embodiments, the dielectric material 141 includes multiple layers of the same dielectric material (e.g., SiO or SiN) formed by different formation methods. For example, a layer of dielectric material may be formed by ALD, and then another layer of the same dielectric material may be formed by, for example, CVD to fill the opening 132. The dielectric material formed by ALD may be dense and have improved etching resistance, while the dielectric material formed by CVD may be formed quickly to reduce production time and cost.

[0113] Next, in Fig.22A and Fig. 22B In the process, a planarization process such as CMP is performed to remove the dielectric material 141 and the hard mask layer 131 from the upper surface of the first ILD 114. The remaining portion of the dielectric material 141 in the opening 132 forms an isolation structure 141. Fig. 22C A top view (eg, plan view) of a NSFET device 100 is shown. Fig. 13C , for simplicity, Fig. 22C Not all features of NSFET device 100 are shown. Fig. 22C In the example shown, the isolation structure 141 is disposed between the dielectric plugs 125 along the direction of the cross section AA, and is disposed between the gate spacers 108 of the gate structure 123B along the direction of the cross section BB. Fig.22A and Fig. 22B In the illustrated embodiment, the isolation structure 141 and the dielectric plug 125 separate the gate structure 123B into two separate gate structures 123B1 and 123B2. The isolation structure 141 also reduces leakage current through the source / drain region 112, the transistor, and the substrate 50. Fig.22A and Fig. 22B Also shown is an etch stop layer 51 embedded in the substrate 50 .

[0114] Next, in Fig.23A and Fig. 23B, a second ILD 145 is formed over the first ILD 114. A source / drain contact 148S is formed to extend through the first ILD 114 and the second ILD 145 to be electrically coupled to the corresponding source / drain region 112. A gate contact 148G is formed to extend through the second ILD 145 to be electrically coupled to the corresponding gate structure 123. The source / drain contact 148S and the gate contact 148G are collectively referred to as a contact 148. In addition, an interconnect structure 158 (also referred to as a front-side interconnect structure 158) (including a dielectric layer 153 and conductive features (e.g., wires 155 and vias 157) formed in the dielectric layer 153) is formed over the second ILD 145 to interconnect electrical components formed in / on the substrate 50 to form a functional circuit.

[0115] The second ILD 145 may be formed of the same dielectric material as the first ILD 114 using the same formation method. Each contact 148 may include a barrier layer 147 (e.g., TiN, TaN, etc.), a seed layer 149 (e.g., Cu), and a fill metal 151 (e.g., Cu, W, Co, etc.). In some embodiments, the source / drain contacts 148S are formed by: forming a patterned mask layer over the second ILD 145, wherein openings of the patterned mask layer overlie the corresponding source / drain regions 112; removing portions of the second ILD 145 and the first ILD 114 below the openings; conformally forming a barrier layer 147 and a seed layer 149 in the openings; and filling the openings with a fill metal 151. The patterned mask layer is then removed, for example, by a CMP process. It should be noted that in Fig.23A In the example of FIG. 1 , a portion of the first ILD 114 disposed between the respective sidewalls of the CESL 116 is completely removed so that the barrier layer 147 of the source / drain contact 148S contacts (e.g., physically contacts) the sidewalls of the CESL 116. The illustrated source / drain contact 148S achieves increased volume and reduced resistance, which improves the electrical performance of the formed device. The dielectric layer 153 of the interconnect structure 158 may be formed of a suitable dielectric material, such as SiO or a low-k dielectric material. The conductive lines 155 and the vias 157 of the interconnect structure 158 may be formed of (one or more) suitable conductive materials (e.g., Cu).

[0116] Next, in Fig.24A and Fig. 24B, the interconnect structure 158 is attached to a carrier 161 (e.g., a glass carrier, a ceramic carrier, a wafer, etc.) by, for example, an adhesive layer. Next, a backside thinning process (e.g., CMP, a grinding process, etc.) is performed to thin the NSFET device 100 from the back side of the substrate 50. The backside thinning process can use the etch stop layer 51 to determine when to stop. In the example shown, after the backside thinning process is completed, the substrate 50, the etch stop layer 51, and a portion of the fin 90 are removed. Fig.24A and Fig. 24B In FIG. 1 , the isolation structure 141 , the fin 90 , and the first ILD 114 have coplanar upper surfaces.

[0117] Next, in Fig.25A and Fig.25B In the embodiment of the present invention, a via 165 (also referred to as a backside via 165) is formed to extend through the fin 90B to connect with the source / drain region 112. The via 165 can be formed by patterning the fin 90B to form an opening, lining the sidewalls of the opening with a barrier layer (e.g., TiN, TaN, etc.), and then filling the opening with a conductive material (e.g., Cu, W, Co, etc.). In some embodiments, the backside via 165 is formed to connect with the corresponding source region 112 but not the drain region 112, or to connect with the corresponding drain region 112 but not the source region 112. In some embodiments, the backside via 165 is formed to connect with both the source region 112 and the drain region 112.

[0118] Next, in Fig.26A and Fig.26B In the embodiment, a backside interconnect structure 168 is formed over the fin 90B and electrically coupled to the via 165. The backside interconnect structure 168 includes a dielectric layer 167 and conductive features, such as a wire 169 and a via 163 formed in the dielectric layer 167. As will be readily appreciated by those skilled in the art, Fig.26A and Fig.26B The number of dielectric layers and conductive features of the frontside interconnect structure 158 and the backside interconnect structure 168 shown in are illustrative and not limiting.

[0119] In some embodiments, the conductor 169 of the backside interconnect structure 168 is configured to provide a reference voltage, a power supply voltage (e.g., +3V, +5V, etc.), etc. to the source / drain region 112, and may be referred to as a power rail 169. Advantages may be achieved by placing the power rail on the back side of the resulting semiconductor die rather than the front side of the semiconductor die. For example, the gate density of the NSFET device and / or the interconnect density of the front side interconnect structure 158 may be increased. In addition, the back side of the semiconductor die may accommodate a wider power rail, thereby reducing resistance and improving power transfer efficiency to the NSFET device. For example, the width of the conductor 169 may be at least twice the width of the conductor of the front side interconnect structure 158. In addition, capacitors such as metal-insulator-metal (MIM) capacitors may be integrated in the backside interconnect structure 168 to form a power supply circuit and / or stabilize the reference voltage and / or power supply voltage in the backside power distribution network, thereby achieving improved performance of the formed device.

[0120] As will be readily appreciated by those skilled in the art, additional processing may be performed to complete the fabrication of the NSFET device. For example, external connectors (e.g., copper pillars, conductive bumps) may be formed to electrically couple to the front side interconnect structure 158 and / or the back side interconnect structure 168. Cutting may be performed to separate the plurality of NSFET devices into individual devices. The details are not discussed here.

[0121] The cutting of the gate structure and nanostructure of the NSFET device 100 is performed after the dummy gate structure is replaced by the replacement gate structure and is referred to as a continuous metal on diffusion edge (CMODE) process (also referred to as a cut metal on diffusion edge (CMODE) process). The continuous polysilicon diffusion edge (CPODE) process (also referred to as a cut polysilicon diffusion edge (CPODE) process) in which the cutting of the gate structure and nanostructure is performed on the dummy gate structure before the gate structure is formed is discussed below with respect to the NSFET device 100A.

[0122] Fig.29A , Fig.29B , Fig. 30A , Fig. 30B , Fig.31A , Fig.31B , Fig.32A , Fig.32B , Fig.33A , Fig.33B , Fig.34A , Fig.34B , Fig.35A , Fig.35B , FIG. 36A to FIG. 36C , Fig.37A and 37B1 is a diagram of a nanostructured field effect transistor (NSFET) device 100A at various stages of fabrication according to another embodiment. The formation process of the NSFET device 100A has many similarities to the formation process of the NSFET device 100. For simplicity, the following discussion focuses on the differences and may not repeat the details of the composition and formation methods of some materials (or features) discussed above in the context of the NSFET device 100.

[0123] Fig.29A and Fig.29B The process follows the formation of the CESL 116 and the first ILD 114 7A to 7C In Fig.29A and Fig.29B In the process, a planarization process such as CMP is performed to make the top surfaces of the first ILD 114 and the CESL 116 flush with the top surfaces of the dummy gate 102 and the gate spacer 108. The planarization process can also remove the mask 104 on the dummy gate 102 (see Fig. 7A ), and portions of the gate spacers 108 along the sidewalls of the mask 104. After the planarization process, the top surfaces of the dummy gates 102, the gate spacers 108, the CESL 116, and the first ILD 114 are flush. Therefore, the top surfaces of the dummy gates 102A, 102B, 102C, and 102D (collectively referred to as the dummy gates 102) are exposed through the first ILD 114.

[0124] Next, use the same method discussed above for Fig. 13B The dielectric plug 125 is formed in the dummy gate 102B using the same or similar formation method as the dielectric plug 125 in FIG. Fig.36C A top view of dielectric plug 125 is shown. Fig.29B The dielectric plugs 125 in FIG. 1 divide the dummy gate 102B into a plurality of separate segments.

[0125] Next, in Fig. 30A and Fig. 30B In the embodiment of the present invention, a hard mask layer 131 is formed over the first ILD 114. A three-layer etch mask 136 is formed over the hard mask layer 131. An opening 138 is formed in the top photoresist layer 139 of the etch mask 136. Fig.14A , Fig. 30A The opening 138 in is intentionally formed to have a lateral offset OVS between the central axis 138X of the opening 138 and the central axis 102BX of the dummy gate 102B. In some embodiments, the amount of the lateral offset OVS is the same or similar to that discussed above for the NSFET device 100, so the details are not repeated.

[0126] Next, in Fig.31A and Fig.31B In the embodiment, the opening 138 in the etch mask 136 is transferred to the hard mask layer 131 as the opening 132 in the mask layer 131. There is a lateral offset OVS between the central axis 132X of the opening 132 and the central axis 102BX of the dummy gate 102B.

[0127] Next, in Fig.32A and Fig.32B In the embodiment, the portion of the dummy gate 102B exposed by the opening 132 (e.g., below it) is recessed by a suitable etching process (e.g., an anisotropic etching process). In some embodiments, the anisotropic etching process may be a plasma etching using an etchant that is selective to the material of the dummy gate 102B. As an example, the plasma etching process may use a gas source including a mixture of NF3 and CH4 or a mixture of NF3 and CH3F. As another example, the plasma etching process may use a gas source including a mixture of HBr and O2 or a mixture of HBr and CO2. As yet another example, the plasma etching process may use a gas source including a mixture of Cl2 and O2. In some embodiments, the anisotropic etching process may be the same etching process used to deepen the opening 132 (e.g., Fig.34A 143 in the embodiment shown). In the embodiment shown, Fig.32A and Fig.32B After the processing of , the topmost nanostructure 54 below the opening 132 is exposed by the opening 132. Due to the lateral offset OVS, a portion 102R of the dummy gate 102B (eg, polysilicon) may remain along the sidewalls of the gate spacer 108.

[0128] Next, if Fig.33A , Fig.33B , Fig.34A and Fig.34B As shown, multiple etching cycles are performed to deepen the opening 132. Each etching cycle includes the following three sequential processing steps: 1) a deposition step, in which a passivation layer 133 is formed on the hard mask layer 131 and along the sidewalls and bottom of the opening 132; 2) a punch-through step, in which a punch-through etching step is performed to remove the passivation layer 133 from the etching front (e.g., the bottom of the opening 132); and 3) an etching step, in which an anisotropic plasma etching process 143 with low etching selectivity is performed to remove the nanostructure 54 below the opening 132. The details of the etching cycle are the same or similar to those discussed above, so they are not repeated here. The three-step etching cycle discussed above is optional. In some embodiments, the deposition step and the punch-through step are omitted, and the plasma dry etching process 143 is used alone to remove the nanostructure 54 and deepen the opening 132.

[0129] Fig.33A , Fig.33B , Fig.34A and Fig.34B One etching cycle is shown. Fig.33A and Fig.33B In the process, a passivation layer 133 is formed over the mask layer 131 and lining the sidewalls and the bottom of the opening 132. Next, a punch-through step is performed to remove the passivation layer 133 from the bottom of the opening 132.

[0130] Next, in Fig.34A and Fig.34B In the embodiment, an anisotropic plasma etching process 143 with low etching selectivity is performed to deepen the opening 132. Fig.33A , Fig.33B , Fig.34A and Fig.34B Multiple etching cycles as shown in and discussed above.

[0131] Next, in Fig.35A and Fig.35B In the embodiment of the present invention, after completing the plurality of etching cycles, the opening 132 is filled with the dielectric material 141. A dielectric material may also be formed over the upper surface of the mask layer 131.

[0132] Next, in Fig.36A and Fig.36B In the embodiment of the present invention, a planarization process such as CMP is performed to remove the dielectric material 141 and the hard mask layer 131 from the upper surface of the first ILD 114. The remaining portion of the dielectric material 141 in the opening 132 forms the isolation structure 141. Next, using the same or similar replacement gate process as discussed above, the dummy gate electrode 102 and the dummy gate dielectric 97 are replaced with replacement gate structures 123 (e.g., 123A, 123B, 123C, and 123D). It should be noted that the two segments of the dummy gate 102B disposed on opposite sides of the isolation structure 141 are replaced with two separate replacement gate structures 123B1 and 123B2. The gate structures 123B1 and 123B2 may be collectively referred to as gate structures 123B. Fig.36C A top view (eg, plan view) of NSFET device 100A is shown.

[0133] Next, in Fig.37A and Fig.37B, a second ILD 145 is formed on the first ILD 114. Source / drain contacts 148S and gate contacts 148G are formed to be electrically coupled to the corresponding source / drain regions 112 and gate structure 123. A front side interconnect structure 158 is formed above the second ILD 145. Next, the front side interconnect structure 158 is attached to the carrier 161, and a back side thinning process is performed to remove the substrate 50 and a portion of the fin 90. Next, a via 165 is formed, which extends through the fin 90B to be electrically coupled to the source / drain region 112. Next, a back side interconnect structure 168 is formed on the fin 90B. A power rail 169 is formed in the back side interconnect structure 168. The details are the same or similar to those discussed above, so they are not repeated here. As will be readily appreciated by those skilled in the art, additional processing may be performed to complete the manufacture of the NSFET device 100A, and the details are not discussed here.

[0134] Embodiments can achieve multiple advantages. By intentionally moving the position of the opening 138 in the photoresist layer 139, the photoresist stripping problem is avoided. However, moving the position of the opening 138 may cause a bow problem of the opening 132 in the CMODE or CPODE process. The present disclosure avoids the bow problem by using an etching process with low etching selectivity. The etching process may optionally include multiple etching cycles, each etching cycle including three etching steps. The passivation layer helps to protect the mask layer 131 and control the feature size. The anisotropic plasma etching process 143 with low etching selectivity reduces scattered ions / radicals to reduce asymmetric etching, thereby avoiding the bow problem. The high directionality of the anisotropic plasma etching process 143 ensures that the desired depth of the opening 132 is achieved. Since the bow situation may interfere with the formation of the subsequent through hole 165 for connecting to the backside power rail, the disclosed embodiment reduces device failures and improves yield.

[0135] Fig.39A and Fig.39B 1 and 2 show a flow chart of a method 1000 of forming a semiconductor device according to some embodiments. It should be understood that Fig.39A and Fig.39B The embodiment methods shown in are merely examples of many possible embodiment methods. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, the embodiments shown in FIG. 39 and FIG. 40 may be added, removed, replaced, rearranged, or repeated. Fig.39B The various steps shown.

[0136] refer to Fig.39A and Fig.39BAt box 1010, a gate structure is formed over a fin protruding above a substrate. At box 1020, an interlayer dielectric (ILD) layer is formed around the gate structure over the fin. At box 1030, a first dielectric plug and a second dielectric plug are formed in the gate structure on opposite sides of the fin, wherein the first dielectric plug and the second dielectric plug cut the gate structure into a plurality of segments separated from each other. At box 1040, a patterned mask layer is formed over the ILD layer, wherein an opening of the patterned mask layer exposes a segment of the gate structure inserted between the first dielectric plug and the second dielectric plug. At box 1050, the segment of the gate structure is etched using the patterned mask layer as an etching mask to form a recess in the gate structure. At box 1060, the recess is extended into the fin, wherein extending the recess includes performing an anisotropic etching process to deepen the recess. At box 1070, after extending the recess, the recess is filled with a dielectric material.

[0137] In an embodiment, a method for forming a semiconductor device includes: forming a first fin, a second fin, and a third fin protruding above a substrate and extending parallel to each other, wherein the third fin is between the first fin and the second fin; forming a gate structure over the first fin, the second fin, and the third fin; forming a gate spacer along opposite sidewalls of the gate structure; forming an interlayer dielectric (ILD) layer over the first fin, the second fin, and the third fin and around the gate structure; forming a first dielectric plug and a second dielectric plug in the gate structure, which divide the gate structure into a plurality of segments, wherein the first dielectric plug is formed between the first fin and the third fin, and the second dielectric plug is formed between the third fin and the second fin; a dielectric plug; forming a patterned mask layer over the ILD layer, wherein a first opening of the patterned mask layer exposes a first segment of the gate structure disposed between the first dielectric plug and the second dielectric plug; performing a first etching process using the patterned mask layer as an etching mask, wherein the first etching process recesses the first segment of the gate structure and forms a recess between the gate spacers; after performing the first etching process, performing a second etching process different from the first etching process to deepen the recess, wherein after completing the second etching process, the recess extends into the substrate; and after performing the second etching process, forming a dielectric structure in the recess. In an embodiment, in a top view, there is a lateral offset between a first central axis of the first opening and a longitudinal central axis of the gate structure, wherein the first central axis of the first opening and the longitudinal central axis of the gate structure extend in parallel. In an embodiment, the lateral offset is between about 5% and about 33% of a width of the gate structure measured between the gate spacers. In an embodiment, forming a patterned mask layer includes: forming a hard mask layer over the ILD layer; forming a photoresist layer over the hard mask layer; forming a second opening in the photoresist layer to form a patterned photoresist layer, wherein, in a top view, a second central axis of the second opening is laterally shifted by a predetermined amount relative to a longitudinal central axis of the gate structure; and patterning the hard mask layer using the patterned photoresist layer to form a patterned mask layer, wherein, due to the patterning of the hard mask layer, the second opening of the patterned photoresist layer corresponds to the first opening of the patterned mask layer. In an embodiment, after the first etching process, a first sidewall of the gate spacer facing the gate structure is exposed to the recess, and a second opposing sidewall of the gate spacer facing the gate structure is covered by a remaining portion of the gate structure, wherein after the second etching process and before filling the recess, the first sidewall and the second opposing sidewall of the gate spacer are exposed to the recess. In an embodiment, an etching selectivity of the second etching process is calculated as a ratio between a first etching rate for the substrate and a second etching rate for the gate spacer, which is between about 0.2 and about 5.In an embodiment, the second etching process is an anisotropic plasma etching process, wherein the method further comprises setting the magnitude of the bias voltage of the anisotropic plasma etching process to be between about 500V and about 1200V. In an embodiment, after the second etching process, the lower portion of the recess extends into the substrate, wherein the sidewalls of the lower portion of the recess have a linear profile and intersect to form a V-shape. In an embodiment, the gate structure is a dummy gate structure, wherein after filling the recess, the method further comprises: removing the patterned mask layer; and replacing the second segment of the dummy gate structure and the third segment of the dummy gate structure with the first replacement gate structure and the second replacement gate structure, respectively, wherein the second segment of the dummy gate structure overlies the first fin, and the third segment of the dummy gate structure overlies the second fin. In an embodiment, the dielectric structure has a multi-layer structure, wherein forming the dielectric structure comprises: forming a first dielectric material along the sidewalls and bottom of the recess; and after forming the first dielectric material, forming a second dielectric material different from the first dielectric material in the recess on the first dielectric material. In an embodiment, after forming the dielectric structure, the method further comprises: forming a front-side interconnect structure over the gate structure and electrically coupled to the gate structure; bonding the front-side interconnect structure to a carrier; after bonding, performing a back-side thinning process to remove the substrate and portions of the first fin, the second fin, and the third fin; after the back-side thinning process, forming a back-side via extending through the third fin and electrically coupled to a source / drain region adjacent to the gate structure; and after forming the back-side via, forming a back-side interconnect structure electrically coupled to the back-side via. In an embodiment, after performing the first etching process and before performing the second etching process, the method further comprises: forming a passivation layer along the sidewalls and bottom of the recess; and after forming the passivation layer, removing the passivation layer from the bottom of the recess.

[0138] In an embodiment, a method of forming a semiconductor device includes: forming a gate structure over a fin protruding above a substrate; forming an interlayer dielectric (ILD) layer over the fin and around the gate structure; forming a first dielectric plug and a second dielectric plug in the gate structure on opposite sides of the fin, wherein the first dielectric plug and the second dielectric plug cut the gate structure into a plurality of segments separated from each other; forming a patterned mask layer over the ILD layer, wherein an opening of the patterned mask layer exposes a segment of the gate structure inserted between the first dielectric plug and the second dielectric plug; etching the segment of the gate structure using the patterned mask layer as an etching mask to form a recess in the gate structure; extending the recess into the fin, wherein extending the recess includes performing an anisotropic etching process to deepen the recess; and after extending the recess, filling the recess with a dielectric material. In an embodiment, after extending the recess, a lower portion of the recess has an inclined linear sidewall, wherein a distance between the inclined linear sidewalls decreases as the recess extends toward the fin. In an embodiment, an etch selectivity of the anisotropic etching process is between about 0.2 and about 5, wherein the etch selectivity is calculated as a ratio between a first etch rate for the substrate and a second etch rate for the gate spacers of the gate structure. In an embodiment, extending the recess comprises: performing a plurality of etching cycles using a patterned mask layer as an etching mask, wherein each of the plurality of etching cycles is performed by: lining the sidewalls and the bottom of the recess with a passivation layer; after the lining, removing the passivation layer from the bottom of the recess; and after removing the passivation layer from the bottom of the recess, performing an anisotropic etching process to deepen the recess. In an embodiment, forming the patterned mask layer comprises: forming an opening of the patterned mask layer to be laterally displaced a predetermined distance relative to a longitudinal center axis of the gate structure.

[0139] In an embodiment, a method of forming a semiconductor device includes: forming a gate structure over a fin protruding above a substrate; forming an interlayer dielectric (ILD) layer over the fin and around the gate structure; forming a first dielectric plug and a second dielectric plug in the gate structure on opposite sides of the fin, wherein the first dielectric plug and the second dielectric plug cut the gate structure into a plurality of discrete segments; forming a patterned mask layer over the ILD layer, wherein an opening of the patterned mask layer exposes a segment of the gate structure inserted between the first dielectric plug and the second dielectric plug, wherein the opening of the patterned mask layer is formed to be laterally displaced a predetermined distance relative to the segment of the gate structure, wherein, in a top view, there is a lateral offset between a longitudinal center axis of the gate structure and a center axis of the opening; etching the segment of the gate structure to form a recess in the gate structure using the patterned mask layer as an etching mask; extending the recess into the fin, wherein extending the recess includes performing an anisotropic etching process to deepen the recess; and after extending the recess, filling the recess with a dielectric material. In an embodiment, after extending the recess and before filling the recess, an upper portion of the recess disposed between gate spacers of the gate structure has a uniform width, wherein a lower portion of the recess disposed between an upper portion of the recess and the substrate has an inclined linear sidewall, and a width of the lower portion of the recess decreases as the lower portion of the recess extends toward the substrate. In an embodiment, the anisotropic etching process is an anisotropic plasma etching process, wherein an etching selectivity of the anisotropic etching process is between about 0.2 and about 5, wherein the etching selectivity is calculated as a ratio between an etching rate for the substrate and an etching rate for the gate spacers of the gate structure.

[0140] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. It should be appreciated by those skilled in the art that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purpose and / or achieving the same advantages of the embodiments introduced herein. It should also be appreciated by those skilled in the art that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

[0141] Example 1. A method for forming a semiconductor device, the method comprising: forming a first fin, a second fin, and a third fin protruding above a substrate and extending parallel to each other, wherein the third fin is between the first fin and the second fin; forming a gate structure above the first fin, the second fin, and the third fin; forming a gate spacer along opposite sidewalls of the gate structure; forming an interlayer dielectric (ILD) layer above the first fin, the second fin, and the third fin and around the gate structure; forming a first dielectric plug and a second dielectric plug in the gate structure, the first dielectric plug and the second dielectric plug dividing the gate structure into a plurality of segments, wherein the first dielectric plug is formed between the first fin and the third fin, and between the third fin and The second dielectric plug is formed between the second fins; a patterned mask layer is formed on the ILD layer, wherein a first opening of the patterned mask layer exposes a first section of the gate structure disposed between the first dielectric plug and the second dielectric plug; a first etching process is performed using the patterned mask layer as an etching mask, wherein the first etching process recesses the first section of the gate structure and forms a recess between the gate spacers; after performing the first etching process, a second etching process different from the first etching process is performed to deepen the recess, wherein after completing the second etching process, the recess extends into the substrate; and after performing the second etching process, a dielectric structure is formed in the recess.

[0142] Example 2. A method according to Example 1, wherein, in a top view, there is a lateral offset between a first center axis of the first opening and a longitudinal center axis of the gate structure, wherein the first center axis of the first opening and the longitudinal center axis of the gate structure extend in parallel.

[0143] Example 3. The method of Example 2, wherein the lateral offset is between about 5% and about 33% of a width of the gate structure measured between the gate spacers.

[0144] Example 4. A method according to Example 2, wherein forming the patterned mask layer includes: forming a hard mask layer above the ILD layer; forming a photoresist layer above the hard mask layer; forming a second opening in the photoresist layer to form a patterned photoresist layer, wherein in the top view, a second center axis of the second opening is laterally shifted a predetermined amount relative to a longitudinal center axis of the gate structure; and using the patterned photoresist layer to pattern the hard mask layer to form the patterned mask layer, wherein, due to the patterning of the hard mask layer, the second opening of the patterned photoresist layer corresponds to the first opening of the patterned mask layer.

[0145] Example 5. A method according to Example 2, wherein, after the first etching process, a first side wall of the gate spacer facing the gate structure is exposed to the recess, and a second opposite side wall of the gate spacer facing the gate structure is covered by a remaining portion of the gate structure, wherein, after the second etching process and before filling the recess, the first side wall and the second opposite side wall of the gate spacer are exposed to the recess.

[0146] Example 6. A method according to Example 1, wherein the etching selectivity of the second etching process is calculated as a ratio between a first etching rate of the substrate and a second etching rate of the gate spacer, and the etching selectivity of the second etching process is between about 0.2 and about 5.

[0147] Example 7. The method of Example 6, wherein the second etching process is an anisotropic plasma etching process, wherein the method further comprises setting the magnitude of the bias voltage of the anisotropic plasma etching process to between about 500V and about 1200V.

[0148] Example 8. The method of Example 6, wherein after the second etching process, a lower portion of the recess extends into the substrate, wherein sidewalls of the lower portion of the recess have a linear profile and intersect to form a V-shape.

[0149] Example 9. A method according to Example 1, wherein the gate structure is a dummy gate structure, and wherein, after filling the recess, the method further includes: removing the patterned mask layer; and replacing the second segment of the dummy gate structure and the third segment of the dummy gate structure with a first replacement gate structure and a second replacement gate structure, respectively, wherein the second segment of the dummy gate structure overlies the first fin, and the third segment of the dummy gate structure overlies the second fin.

[0150] Example 10. A method according to Example 1, wherein the dielectric structure has a multilayer structure, wherein forming the dielectric structure includes: forming a first dielectric material along the sidewalls and bottom of the recess; and after forming the first dielectric material, forming a second dielectric material different from the first dielectric material in the recess on top of the first dielectric material.

[0151] Example 11. The method according to Example 1, after forming the dielectric structure, further includes: forming a front side interconnect structure above the gate structure, and the front side interconnect structure is electrically coupled to the gate structure; bonding the front side interconnect structure to a carrier; after the bonding, performing a back side thinning process to remove the substrate and portions of the first fin, the second fin and the third fin; after the back side thinning process, forming a back side through hole, the back side through hole extending through the third fin and electrically coupled to a source / drain region adjacent to the gate structure; and after forming the back side through hole, forming a back side interconnect structure electrically coupled to the back side through hole.

[0152] Example 12. The method according to Example 1, after performing the first etching process and before performing the second etching process, further includes: forming a passivation layer along the sidewalls and bottom of the recess; and after forming the passivation layer, removing the passivation layer from the bottom of the recess.

[0153] Example 13. A method for forming a semiconductor device, the method comprising: forming a gate structure over a fin protruding above a substrate; forming an interlayer dielectric (ILD) layer over the fin and around the gate structure; forming a first dielectric plug and a second dielectric plug in the gate structure on opposite sides of the fin, wherein the first dielectric plug and the second dielectric plug cut the gate structure into a plurality of segments separated from each other; forming a patterned mask layer over the ILD layer, wherein openings of the patterned mask layer expose segments of the gate structure inserted between the first dielectric plug and the second dielectric plug; using the patterned mask layer as an etching mask, etching the segments of the gate structure to form a recess in the gate structure; extending the recess into the fin, wherein extending the recess comprises performing an anisotropic etching process to deepen the recess; and after extending the recess, filling the recess with a dielectric material.

[0154] Example 14. The method of Example 13, wherein after extending the recess, a lower portion of the recess has sloped linear sidewalls, wherein a distance between the sloped linear sidewalls decreases as the recess extends toward the fin.

[0155] Example 15. A method according to Example 13, wherein the etch selectivity of the anisotropic etching process is between about 0.2 and about 5, wherein the etch selectivity is calculated as a ratio between a first etch rate of the substrate and a second etch rate of the gate spacer of the gate structure.

[0156] Example 16. A method according to Example 13, wherein extending the recess includes: performing multiple etching cycles using the patterned mask layer as the etching mask, wherein each of the multiple etching cycles is performed by the following steps: lining the sidewalls and bottom of the recess with a passivation layer; after the lining, removing the passivation layer from the bottom of the recess; and after removing the passivation layer from the bottom of the recess, performing the anisotropic etching process to deepen the recess.

[0157] Example 17. The method of Example 13, wherein forming the patterned mask layer comprises forming an opening of the patterned mask layer to be laterally shifted a predetermined distance relative to a longitudinal center axis of the gate structure.

[0158] Example 18. A method of forming a semiconductor device, the method comprising: forming a gate structure over a fin protruding above a substrate; forming an interlayer dielectric (ILD) layer over the fin and around the gate structure; forming a first dielectric plug and a second dielectric plug in the gate structure on opposite sides of the fin, wherein the first dielectric plug and the second dielectric plug cut the gate structure into a plurality of discrete segments; forming a patterned mask layer over the ILD layer, wherein an opening of the patterned mask layer allows a dielectric layer inserted between the first dielectric plug and the second dielectric plug to be formed; A segment of the gate structure is exposed, wherein an opening of the patterned mask layer is formed to be laterally shifted a predetermined distance relative to the segment of the gate structure, wherein, in a top view, there is a lateral offset between a longitudinal center axis of the gate structure and a center axis of the opening; using the patterned mask layer as an etching mask, etching the segment of the gate structure to form a recess in the gate structure; extending the recess into the fin, wherein extending the recess includes performing an anisotropic etching process to deepen the recess; and after extending the recess, filling the recess with a dielectric material.

[0159] Example 19. A method according to Example 18, wherein, after extending the recess and before filling the recess, an upper portion of the recess disposed between gate spacers of the gate structure has a uniform width, wherein a lower portion of the recess disposed between the upper portion of the recess and the substrate has an inclined linear sidewall, and the width of the lower portion of the recess continuously decreases as the lower portion of the recess extends toward the substrate.

[0160] Example 20. A method according to Example 18, wherein the anisotropic etching process is an anisotropic plasma etching process, wherein the etching selectivity of the anisotropic etching process is between about 0.2 and about 5, wherein the etching selectivity is calculated as a ratio between an etching rate of the substrate and an etching rate of the gate spacer of the gate structure.

Claims

1. A method for forming a semiconductor device, the method comprising: forming a first fin, a second fin, and a third fin protruding above the substrate and extending parallel to each other, wherein the third fin is between the first fin and the second fin; forming a gate structure on the first fin, the second fin, and the third fin; forming gate spacers along opposite sidewalls of the gate structure; forming an interlayer dielectric (ILD) layer over the first fin, the second fin, and the third fin and around the gate structure; forming a first dielectric plug and a second dielectric plug in the gate structure, the first dielectric plug and the second dielectric plug dividing the gate structure into a plurality of segments, wherein the first dielectric plug is formed between the first fin and the third fin, and the second dielectric plug is formed between the third fin and the second fin; forming a patterned mask layer over the ILD layer, wherein a first opening of the patterned mask layer exposes a first section of the gate structure disposed between the first dielectric plug and the second dielectric plug; performing a first etching process using the patterned mask layer as an etching mask, wherein the first etching process recesses the first segment of the gate structure and forms recesses between the gate spacers; After performing the first etching process, performing a second etching process different from the first etching process to deepen the recess, wherein after completing the second etching process, the recess extends into the substrate; and After performing the second etching process, a dielectric structure is formed in the recess.

2. The method according to claim 1, wherein: In top view, there is a lateral offset between a first central axis of the first opening and a longitudinal central axis of the gate structure, wherein the first central axis of the first opening and the longitudinal central axis of the gate structure extend in parallel.

3. The method according to claim 2, wherein: The lateral offset is between about 5% and about 33% of a width of the gate structure measured between the gate spacers.

4. The method according to claim 2, wherein: Forming the patterned mask layer includes: forming a hard mask layer over the ILD layer; forming a photoresist layer over the hard mask layer; forming a second opening in the photoresist layer to form a patterned photoresist layer, wherein in the top view, a second central axis of the second opening is laterally displaced by a predetermined amount relative to a longitudinal central axis of the gate structure; and The hard mask layer is patterned using the patterned photoresist layer to form the patterned mask layer, wherein the second openings of the patterned photoresist layer correspond to the first openings of the patterned mask layer due to the patterning of the hard mask layer.

5. The method according to claim 2, wherein: After the first etching process, a first side wall of the gate spacer facing the gate structure is exposed to the recess, and a second opposite side wall of the gate spacer facing the gate structure is covered by a remaining portion of the gate structure, wherein after the second etching process and before filling the recess, the first side wall and the second opposite side wall of the gate spacer are exposed to the recess.

6. The method according to claim 1, wherein: An etch selectivity of the second etch process is calculated as a ratio between a first etch rate of the substrate and a second etch rate of the gate spacer, and the etch selectivity of the second etch process is between about 0.2 and about 5.

7. The method according to claim 6, wherein: The second etching process is an anisotropic plasma etching process, wherein the method further comprises setting a magnitude of a bias voltage of the anisotropic plasma etching process between about 500V and about 1200V.

8. The method according to claim 6, wherein: After the second etching process, a lower portion of the recess extends into the substrate, wherein sidewalls of the lower portion of the recess have linear profiles and intersect to form a V-shape.

9. A method for forming a semiconductor device, the method comprising: forming a gate structure on the fin protruding above the substrate; forming an interlayer dielectric (ILD) layer over the fin and around the gate structure; forming a first dielectric plug and a second dielectric plug in the gate structure on opposite sides of the fin, wherein the first dielectric plug and the second dielectric plug cut the gate structure into a plurality of segments separated from each other; forming a patterned mask layer over the ILD layer, wherein an opening of the patterned mask layer exposes a segment of the gate structure interposed between the first dielectric plug and the second dielectric plug; etching the segment of the gate structure to form a recess in the gate structure using the patterned mask layer as an etch mask; extending the recess into the fin, wherein extending the recess comprises performing an anisotropic etching process to deepen the recess; and After extending the recess, the recess is filled with a dielectric material.

10. A method for forming a semiconductor device, the method comprising: forming a gate structure on the fin protruding above the substrate; forming an interlayer dielectric (ILD) layer over the fin and around the gate structure; forming a first dielectric plug and a second dielectric plug in the gate structure on opposite sides of the fin, wherein the first dielectric plug and the second dielectric plug cut the gate structure into a plurality of discrete segments; forming a patterned mask layer over the ILD layer, wherein an opening of the patterned mask layer exposes a segment of the gate structure interposed between the first dielectric plug and the second dielectric plug, wherein the opening of the patterned mask layer is formed to be laterally displaced a predetermined distance relative to the segment of the gate structure, wherein in a top view, there is a lateral offset between a longitudinal center axis of the gate structure and a center axis of the opening; etching the segment of the gate structure to form a recess in the gate structure using the patterned mask layer as an etch mask; extending the recess into the fin, wherein extending the recess comprises performing an anisotropic etching process to deepen the recess; and After extending the recess, the recess is filled with a dielectric material.

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