Method for processing a CFET device

Abstract

The invention relates to a method for processing a CFET device. The method comprises the following steps: forming at least one fin structure horizontally extending in one direction on a substrate, wherein the at least one fin structure comprises a first layer stack and a second layer stack located above the first layer stack; forming a set of gate structures around the at least one fin structure, where the set of gate structures is arranged perpendicular to the at least one fin structure and at a determined distance from each other, and wherein the set of gate structures covers the at least one fin structure in a channel region and exposes the at least one fin structure in fin cut regions on opposite sides of the channel region; forming a preliminary fin cut by at least partially removing at least one fin structure in the fin cut region, thereby creating a respective recess between the gate structures in which end faces of the channel layers of the first and second layer stacks are exposed; and forming a cover layer partially covering a sidewall of the recess.

Description

Technical Field

[0001] The present disclosure relates to a method for processing a complementary field effect transistor (CFET) device. Background Art

[0002] In CFETs, different transistor structures, in particular NMOS and PMOS transistor structures, can be stacked on top of each other. For example, compared to nanosheet devices, nanosheet devices include NMOS and PMOS transistors arranged side by side with spacing between them. The stacking of transistor structures enables the effective channel width to be increased.

[0003] A key step in CFET fabrication is the design and fabrication of the source and drain (S / D) terminals of the stacked (top and bottom) transistor structures. Typically, the S / D terminals are then formed on the channels of the bottom and top transistor structures in a complex process that requires multiple CFET-specific process modules, including the formation and removal of multiple layers until the bottom and top epitaxy (epi) are fabricated.

[0004] It would be advantageous to reduce the number of steps (deposition, etching and / or cleaning) and modules during S / D design fabrication in order to reduce the complexity of CFET fabrication. Summary of the invention

[0005] Therefore, it is an object to provide an improved method for processing CFET devices. In particular, the above-mentioned disadvantages should be avoided.

[0006] This object is achieved by the embodiments provided in the appended independent claim. Advantageous implementations of embodiments of the invention are further defined in the dependent claims.

[0007] The first aspect of the present disclosure relates to a method for processing a complementary field effect transistor (CFET) device. The method includes the following steps: forming at least one fin structure extending horizontally in one direction on a substrate, wherein the at least one fin structure includes a first layer stack and a second layer stack located above the first layer stack, wherein the first layer stack includes at least a first channel layer and the second layer stack includes at least a second channel layer; forming a group of gate structures around the at least one fin structure, wherein the group of gate structures are arranged to be perpendicular to the at least one fin structure and at a determined distance from each other, and wherein the group of gate structures covers the at least one fin structure in the channel region and exposes the at least one fin structure in a fin cut region on the opposite side of the channel region; forming a preliminary fin cut by at least partially removing at least one fin structure in the fin cut region, thereby generating a corresponding recess between the gate structures, wherein the end surface of the channel layer of the first and second layer stacks is exposed in the recess; and forming a covering layer partially covering the sidewalls of the recess, wherein the covering layer thereby covers the exposed end surface of the second channel layer, but does not cover the exposed end surface of the first channel layer.

[0008] This achieves the advantage of creating a capping layer in the recess between the two gate structures, which exposes the channel layer of the bottom transistor of the CFET device but covers the channel layer of the top transistor. This greatly facilitates the design and manufacture of the bottom source or drain (S / D) epitaxy and prevents unwanted (on the top) epitaxial growth during the bottom S / D formation process.

[0009] In addition, the formation of the non-conformal cap layer in the recess can eliminate the need for an additional capping spacer (CSP) module that protects the top channel during the bottom S / D epitaxial growth. Therefore, several constraints associated with the CSP module setup can be avoided. For example, spin-on carbon deposition is usually required to protect the bottom channel before the CSP module deposition, which brings additional workload when using CSP modules.

[0010] The first channel layer may be a channel of a first transistor structure of the CFET device, and the second channel layer may be a channel of a second transistor structure.

[0011] The first (or bottom) transistor structure may be arranged in a first level (or tier) of the CFET device, and the second (or top) transistor structure may be arranged in a second level (or tier), wherein the second level is arranged above the first level. This may result in a stacked transistor structure of the CFET device. The CFET device may include further transistor structures or other elements, which may be directly above or below the first and second transistor structures, respectively.

[0012] For example, a CFET device includes a first transistor structure and a second transistor structure. A CFET cell may include one or more CFET devices or portions thereof. A CFET device may be a unit of a CFET cell.

[0013] It is worth noting that in the present disclosure, the terms "below" and "above", "bottom" and "top" or similar terms should be interpreted relative to each other. Specifically, these terms describe the opposite sides of the CFET device, or the opposite sides of any element of the CFET device. These terms can describe the relationship of the elements of the CFET device (e.g., transistor structures, signal wiring lines, power rails, etc.) along the stacking direction of each level (or level) of the CFET device. Therefore, the stacking direction can be aligned with the arrangement of two levels (or even more than two levels) of the CFET device. That is, two or more levels arranged above each other means that the levels are arranged one after another along a certain direction (stacking direction).

[0014] The transistor structure in the present disclosure may be or may include a transistor, such as a field effect transistor (FET), or may be or may include a more complex semiconductor-based structure that functions similarly to a transistor. For example, the semiconductor-based structure may be, for example, a nanosheet structure, a fin structure, or a fork-sheet structure having a gate that partially surrounds or fully surrounds a channel portion. The gate that fully surrounds the channel portion may be, for example, a fully surrounding gate structure.

[0015] The transistor structure of the CFET device of the first aspect can be an NMOS transistor structure or a PMOS transistor structure. For example, the first transistor structure can be an NMOS transistor structure, and the second transistor structure can be a PMOS transistor structure, or vice versa.

[0016] The gate structure may be a dummy gate structure or a virtual gate electrode structure. In a subsequent step, the dummy gate structure may be replaced by a metal gate (ie, electrode).

[0017] The capping layer may be an inner spacer layer or an inner spacer module. The capping layer may cover a sidewall of the gate structure above the recess.

[0018] For example, forming a fin cut means forming a cut, interruption or gap through the fin structure, thereby forming fin portions on either side of the cut.The preliminary fin cut may extend through the fin structure to a preliminary cut level (above the intended final cut level).

[0019] Thus, processing a CFET device may refer to manufacturing or producing a CFET device.

[0020] In one embodiment, the capping layer is made of a dielectric material such as SiN, SiOC, SiON or SiCN.

[0021] In one embodiment, the capping layer is formed by a plasma enhanced atomic layer deposition (PEALD) process.

[0022] In an embodiment, forming the capping layer includes depositing the capping layer with a non-uniform layer thickness in the recess.

[0023] For example, the capping layer may be deposited directly as a non-conformal layer (ie, a non-uniform layer) in the recess.

[0024] In one embodiment, the layer thickness of the cover layer decreases gradually from a top region of the recess facing away from the substrate toward a bottom region of the recess facing the substrate.

[0025] In an embodiment, the capping layer is deposited in the top region of the recess at a higher deposition rate than in the bottom region of the recess.

[0026] This may be due to the high aspect ratio of the gate structures on both sides of the recess, which results in fewer film-forming precursors or atoms reaching the bottom of the recess during deposition. This effect can be enhanced if the distance between the two gate structures is low and / or if the side surfaces of the gate structures are covered by additional layers that further limit the space between the two gate structures.

[0027] In one embodiment, forming the cover layer further comprises: removing a portion of the cover layer deposited in a bottom region of the recess by an etching step.

[0028] In this way, the cover layer can be removed in the bottom region of the recess, in which the exposed end face of the (bottom) channel layer is arranged. As a result, the end face of the bottom channel layer is no longer covered by the cover layer.

[0029] This can be facilitated by the fact that the cover layer has a lower layer thickness in the bottom region of the recess, thereby allowing it to be completely removed there, whereas the cover layer remains intact in the top region of the recess, where it has a greater layer thickness.

[0030] The etching may be a wet etching, for example using a hydrofluoric acid (HF) solution.

[0031] In another example, during the deposition step, no capping layer material is deposited in the bottom region of the recess, or only a small amount of capping layer material is deposited in the bottom region (e.g., due to the high aspect ratio of the recess). In this case, it may not be necessary to perform a removal step (e.g., an additional etching step) to remove the capping layer in the bottom region in order to grow source and / or drain (S / D) epitaxy in this region.

[0032] In one embodiment, the method further comprises the following steps: before forming the capping layer, forming an oxide layer in the recess, wherein the capping layer is formed on the oxide layer. For example, the oxide layer is deposited by ALD (atomic layer deposition).

[0033] This can lead to further degradation of the uniformity of the capping layer and thickness variations of the capping layer, especially on high aspect ratio gate structures. For example, when a PEALD SiN capping layer is applied on an oxide liner (ox+SiN), the SiN thickness depends on the incubation of the SiN on the oxide bottom layer. Different SiN growth and non-uniformity on the recessed sidewalls (respectively the gate structure) may occur, as the plasma from the SiN deposition cannot recover the incubation from the top to the bottom of the sidewalls (i.e., the time when the SiN is not fully deposited may vary from top to bottom).

[0034] In an embodiment, the method further comprises the step of forming a source and / or drain structure in the recess, wherein the source and / or drain structure is arranged to electrically contact the exposed end surface of the first channel layer.

[0035] The source and / or drain structure may be a bottom source and / or drain structure, ie a source and / or drain structure of a bottom transistor structure of a CFET device.

[0036] In one embodiment, the source and / or drain structures are formed only on the surface areas of the recess not covered by the capping layer.

[0037] Thus, the source and / or drain structures are formed with exposed layers of the electrical contact layer stack that are not covered by the cover layer.

[0038] In one embodiment, the source and / or drain structure is formed by an epitaxial growth process. Therefore, the source and / or drain structure may be a source and / or drain epitaxial structure.

[0039] Specifically, source and / or drain (S / D) epitaxy is not grown on the capping layer. Therefore, undesired SD epitaxial growth does not occur in the recessed region covered by the capping layer.

[0040] In an embodiment, the method further comprises the step of forming a further source and / or drain structure in the recess, wherein the further source and / or drain structure is arranged to electrically contact the second channel layer.

[0041] The further source and / or drain structure may be a top source and / or drain structure, ie a source and / or drain structure of a top transistor structure of the CFET device.

[0042] The (bottom) source and / or drain structure may be an n-type structure, while the further (top) source or drain may be a p-type structure, or vice versa.

[0043] In one embodiment, before forming the further source and / or drain structure, a capping layer covering an end surface of the second channel layer is removed.

[0044] For example, after the metallization of the (bottom) source and / or drain structure, metal trenching can be performed and the capping layer covering the second channel layer can be removed. A Si3N4 liner and / or a SiO2 layer can then be deposited in the recess. Subsequently, the Si3N4 / SiO2 layer can be partially removed and the further S / D structure can be metallized.

[0045] A second aspect of the present invention provides a complementary field effect transistor (CFET) device obtainable by a method according to the first aspect of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The above aspects and implementations are explained in the following detailed description with reference to the accompanying drawings:

[0047] Figure 1 AE shows the steps of a method for processing a CFET device according to an embodiment;

[0048] Figure 2A -D shows the steps of a method for processing a CFET device according to an embodiment;

[0049] Figure 3 shows a cross-sectional view of a CFET device according to an embodiment; and

[0050] Figure 4 An electron microscopic image of a CFET device according to an embodiment is shown. DETAILED DESCRIPTION

[0051] Figure 1 AE shows the steps of a method for processing a CFET device according to an embodiment. Figure 1 AE show cross-sectional views through the yz plane (as shown in a Cartesian coordinate system), which is parallel to the channel direction (y direction) of the CFET device.

[0052] In the first step, if Figure 1 As shown in FIG. 1A , the method includes forming at least one fin structure 23 extending horizontally in one direction (here: y direction) on a substrate 14, wherein the at least one fin structure 23 includes a first layer stack 23a and a second layer stack 23b above the first layer stack. The first layer stack 23a includes at least a first channel layer 11a, and the second layer stack 23b includes at least a second channel layer 12a.

[0053] The first channel layer 11a can form one or more channels of a first transistor structure of the CFET device, and the second channel layer 12a can form one or more channels of a second transistor structure of the CFET device. For example, the first transistor structure is the bottom transistor structure of the CFET device, and the second transistor structure is the top transistor structure. The bottom transistor structure can be NMOS, and the top transistor structure can be PMOS, or vice versa.

[0054] The first layer stack 23a and the second layer stack 23b may be arranged directly on top of each other. Each layer stack 23a, 23b may include a plurality of alternating layers, including at least one channel layer (e.g., Si layer) and at least one dielectric layer. For example, each layer stack 23a, 23b may include alternating Si and SiGe layers. The top layer of the fin structure 23 may be a Si3N4 layer. A dielectric separation layer stack (e.g., an intermediate dielectric isolation MDI) may be formed between the first layer stack 23a and the second layer stack 23b. However, the dielectric separation layer stack may also be part of the first layer stack 23a or the second layer stack 23b.

[0055] The fin structure 23 may be formed on the substrate 14 by active nanosheet patterning, for example by patterning of a nanosheet stack on the substrate 14. The nanosheet stack may include a layer stack 23a, 23b and a dielectric separation layer stack. The substrate 14 may be a silicon substrate or a silicon on insulator (SOI) substrate.

[0056] exist Figure 1 In the second step shown in FIG. 2B , the method includes forming a group of gate structures 32 around at least one fin structure 23 , wherein the group of gate structures 31 are arranged to be perpendicular to at least one fin structure 23 and to be at a certain distance from each other. In addition, the group of gate structures 32 covers at least one fin structure 23 in the channel region 51 and exposes at least one fin structure in the fin cut region 52 on the opposite side of the channel region 51 .

[0057] The gate structure 32 may extend along the x-direction (perpendicular to the channel direction) and surround at least one fin structure 23. This may be referred to as a full-surround gate design.

[0058] The gate structure 32 may be a dummy gate structure that is replaced by a replacement metal gate in a subsequent step. The gate structure 32 may be formed on a gate dielectric layer (eg, gate oxide) disposed around the fin structure 23 .

[0059] In a further step, if Figure 1As shown in FIG. 3 , the method includes forming a preliminary fin cut by at least partially removing at least one fin structure 23 in a fin cut region 52 , thereby producing a corresponding recess 53 between the gate structures 32 , wherein an end surface of the channel layer 11a of the first layer stack 23a and an end surface of the channel layer 12a of the second layer stack 23b are exposed in the recess 53 .

[0060] For example, the fin structure 23 including the channel layers 11a, 12a is at least partially removed in the fin cut region 52. However, the channel layers 11a, 12a may remain intact in the channel region 51 between the fin cut regions 52.

[0061] The fin structure 23 may be grooved in the fin cut region 52 by a suitable wet or dry etching process. The location of the fin cut region 52 may be defined by a photolithography mask (eg, a fin cut mask).

[0062] After forming the fin cut region, the SiGe layer of the first layer stack 23 a and / or the second layer stack 23 b may be removed and / or an intermediate dielectric isolation layer may be formed.

[0063] In a further step, if Figure 1 As shown in FIG. D, a capping layer 54 is formed. The capping layer 54 partially covers the sidewalls of the recess 53 and thus covers the exposed end surface of the second channel layer 12a, but does not cover the exposed end surface of the first channel layer 11a.

[0064] Specifically, the cover layer 54 may be an inner spacer layer.

[0065] The capping layer may be a dielectric layer. For example, the capping layer 54 is a silicon nitride (Si3N4, or simply SiN) layer, a silicon oxycarbide (SiOC) layer, a silicon oxynitride (SiON) layer, or a silicon carbonitride (SiCN) layer.

[0066] The capping layer 54 may be formed by a plasma enhanced atomic layer deposition (PEALD) process.

[0067] The cover layer 54 may be a non-conformal layer, for example a layer having a non-uniform layer thickness in the recess 53. There may be many different reasons why the cover layer is non-conformal, which are discussed below:

[0068] First, as a result of the deposition process (e.g., PEALD) itself, the capping layer 54 may have an inherently low conformality. For example, the layer thickness of the capping layer 54 may gradually decrease from the top region of the recess 53 (the top region is the region facing away from the substrate 14) toward the bottom region of the recess 53 (the bottom region is directly above the substrate 14).

[0069] This gradual reduction in layer thickness from top to bottom may be caused and / or enhanced by the geometry of the recess 53. Specifically, the high aspect ratio of the gate structure 32 and / or the reduced space between the two gate structures 32 may result in reduced deposition of the capping layer 54 material in the bottom region of the recess 53 (i.e., a reduced deposition rate) compared to the top region of the recess 53. For example, there may be additional layers, such as gate spacers, on the sidewalls of the gate structure 32 to reduce the CPP (contact polysilicon pitch) at the ISP (internal spacer) module level. Therefore, due to the high aspect ratio (e.g., height and critical dimension spacing) of the gate structure 23 and / or the narrow recess 53 geometry, fewer film-forming precursors or atoms may reach the bottom region during deposition.

[0070] The method may also include the step of forming an oxide (e.g., SiO2) layer in the recess prior to forming the capping layer, wherein the capping layer is formed on the oxide layer. This may result in a further reduction in the uniformity of the capping layer 54, for example, when the PEALDSiN capping layer 54 is applied in combination with an oxide liner layer (ox+SiN) that relies on the incubation of plasma SiN on an oxide bottom layer.

[0071] The oxide layer may be formed by a suitable deposition process, such as CVD or ALD. The oxide layer may also be formed due to intrinsic oxidation.

[0072] All of these effects can be used to produce a non-conformal capping layer 54 with a suitable target thickness at the top and bottom of the recess 53. In particular, the capping layer 54 can be sufficient to achieve cavity sealing of the trenched SiGe layers of the first layer stack 23a and the second layer stack 23b.

[0073] After deposition of the (non-uniform) capping layer 54, the portion of the capping layer deposited in the bottom region of the recess 53 may be removed by a suitable etching step. For example, the capping layer 54 in the bottom region of the recess may be removed by a wet etching step, for example with an HF solution. Subsequently, the CFET device may be cleaned with a soft ex-situ pre-epi cleaning step.

[0074] Thus, it is possible to utilize the non-uniform layer thickness of the cover layer 54. For example, the etching parameters (etchant concentration, etching time) can be selected such that the thinner cover layer 54 at the bottom of the recess 53 (covering the channel layer 11a of the first layer stack 23a) is completely removed, while the thicker cover layer 54 at the top of the recess 53 (covering the channel layer 12a of the second layer stack 23a) remains intact.

[0075] Therefore, in Figure 1In the next step shown in E, the end surface of the bottom channel layer is no longer covered by the capping layer 54 and can contact the bottom source and / or drain (S / D) structure 11b.

[0076] The S / D structure 11 b may be formed through an epitaxial growth process, and is arranged to electrically contact an exposed end surface of the first channel layer 11 a that is not covered by the capping layer 54 .

[0077] For example, the source and / or drain structure 11b is thus formed (grown) only on the surface area of ​​the recess 53 that is not covered by the cover layer 54. As a result, the source and / or drain structure 11b contacts only the exposed layers of the layer stack 23a that are not covered by the cover layer (on the bottom of the recess). This may be due to the fact that the dielectric material of the cover layer 54 prevents the epitaxial growth of the S / D structure.

[0078] Before forming the S / D structure 11 b , a pre-epitaxial cleaning step may be performed, thereby removing residues that may hinder good epitaxial growth on the end face of the Si channel.

[0079] Due to the non-conformal cover layer, no other layers or modules are required, in particular no cover spacer module and / or spin-on carbon is required to design and manufacture the bottom S / D structure 11b. Eliminating the need for a cover spacer module has the advantage of reducing the impact of downstream processing steps (deposition+etching+cleaning) required for the formation and removal of the cover spacer. For example, when applying a cover spacer module, additional plasma SiN or other dielectric layers will be deposited that are difficult to completely remove. Applying too many SiN removal steps (wet or dry) to remove the cover spacer module may be detrimental to the epitaxial growth at the bottom of the recess 53.

[0080] The method for processing a CFET device may further comprise forming a further (top) source and / or drain structure in the recess 53 , wherein the further source and / or drain epitaxial structure is arranged to electrically contact the second channel layer.

[0081] For example, the (bottom) source and / or drain structure 11 b is an n-type structure, while the further (top) source or drain is a p-type structure, or vice versa.

[0082] In order to form the further source and / or drain structure, the capping layer covering the end surface of the second channel layer 12 a may be removed before forming the further source and / or drain structure.

[0083] For example, after forming the (bottom) source and / or drain structure, metal trenching can be performed and the capping layer 54 covering the second channel layer 12a can be removed. Subsequently, a Si3N4 liner and / or a SiO2 layer can be deposited in the recess. Subsequently, the Si3N4 / SiO2 layer can be partially removed and the formation (metallization) of the further S / D structure can be performed. Figure 3 A cross-section of a fully formed CFET with bottom and top S / D structures is shown in FIG.

[0084] Figure 2A -D shows a process flow of a method for fabricating a CFET device according to an embodiment.

[0085] Figure 2A The fin cutting step (such as Figure 1 C) is a cross-sectional view of the fin structure 23 covered by the gate structure 32. Fin cutting can also be referred to as S / D groove etching. The gate structure 32 may include a gate spacer to define the fin cut.

[0086] The (dummy) gate structure 32 may be formed of aSi (amorphous silicon). The gate structure 32 may include silicon nitride (Si3N4) and silicon oxide (SiO x )layer.

[0087] In the next step, if Figure 2B As shown, further cavity etching is performed, whereby various layers of the fin structure 23 , such as various SiGe layers, are at least partially removed.

[0088] Then, if Figure 2C As shown, the capping layer 54 is deposited in the recess 53 between the gate structures 32. Thus, the capping layer 54 covering the bottom region of the recess 53 (eg, the bottom channel layer 11a) may have a lower layer thickness than the capping layer 54 covering the upper region of the recess (eg, the top channel layer 12a).

[0089] In an optional further step (not shown), the capping layer 54 may be further grooved (eg by wet etching) so that the layer 54 is completely removed in the bottom region and the end face of the bottom channel layer 11a is exposed, while the top channel layer 12a remains covered.

[0090] Then, if Figure 2D As shown, a (bottom) source and / or drain structure 11 b may be formed in electrical contact with the bottom channel layer 11 a. Such formation may be achieved by an epitaxial growth process in which S / D epitaxy is grown only in the region of the recess 53 not covered by the capping layer 54 .

[0091] Figure 3 It is shown that by Figure 1A CFET device 10 is manufactured by the method shown in any one of AE and / or FIG. 2 .

[0092] like Figure 3 As shown, the bottom device S / D contact 61 may be arranged on top of the bottom S / D structure 11b, and the top device S / D contact 63 may be arranged on top of the top S / D structure 12b. A contact isolation 62 may be arranged between the bottom device S / D contact 61 and the top S / D structure 12b.

[0093] The bottom S / D structure 11b and the top S / D structure 12b can be formed of doped silicon, for example, by an epitaxial growth process. For example, the bottom S / D structure 11b can be formed of Si:B, and the top S / D structure 12b can be formed of Si:P, or vice versa. Generally, depending on the requirements for the CFET device, the bottom transistor structure can be an NMOS or PMOS structure. Therefore, a suitable material for the bottom S / D structure 11b can be selected (for example, SiGe:B for NMOS or Si:P for PMOS).

[0094] exist Figure 3 In the illustrated CFET device 10 , the dummy gate structure 32 is replaced with a replacement metal gate 12 c , which is electrically connected to the gate contact 65 .

[0095] Figure 3 Also shown is an intermediate dielectric isolation layer 66 disposed between the various layers of the fin structure 23 , in particular between the bottom channel 11 a and the top channel 12 a .

[0096] Figure 4 An electron microscopy (EM) image of a CFET device according to an embodiment is shown.

[0097] Both EM images show a cross section of a CFET device after forming a bottom source and / or drain structure 11b. The CFET device shown in the left EM image is processed using conventional techniques using an additional capping spacer (CSP) module, while the CFET device in the right EM image is processed using Figure 1 The methods AE and FIG. 2 are processed using a non-conformal cap layer 54 dielectric.

[0098] In both CFET devices, epitaxial growth around the top channel 12a can be avoided during the formation of the bottom S / D structure 11b. However, in the left EM image, unwanted residual CSP material still remains on the top region of the gate structure 32 of the CFET device. This unwanted CSP residue is to be removed in further processing steps, which may be a source of device damage and increase manufacturing workload.

[0099] In contrast, the CFET device shown in the right EM image has no such residue remaining and therefore requires no additional processing steps.

[0100] In the claims and in the description of the present disclosure, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single element may fulfill the functions of several entities or items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used in an advantageous implementation.

Claims

1. A method for processing a complementary field effect transistor (CFET) device (10), comprising the following steps: At least one fin structure (23) extending horizontally in one direction is formed on a substrate (14), wherein the at least one fin structure (23) includes a first layer stack (23a) and a second layer stack (23b) above the first layer stack, wherein the first layer stack (23a) includes at least a first channel layer (11a), and the second layer stack (23b) includes at least a second channel layer (12a); forming a set of gate structures (32) around the at least one fin structure (23), wherein the set of gate structures (32) are arranged perpendicular to the at least one fin structure (23) and at a determined distance from each other, and wherein the set of gate structures (32) covers the at least one fin structure (23) in the channel region (51) and exposes the at least one fin structure (23) in the fin cut region (52) on the opposite side of the channel region (51); A preliminary fin cut is formed by at least partially removing the at least one fin structure (23) in the fin cut region (52), thereby generating corresponding recesses (53) between the gate structures (32), wherein end surfaces of the channel layer (11a) of the first layer stack (23a) and end surfaces of the channel layer (12a) of the second layer stack (23b) are exposed in the recesses (53); and A cover layer (54) is formed to partially cover the sidewall of the recess (53), wherein the cover layer (54) thereby covers the exposed end surface of the second channel layer (12a) but does not cover the exposed end surface of the first channel layer (11a).

2. The method according to claim 1, Features The capping layer (54) is made of a dielectric material such as SiN, SiOC, SiON or SiCN.

3. The method according to claim 1 or 2, It is characterized in that The capping layer (54) is formed by a plasma enhanced atomic layer deposition (PEALD) process.

4. The method according to any one of the preceding claims, It is characterized in that Forming the covering layer (54) comprises: A covering layer (54) having a non-uniform layer thickness is deposited in the recess (53).

5. The method according to claim 4, It is characterized in that The layer thickness of the cover layer (54) gradually decreases from a top region of the recess (53) facing away from the substrate (14) toward a bottom region of the recess (53) facing the substrate (14).

6. The method according to claim 4 or 5, It is characterized in that The capping layer (54) is deposited in the top region of the recess (53) at a higher deposition rate than in the bottom region of the recess (53).

7. The method according to any one of claims 4 to 6, It is characterized in that Forming the covering layer (54) further comprises: Part of the cover layer (54) deposited in the bottom region of the recess (53) is removed by an etching step.

8. The method according to any one of the preceding claims, characterized in that The following steps are also included: Before forming the capping layer (54), an oxide layer is formed in the recess (53), wherein the capping layer (54) is formed on the oxide layer.

9. The method according to any one of the preceding claims, characterized in that The following steps are also included: A source and / or drain structure (11b) is formed in the recess (53), wherein the source and / or drain structure (11b) is arranged to electrically contact the exposed end surface of the first channel layer (11a).

10. The method according to claim 9, It is characterized in that The source and / or drain structure (11b) is formed only on the surface area of ​​the recess (53) not covered by the cover layer (54).

11. The method according to claim 9 or 10, It is characterized in that The source and / or drain structure (11b) is formed by an epitaxial growth process.

12. The method according to any one of claims 9 to 11, characterized in that The following steps are also included: A further source and / or drain structure (12b) is formed in the recess (53), wherein the further source and / or drain structure (12b) is arranged to electrically contact the second channel layer (12a).

13. The method according to claim 12, Before forming the further source and / or drain structure (12b), the covering layer (54) covering the end surface of the second channel layer (12a) is removed.

14. A complementary field effect transistor (CFET) device (10) obtainable by a method according to any one of the preceding claims.

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