Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof, in the preparation method, a photomask used for opening lightly-doped drain regions is adjusted, and the distance between second lightly-doped drain regions of a medium-voltage device region is enlarged, so that after a grid electrode of the medium-voltage device region is prepared, the lightly-doped drain regions of the medium-voltage device region are separated from the second lightly-doped drain regions of the medium-voltage device region; according to the invention, the transverse size of the spatial overlapping region of the grid electrode of the medium-voltage device region and the lightly doped drain region 2 is smaller than the transverse size of the spatial overlapping region of the grid electrode of the traditional medium-voltage device and the lightly doped drain region; meanwhile, the oxidation dielectric layer in the medium-voltage device area is thinned, so that the final thickness of the gate oxide layer is smaller than that of the gate oxide layer of a traditional medium-voltage device, the current Ioff of the medium-voltage device in an off state can be reduced, the current Idsat of the medium-voltage device working in a saturation area can be improved, and the electrical performance of the device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] The UD18 CMOS device can replace the existing UD33 / UD55 CMOS devices used for switching functions, reducing area and thus improving competitiveness.

[0003] However, the current UD18 CMOS device model is based on an 8V gate oxide layer, which has poor roll-off. The length of the UD1.8V PMOS device (P18 L) is 0.67μm, and I off The current under reverse bias is too large, and the UD1.8V NMOS device turns on slowly.

[0004] At present, due to the problem of slow turn-on speed of UD1.8V NMOS device, the gate oxide layer is thinned for use in subsequent products. After the gate oxide layer of the CMOS device is thinned, the length of the UD1.8V PMOS device (P18 L) = 0.78 / 0.83μm. The length of the UD1.8V PMOS device of the thinned CMOS device is longer than the length of the UD1.8V PMOS device of the CMOS device before thinning, which improves the turn-on speed of the UD1.8VNMOS device. However, I off It is still too large and does not meet the electrical requirements of the device. Summary of the Invention

[0005] The present application provides a semiconductor device and a method for manufacturing the same, which can solve the problem of I / O of medium voltage devices in CMOS devices. off A rather large problem.

[0006] In one aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, comprising:

[0007] A substrate is provided, wherein the substrate comprises a low-voltage device region, a medium-voltage device region, and a high-voltage device region, and a plurality of shallow trench isolation structures for isolating different device regions are formed in the substrate;

[0008] Performing ion implantation on the substrate to form a first lightly doped drain region in the low-voltage device region, a second lightly doped drain region in the medium-voltage device region, and a third lightly doped drain region in the high-voltage device region;

[0009] forming an oxidizing medium layer, wherein the oxidizing medium layer covers the substrate;

[0010] coating a photoresist layer on the oxidizing dielectric layer;

[0011] defining an opening pattern of the medium voltage device area on the photoresist layer by a photolithography process to obtain a patterned photoresist layer;

[0012] Using the patterned photoresist layer as a mask, etching a portion of the oxide dielectric layer in the medium voltage device area to obtain a gate oxide layer in the medium voltage device area;

[0013] removing the patterned photoresist layer;

[0014] forming a polysilicon layer, wherein the polysilicon layer covers the gate oxide layer of the medium voltage device region;

[0015] The polysilicon layer of the medium voltage device area is etched to obtain a gate of the medium voltage device area, wherein the lateral dimension of the spatial overlapping area between the gate and the lightly doped drain region 2 in the substrate does not exceed one-sixth of the lateral dimension of the gate of the medium voltage device area.

[0016] Optionally, in the method for preparing the semiconductor device, in the substrate of the medium voltage device area, the spacing between the two lightly doped drain regions 2 on both sides of the gate of the medium voltage device area is at least three-fifths of the lateral dimension of the gate of the medium voltage device area.

[0017] Optionally, in the method for preparing the semiconductor device, the thickness of the gate oxide layer in the medium voltage device region is less than or equal to

[0018] Optionally, in the method for preparing the semiconductor device, before removing the patterned photoresist layer and after forming the polysilicon layer, the method for preparing the semiconductor device further comprises:

[0019] Ion implantation is performed on the substrate of the medium voltage device region to form a source region and a drain region in the second lightly doped drain region on both sides of the gate of the medium voltage device region.

[0020] Optionally, in the method for preparing the semiconductor device, after etching the polysilicon layer of the medium voltage device region to obtain the gate of the medium voltage device region, the method for preparing the semiconductor device further includes:

[0021] A gate sidewall spacer is formed, wherein the gate sidewall spacer is located on both sides of the gate of the medium voltage device region and on the gate oxide layer.

[0022] On the other hand, an embodiment of the present application further provides a semiconductor device, including:

[0023] A substrate comprising a low-voltage device region, a medium-voltage device region, and a high-voltage device region, wherein a plurality of shallow trench isolation structures for isolating different device regions are formed in the substrate;

[0024] a lightly doped drain region 1, a lightly doped drain region 2, and a lightly doped drain region 3, wherein the lightly doped drain region 1 is located in the substrate of the low-voltage device region, the lightly doped drain region 2 is located in the substrate of the medium-voltage device region, and the lightly doped drain region 3 is located in the substrate of the high-voltage device region;

[0025] an oxidizing dielectric layer, the oxidizing dielectric layer covering the substrate of the low-voltage device region and the high-voltage device region;

[0026] a gate oxide layer, wherein the gate oxide layer covers the substrate of the medium voltage device area;

[0027] A gate is located on the gate oxide layer, wherein the lateral dimension of the spatial overlap area between the gate and the lightly doped drain region 2 in the substrate does not exceed one-sixth of the lateral dimension of the gate in the medium voltage device region.

[0028] Optionally, in the semiconductor device, in the substrate of the medium voltage device region, the spacing between the two lightly doped drain regions 2 on both sides of the gate of the medium voltage device region is at least three-fifths of the lateral dimension of the gate of the medium voltage device region.

[0029] Optionally, in the semiconductor device, the thickness of the gate oxide layer of the medium voltage device region is less than or equal to

[0030] The technical solution of this application has at least the following advantages:

[0031] In the present application, without adding an additional mask, by adjusting the mask for opening the lightly doped drain region of the CMOS device, the spacing between the lightly doped drain regions 2 of the medium voltage device region in the CMOS device is expanded. Therefore, after preparing the gate of the medium voltage device region, the lateral size of the spatially overlapping region between the gate of the medium voltage device region and the lightly doped drain region 2 of the present application is smaller than the lateral size of the spatially overlapping region between the gate and the lightly doped drain region of a conventional medium voltage device. At the same time, the oxide dielectric layer of the medium voltage device region is thinned so that the final gate oxide layer thickness is smaller than the gate oxide layer thickness of the conventional medium voltage device. This can reduce the current I of the medium voltage device in the off state. off , and can also increase the current I of the medium voltage device when it is working in the saturation region dsat , when the device size is further reduced, the leakage of the device is reduced and the electrical performance of the device is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0033] Figure 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0034] Figure 2-Figure 7 Schematic diagram of a semiconductor structure in each process step of manufacturing a semiconductor device according to an embodiment of the present invention;

[0035] The description of the accompanying drawings is as follows:

[0036] 10 - substrate, 11 - shallow trench isolation structure, 21 - photoresist layer 1, 22 - photoresist layer 2, 31 - lightly doped drain region 1, 32 - lightly doped drain region 2, 33 - lightly doped drain region 3, 40 - oxide dielectric layer, 41 - gate oxide layer of the medium voltage device, 50 - gate of the medium voltage device. DETAILED DESCRIPTION

[0037] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0038] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0039] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0040] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0041] The present invention provides a method for preparing a semiconductor device. Figure 1 , Figure 1 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein the method for manufacturing a semiconductor device comprises:

[0042] First, perform step S1: refer to Figure 2 , Figure 2 This is a schematic diagram of the semiconductor structure after the shallow trench isolation structure is formed in an embodiment of the present application. A substrate 10 is provided, and the substrate 10 includes a low-voltage device area, a medium-voltage device area and a high-voltage device area. A plurality of shallow trench isolation structures 11 for isolating different device areas (high-voltage device area, medium-voltage device area and low-voltage device area) are formed in the substrate 10.

[0043] This embodiment takes the medium-voltage device region as PMOS as an example to continue to introduce the method for preparing the semiconductor device provided by the present application.

[0044] In this embodiment, an N-type well region (not shown) is further formed in the substrate 10 of the medium voltage device region.

[0045] Then, execute step S2: refer to Figure 3 , Figure 3 This is a schematic diagram of the semiconductor structure after forming the lightly doped drain region 1, the lightly doped drain region 2 and the lightly doped drain region 3 in an embodiment of the present application. First, a photoresist layer 21 is coated on the substrate 10, and then a lightly doped drain region pattern is defined on the photoresist layer 21 through a specific mask. Then, the patterned photoresist layer 21 is used as a mask, and finally, ion implantation is performed on the substrate 10 to form a lightly doped drain region 1 31 in the low-voltage device area, a lightly doped drain region 2 32 in the medium-voltage device area, and a lightly doped drain region 33 in the high-voltage device area.

[0046] In this embodiment, P-type ion implantation is performed on the substrate 10 in the medium voltage device region to form a second P-type lightly doped drain region 32 in the medium voltage device region.

[0047] Next, execute step S3: refer to Figure 4 , Figure 4 1 is a schematic diagram of a semiconductor structure after forming an oxidizing dielectric layer according to an embodiment of the present application. The oxidizing dielectric layer 40 is formed, and the oxidizing dielectric layer 40 covers the substrate 10 .

[0048] For further reference, Figure 5 , Figure 5 This is a schematic diagram of the semiconductor structure after forming the oxide dielectric layer of each device area in an embodiment of the present application. The oxide dielectric layer 40 can be etched to obtain the oxide dielectric layer 40 of each device area (high-voltage device area, medium-voltage device area and low-voltage device area).

[0049] Next, execute step S4: refer to Figure 6 , Figure 6 1 is a schematic diagram of a semiconductor structure after forming a gate oxide layer in a medium voltage device region according to an embodiment of the present application. A second photoresist layer 22 is coated on the oxide dielectric layer 40 and the surface of the substrate 10 .

[0050] Further, execute step S5: continue to refer to Figure 6 , an opening pattern (gate oxide layer) of the medium voltage device area is defined on the second photoresist layer 22 by a photolithography process to obtain a patterned second photoresist layer 22 .

[0051] Then, execute step S6: continue to refer to Figure 6 Using the patterned photoresist layer 22 as a mask, the oxide dielectric layer 40 of a portion of the thickness of the medium voltage device region is etched to obtain a gate oxide layer 41 of the medium voltage device region.

[0052] Preferably, the thickness of the gate oxide layer 41 of the medium voltage device region is less than or equal to

[0053] Furthermore, step S7 is performed: removing the patterned photoresist layer 22 .

[0054] In this embodiment, after removing the patterned photoresist layer 22, ion implantation may be performed on the medium voltage device region substrate 10 to form source and drain regions (not shown) in the lightly doped drain region 2 32 on both sides of the gate 50 of the medium voltage device region.

[0055] In other embodiments, after removing the patterned photoresist layer 22, the oxide dielectric layer 40 of the high-voltage device area and the oxide dielectric layer 40 of the low-voltage device can be etched back through the same photolithography and etching process to obtain the gate oxide layer of the high-voltage device area and the gate oxide layer of the low-voltage device area (not shown), respectively.

[0056] Next, step S8 is performed: forming a polysilicon layer (not shown), wherein the polysilicon layer at least covers the gate oxide layer 41 of the medium voltage device region.

[0057] Finally, execute step S9: reference Figure 7 , Figure 7 This is a schematic diagram of the semiconductor structure after forming the gate of the medium-voltage device region in an embodiment of the present application. The polysilicon layer of the medium-voltage device region is etched to obtain the gate 50 of the medium-voltage device region, wherein the lateral dimension d1 of the spatial overlap region between the gate 50 and the lightly doped drain region 2 32 in the substrate 10 does not exceed one-sixth of the lateral dimension d2 of the gate of the medium-voltage device region. Without adding an additional mask, the present application expands the spacing between two adjacent lightly doped drain regions 2 in the medium-voltage device region in the CMOS device by adjusting the mask to open the lightly doped drain region. After preparing the gate of the medium-voltage device region, the lateral dimension of the spatial overlap region between the gate of the medium-voltage device region of the present application and the lightly doped drain region 2 is smaller than the lateral dimension of the spatial overlap region between the gate and the lightly doped drain region of a conventional medium-voltage device. When the device size is further reduced, the current I of the medium-voltage device in the off state can be reduced. off .

[0058] In this embodiment, the lateral dimension d1 of the spatially overlapping region between the gate 50 and the second lightly doped drain region 32 in the substrate 10 is one sixth of the lateral dimension d2 of the gate in the medium voltage device region.

[0059] Preferably, in the substrate of the medium voltage device region, a distance between the two lightly doped drain regions 2 on both sides of the gate of the medium voltage device region is at least three fifths of a lateral dimension d2 of the gate of the medium voltage device region.

[0060] In this embodiment, in the substrate of the medium voltage device region, the distance between the two lightly doped drain regions 2 on both sides of the gate of the medium voltage device region is three fifths of the lateral dimension d2 of the gate of the medium voltage device region.

[0061] In the present application, without adding an additional mask, by adjusting the mask for opening the lightly doped drain region of the CMOS device, the distance between two adjacent lightly doped drain regions 2 in the medium voltage device region of the CMOS device is expanded. Therefore, after preparing the gate of the medium voltage device region, the lateral size of the spatially overlapping area between the gate and the lightly doped drain region 2 of the medium voltage device region of the present application is smaller than the lateral size of the spatially overlapping area between the gate and the lightly doped drain region of the conventional medium voltage device. At the same time, the oxide dielectric layer of the medium voltage device region is thinned so that the final gate oxide layer thickness is smaller than the gate oxide layer thickness of the conventional medium voltage device. This can reduce the current I of the medium voltage device in the off state. off , and can also increase the current I of the medium voltage device when it is working in the saturation region dsat, when the device size is further reduced, the leakage of the device is reduced and the electrical performance of the device is improved.

[0062] Furthermore, after etching the polysilicon layer of the medium voltage device area to obtain the gate 50 of the medium voltage device area, the preparation method of the semiconductor device may also include: forming a gate sidewall (not shown), which is located on both sides of the gate of the medium voltage device area and on the gate oxide layer.

[0063] Based on the same inventive concept, the present application also provides a semiconductor device, referring to Figure 7 , the semiconductor device comprises:

[0064] A substrate 10, comprising a low-voltage device region, a medium-voltage device region, and a high-voltage device region, wherein a plurality of shallow trench isolation structures 11 for isolating different device regions are formed in the substrate;

[0065] A lightly doped drain region 1 31, a lightly doped drain region 2 32, and a lightly doped drain region 33, wherein the lightly doped drain region 1 31 is located in the substrate 10 of the low-voltage device region, the lightly doped drain region 2 32 is located in the substrate 10 of the medium-voltage device region, and the lightly doped drain region 33 is located in the substrate 10 of the high-voltage device region;

[0066] an oxidized dielectric layer 40 , the oxidized dielectric layer 40 being located on the substrate 10 in the low-voltage device region and the high-voltage device region;

[0067] A gate oxide layer 41 of a medium voltage device region, wherein the gate oxide layer 41 is located on the substrate 10 of the medium voltage device region;

[0068] The gate 50 of the medium voltage device area is located on the gate oxide layer 41, wherein the lateral dimension d1 of the spatial overlapping area between the gate 50 and the lightly doped drain region 2 32 in the substrate 10 does not exceed one sixth of the lateral dimension d2 of the gate of the medium voltage device area.

[0069] Preferably, in the substrate 10 of the medium voltage device region, the spacing between the two lightly doped drain regions 32 on both sides of the gate 50 of the medium voltage device region is at least three-fifths of the lateral dimension d2 of the gate 50 of the medium voltage device region.

[0070] Preferably, the thickness of the gate oxide layer 41 of the medium voltage device region is less than or equal to

[0071] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: A substrate is provided, wherein the substrate comprises a low voltage device region, a medium voltage device region and a high voltage device region, and a plurality of shallow trench isolation structures for isolating different device regions are formed in the substrate; Performing ion implantation on the substrate respectively, so as to form a lightly doped drain region 1 in the low voltage device region, a lightly doped drain region 2 in the medium voltage device region, and a lightly doped drain region 3 in the high voltage device region; forming an oxidizing medium layer, wherein the oxidizing medium layer covers the substrate; coating a photoresist layer on the oxidizing medium layer; Defining an opening pattern of the medium voltage device area on the photoresist layer by a photolithography process to obtain a patterned photoresist layer; Using the patterned photoresist layer as a mask, etching a partial thickness of the oxide dielectric layer in the medium voltage device area to obtain a gate oxide layer in the medium voltage device area; removing the patterned photoresist layer; forming a polysilicon layer, wherein the polysilicon layer covers the gate oxide layer of the medium voltage device region; The polysilicon layer of the medium voltage device area is etched to obtain a gate of the medium voltage device area, wherein the lateral dimension of the spatially overlapping area between the gate and the lightly doped drain region 2 in the substrate does not exceed one sixth of the lateral dimension of the gate of the medium voltage device area.

2. The method for preparing a semiconductor device according to claim 1, wherein: In the substrate of the medium voltage device region, a distance between the two lightly doped drain regions 2 on both sides of the gate of the medium voltage device region is at least three fifths of a lateral dimension of the gate of the medium voltage device region.

3. The method for preparing a semiconductor device according to claim 1, characterized in that: The thickness of the gate oxide layer in the medium voltage device region is less than or equal to 4. The method for preparing a semiconductor device according to claim 1, wherein: Before removing the patterned photoresist layer and after forming the polysilicon layer, the method for preparing the semiconductor device further includes: Ion implantation is performed on the medium voltage device region substrate to form a source region and a drain region in the lightly doped drain region 2 on both sides of the gate of the medium voltage device region.

5. The method for preparing a semiconductor device according to claim 1, characterized in that: After etching the polysilicon layer of the medium voltage device region to obtain a gate of the medium voltage device region, the method for preparing the semiconductor device further includes: A gate sidewall spacer is formed, wherein the gate sidewall spacer is located at two sides of the gate of the medium voltage device region and on the gate oxide layer.

6. A semiconductor device, characterized in that: include: A substrate, the substrate comprising a low voltage device region, a medium voltage device region and a high voltage device region, wherein a plurality of shallow trench isolation structures for isolating different device regions are formed in the substrate; A lightly doped drain region 1, a lightly doped drain region 2 and a lightly doped drain region 3, wherein the lightly doped drain region 1 is located in the substrate of the low voltage device region, the lightly doped drain region 2 is located in the substrate of the medium voltage device region, and the lightly doped drain region 3 is located in the substrate of the high voltage device region; An oxidized dielectric layer, the oxidized dielectric layer covering the substrate of the low voltage device area and the high voltage device area; A gate oxide layer, the gate oxide layer covering the substrate of the medium voltage device area; A gate is located on the gate oxide layer, wherein the lateral dimension of the spatially overlapping area between the gate and the lightly doped drain region 2 in the substrate does not exceed one sixth of the lateral dimension of the gate in the medium voltage device region.

7. The semiconductor device according to claim 6, characterized in that In the substrate of the medium voltage device region, a distance between the two lightly doped drain regions 2 on both sides of the gate of the medium voltage device region is at least three fifths of a lateral dimension of the gate of the medium voltage device region.

8. The semiconductor device according to claim 6, characterized in that The thickness of the gate oxide layer in the medium voltage device region is less than or equal to

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