Manufacturing method of U-shaped trench gate with inner side wall structure

Abstract

The invention provides a manufacturing method of a U-shaped trench gate with inner side wall structures, and the method comprises the steps: forming a side wall structure located at each protruding polycrystalline silicon side wall, and enabling the side wall structures to extend into an epitaxial layer from the side wall of the top end of a polycrystalline silicon layer; forming a pre-metal dielectric layer, forming a second photoresist layer on the pre-metal dielectric layer, opening the second photoresist layer through photoetching to define a formation position of a contact hole, and forming the contact hole which is positioned in the cellular region and between the two side wall structures by utilizing high-selection-ratio etching of the pre-metal dielectric layer relative to the outer-layer protection layer, the contact hole extends into the epitaxial layer from the upper surface of the metal front dielectric layer, and removing the second photoresist layer to form a metal layer for filling the contact hole. According to the method, under the small-period deep-groove MOSFET process, the situation that the contact hole is short-circuited to a polycrystalline silicon layer to cause device failure due to the photoetching key size or overlay fluctuation of the contact hole or parameter fluctuation of the device is caused due to the fact that the contact hole is injected to be close to an MOS channel is avoided, and the gate source capacitance can be reduced.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a U-shaped trench gate with an inner sidewall structure. Background Art

[0002] Usually, trench MOSFET with trench contact hole is a non-self-aligned process, and the distance between the trench contact hole and the trench gate is controlled by the layout design and the precision of the photolithography process. In the process of constantly pursuing size reduction and reducing on-resistance, when the pitch (period) is less than 0.6um, forming a contact hole with good morphology brings great challenges to the photolithography and etching process.

[0003] In order to solve the above problems, it is necessary to propose a novel method for manufacturing a U-shaped trench gate with an inner sidewall structure. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for manufacturing a U-shaped trench gate with an inner sidewall structure, which is used to solve the problem in the prior art that as the size decreases, forming a contact hole with good morphology poses a huge challenge to the lithography and etching processes.

[0005] To achieve the above-mentioned object and other related objects, the present invention provides a method for manufacturing a U-shaped trench gate with an inner sidewall structure, comprising:

[0006] Step 1, providing a substrate, forming an epitaxial layer on the substrate, forming a hard mask layer on the epitaxial layer, forming a first photoresist layer on the hard mask layer, and photolithographically opening the first photoresist layer so that a portion of the hard mask layer is exposed to define the formation positions of the gate trenches on the cell region and the substrate lead-out region;

[0007] Step 2, etching the exposed hard mask layer until the epitaxial layer is exposed to form an opening pattern, removing the remaining first photoresist layer, and continuing to etch the exposed epitaxial layer to form a deep trench;

[0008] Step 3, forming a gate dielectric layer in the deep trench and a polysilicon layer filling the remaining deep trench;

[0009] Step 4: removing the hard mask layer, the top of the polysilicon layer is convex relative to the epitaxial layer, and ion implantation is used to form a body region and a source region on the cell region;

[0010] Step 5: forming a thermal oxide layer on the epitaxial layer and the protruding polysilicon layer by a thermal oxidation method, depositing an outer protective layer, and etching back the thermal oxide layer and the outer protective layer to form a sidewall structure located at each protruding polysilicon sidewall, wherein the sidewall structure extends from the top sidewall of the polysilicon layer to the epitaxial layer;

[0011] Step six, forming a pre-metal dielectric layer, forming a second photoresist layer on the pre-metal dielectric layer, photolithographically opening the second photoresist layer to define a formation position of a contact hole, utilizing high selectivity etching of the pre-metal dielectric layer relative to the outer protective layer to form a contact hole located in the cell region and between the two sidewall structures, wherein the contact hole extends from the upper surface of the pre-metal dielectric layer to the epitaxial layer, removing the second photoresist layer, and forming a metal layer filling the contact hole.

[0012] Preferably, the material of the hard mask layer in step 1 is oxide.

[0013] Preferably, the etching method in step 2 is dry etching.

[0014] Preferably, the method of forming a gate dielectric layer in the deep trench and a polysilicon layer filling the remaining deep trench in step three includes: forming the gate dielectric layer in the deep trench by a thermal oxidation method; depositing the polysilicon layer, and grinding the polysilicon layer onto the hard mask layer.

[0015] Preferably, the sidewall structure in step five is in the shape of two approximate ellipses on both sides of the same deep trench when viewed from a cross-sectional perspective.

[0016] Preferably, the material of the outer protective layer in step five is Si3N4.

[0017] Preferably, step six further includes ion implantation into the contact hole before forming the metal layer filling the contact hole.

[0018] As described above, the method for manufacturing a U-shaped trench gate with an inner sidewall structure of the present invention has the following beneficial effects:

[0019] The present invention does not cause device failure due to short circuit of the contact hole to the polysilicon layer or device parameter fluctuation due to contact hole injection close to the MOS channel under the small-cycle deep trench MOSFET process due to fluctuation of the contact hole photolithography key size or overlay, and can reduce the gate-source capacitance. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Shown is a schematic diagram of the process flow of the present invention;

[0021] Figure 2 It is a schematic diagram showing the photolithography process of opening the first photoresist layer according to the present invention;

[0022] Figure 3 Shown is a schematic diagram of opening the hard mask layer of the present invention;

[0023] Figure 4It is a schematic diagram of forming a deep trench according to the present invention;

[0024] Figure 5 It is a schematic diagram showing the formation of a gate dielectric layer and a polysilicon layer according to the present invention;

[0025] Figure 6 Shown is a schematic diagram of removing the hard mask layer of the present invention;

[0026] Figure 7 Shown is a schematic diagram of forming a side wall structure of the present invention;

[0027] Figure 8 It is a schematic diagram of forming a self-aligned contact hole according to the present invention. DETAILED DESCRIPTION

[0028] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0029] See also Figure 1 The present invention provides a method for manufacturing a U-shaped trench gate with an inner sidewall structure, comprising:

[0030] Step 1: Provide a substrate 101, form an epitaxial layer 102 on the substrate 101, form a hard mask layer 103 on the epitaxial layer 102, form a first photoresist layer 104 on the hard mask layer 103, and open the first photoresist layer 104 by photolithography to expose a portion of the hard mask layer 103, so as to define the formation position of the gate trench on the cell region and the lead-out region of the substrate 101, so as to form a gate electrode 104. Figure 2 The structure shown;

[0031] In some embodiments, the material of the hard mask layer 103 in step 1 is oxide.

[0032] Step 2: Etch the exposed hard mask layer 103 until the epitaxial layer 102 is exposed to form an opening pattern, and remove the remaining first photoresist layer 104. Usually, the first photoresist layer 104 can be removed by ashing process and wet cleaning, so as to form a Figure 3 The structure shown in FIG. 1 is further etched to form a deep trench in the exposed epitaxial layer 102. Figure 4 The structure shown;

[0033] In some embodiments, the etching method in step 2 is dry etching.

[0034] Step 3: forming a gate dielectric layer 105 in the deep trench and a polysilicon layer 106 filling the remaining deep trench, forming a Figure 5 The structure shown;

[0035] In some embodiments, the method of forming a gate dielectric layer 105 in the deep trench and a polysilicon layer 106 filling the remaining deep trench in step three includes: forming a gate dielectric layer 105 on the epitaxial layer 102 in the deep trench by a thermal oxidation method; depositing a polysilicon layer 106, and grinding the polysilicon layer 106 onto the hard mask layer 103, and the grinding method is generally chemical mechanical planarization grinding.

[0036] Step 4: Remove the hard mask layer 103. The top of the polysilicon layer 106 is convex relative to the epitaxial layer 102. Ion implantation is used to form a body region 107 and a source region 108 on the cell region. Figure 6 The structure shown;

[0037] Step 5: Form a thermal oxide layer 1091 on the epitaxial layer 102 and the protruding polysilicon layer 106 by thermal oxidation, deposit an outer protective layer 1092, and etch back the thermal oxide layer 1091 and the outer protective layer 1092. The etching back method can be dry etching or wet etching to form a sidewall structure 109 located at each protruding polysilicon sidewall. The sidewall structure 109 extends from the top sidewall of the polysilicon layer 106 to the epitaxial layer 102, forming a sidewall structure 109 as shown in FIG. Figure 7 The structure shown;

[0038] In some embodiments, the sidewall structure 109 in step five is in the shape of two approximate ellipses on both sides of the same deep trench when viewed from a cross-sectional perspective.

[0039] In some embodiments, the material of the outer protective layer 1092 in step five is Si3N4.

[0040] Step 6: Form a pre-metal dielectric layer 110, form a second photoresist layer on the pre-metal dielectric layer 110, open the second photoresist layer by photolithography to define the formation position of the contact hole, and use the high selectivity of the pre-metal dielectric layer 110 relative to the outer protective layer 1092 to form a contact hole located in the cell area and between the two side wall structures 109, the contact hole extends from the upper surface of the pre-metal dielectric layer 110 to the epitaxial layer 102, remove the second photoresist layer, and form a metal layer 111 filling the contact hole, so as to form a Figure 8The structure shown. For example, the material of the metal pre-dielectric is oxide, and the material of the outer protective layer 1092 in the sidewall structure 109 is Si3N4. By utilizing the high selectivity of oxide relative to Si3N4, a contact hole of a self-aligned groove can be formed. Under the process of small pitch (period) deep trench MOSFET, the contact hole will not be short-circuited to the polysilicon layer 106 due to the fluctuation of the contact hole photolithography CD (critical dimension) or Overlay (overlay), causing device failure, or the contact hole injection close to the MOS channel will cause device parameter fluctuation, and the gate-source capacitance Cgs can be reduced.

[0041] In some embodiments, before forming the metal layer 111 filling the contact hole in step six, ion implantation into the contact hole is also included.

[0042] In some embodiments, the metal layer 111 filling the contact hole may include tungsten, silicide, nickel, cobalt, copper, other suitable conductive materials or combinations thereof. In some examples, the contact hole may further include a barrier layer such as tantalum and tantalum nitride, titanium and titanium nitride.

[0043] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0044] In summary, the present invention does not cause device failure due to contact hole short-circuiting to the polysilicon layer or device parameter fluctuation caused by contact hole injection close to the MOS channel under the process of small-period deep trench MOSFET. It can also reduce gate-source capacitance. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0045] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a U-shaped trench gate with an inner sidewall structure, characterized in that: At least: Step 1, providing a substrate, forming an epitaxial layer on the substrate, forming a hard mask layer on the epitaxial layer, forming a first photoresist layer on the hard mask layer, and photolithographically opening the first photoresist layer so that a portion of the hard mask layer is exposed to define the formation positions of the gate trenches on the cell region and the substrate lead-out region; Step 2, etching the exposed hard mask layer until the epitaxial layer is exposed to form an opening pattern, removing the remaining first photoresist layer, and continuing to etch the exposed epitaxial layer to form a deep trench; Step 3, forming a gate dielectric layer in the deep trench and a polysilicon layer filling the remaining deep trench; Step 4: removing the hard mask layer, the top of the polysilicon layer is convex relative to the epitaxial layer, and ion implantation is used to form a body region and a source region on the cell region; Step 5: forming a thermal oxide layer on the epitaxial layer and the protruding polysilicon layer by a thermal oxidation method, depositing an outer protective layer, and etching back the thermal oxide layer and the outer protective layer to form a sidewall structure located at each protruding polysilicon sidewall, wherein the sidewall structure extends from the top sidewall of the polysilicon layer to the epitaxial layer; Step six, forming a pre-metal dielectric layer, forming a second photoresist layer on the pre-metal dielectric layer, photolithographically opening the second photoresist layer to define a formation position of a contact hole, utilizing high selectivity etching of the pre-metal dielectric layer relative to the outer protective layer to form a contact hole located in the cell region and between the two sidewall structures, wherein the contact hole extends from the upper surface of the pre-metal dielectric layer to the epitaxial layer, removing the second photoresist layer, and forming a metal layer filling the contact hole.

2. The method for manufacturing a U-shaped trench gate with an inner sidewall structure according to claim 1, characterized in that: The material of the hard mask layer in step 1 is oxide.

3. The method for manufacturing a U-shaped trench gate with an inner sidewall structure according to claim 1, characterized in that: The etching method in step 2 is dry etching.

4. The method for manufacturing a U-shaped trench gate with an inner sidewall structure according to claim 1, characterized in that: The method of forming a gate dielectric layer in the deep trench and a polysilicon layer filling the remaining deep trench in step three includes: forming the gate dielectric layer in the deep trench by a thermal oxidation method; depositing the polysilicon layer, and grinding the polysilicon layer onto the hard mask layer.

5. The method for manufacturing a U-shaped trench gate with an inner sidewall structure according to claim 1, characterized in that: The sidewall structure in step five is observed from a cross-sectional perspective to be in the shape of two approximate ellipses on both sides of the same deep trench.

6. The method for manufacturing a U-shaped trench gate with an inner sidewall structure according to claim 1, characterized in that: The material of the outer protective layer in step five is Si3N4.

7. The method for manufacturing a U-shaped trench gate with an inner sidewall structure according to claim 1, characterized in that: In step six, before forming the metal layer filling the contact hole, ion implantation into the contact hole is also included.

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