Preparation method for reducing parasitic capacitance of high-voltage SOI BCD process

Abstract

The invention discloses a preparation method for reducing parasitic capacitance of a high-voltage SOI (Silicon On Insulator) BCD (Bipolar Compact Disc) process. The preparation method comprises the following steps: manufacturing a Trench isolation groove and filling the groove with a SiO2 medium; a Trench connecting groove is manufactured, and the groove is filled with polycrystalline silicon; respectively carrying out P well photoetching, injection and well pushing in the high-pressure tube region and the low-pressure tube region; manufacturing an LDD N-drift region in the high-voltage tube region; photoetching and corroding the field plate to complete the high-voltage tube polycrystal field plate modulation electric field; growing a gate oxide SiO2 medium, and depositing and corroding a gate polycrystalline control region; performing N + and P + photoetching, injection and annealing activation on the high-voltage tube and the low-voltage tube; growing a SiO2 dielectric layer for full coverage, carrying out photoetching and dry etching on a contact hole, carrying out body region P + injection, and forming tungsten in the contact hole; and completing metal deposition, photoetching and corrosion, and performing chemical deposition, photoetching and corrosion of a layer of passivation medium to protect the device. According to the invention, an electric leakage path after the total dose test can be cut off, and the total dose reinforcing function of the shield grid VDMOS is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a preparation method for reducing parasitic capacitance of a high-voltage SOI BCD process. Background Art

[0002] SOI (Silicon on Insulator) refers to a manufacturing method of forming a semiconductor device in a semiconductor thin film material (device layer) above an insulator (buried oxygen insulating layer), and the semiconductor thin film material below the buried oxygen insulating layer is called a substrate layer.

[0003] Compared with the bulk silicon (no intermediate buried oxygen insulating layer) process, devices manufactured by SOI process have certain advantages: steeper subvalue slope, higher transconductance and current driving capability, reduced sensitive volume of single-particle transient and single-particle flip effects, stronger radiation resistance, no latch effect, etc. However, in the high-voltage SOI process manufacturing process platform, it is found that the device layer brings parasitic resistance and capacitance to the low-voltage tube while meeting the withstand voltage of the high-voltage tube. This is because the device layer thickness required for the high-voltage tube is much larger than that of the low-voltage tube, which makes the low-voltage tube, especially the use of low-voltage NMOS tubes, introduce unnecessary parasitic resistance and capacitance in the device layer, and the original advantage of low parasitic capacitance of the SOI process cannot be reflected.

[0004] Therefore, how to reduce the parasitic capacitance of the high-voltage SOI process through a convenient manufacturing process is a technical problem that needs to be solved urgently. Summary of the invention

[0005] The object of the present invention is to provide a method for reducing parasitic capacitance of a high-voltage SOI BCD process, so as to solve the problems in the background technology.

[0006] In order to solve the above technical problems, the present invention provides a method for reducing parasitic capacitance of a high-voltage SOI BCD process, comprising:

[0007] A trench isolation groove is made on the device layer, SiO2 medium is grown and deposited in the trench isolation groove, and the trench groove is filled to meet the pressure resistance requirements between different tubes;

[0008] Perform photolithography and etching of the Trench connection groove, open the buried oxide insulation layer of the low-voltage NMOS tube area, connect the device layer and the substrate layer, and achieve zero voltage difference between the upper and lower layers.

[0009] Growing and depositing polysilicon in the trench connection groove, completing the filling of the trench connection groove, and realizing the polycrystalline interconnection between the upper and lower layers;

[0010] P-well photolithography, implantation, and well pushing are performed in the high-voltage tube area and low-voltage tube area of ​​the device to form a high-voltage tube P-well and a low-voltage tube P-well, respectively, to achieve NMOS tube voltage resistance and isolation;

[0011] In the high-voltage tube area, the LDD N-drift region is fabricated, and the photolithography, implantation and annealing of the LDD N-drift region are completed; the field plate is photolithographically etched, and the electric field modulation of the high-voltage tube polycrystalline field plate is completed;

[0012] Grow gate oxide SiO2 dielectric, and deposit and etch gate polycrystalline control area to serve as gate control terminal of high and low voltage tubes;

[0013] Perform N+ and P+ photolithography, implantation and annealing activation on both high and low voltage tubes to form source, drain and body regions;

[0014] Grow SiO2 dielectric layer for full coverage, perform photolithography and dry etching of contact holes, and perform P+ implantation in body region to form tungsten in contact holes, and lead out gate polycrystalline control terminal, source body contact terminal and source polycrystalline control terminal respectively;

[0015] After metal deposition, photolithography and corrosion are completed, a layer of passivation medium is chemically deposited, photolithographically and corroded to protect the device based on the above functional design and production.

[0016] In one embodiment, the trench isolation groove is formed into a desired morphology by photolithography and etching, the depth of the trench isolation groove is 3 μm to 50 μm, the width is 2 μm to 5 μm, and the inclination angle and bottom morphology of the trench isolation groove are well controlled.

[0017] In one implementation, the thickness of the SiO2 medium in the trench isolation groove is 1.5 μm to 3.5 μm, which can completely fill the trench isolation groove and achieve full coverage.

[0018] In one embodiment, the width of the trench connection groove is 1 μm to 3 μm, and the depth of the trench connection groove depends on the depth of the buried oxygen insulating layer and is deeper than the buried oxygen insulating layer by more than 1 μm.

[0019] In one embodiment, the high-voltage tube P well and the low-voltage tube P well are formed, the impurities injected into the P well are P-type impurities including B, BF2, and BF3, the injection energy of the P well is 50keV~100keV, the injection dose is 5E13~5E14, and a voltage-resistant and isolation area is formed.

[0020] In one embodiment, the production of the LDD N-drift region in the high-voltage tube region includes: first performing photolithography, implantation and annealing of the drift region LDD N-, implanting N- impurities As or P, the LDD implantation energy is 50keV~100keV, the implantation dose is 1E13~1E14, and forming a voltage-resistant and connection area.

[0021] In one embodiment, the polycrystalline field plate manufacturing includes: field oxide SiO2 dielectric deposition, photolithography, and etching to form a desired morphology, and the thickness of the field oxide SiO2 dielectric is 350nm to 1500nm.

[0022] In one embodiment, the gate oxide SiO2 dielectric has a thickness of 30 nm to 80 nm, and the gate polycrystalline has a thickness of 0.5 μm to 1.0 μm, forming a device gate control terminal.

[0023] In one embodiment, the high and low voltage tubes are both subjected to N+ and P+ photolithography, implantation and annealing activation, wherein the N+ implantation is performed, the N-type impurities implanted are As or P, the N-type impurity implantation energy is 40keV to 80keV, and the implantation dose is 1E15-1E16; the P+ implantation is performed, the P-type impurities implanted are B or BF2 or BF3, the P-type impurity implantation energy is 20keV to 60keV, and the implantation dose is 1E15-5E15.

[0024] In one embodiment, the SiO2 dielectric layer is grown by chemical deposition, and the thickness of the SiO2 dielectric layer is 0.6 μm to 0.8 μm; the size of the contact hole is 150 nm to 300 nm.

[0025] In one embodiment, the metal has a thickness of 0.7 μm to 1.5 μm, is connected to the contact hole, and is used for chip functional connection and subsequent bonding; the passivation medium is SiO2, or SiO2+Si3N4, with a thickness of 0.5 μm to 1.0 μm, and is used for device isolation and protection.

[0026] The present invention provides a method for reducing parasitic capacitance of a high-voltage SOI BCD process, which has the following characteristics:

[0027] Beneficial effects:

[0028] (1) Innovatively proposed connecting the low-voltage NMOS tube device layer with the substrate layer to ensure that the high-voltage and low-voltage tubes are not damaged, giving the low-voltage NMOS tube the same upper and lower potentials, eliminating the parasitic resistance and capacitance of the low-voltage NMOS tube, and reducing the parasitic capacitance of the high-voltage SOI process;

[0029] (2) Adopting common semiconductor device manufacturing technology and process methods; the manufacturing method is simple and has strong operability. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a schematic flow chart of a method for reducing parasitic capacitance of a high-voltage SOI BCD process provided by the present invention;

[0031] Figure 2 It is a schematic diagram of making high and low voltage tube trench isolation grooves on the device layer;

[0032] Figure 3 It is a schematic diagram of growing and depositing SiO2 medium in the trench isolation groove;

[0033] Figure 4 It is a schematic diagram of the photolithography and etching process for making trench connection grooves;

[0034] Figure 5 It is a schematic diagram of the polycrystalline deposition in the trench connection groove;

[0035] Figure 6 It is a schematic diagram of making high and low pressure tube P trap;

[0036] Figure 7 This is a schematic diagram of making the N-drift region of the high-voltage tube LDD;

[0037] Figure 8 It is a schematic diagram of making a polycrystalline field plate for a high-voltage tube;

[0038] Fig. 9 It is a schematic diagram of the deposition and etching of gate oxide SiO2 dielectric and gate polycrystalline control area;

[0039] Fig.10 It is a schematic diagram of making N+ and P+ photolithography and implantation;

[0040] Fig.11 It is a schematic diagram of making contact holes and completing tungsten plugs;

[0041] Fig.12 It is a schematic diagram of making metal AlSiCu and passivation layer SiO2 medium. DETAILED DESCRIPTION

[0042] The following is a further detailed description of a method for reducing parasitic capacitance of a high-voltage SOI BCD process proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0043] The present invention provides a method for reducing parasitic capacitance of a high-voltage SOI BCD process, the process of which is as follows: Figure 1 As shown, the following steps are included:

[0044] Step S11, making high and low pressure pipe trench isolation grooves;

[0045] Step S12, making a trench connection groove of a low voltage NMOS tube area;

[0046] Step S13, making the high and low voltage tube P wells and the high voltage tube LDD N-voltage-resistant drift region;

[0047] Step S14, making a high-voltage tube polycrystalline field plate;

[0048] Step S15, making gate oxide and gate polycrystalline;

[0049] Step S16, making N+, P+ and contact holes;

[0050] Step S17: making metal and passivation layers.

[0051] The specific process steps are as follows:

[0052] First, a photomask 4 (PHOTO) is formed on the surface of the device layer 3 (N-EPI) of the Si substrate 1 (N+SUB), and a trench isolation groove 5 is made at the exposed part of the photomask 4 to isolate the high-voltage tube from the low-voltage tube in the high-voltage area, and the low-voltage tubes from each other to withstand the pressure; the trench isolation groove 5 is photoetched to form an isolation ring isolated from the buried oxide insulation layer; the depth of the trench isolation groove 5 is 3μm to 50μm, and it ends at the upper surface of the buried oxide insulation layer 2 at most, and the width is 2μm to 5μm, and the inclination angle and bottom morphology of the trench isolation groove 5 are controlled, such as Figure 2 Shown is a cross-sectional schematic diagram after completing this step;

[0053] Remove the photomask 4 (PHOTO), and deposit SiO2 medium 6 in the trench isolation groove 5, as shown in FIG. Figure 3 As shown. Since the production of high-voltage tubes will inevitably cause additional resistance and capacitance in the low-voltage tube area, in order to reduce the parasitic resistance and capacitance in the low-voltage NMOS tube area, a Trench connection groove 7 is produced. Through the Trench connection groove 7, the upper and lower resistors in the low-voltage tube are connected through the rear polycrystalline, and at the same time, there is no voltage difference between the device layer and the substrate layer, eliminating the parasitic capacitance caused by the buried oxide insulation layer 2. The width of the Trench connection groove 7 is 1μm to 3μm, and the depth of the Trench connection groove 7 depends on the depth of the buried oxygen insulation layer 2, and is more than 1μm deeper than the buried oxygen insulation layer 2, that is, the Trench connection groove 7 penetrates the buried oxygen insulation layer 2 and contacts the Si substrate 1, as shown Figure 4 Shown is a cross-sectional schematic diagram after completing this step;

[0054] Polycrystalline 8 is deposited in the trench connection groove 7, and the deposition thickness is 0.75 μm to 2 μm. Figure 5Shown is a cross-sectional schematic diagram after completing this step;

[0055] The high-pressure tube P well 9 and the low-pressure tube P well 10 are manufactured. The impurities injected into the high-pressure tube P well 9 and the low-pressure tube P well 10 are P-type impurities such as B / BF2 / BF3. The injection energy of the high-pressure tube P well 9 and the low-pressure tube P well 10 is 50keV~100keV, and the injection dose is 5E13~5E14, so as to form a withstand voltage and isolation area. Figure 6 Shown is a cross-sectional schematic diagram after completing this step;

[0056] The production of the high-voltage tube LDD N-drift region 11 first involves photolithography, implantation and annealing of the high-voltage tube LDD N-drift region 11, and the N-impurities are implanted with N-type impurities such as As or P. The LDD implantation energy is 50keV to 100keV, and the implantation dose is 1E13 to 1E14, forming a withstand voltage and connection region, such as Figure 7 Shown is a cross-sectional schematic diagram after completing this step;

[0057] The polycrystalline field plate is manufactured, and the field oxide SiO2 dielectric 12 is deposited, photolithographically and etched to form the desired morphology. The thickness of the field oxide SiO2 dielectric 12 is 350nm to 1500nm. Figure 8 Shown is a cross-sectional schematic diagram after completing this step;

[0058] A gate oxide SiO2 dielectric 13 is formed on the surface, the thickness of the gate oxide SiO2 dielectric 13 is 30nm to 80nm, and a gate polycrystalline 14 control region is deposited, photolithographically and etched on the surface of the gate oxide SiO2 dielectric 13, the thickness of the gate polycrystalline 14 is 0.5μm to 1.0μm, forming a device gate control terminal, such as Fig. 9 Shown is a cross-sectional schematic diagram after completing this step;

[0059] N+15 and P+16 photolithography and implantation are performed. For N+15 implantation, the N-type impurities injected are mostly As or P, the N-type impurity implantation energy is 40keV~80keV, and the implantation dose is 1E15-1E16; for P+16 implantation, the P-type impurities are B or BF2 or BF3, the P-type impurity implantation energy is 20keV~60keV, and the implantation dose is 1E15-5E15. Fig.10 Shown is a cross-sectional schematic diagram after completing this step;

[0060] A SiO2 dielectric layer is grown by chemical deposition as a full coverage of the isolation layer. The thickness of the SiO2 dielectric layer 17 is 0.6μm to 0.8μm. The contact hole 18 is photolithographically and dry-etched. The design size of the contact hole 18 is 150nm to 300nm. Tungsten is formed in the contact hole 18 by chemical vapor deposition. The gate, drain, source, and body regions of the high and low voltage tubes are respectively led out from the contact hole 18 to realize the connection function, such as Fig.11 Shown is a cross-sectional schematic diagram after completing this step;

[0061] After metal deposition, photolithography and etching are completed, the thickness of metal 19 is 0.7μm~1.5μm, which is connected to contact hole 19 for chip functional connection and subsequent bonding; then a layer of passivation medium is chemically deposited, photolithographically and etched, and the passivation medium 20 is SiO2, or SiO2+Si3N4, with a thickness of 0.5μm~1.0μm, to complete device isolation and protection, such as Fig.12 The figure shows a cross-sectional view after completing this step.

[0062] Through the above main design methods, a method for reducing the parasitic capacitance of the high-voltage SOI BCD process is formed. The present invention connects the device layer 3 and the substrate layer 1 through polycrystalline 8 to achieve zero upper and lower potential difference. On the one hand, it shields the inherent series resistance in the thick device layer 3, and on the other hand, it eliminates the parasitic capacitance of the buried oxygen insulating layer 2, thereby improving the operating frequency and dv / dt capability of the circuit using the high-voltage SOI process. The present invention can achieve the device with total dose reinforcement capability without adding any new process steps.

[0063] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for reducing parasitic capacitance of a high voltage SOIBCD process, characterized in that: include: A trench isolation groove is made on the device layer, SiO2 medium is grown and deposited in the trench isolation groove, and the trench groove is filled to meet the pressure resistance requirements between different tubes; Perform photolithography and etching of the Trench connection groove, open the buried oxide insulation layer of the low-voltage NMOS tube area, connect the device layer and the substrate layer, and achieve zero voltage difference between the upper and lower layers. Growing and depositing polysilicon in the trench connection groove, completing the filling of the trench connection groove, and realizing the polycrystalline interconnection between the upper and lower layers; P-well photolithography, implantation, and well pushing are performed in the high-voltage tube area and low-voltage tube area of ​​the device to form a high-voltage tube P-well and a low-voltage tube P-well, respectively, to achieve NMOS tube voltage resistance and isolation; In the high-voltage tube area, the LDD N-drift region is fabricated, and the photolithography, implantation and annealing of the LDD N-drift region are completed; the field plate is photolithographically etched, and the electric field modulation of the high-voltage tube polycrystalline field plate is completed; Grow gate oxide SiO2 dielectric, and deposit and etch gate polycrystalline control area to serve as gate control terminal of high and low voltage tubes; Perform N+ and P+ photolithography, implantation and annealing activation on both high and low voltage tubes to form source, drain and body regions; Grow SiO2 dielectric layer for full coverage, perform photolithography and dry etching of contact holes, and perform P+ implantation in body region to form tungsten in contact holes, and lead out gate polycrystalline control terminal, source body contact terminal and source polycrystalline control terminal respectively; After metal deposition, photolithography and corrosion are completed, a layer of passivation medium is chemically deposited, photolithographically and corroded to protect the device based on the above functional design and production.

2. The method for reducing parasitic capacitance of high voltage SOIBCD process according to claim 1, characterized in that: The trench isolation groove is formed into the required morphology by photolithography and etching. The depth of the trench isolation groove is 3μm-50μm and the width is 2μm-5μm. The inclination angle and bottom morphology of the trench isolation groove are well controlled.

3. The method for reducing parasitic capacitance of high voltage SOIBCD process as claimed in claim 1, characterized in that: The thickness of the SiO2 medium in the trench isolation groove is 1.5 μm to 3.5 μm, which can completely fill the trench isolation groove and achieve full coverage.

4. The method for reducing parasitic capacitance of high voltage SOIBCD process according to claim 1, characterized in that: The width of the trench connection groove is 1 μm to 3 μm, and the depth of the trench connection groove depends on the depth of the buried oxygen insulating layer and is deeper than the buried oxygen insulating layer by more than 1 μm.

5. The method for reducing parasitic capacitance of high voltage SOIBCD process as claimed in claim 1, characterized in that: The high-voltage tube P well and the low-voltage tube P well are formed, the impurities injected into the P well are P-type impurities including B, BF2, and BF3, the injection energy of the P well is 50keV-100keV, the injection dose is 5E13-5E14, and the withstand voltage and isolation area are formed.

6. The method for reducing parasitic capacitance of high voltage SOIBCD process as claimed in claim 7, characterized in that: The manufacturing of the LDD N-drift region in the high-voltage tube region includes: firstly performing photolithography, implantation and annealing of the drift region LDD N-, implanting As or P into the N- impurity, the LDD implantation energy is 50keV-100keV, the implantation dose is 1E13-1E14, and forming a withstand voltage and connection region.

7. The method for reducing parasitic capacitance of high voltage SOIBCD process according to claim 1, characterized in that: The polycrystalline field plate manufacturing includes: field oxide SiO2 medium deposition, photolithography, and etching to form a desired morphology, and the thickness of the field oxide SiO2 medium is 350nm-1500nm.

8. The method for reducing parasitic capacitance of high voltage SOIBCD process according to claim 1, characterized in that: The thickness of the gate oxide SiO2 medium is 30nm-80nm, and the thickness of the gate polycrystalline is 0.5μm-1.0μm, forming the gate control terminal of the device.

9. The method for reducing parasitic capacitance of high voltage SOIBCD process as claimed in claim 1, characterized in that: The high and low voltage tubes are both subjected to N+ and P+ photolithography, implantation and annealing activation, wherein the N+ implantation, the injected N-type impurities are As or P, the N-type impurity implantation energy is 40keV to 80keV, and the implantation dose is 1E15-1E16; the P+ implantation, the injected P-type impurities are B or BF2 or BF3, the P-type impurity implantation energy is 20keV to 60keV, and the implantation dose is 1E15-5E15.

10. The method for reducing parasitic capacitance of high voltage SOIBCD process according to claim 1, characterized in that: The SiO2 dielectric layer is grown by chemical deposition, and the thickness of the SiO2 dielectric layer is 0.6 μm to 0.8 μm; the size of the contact hole is 150 nm to 300 nm.

11. The method for reducing parasitic capacitance of high voltage SOIBCD process according to claim 1, characterized in that: The metal has a thickness of 0.7 μm to 1.5 μm, is connected to the contact hole, and is used for chip functional connection and subsequent bonding; the passivation medium is SiO2, or SiO2+Si3N4, has a thickness of 0.5 μm to 1.0 μm, and is used for device isolation and protection.

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