Semiconductor device

Abstract

A semiconductor device includes: a plurality of lower channel patterns spaced apart from each other; a plurality of upper channel patterns spaced apart from each other on the plurality of lower channel patterns; a gate structure surrounding the plurality of lower channel patterns and the plurality of upper channel patterns; a lower source / drain trench located on at least one side of the plurality of lower channel patterns; an upper source / drain trench located on at least one side of the plurality of upper channel patterns; a lower source / drain pattern within the lower source / drain trench; and an upper source / drain pattern including first upper source / drain layers on opposite sidewalls of the upper source / drain trench and a second upper source / drain layer between the first upper source / drain layers, where the first upper source / drain layers do not cover at least a portion of a bottom surface of the upper source / drain trench.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices. Background Art

[0002] Semiconductors are materials that belong to the middle region between conductors and nonconductors, and refer to materials that conduct electricity under certain conditions. Various semiconductor devices can be manufactured by using these semiconductor materials, for example, memory devices and the like can be manufactured. Such semiconductor devices can be used in various electronic devices.

[0003] With the gradual development of the electronics industry, the requirements for the characteristics of semiconductor devices are gradually increasing. For example, the demand for high reliability, high speed and / or multifunctionality of semiconductor devices is gradually increasing. In order to meet these required characteristics, the structure within the semiconductor device is becoming more and more complex and integrated. Summary of the invention

[0004] The present disclosure seeks to provide a semiconductor device with improved reliability.

[0005] An implementation of the present disclosure provides a semiconductor device, which includes: a plurality of lower channel patterns spaced apart from each other; a plurality of upper channel patterns spaced apart from each other on the plurality of lower channel patterns; a gate structure surrounding the plurality of lower channel patterns and the plurality of upper channel patterns; a lower source / drain groove located on one side of the plurality of lower channel patterns; an upper source / drain groove located on one side of the plurality of upper channel patterns; a lower source / drain pattern located within the lower source / drain groove; and an upper source / drain pattern including a first upper source / drain layer located at opposite side walls of the upper source / drain groove and a second upper source / drain layer located between the first upper source / drain layers, wherein the first upper source / drain layer exposes at least a portion of a bottom surface of the upper source / drain groove.

[0006] Another implementation of the present disclosure provides a semiconductor device, which includes: a plurality of upper channel patterns spaced apart from each other; a gate structure surrounding the plurality of upper channel patterns; an upper source / drain groove located on one side of the plurality of upper channel patterns; and an upper source / drain pattern, including a first upper source / drain layer protruding from opposite side walls of the upper source / drain groove and a second upper source / drain layer located between the first upper source / drain layers, wherein the width of the first upper source / drain layer gradually increases from the upper and lower portions of the upper source / drain groove toward the center portion.

[0007] Another implementation of the present disclosure provides a semiconductor device, which includes: a substrate; an active pattern located on the substrate; a plurality of lower channel patterns spaced apart from each other on the active pattern; a plurality of upper channel patterns spaced apart from each other on the plurality of lower channel patterns; a gate structure surrounding the plurality of lower channel patterns and the plurality of upper channel patterns; a lower source / drain pattern located on one side of the plurality of lower channel patterns; an upper source / drain pattern located on one side of the plurality of upper channel patterns and including a first upper source / drain layer and a second upper source / drain layer; and a blocking structure located between the lower source / drain pattern and the upper source / drain pattern, wherein the first upper source / drain layer is located on opposite sides of the second upper source / drain layer, and the width of the first upper source / drain layer along one direction gradually increases from the upper and lower portions of the upper source / drain groove toward the central portion of the upper source / drain groove.

[0008] According to the implementation, the reliability of the semiconductor device can be ensured. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a top plan view of an example semiconductor device.

[0010] Figure 2 It is along Figure 1 A cross-sectional view taken along line I-I'.

[0011] Figure 3 It is along Figure 1 A cross-sectional view taken along line II-II'.

[0012] Figure 4 It is along Figure 1 A cross-sectional view taken along line III-III'.

[0013] Figure 5 yes Figure 2 A cross-sectional view of the enlarged area A1.

[0014] Figures 6 to 12 Is the semiconductor device corresponding to Figure 2 A cross-sectional view of area A1.

[0015] Fig.13 is the semiconductor device corresponding to the Figure 1 A cross-sectional view of the area taken along line III-III'.

[0016] Fig.14 and Fig.15 Is the semiconductor device corresponding to Figure 2 A cross-sectional view of area A1.

[0017] Fig.16 and Fig.17 is the semiconductor device corresponding to the Figure 1 A cross-sectional view of the area taken along line I-I'.

[0018] Fig.18 is the semiconductor device corresponding to the Figure 1 A cross-sectional view of the area taken along line I-I'.

[0019] Fig.19 is the semiconductor device corresponding to the Figure 1 A cross-sectional view of the area taken along line II-II'.

[0020] Fig. 20 is the semiconductor device corresponding to the Figure 1 A cross-sectional view of the area taken along line III-III'.

[0021] Figure 21 to Figure 53 is a cross-sectional view illustrating an example method of manufacturing a semiconductor device.

[0022] Specific implementation method

[0023] In the following detailed description, only certain implementations of the present disclosure are shown and described by way of illustration only. The present disclosure can be variously implemented and is not limited to the following implementations.

[0024] The drawings and description are to be regarded as illustrative in nature and not restrictive.Throughout the specification, like reference numerals refer to like elements.

[0025] In addition, for the sake of understanding and ease of description, the size and thickness of each configuration shown in the drawings are arbitrarily shown, but the present disclosure is not limited thereto. In the drawings, for the sake of clarity, the thickness of layers, films, panels, regions, etc. are exaggerated. In the drawings, for the sake of understanding and ease of description, the thickness of some layers and regions are exaggerated.

[0026] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Conversely, when an element is referred to as being "directly on" another element, there are no intervening elements. Furthermore, it will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present.

[0027] In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprising” or “including”, will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0028] Furthermore, throughout the specification, when referred to as “in a plan view”, it means when the target component is viewed from above, and when referred to as “in a cross-sectional view”, it means when a cross section obtained by vertically cutting the target component is viewed from the side.

[0029] In the drawings of the semiconductor device, the semiconductor device may be formed into a gate all around (GAA) structure, a 3D stacked field effect transistor (3DSFET) structure, etc., in which all four sides of the channel are surrounded by gate electrodes. However, the present disclosure is not limited thereto, and the transistor may be a fin field effect transistor (FinFET) structure, a multi-bridge channel field effect transistor (MBCFET) structure, or a plurality of other structures. TM ) structure, complementary field effect transistor (CFET) structure, etc.

[0030] In the following, reference will be made to Figures 1 to 5 An example semiconductor device is described.

[0031] Figure 1 is a top plan view of an example semiconductor device. Figure 2 It is along Figure 1 A cross-sectional view taken along line I-I'. Figure 3 It is along Figure 1 A cross-sectional view taken along line II-II'. Figure 4 It is along Figure 1 A cross-sectional view taken along line III-III'. Figure 5 yes Figure 2 A cross-sectional view of the enlarged area A1.

[0032] First, refer to Figures 1 to 4 , an example semiconductor device may include a substrate 101, an active pattern 105 located on the substrate 101, a plurality of channel patterns 140 located on the active pattern 105, an intermediate dielectric isolation structure MDI located between the plurality of lower channel patterns 140A and the plurality of upper channel patterns 140B, a field insulation layer 110 located above the substrate 101, a gate structure 160 located on the active pattern 105, a source / drain pattern 300 located on at least one side of the gate structure 160, and a blocking structure 170 located between the lower source / drain pattern 300A and the upper source / drain pattern 300B.

[0033] The substrate 101 may be silicon on insulator (SOI) or bulk silicon. Alternatively, the substrate 101 may be a silicon substrate, or may include other materials such as silicon germanium (SiGe), silicon germanium on insulator (SGOI), indium antimonide, lead telluride compounds, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto. In another example, the substrate 101 may be an insulating substrate including an insulating material.

[0034] The substrate 101 may include a top surface and a bottom surface. The top surface and the bottom surface of the substrate 101 may include a plane parallel to a first direction (X direction) and a second direction (Y direction) intersecting the first direction (X direction). The top surface of the substrate 101 may be a surface opposite to the bottom surface of the substrate 101 in a third direction (Z direction). The top surface of the substrate 101 may be referred to as the front side. The bottom surface of the substrate 101 may be referred to as the back side. In some implementations, the logic circuit of the unit area may be implemented on the top surface of the substrate 101.

[0035] The active pattern 105 may be located on the substrate 101. The active pattern 105 may extend in a first direction (X direction). The active pattern 105 may have a structure protruding from the substrate 101. The top surface of the active pattern 105 may be positioned to protrude from the top surface of the field insulating layer 110, which will be described later but is not limited thereto. The active pattern 105 may also be formed by etching a portion of the substrate 101, or may include an epitaxial layer grown from the substrate 101. The active pattern 105 may include an elemental semiconductor material, such as silicon (Si) or germanium (Ge). The active pattern 105 may include impurities or may include a doped region containing impurities. As another example, an insulating pattern including an insulating material may be applied instead of the active pattern 105.

[0036] The example semiconductor device 100 according to the present disclosure may include at least one transistor structure. For example, the example semiconductor device 100 may include a first transistor structure and a second transistor structure, the first transistor structure including a plurality of lower channel patterns 140A, and the second transistor structure including a plurality of upper channel patterns 140B. The first transistor structure and the second transistor structure according to the implementation may be fabricated into a gate all around field effect transistor (GAAFET) structure, such as a multi-bridge channel field effect transistor (MBCFET). TM ), wherein the plurality of lower channel patterns 140A and the plurality of upper channel patterns 140B are surrounded by a gate structure 160.

[0037] In addition, the first transistor structure and the second transistor structure can be made into a three-dimensional stacked FET (3D-SFET) structure stacked in a third direction (Z direction). In this case, the first transistor structure can be any one of an N-type MOSFET and a P-type MOSFET, and the second transistor structure can be the other of a P-type MOSFET and an N-type MOSFET. In this implementation, the first transistor structure and the second transistor structure can be an N-type MOSFET and a P-type MOSFET, respectively, but are not limited to this. In the following, a case will be described in which a plurality of lower channel patterns 140A and a plurality of upper channel patterns 140B are stacked in a third direction (Z direction) to form a 3D-SFET structure. However, the present disclosure is not limited to this case.

[0038] The plurality of channel patterns 140 may be located on the active pattern 105. In this implementation, the plurality of channel patterns 140 may include a plurality of lower channel patterns 140A located on the active pattern 105 and a plurality of upper channel patterns 140B located on the plurality of lower channel patterns 140A.

[0039] The plurality of lower channel patterns 140A may be located on the top surface of the active pattern 105. The plurality of lower channel patterns 140A may be spaced apart from the active pattern 105 in a third direction (Z direction). The plurality of lower channel patterns 140A may be spaced apart from each other in a third direction (Z direction). Here, the third direction (Z direction) may be a direction intersecting the first direction (X direction) and the second direction (Y direction). For example, the third direction (Z direction) may be a thickness direction of the substrate 101.

[0040] In this implementation, if Figure 3 As shown, the widths of the plurality of lower channel patterns 140A along the second direction (Y direction) may decrease as they are away from the top surface of the substrate 101. Figure 2 As shown, the widths of the plurality of lower channel patterns 140A along the first direction (X direction) may decrease as they are away from the top surface of the substrate 101. However, the present disclosure is not limited thereto, and the widths of the plurality of lower channel patterns 140A along the second direction (Y direction) may be substantially the same. In addition, the widths of the plurality of lower channel patterns 140A along the first direction (X direction) may be substantially the same.

[0041] The plurality of upper channel patterns 140B may be located on the plurality of lower channel patterns 140A. Specifically, the plurality of upper channel patterns 140B may be located on the top surface of an intermediate dielectric isolation structure MDI, which is located on the plurality of lower channel patterns 140A. The plurality of upper channel patterns 140B may be spaced apart from the plurality of lower channel patterns 140A in a third direction (Z direction). For example, the intermediate dielectric isolation structure MDI may be located between the plurality of upper channel patterns 140B and the plurality of lower channel patterns 140A, and the plurality of upper channel patterns 140B may be spaced apart from the plurality of lower channel patterns 140A in the third direction (Z direction) by the intermediate dielectric isolation structure MDI. The plurality of upper channel patterns 140B may be spaced apart from each other in the third direction (Z direction).

[0042] In this implementation, if Figure 3As shown in FIG. 1 , the widths of the plurality of upper channel patterns 140B along the second direction (Y direction) may decrease as they are away from the top surface of the substrate 101. However, the widths of the plurality of upper channel patterns 140B along the second direction (Y direction) may be substantially the same, but are not limited thereto. Figure 2 As shown, the widths of the plurality of upper channel patterns 140B along the first direction (X direction) may be substantially the same, but are not limited thereto.

[0043] The plurality of lower channel patterns 140A and the plurality of upper channel patterns 140B may be multi-channel active patterns. In this implementation, the plurality of lower channel patterns 140A and the plurality of upper channel patterns 140B may have a nanosheet shape and may be semiconductor patterns including a semiconductor material.

[0044] The plurality of lower channel patterns 140A and the plurality of upper channel patterns 140B may be formed by etching a portion of the substrate 101, or may include an epitaxial layer grown from the substrate 101. The plurality of lower channel patterns 140A and the plurality of upper channel patterns 140B may include an elemental semiconductor material, such as silicon (Si) or germanium (Ge). In addition, the plurality of lower channel patterns 140A and the plurality of upper channel patterns 140B may include a compound semiconductor, such as a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0045] Each of the plurality of lower channel patterns 140A and the plurality of upper channel patterns 140B may include the same material as the active pattern 105 , or may include a different material from the active pattern 105 .

[0046] The Group IV-IV compound semiconductor may be, for example, a binary compound or a ternary compound including at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn).

[0047] The III-V compound semiconductor may be one of a binary compound, a ternary compound, and a quaternary compound formed, for example, by combining at least one of the III group elements of aluminum (Al), gallium (Ga), and indium (In) with one of the V group elements of phosphorus (P), arsenic (As), and antimony (Sb).

[0048] In this implementation, the active pattern 105 and the plurality of channel patterns 140 may include silicon (Si). In another example, the active pattern 105 and the plurality of channel patterns 140 may include silicon germanium (SiGe). In another example, the active pattern 105 may include silicon (Si), and the plurality of channel patterns 140 may include silicon germanium (SiGe).

[0049] exist Figure 2and Figure 3 , two lower channel patterns 140A and two upper channel patterns 140B are shown as being stacked spaced apart along a third direction (Z direction), but this is for illustrative purposes only. The number of channel patterns is not limited thereto. For example, three or more lower channel patterns 140A and / or three or more upper channel patterns 140B may be stacked and spaced apart along a third direction (Z direction). Alternatively, one lower channel pattern 140A and / or one upper channel pattern 140B may be stacked along a third direction (Z direction).

[0050] The intermediate dielectric isolation structure MDI may be located on the plurality of lower channel patterns 140A. The intermediate dielectric isolation structure MDI may be located between the topmost lower channel pattern 140A and the bottommost upper channel pattern 140B. In addition, the intermediate dielectric isolation structure MDI may be located between the topmost lower gate structure 160A and the bottommost upper gate structure 160B.

[0051] The intermediate dielectric isolation structure MDI may include an intermediate dielectric isolation pattern 210. The intermediate dielectric isolation pattern 210 may include various insulating materials. The intermediate dielectric isolation pattern 210 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The intermediate dielectric isolation structure MDI may space the plurality of lower channel patterns 140A and the plurality of upper channel patterns 140B apart from each other.

[0052] In this implementation, the intermediate dielectric isolation structure MDI is described as including a single intermediate dielectric isolation pattern 210, but the present disclosure is not limited thereto. The intermediate dielectric isolation structure MDI may also include a plurality of intermediate dielectric isolation patterns 210. Alternatively, the intermediate dielectric isolation structure MDI may include a plurality of intermediate dielectric isolation patterns 210 and a semiconductor pattern located between the plurality of intermediate dielectric isolation patterns 210. Even in this case, the plurality of upper channel patterns 140B and the plurality of lower channel patterns 140A may be spaced apart by the intermediate dielectric isolation structure MDI.

[0053] The field insulating layer 110 may be located on the substrate 101. The field insulating layer 110 may cover at least a portion of a side surface of the active pattern 105. Figure 3As shown, the field insulation layer 110 may cover a portion of the side of the active pattern 105. That is, a portion of the side wall of the active pattern 105 may be covered by the field insulation layer 110, and the remaining portion of the side wall of the active pattern 105 may be covered by the gate structure 160, which will be described later. The field insulation layer 110 may overlap with the active pattern 105 in the second direction (Y direction). In addition, the field insulation layer 110 may not be located on the top surface of the active pattern 105. In this implementation, the top surface of the field insulation layer 110 is shown to extend in a direction parallel to the top surface of the substrate 101, but the present disclosure is not limited thereto. For example, the field insulation layer 110 may have a curved top surface, and the curved top surface has a higher level as it approaches the active pattern 105.

[0054] exist Figure 3 , it is shown that the field insulation layer 110 covers at least a portion of the side of the active pattern 105, but the present disclosure is not limited thereto. For example, the field insulation layer 110 may completely cover the side of the active pattern 105. In this case, the side of the active pattern 105 may be completely covered by the field insulation layer 110.

[0055] The field insulating layer 110 may include a film of, for example, oxide, nitride, oxynitride, or a combination thereof. The field insulating layer 110 is illustrated as a single film, but is illustrated only for illustrative purposes and the present disclosure is not limited thereto.

[0056] The gate structure 160 may be located on the active pattern 105. The gate structure 160 may extend in the second direction (Y direction). The gate structures 160 may be spaced apart in the first direction (X direction). The gate structure 160 may be located on the active pattern 105. The gate structure 160 may intersect the active pattern 105. The gate structure 160 may surround each of the plurality of channel patterns 140.

[0057] In this implementation, the first transistor structure and the second transistor structure may be configured to share a single gate structure 160. Specifically, the first transistor structure may include a plurality of lower channel patterns 140A, a gate structure 160 surrounding the plurality of lower channel patterns 140A, and a lower source / drain pattern 300A connected to the plurality of lower channel patterns 140A at one side of the gate structure 160. In addition, the second transistor structure may include a plurality of upper channel patterns 140B, a gate structure 160 surrounding the plurality of upper channel patterns 140B, and an upper source / drain pattern 300B connected to the plurality of upper channel patterns 140B at one side of the gate structure 160. In this case, as Figure 3As shown, one gate structure 160 surrounds the plurality of lower channel patterns 140A and the plurality of upper channel patterns 140B together, so that the first transistor structure and the second transistor structure can be configured to share one gate structure 160 .

[0058] The gate structure 160 may include a lower gate structure 160A, an upper gate structure 160B, and a main gate structure 160M. The lower gate structure 160A may be located between the plurality of lower channel patterns 140A adjacent in the third direction (Z direction), between the active pattern 105 and the bottommost lower channel pattern 140A, and between the topmost lower channel pattern 140A and the intermediate dielectric isolation structure MDI. The upper gate structure 160B may be located between the plurality of upper channel patterns 140B adjacent in the third direction (Z direction), and between the bottommost upper channel pattern 140B and the intermediate dielectric isolation structure MDI. The main gate structure 160M may be located on the topmost upper channel pattern 140B.

[0059] The lower gate structure 160A may be adjacent to the lower source / drain pattern 300A, which will be described later. The upper gate structure 160B may be adjacent to the upper source / drain pattern 300B, which will be described later. The main gate structure 160M may be located on the lower gate structure 160A, the upper gate structure 160B, and the plurality of upper channel patterns 140B.

[0060] According to the implementation, each of the lower gate structure 160A and the upper gate structure 160B may include a plurality of layers, and the plurality of layers may be alternately stacked with the plurality of channel patterns 140. Figure 2 and Figure 3 As shown, the lower gate structure 160A may include three layers alternately stacked with the plurality of lower channel patterns 140A, and the upper gate structure 160B may include two layers alternately stacked with the plurality of upper channel patterns 140B. However, the present disclosure is not limited thereto, and the number of layers of the lower gate structure 160A and the upper gate structure 160B may vary.

[0061] Each of the lower gate structure 160A and the upper gate structure 160B may include a gate electrode 165A or 165B and a gate insulating film 162A or 162B.

[0062] The gate electrodes 165A and 165B may be located on the active pattern 105. For example, the lower gate electrode 165A may be located on the active pattern 105, and the upper gate electrode 165B may be located on the lower gate electrode 165A. The gate electrodes 165A and 165B may intersect the active pattern 105. The gate electrodes 165A and 165B may surround the plurality of channel patterns 140. For example, the lower gate electrode 165A may surround the plurality of lower channel patterns 140A, and the upper gate electrode 165B may surround the plurality of upper channel patterns 140B.

[0063] In addition, at least some of the gate electrodes 165A and 165B may be located between the plurality of channel patterns 140. For example, the lower gate electrode 165A may be located between the plurality of lower channel patterns 140A, and the upper gate electrode 165B may be located between the plurality of upper channel patterns 140B. Other portions of the gate electrodes 165A and 165B may be located to cover opposite sides of the stacked structure of the gate electrodes 165A and 165B and the plurality of channel patterns 140.

[0064] The gate electrodes 165A and 165B may include a conductive material. The gate electrodes 165A and 165B may include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride. The gate electrodes 165A and 165B may include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (Ta The conductive metal oxide and the conductive metal oxynitride may include oxidized forms of the above materials, but are not limited thereto. The gate electrodes 165A and 165B may include the same material, but are not limited thereto, and the gate electrodes 165A and 165B may also include different materials.

[0065] The gate insulating films 162A and 162B may be positioned along the peripheries of the plurality of channel patterns 140. For example, the lower gate insulating film 162A may be positioned along the peripheries of the plurality of lower channel patterns 140A, and the upper gate insulating film 162B may be positioned along the peripheries of the plurality of upper channel patterns 140B. In addition, the lower gate insulating film 162A may extend along the top surface of the active pattern 105.

[0066] The lower gate insulating film 162A may be in direct contact with the active pattern 105, the plurality of lower channel patterns 140A, and the intermediate dielectric isolation structure MDI. The upper gate insulating film 162B may be in direct contact with the plurality of upper channel patterns 140B and the intermediate dielectric isolation structure MDI. The gate insulating films 162A and 162B may be interposed between the plurality of channel patterns 140 and the gate electrodes 165A and 165B. The gate insulating films 162A and 162B may include various insulating materials.

[0067] In this implementation, the gate insulating films 162A and 162B are shown as a single film, but are not limited thereto. For example, the gate insulating films 162A and 162B may be a single film including silicon oxide (SiO 2 ) and a plurality of films of a high dielectric constant material. In this case, the high dielectric constant material may include a dielectric constant having a dielectric constant greater than silicon oxide (SiO 2 ) Materials with higher dielectric constants, such as hafnium oxide (HfO), aluminum oxide (AlO) or tantalum oxide (TaO).

[0068] The main gate structure 160M may be located on the upper gate structure 160B and the plurality of upper channel patterns 140B. The main gate structure 160M may be located on top surfaces of the plurality of upper channel patterns 140B.

[0069] The main gate structure 160M may include a main gate electrode 165M and a main gate insulating film 162M.

[0070] The main gate electrode 165M may be located on the upper gate structure 160B and the plurality of upper channel patterns 140B. The main gate electrode 165M may be located on the top surface of the plurality of upper channel patterns 140B. Therefore, the four sides of the plurality of channel patterns 140 may be surrounded by the gate electrodes 165A and 165B and the main gate electrode 165M. The main gate electrode 165M may include the same conductive material as the gate electrodes 165A and 165B. For example, the main gate electrode 165M may include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride.

[0071] The main gate insulating film 162M may extend along the side of the main gate electrode 165M. The main gate insulating film 162M may extend along the side of the gate spacer 164. The main gate insulating film 162M may include various insulating materials.

[0072] In this implementation, the main gate insulating film 162M is shown as a single film, but is not limited thereto. For example, the main gate insulating film 162M may be made of a layer including silicon oxide (SiO 2 ) and a plurality of films of a high dielectric constant material. In this case, the high dielectric constant material may include a dielectric constant having a dielectric constant greater than silicon oxide (SiO 2 ) Materials with higher dielectric constants, such as hafnium oxide (HfO), aluminum oxide (AlO) or tantalum oxide (TaO).

[0073] The semiconductor device according to this implementation may further include a gate spacer 164 and a capping layer 166 .

[0074] The gate spacer 164 may be located on a side of the main gate electrode 165M. The gate spacer 164 may not be located between the active pattern 105 and the plurality of channel patterns 140. The gate spacer 164 may not be located between the plurality of channel patterns 140 adjacent in the third direction (Z direction).

[0075] The gate spacer 164 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof. Although the gate spacer 164 is shown as a single film, this is only for ease of description and is not limited thereto.

[0076] The capping layer 166 may be located on the main gate structure 160M and the gate spacer 164. The top surface of the capping layer 166 and the top surface of the interlayer insulating layer 190 may be located on the same plane. Unlike the illustration, the capping layer 166 may be located between the gate spacers 164.

[0077] The capping layer 166 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), and combinations thereof. The capping layer 166 may include a material having an etching selectivity with respect to the interlayer insulating layer 190 .

[0078] The following will further refer to Figure 5 The source / drain pattern 300 is described.

[0079] Further references Figure 5, the source / drain pattern 300 may be located on at least one side of the gate structure 160. For example, the source / drain pattern 300 may be located on opposite sides of the gate structure 160. The source / drain pattern 300 may be located on the active pattern 105. The source / drain pattern 300 may contact the side of the plurality of channel patterns 140. The source / drain pattern 300 may be connected to the plurality of channel patterns 140.

[0080] The source / drain pattern 300 according to this implementation may include a lower source / drain pattern 300A and an upper source / drain pattern 300B.

[0081] The lower source / drain pattern 300A may be located on the active pattern 105. The lower source / drain pattern 300A may be located on at least one side of the lower gate structure 160A. For example, the lower source / drain pattern 300A may be located on opposite sides of the lower gate structure 160A. The lower source / drain pattern 300A may be connected to the plurality of lower channel patterns 140A.

[0082] The lower source / drain pattern 300A may be located in a lower source / drain trench 300AT extending along a third direction (Z direction). The lower source / drain pattern 300A may fill the lower source / drain trench 300AT. The lower source / drain trench 300AT may be located on opposite sides of the plurality of lower channel patterns 140A. The bottom surface of the lower source / drain trench 300AT may be defined by the active pattern 105. The sidewalls of the lower source / drain trench 300AT may be defined by the plurality of lower channel patterns 140A, the plurality of lower gate structures 160A, and the intermediate dielectric isolation structure MDI. Therefore, the lower source / drain pattern 300A may contact the top surface of the active pattern 105 and the side surfaces of the plurality of lower channel patterns 140A, respectively.

[0083] The lower source / drain pattern 300A may be an epitaxial pattern formed by a selective epitaxial growth process using the active pattern 105 and the plurality of lower channel patterns 140A as seeds. The lower source / drain pattern 300A may be used as a source / drain of a first transistor structure using the plurality of lower channel patterns 140A as a channel region. Here, the first transistor structure may be, but is not limited to, an N-type MOSFET.

[0084] like Figure 4As shown, in the cross-sections along the second direction (Y direction) and the third direction (Z direction), the lower source / drain pattern 300A may have a trapezoidal shape that increases in width as it approaches the top surface of the substrate 101. That is, in the cross-sections along the second direction (Y direction) and the third direction (Z direction), the lower source / drain pattern 300A may include an inclined surface inclined from the top surface of the substrate 101. This inclination may be due to a process characteristic in which the lower source / drain pattern 300A is formed in a space between gate spacers 164 facing each other.

[0085] However, the present disclosure is not limited thereto, and in one example, the width of the lower source / drain pattern 300A along the second direction (Y direction) may be constant. In another example, the lower source / drain pattern 300A may further include a portion protruding toward the interlayer insulating layer 190. This will be described later with reference to Fig.12 Give a description.

[0086] In this implementation, if Figure 5 As shown, the top surface of the lower source / drain pattern 300A may be located at a higher level than the top surface of the topmost lower gate structure 160A. That is, the top surface of the lower source / drain pattern 300A may be positioned farther from the top surface of the substrate 101 than the top surface of the topmost lower gate structure 160A. In other words, the length from the top surface of the substrate 101 to the top surface of the lower source / drain pattern 300A along the third direction (Z direction) may be greater than the length from the top surface of the substrate 101 to the top surface of the topmost lower gate structure 160A along the third direction (Z direction). Therefore, a portion of the side of the lower source / drain pattern 300A may contact the intermediate dielectric isolation structure MDI. That is, the top surface of the lower source / drain pattern 300A may be located at a higher level than the bottom surface of the intermediate dielectric isolation structure MDI. The top surface of the lower source / drain pattern 300A may be located farther from the top surface of the substrate 101 than the bottom surface of the middle dielectric isolation structure MDI. However, the present disclosure is not limited thereto, and the top surface of the lower source / drain pattern 300A may be located at substantially the same level as the top surface of the topmost lower gate structure 160A.

[0087] In this implementation, in the cross-sections along the first direction (X direction) and the third direction (Z direction), the lower source / drain pattern 300A may have an inclined side surface based on the aspect ratio so that the width of the lower portion is narrower than the width of the upper portion, but is not limited thereto. For example, the lower width and the upper width of the lower source / drain pattern 300A may be substantially the same.

[0088] The lower source / drain pattern 300A of the semiconductor device according to the implementation may include a first lower source / drain layer 310A and a second lower source / drain layer 320A.

[0089] The first lower source / drain layer 310A may be positioned along the inner sidewall and bottom surface of the lower source / drain trench 300AT. The portion of the first lower source / drain layer 310A positioned along the inner sidewall of the lower source / drain trench 300AT may contact the plurality of lower channel patterns 140A. The portion of the first lower source / drain layer 310A positioned along the bottom surface of the lower source / drain trench 300AT may contact the active pattern 105. The first lower source / drain layer 310A may include a semiconductor material. For example, the first lower source / drain layer 310A may include a semiconductor material such as silicon (Si) or silicon germanium (SiGe).

[0090] The second lower source / drain layer 320A may be located on the first lower source / drain layer 310A. The second lower source / drain layer 320A may fill the portion of the lower source / drain trench 300AT remaining after forming the first lower source / drain layer 310A. The top surface of the second lower source / drain layer 320A may be located at the same level as the top surface of the first lower source / drain layer 310A. That is, the top surface of the lower source / drain pattern 300A may be defined by the top surface of the first lower source / drain layer 310A and the top surface of the second lower source / drain layer 320A.

[0091] The second lower source / drain layer 320A may include a semiconductor material. For example, the second lower source / drain layer 320A may include the same material as the first lower source / drain layer 310A. In one example, the first lower source / drain layer 310A and the second lower source / drain layer 320A may include a semiconductor material such as silicon (Si) or silicon germanium (SiGe).

[0092] In this implementation, the first lower source / drain layer 310A and / or the second lower source / drain layer 320A may be doped with impurities. For example, when the first transistor structure is n-type, the first lower source / drain layer 310A and / or the second lower source / drain layer 320A may include n-type impurities. In one example, the first lower source / drain layer 310A and the second lower source / drain layer 320A may include P, Sb, As, or a combination thereof. In this case, the material of the impurities contained in the first lower source / drain layer 310A may be different from the material of the impurities contained in the second lower source / drain layer 320A. Optionally, the concentration of the impurities doped in the first lower source / drain layer 310A may be different from the concentration of the impurities doped in the second lower source / drain layer 320A. For example, the concentration of n-type impurities doped into the second lower source / drain layer 320A may be greater than the concentration of n-type impurities doped into the first lower source / drain layer 310A, but the present disclosure is not limited thereto. As another example, when the first transistor structure is p-type, the second lower source / drain layer 320A may include p-type impurities.

[0093] Although the second lower source / drain layer 320A may include the same material as the first lower source / drain layer 310A, the present disclosure is not limited thereto. For example, the second lower source / drain layer 320A may also include a material different from the material of the first lower source / drain layer 310A. For example, the second lower source / drain layer 320A may also include carbon (C), silicon (Si), germanium (Ge), or tin (Sn). In one example, the first lower source / drain layer 310A may include silicon (Si), and the second lower source / drain layer 320A may include silicon germanium (SiGe). In another example, the second lower source / drain layer 320A may include the same material as the first lower source / drain layer 310A, and the concentrations of the constituent materials in the first lower source / drain layer 310A and the second lower source / drain layer 320A may be different. For example, when the first lower source / drain layer 310A and the second lower source / drain layer 320A include silicon germanium (SiGe), the concentration of germanium (Ge) in the first lower source / drain layer 310A may be less than the concentration of germanium (Ge) in the second lower source / drain layer 320A, but the present disclosure is not limited thereto. As another example, the second lower source / drain layer 320A may include the same material as the first lower source / drain layer 310A, and the first lower source / drain layer 310A and the second lower source / drain layer 320A may have the same concentration of constituent materials.

[0094] In an implementation, the lower source / drain pattern 300A is described as having a plurality of layers, but is not limited thereto. The lower source / drain pattern 300A may have a single layer including a semiconductor material.

[0095] The upper source / drain pattern 300B of the semiconductor device 100 according to this implementation may be located on the lower source / drain pattern 300A.

[0096] The upper source / drain pattern 300B may be spaced apart from the lower source / drain pattern 300A in the third direction (Z direction). For example, the blocking structure 170 may be located between the upper source / drain pattern 300B and the lower source / drain pattern 300A, and the upper source / drain pattern 300B and the lower source / drain pattern 300A may be spaced apart by the blocking structure 170. Therefore, the upper source / drain pattern 300B and the lower source / drain pattern 300A may be electrically insulated.

[0097] The upper source / drain pattern 300B may be located at least one side of the upper gate structure 160B. For example, the upper source / drain pattern 300B may be located at opposite sides of the upper gate structure 160B. The upper source / drain pattern 300B may be connected to the plurality of upper channel patterns 140B.

[0098] The upper source / drain pattern 300B may be located within the upper source / drain trench 300BT. The upper source / drain pattern 300B may fill the upper source / drain trench 300BT. The upper source / drain trench 300BT may be located on opposite sides of the plurality of upper channel patterns 140B. The bottom surface 300BT_B of the upper source / drain trench 300BT may be defined by the blocking structure 170, but is not limited thereto. The sidewall 300BT_S of the upper source / drain trench 300BT may be defined by the plurality of upper channel patterns 140B and the plurality of upper gate structures 160B. However, the present disclosure is not limited thereto, and the sidewall 300BT_S of the upper source / drain trench 300BT may be defined by the plurality of upper channel patterns 140B and the plurality of upper gate structures 160B, as well as by the intermediate dielectric isolation structure MDI and / or the gate spacer 164. These will be referred to below. Figure 7 Give a description.

[0099] Therefore, the upper source / drain pattern 300B may contact the side surfaces of the plurality of upper channel patterns 140B. In addition, unlike the lower source / drain pattern 300A, since the upper source / drain pattern 300B is spaced apart from the lower source / drain pattern 300A in the third direction (Z direction), the upper source / drain pattern 300B may not contact the top surface of the active pattern 105.

[0100] The upper source / drain pattern 300B may be an epitaxial pattern formed by a selective epitaxial growth process using the plurality of upper channel patterns 140B as a seed. In this case, the upper source / drain pattern 300B may be a pattern formed by using the opposite sides of the plurality of upper channel patterns 140B as a seed. That is, unlike the lower source / drain pattern 300A (which is a pattern formed using the top surface of the active pattern 105 and the opposite sides of the plurality of lower channel patterns 140A as a seed), the upper source / drain pattern 300B may be a pattern formed using only the opposite sides of the plurality of upper channel patterns 140B as a seed. The upper source / drain pattern 300B may be used as a source / drain of a second transistor structure using the plurality of upper channel patterns 140B as a channel region. Here, the second transistor structure may be, but is not limited to, a P-type MOSFET.

[0101] like Figure 4 As shown, in the cross section along the second direction (Y direction) and the third direction (Z direction), the upper source / drain pattern 300B may have a shape different from the lower source / drain pattern 300A. For example, in the cross section along the second direction (Y direction) and the third direction (Z direction), the upper source / drain pattern 300B may have a hexagonal shape, but is not limited thereto. In one example, the upper source / drain pattern 300B may have a circular, elliptical or pentagonal shape, or a shape similar thereto. At the same time, as described above, the lower source / drain pattern 300A may have a trapezoidal shape, which increases in width when it approaches the top surface of the substrate 101. This may be due to the following process characteristics, in which the lower source / drain pattern 300A is formed in the space between the gate spacers 164 facing each other, and the upper source / drain pattern 300B is formed in the open space above the blocking structure 170.

[0102] exist Figure 5In the example shown, the top surface of the upper source / drain pattern 300B may be located at substantially the same level as the top surface of the topmost upper channel pattern 140B. That is, the top surface of the upper source / drain pattern 300B and the top surface of the topmost upper channel pattern 140B may have substantially the same distance from the top surface of the substrate 101. In addition, the bottom surface of the upper source / drain pattern 300B may be located at substantially the same level as the top surface of the intermediate dielectric isolation structure MDI. The bottom surface of the upper source / drain pattern 300B may be located at substantially the same level as the bottom surface of the bottommost upper gate structure 160B. However, the present disclosure is not limited thereto, and the top surface of the upper source / drain pattern 300B may be located at a higher level than the top surface of the topmost upper channel pattern 140B. In addition, the bottom surface of the upper source / drain pattern 300B may be located at a lower level than the bottom surface of the bottommost upper gate structure 160B. This will be referred to later. Figure 6 Give a description.

[0103] In this implementation, the top surface of the upper source / drain pattern 300B may include a flat portion. For example, the portion of the top surface of the upper source / drain pattern 300B that contacts the interlayer insulating layer 190 may be flat. That is, the top surface of the upper source / drain pattern 300B may include a portion that extends straight in the first direction (X direction). In addition, the bottom surface of the upper source / drain pattern 300B may be flat. For example, the bottom surface of the upper source / drain pattern 300B that contacts the blocking structure 170 may extend straight in the first direction (X direction). However, the present disclosure is not limited to this, and the top surface of the upper source / drain pattern 300B may have a convex shape facing in a direction away from the substrate 101. Optionally, the bottom surface of the upper source / drain pattern 300B may have a convex shape toward the substrate 101. This will be referred to later. Figure 8 and Fig. 9 Give a description.

[0104] In this implementation, the lower width and upper width of the upper source / drain pattern 300B may be substantially equal, but are not limited thereto. For example, the upper source / drain pattern 300B may have an inclined side surface depending on the aspect ratio so that the width of the lower portion is narrower than the width of the upper portion.

[0105] An upper source / drain pattern 300B of a semiconductor device according to an implementation may include a first upper source / drain layer 310B and a second upper source / drain layer 320B.

[0106] The first upper source / drain layer 310B may be located on the sidewall 300BT_S of the upper source / drain trench 300BT. For example, the first upper source / drain layer 310B may be located on opposite sidewalls of the upper source / drain trench 300BT. The first upper source / drain layer 310B located along the sidewall 300BT_S of the upper source / drain trench 300BT may contact the plurality of upper channel patterns 140B.

[0107] In one implementation, the first upper source / drain layer 310B may not cover at least a portion of the bottom surface 300BT_B of the upper source / drain trench 300BT. For example, the first upper source / drain layer 310B may not be located on the bottom surface 300BT_B of the upper source / drain trench 300BT. This may be due to the following process characteristics, in which the first upper source / drain layer 310B is formed using the opposite side of the plurality of upper channel patterns 140B as a seed. That is, unlike the lower source / drain pattern 300A (which is a pattern formed by using the top surface of the active pattern 105 and the opposite side of the plurality of lower channel patterns 140A as a seed), the upper source / drain pattern 300B may be a pattern formed by using only the opposite side of the plurality of upper channel patterns 140B as a seed. Therefore, the first upper source / drain layer 310B may not cover at least a portion of the bottom surface 300BT_B of the upper source / drain trench 300BT.

[0108] In one implementation, the first upper source / drain layers 310B may be spaced apart from each other in the first direction (X direction). For example, the first upper source / drain layer 310B located on one side of the upper source / drain trench 300BT and the first upper source / drain layer 310B located on the other side of the upper source / drain trench 300BT may be spaced apart in the first direction (X direction). Therefore, a predetermined gap may be generated between the first upper source / drain layers 310B. However, the present disclosure is not limited thereto, and in some implementations, the first upper source / drain layers 310B may contact each other. This will refer to Fig. 9 Further discussion.

[0109] In one implementation, the first upper source / drain layer 310B may be in contact with the multiple upper channel patterns 140B and the upper gate structure 160B. The first upper source / drain layer 310B may overlap with the multiple upper channel patterns 140B and the upper gate structure 160B in the first direction (X direction). In one example, the edge of the first upper source / drain layer 310B may be aligned with the top surface of the topmost upper channel pattern 140B. In addition, the first upper source / drain layer 310B may not overlap with the intermediate dielectric isolation structure MDI and the gate spacer 164 in the first direction (X direction). However, the present disclosure is not limited to this, and the inner gate spacer 168 may be further positioned between the first upper source / drain layer 310B and the upper gate structure 160B. In addition, the first upper source / drain layer 310B may be in contact with the intermediate dielectric isolation structure MDI and / or the gate spacer 164. This will be referred to later Fig.16 and Fig.17 Give a description.

[0110] In one implementation, the first upper source / drain layer 310B may protrude from the sidewall 300BT_S of the upper source / drain trench 300BT. For example, the side 310B_S of the first upper source / drain layer 310B may have a convex shape from the sidewall 300BT_S of the upper source / drain trench 300BT. In one example, the side 310B_S of the first upper source / drain layer 310B may include a curved surface protruding from the sidewall 300BT_S of the upper source / drain trench 300BT. For example, as Figure 5 As shown, the side surface 310B_S of the first upper source / drain layer 310B may have a rounded shape. This may be due to the following process characteristics, in which the first upper source / drain layer 310B is formed using the opposite side surfaces of the plurality of upper channel patterns 140B as seeds.

[0111] Therefore, the width of the first upper source / drain layer 310B along the first direction (X direction) may gradually increase from the upper and lower portions of the upper source / drain trench 300BT toward the central portion. For example, the first width W1 along the first direction (X direction) at the central portion of the first upper source / drain layer 310B may be greater than the second width W2 along the first direction (X direction) at the upper portion of the first upper source / drain layer 310B. In addition, the first width W1 along the first direction (X direction) of the central portion of the first upper source / drain layer 310B may be greater than the third width W3 along the first direction (X direction) of the lower portion of the first upper source / drain layer 310B. In this case, the first width W1 along the first direction (X direction) of the central portion of the first upper source / drain layer 310B may be the maximum width of the first upper source / drain layer 310B along the first direction (X direction). In one example, a first width W1 of a central portion of the first upper source / drain layer 310B along the first direction (X direction) may be greater than about 0 nm and less than about 10 nm.

[0112] In addition, the first angle θ1 formed by the side 310B_S of the first upper source / drain layer 310B and the sidewall 300BT_S of the upper source / drain trench 300BT may be from 0° to 90°. In one example, the first angle θ1 formed by the side 310B_S of the first upper source / drain layer 310B and the sidewall 300BT_S of the upper source / drain trench 300BT may be 80° to 90°. Within this range, when the second upper source / drain layer 320B is formed between the first upper source / drain layers 310B, the second upper source / drain layer 320B may be formed to completely fill the upper source / drain trench 300BT.

[0113] In this implementation, the first upper source / drain layer 310B may have a symmetrical shape relative to a symmetry axis parallel to the third direction (Z direction). For example, the first upper source / drain layer 310B located on one sidewall 300BT_S of the upper source / drain trench 300BT and the first upper source / drain layer 310B located on the other sidewall 300BT_S of the upper source / drain trench 300BT may have a symmetrical shape relative to the symmetry axis. Here, the symmetry axis parallel to the third direction (Z direction) may refer to an axis that passes through the central portion of the upper source / drain trench 300BT and extends in a direction parallel to the third direction (Z direction).

[0114] In this implementation, at least one of the first upper source / drain layers 310B may have a maximum width in the first direction (X direction) above or below the central portion in the third direction (Z direction). Alternatively, the first upper source / drain layers 310B located on opposite sides of the upper source / drain pattern 310 may have different maximum widths.

[0115] although Figure 5 The side surface 310B_S of the first upper source / drain layer 310B is shown to be a curved surface, but the present disclosure is not limited thereto, and the side surfaces 310B_S of the first upper source / drain layer 310B may vary to the extent that they have a convex shape from the sidewall 300BT_S of the upper source / drain trench 300BT. For example, the side surface 310B_S of the first upper source / drain layer 310B may also include a side surface extending in a third direction (Z direction). Optionally, the side surface 310B_S of the first upper source / drain layer 310B may include a plurality of inclined surfaces. This will be described later with reference to Figure 6 , Fig.10 and Fig.11 Give a description.

[0116] The first upper source / drain layer 310B may include a semiconductor material. For example, the first upper source / drain layer 310B may include a semiconductor material such as silicon (Si) or silicon germanium (SiGe).

[0117] In this implementation, the first upper source / drain layer 310B may include impurities. For example, if the second transistor structure is p-type, the first upper source / drain layer 310B may include p-type impurities. In one example, the first upper source / drain layer 310B may include B, V, In, Ga, Al, or a combination thereof.

[0118] The second upper source / drain layer 320B may be located between the first upper source / drain layers 310B.

[0119] The second upper source / drain layer 320B may fill the remaining portion after forming the first upper source / drain layer 310B in the upper source / drain trench 300BT. The second upper source / drain layer 320B may be located on the blocking structure 170 defining the bottom surface 300BT_B of the upper source / drain trench 300BT. Therefore, the second upper source / drain layer 320B may be spaced apart from the lower source / drain pattern 300A in the third direction (Z direction) by the blocking structure 170. The second upper source / drain layer 320B may contact the side 310B_S of the first upper source / drain layer 310B. Therefore, the first upper source / drain layer 310B is located between the second upper source / drain layer 320B and the plurality of upper channel patterns 140B, and the second upper source / drain layer 320B may not contact the plurality of upper channel patterns 140B, but the present disclosure is not limited thereto.

[0120] In this implementation, the second upper source / drain layer 320B may fill the portion remaining after the first upper source / drain layer 310B is formed in the upper source / drain trench 300BT. Therefore, the side surface of the second upper source / drain layer 320B may have a shape complementary to the side surface of the first upper source / drain layer 310B. For example, when viewed from the sidewall 300BT_S of the upper source / drain trench 300BT, the side surface 310B_S of the first upper source / drain layer 310B may have a convex shape (e.g., curved away), and accordingly, the side surface of the second upper source / drain layer 320B may have a curved shape (e.g., concave) toward the central portion of the second upper source / drain layer 320B.

[0121] Therefore, the width of the second upper source / drain layer 320B along the first direction (X direction) can be gradually reduced from the upper and lower parts of the upper source / drain trench 300BT toward the central part. For example, the fourth width W4 of the central part of the second upper source / drain layer 320B along the first direction (X direction) can be less than the width of the upper part of the second upper source / drain layer 320B along the first direction (X direction). In addition, the fourth width W4 of the central part of the second upper source / drain layer 320B along the first direction (X direction) can be less than the width of the lower part of the second upper source / drain layer 320B along the first direction (X direction). In this case, the fourth width W4 of the central part of the second upper source / drain layer 320B along the first direction (X direction) can be the minimum width of the second upper source / drain layer 320B along the first direction (X direction). In one example, a fourth width W4 of a central portion of the second upper source / drain layer 320B along the first direction (X direction) may be greater than about 5 nm and less than about 25 nm.

[0122] In this implementation, the top surface 320B_U of the second upper source / drain layer 320B may be located at the same level as the top surface of the topmost upper channel pattern 140B among the plurality of upper channel patterns 140B. That is, the distance from the top surface of the substrate 101 to the top surface 320B_U of the second upper source / drain layer 320B may be substantially the same as the distance from the top surface of the substrate 101 to the top surface of the topmost upper channel pattern 140B among the plurality of upper channel patterns 140B. Therefore, the second upper source / drain layer 320B may not overlap with the main gate structure 160M in the first direction (X direction). In addition, the top surface 320B_U of the second upper source / drain layer 320B may be aligned with the edge of the first upper source / drain layer 310B. However, the present disclosure is not limited thereto, and the top surface 320B_U of the second upper source / drain layer 320B may be located at a higher level than the top surface of the topmost upper channel pattern 140B among the plurality of upper channel patterns 140B. This will be described later with reference to Figure 7 Give a description.

[0123] In this implementation, the top surface 320B_U of the second upper source / drain layer 320B may include a flat portion. For example, a portion of the top surface 320B_U of the second upper source / drain layer 320B that contacts the interlayer insulating layer 190 may be flat.

[0124] That is, the top surface 320B_U of the second upper source / drain layer 320B may include a portion extending straight in the first direction (X direction). In addition, the bottom surface of the second upper source / drain layer 320B may be flat. For example, the bottom surface of the second upper source / drain layer 320B in contact with the blocking structure 170 may extend straight in the first direction (X direction). However, the present disclosure is not limited to this, and the top surface 320B_U of the second upper source / drain layer 320B may have a convex shape facing away from the substrate 101. Optionally, the bottom surface of the second upper source / drain layer 320B may have a convex shape toward the substrate 101. This will be referred to later Figure 8 and Fig. 9 Give a description.

[0125] The second upper source / drain layer 320B may include a semiconductor material. For example, the second upper source / drain layer 320B may include the same material as the first upper source / drain layer 310B. In one example, the first upper source / drain layer 310B and the second upper source / drain layer 320B may include a semiconductor material such as silicon (Si) or silicon germanium (SiGe).

[0126] In this case, the concentrations of the constituent materials of the first upper source / drain layer 310B and the second upper source / drain layer 320B may be different. For example, when the first upper source / drain layer 310B and the second upper source / drain layer 320B include silicon germanium (SiGe), the concentration of germanium (Ge) in the second upper source / drain layer 320B may be greater than the concentration of germanium (Ge) in the first upper source / drain layer 310B. In one example, the concentration of germanium (Ge) in the second upper source / drain layer 320B may be equal to or greater than 60at% and less than 70at%, but the present disclosure is not limited thereto. Within this range, when the second upper source / drain layer 320B is formed between the first upper source / drain layer 310B, the second upper source / drain layer 320B may include a flat portion of the top surface 320B_U and the bottom surface. However, the present disclosure is not limited thereto, and the concentration of germanium (Ge) in the second upper source / drain layer 320B may be less than 60at%. This will be referenced below Figure 8 and Fig. 9 Give a description.

[0127] In one implementation, the first upper source / drain layer 310B and / or the second upper source / drain layer 320B may be doped with impurities. For example, when the first transistor structure is p-type, the first upper source / drain layer 310B and / or the second upper source / drain layer 320B may include p-type impurities. In one example, the first upper source / drain layer 310B and the second upper source / drain layer 320B may include B, C, In, Ga, Al, or a combination thereof. In this case, the material of the impurities contained in the first upper source / drain layer 310B may be different from the material of the impurities contained in the second upper source / drain layer 320B. Optionally, the concentration of the impurities doped in the first upper source / drain layer 310B may be different from the concentration of the impurities doped in the second upper source / drain layer 320B. In this case, the concentration of the p-type impurities doped into the second upper source / drain layer 320B may be less than the concentration of the p-type impurities doped into the first upper source / drain layer 310B, but the present disclosure is not limited thereto.

[0128] Although it is described that in the implementation mode, the second upper source / drain layer 320B includes the same material as the first upper source / drain layer 310B, the present disclosure is not limited thereto. For example, the second upper source / drain layer 320B may also include a material different from the material of the first upper source / drain layer 310B. For example, the second upper source / drain layer 320B may also include carbon (C), silicon (Si), germanium (Ge) or tin (Sn). In one example, the first upper source / drain layer 310B may include silicon (Si), and the second upper source / drain layer 320B may include silicon germanium (SiGe). As another example, the second upper source / drain layer 320B may include the same material as the first upper source / drain layer 310B, and the first upper source / drain layer 310B and the second upper source / drain layer 320B may have the same concentration of constituent materials.

[0129] In an implementation, the upper source / drain pattern 300B is described as including a first upper source / drain layer 310B and a second upper source / drain layer 320B, but the present disclosure is not limited thereto. For example, the upper source / drain pattern 300B may be divided into three or more layers.

[0130] In the process of forming the upper source / drain pattern 300B of the semiconductor device 100 according to the implementation, the opposite sides of the plurality of upper channel patterns 140B may be used as seeds to form the first upper source / drain layer 310B. That is, unlike the lower source / drain pattern 300A (which is a pattern formed using the top surface of the active pattern 105 and the opposite sides of the plurality of lower channel patterns 140A as seeds), the upper source / drain pattern 300B may be a pattern formed using only the opposite sides of the plurality of upper channel patterns 140B as seeds. Therefore, the first upper source / drain layer 310B may not cover at least a portion of the bottom surface 300BT_B of the upper source / drain trench 300BT.

[0131] In addition, the first upper source / drain layer 310B of the semiconductor device 100 according to the implementation has a convex shape from the sidewall 300BT_S of the upper source / drain trench 300BT, and the second upper source / drain layer 320B can be stably formed in the space between the first upper source / drain layers 310B. Therefore, the proportion of the second upper source / drain layer 320B formed in the upper source / drain trench 300BT can be increased.

[0132] The blocking structure 170 may be located between the lower source / drain pattern 300A and the upper source / drain pattern 300B. The blocking structure 170 may overlap the lower source / drain pattern 300A and the upper source / drain pattern 300B in the third direction (Z direction). The blocking structure 170 may be located between the intermediate dielectric isolation structure MDI. The top surface and the bottom surface of the blocking structure 170 may be flat, but are not limited thereto. For example, the top surface and / or the bottom surface of the blocking structure 170 may have a shape that is convex upward or convex downward.

[0133] The barrier structure 170 may include a first barrier pattern 171 extending along the side of the middle dielectric isolation structure MDI and the top surface of the lower source / drain pattern 300A and a second barrier pattern 172 located on the first barrier pattern 171. The first barrier pattern 171 may be located on the side of the gate spacer 164, such as Figure 4 For example, the first barrier pattern 171 may not be located on the side of the gate spacer 164 .

[0134] The first barrier pattern 171 and the second barrier pattern 172 may include various insulating materials. The first barrier pattern 171 and the second barrier pattern 172 may include different materials, but are not limited thereto. For example, the first barrier pattern 171 may include silicon nitride, silicon oxynitride, or a combination thereof, and the second barrier pattern 172 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The barrier structure 170 may space the lower source / drain pattern 300A and the upper source / drain pattern 300B apart from each other in the third direction (Z direction).

[0135] The semiconductor device 100 may further include an interlayer insulating layer 190 .

[0136] The interlayer insulating layer 190 may be located on the side of the gate spacer 164 , the side of the capping layer 166 , and the top surface of the upper source / drain pattern 300B. The interlayer insulating layer 190 may not cover the top surface of the capping layer 166 .

[0137] The interlayer insulating layer 190 may include, for example, silicon oxide (SiO 2), silicon nitride (SiN), silicon oxynitride (SiON) and at least one of a low dielectric constant material. The low dielectric constant material may include, for example, fluorinated tetraethyl orthosilicate (FTEOS), hydrogen silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), diacetyl ditert-butyl siloxane (TMSB), diacetoxy ditert-butyl siloxane (DADBS), trimethyl silicon phosphate (TMSP), polytetrafluoroethylene (PTFE), eastern silazane (TOSZ), fluoride silicate glass (FSG), polyimide nanofoam such as polypropylene oxide, carbon-doped silicon oxide (CDO), organosilicate glass (OSG), SiLK, amorphous fluorinated carbon, silica aerogel, silica xerogel, mesoporous silica or a combination thereof, but is not limited thereto.

[0138] In an implementation, although not shown, an etch stop film may be further located between the gate spacer 164 and the interlayer insulating layer 190 and between the upper source / drain pattern 300B and the interlayer insulating layer 190. The etch stop film may include a material having an etch selectivity with respect to the interlayer insulating layer 190. The etch stop film may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof.

[0139] The semiconductor device 100 may further include a contact structure 180 .

[0140] The contact structure 180 may be located on the upper source / drain pattern 300B. The contact structure 180 may be electrically connected to the upper source / drain pattern 300B through the interlayer insulating layer 190. The contact structure 180 may have an inclined side surface based on an aspect ratio, the lower width of the inclined side surface being narrower than the upper width, but is not limited thereto. The contact structure 180 may be positioned to recess the upper source / drain pattern 300B to a predetermined depth.

[0141] For example, the bottom surface of the contact structure 180 may be higher than the bottom surface of the topmost upper channel pattern 140B among the plurality of upper channel patterns 140B. However, the present disclosure is not limited thereto, and the bottom surface of the contact structure 180 may be located at a level similar to the bottom surface of the topmost upper channel pattern 140B among the plurality of upper channel patterns 140B, or may be lower than the bottom surface of the topmost upper channel pattern 140B. Alternatively, the bottom surface of the contact structure 180 may be located between the bottom surface of the bottommost upper channel pattern 140B and the bottom surface of the topmost upper channel pattern 140B among the plurality of upper channel patterns 140B.

[0142] The contact structure 180 of the semiconductor device 100 according to an implementation may include a contact electrode 186 , a first barrier layer 184 surrounding the contact electrode 186 , and a first silicide film 182 between the first barrier layer 184 and the upper source / drain pattern 300B.

[0143] The contact electrode 186 may include, for example, at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material. The first barrier layer 184 may include, for example, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN).

[0144] The first silicide film 182 may surround the portion of the contact electrode 186 protruding into the upper source / drain pattern 300B. The first silicide film 182 may include a metal silicide. For example, the first silicide film 182 may include at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide. In an implementation, the number and arrangement of the conductive layers configuring the contact structure 180 may vary. In some implementations, the first barrier layer 184 and / or the first silicide film 182 may be omitted.

[0145] It has been described above that the lower source / drain pattern 300A is located on the substrate 101, the upper source / drain pattern 300B is located on the lower source / drain pattern 300A, and the upper source / drain pattern 300B includes a first upper source / drain layer 310B located on the sides of the plurality of upper channel patterns 140B and a second upper source / drain layer 320B located between the first upper source / drain layer 310B. However, the present disclosure is not limited thereto, and even includes a semiconductor device 100 without the lower source / drain pattern 300A, as long as the upper source / drain pattern 300B is formed to be spaced apart from the substrate 101.

[0146] In the process of forming the upper source / drain pattern 300B of the semiconductor device 100 according to the implementation, the opposite sides of the plurality of upper channel patterns 140B may be used as seeds to form the first upper source / drain layer 310B. That is, unlike the lower source / drain pattern 300A (which is a pattern formed using the top surface of the active pattern 105 and the opposite sides of the plurality of lower channel patterns 140A as seeds), the first upper source / drain layer 310B may be a pattern formed using only the opposite sides of the plurality of upper channel patterns 140B as seeds. Therefore, the first upper source / drain layer 310B may not cover at least a portion of the bottom surface 300BT_B of the upper source / drain trench 300BT.

[0147] In addition, since the first upper source / drain layer 310B of the semiconductor device 100 according to the implementation has a convex shape from the sidewall 300BT_S of the upper source / drain trench 300BT, the second upper source / drain layer 320B can be stably formed in the space between the first upper source / drain layers 310B. That is, the second upper source / drain layer 320B can be completely filled in the upper source / drain trench 300BT. Therefore, the proportion of the second upper source / drain layer 320B formed in the upper source / drain trench 300BT can be increased, and thus the reliability of the semiconductor device 100 can be improved.

[0148] In the following, further reference will be made to Figures 6 to 12 An upper source / drain pattern of a semiconductor device is described.

[0149] Figure 6 is a diagram showing the semiconductor device corresponding to Figure 2 A cross-sectional view of area A1.

[0150] Figure 6 The example shown in Figures 1 to 5 The examples shown in are substantially the same, so the same items will not be described, but will be described in terms of differences. In the present implementation, the shape of the first upper source / drain layer 310B is different from the previous implementation, as will be described below.

[0151] The side surface of the first upper source / drain layer 310B according to an implementation may include a first side surface 310B_S1 protruding from the sidewall 300BT_S of the upper source / drain trench 300BT and a second side surface 310B_S2 extending in the third direction (Z direction).

[0152] The first side 310B_S1 of the first upper source / drain layer 310B may extend from the sidewall 300BT_S of the upper source / drain trench 300BT. The first side 310B_S1 of the first upper source / drain layer 310B may have a rounded shape. The second angle θ2 formed by the first side 310B_S1 of the first upper source / drain layer 310B and the sidewall 300BT_S of the upper source / drain trench 300BT may be 80° to 90°. Within this range, when the second upper source / drain layer 320B is formed between the first upper source / drain layer 310B, the second upper source / drain layer 320B may be formed to completely fill the upper source / drain trench 300BT. In addition, the second upper source / drain layer 320B may be formed so that the top surface 320B_U of the second upper source / drain layer 320B includes a flat portion.

[0153] In an implementation, the first side 310B_S1 of the first upper source / drain layer 310B may form a portion of the top surface of the upper source / drain pattern 300B. In this case, the first side 310B_S1 of the first upper source / drain layer 310B and the top surface 320B_U of the second upper source / drain layer 320B may be located at the same level. That is, the first side 310B_S1 of the first upper source / drain layer 310B and the top surface 320B_U of the second upper source / drain layer 320B may be located at the same distance from the top surface of the substrate 101. The first side 310B_S1 of the first upper source / drain layer 310B may contact the interlayer insulating layer 190. However, the present disclosure is not limited thereto, and the first side 310B_S1 of the first upper source / drain layer 310B may be surrounded by the second upper source / drain layer 320B.

[0154] The second side 310B_S2 of the first upper source / drain layer 310B may extend straightly in a third direction (Z direction) from one side of the first side 310B_S1 of the first upper source / drain layer 310B. For example, the side of the central portion of the first upper source / drain layer 310B may extend in the third direction (Z direction). In this case, the first upper source / drain layer 310B may also have a shape protruding from the sidewall 300BT_S of the upper source / drain trench 300BT due to the first side 310B_S1. In other words, the side of the first upper source / drain layer 310B may have a shape protruding from the sidewall 300BT_S of the upper source / drain trench 300BT.

[0155] In this implementation, the first width W1 of the central portion of the first upper source / drain layer 310B along the first direction (X direction) may be greater than the width of the top of the first upper source / drain layer 310B along the first direction (X direction) and the width of the bottom of the first upper source / drain layer 310B along the first direction (X direction). In one example, the first width W1 of the central portion of the first upper source / drain layer 310B along the first direction (X direction) may be greater than about 0 nm and less than about 10 nm. Here, the first width W1 of the central portion of the first upper source / drain layer 310B along the first direction (X direction) may be the maximum width of the first upper source / drain layer 310B along the first direction (X direction).

[0156] The second upper source / drain layer 320B may be located between the first upper source / drain layers 310B. The second upper source / drain layer 320B may fill a portion remaining after forming the first upper source / drain layer 310B in the upper source / drain trench 300BT.

[0157] Therefore, the side surface of the second upper source / drain layer 320B may have a shape complementary to the side surface of the first upper source / drain layer 310B. For example, the side surface of the first upper source / drain layer 310B may include a first side surface 310B_S1 protruding from the opposite sidewall 300BT_S of the upper source / drain trench 300BT and a second side surface 310B_S2 extending in a third direction (Z direction), and the side surface of the second upper source / drain layer 320B may be conformal to the side surface of the first upper source / drain layer 310B and include a portion recessed toward the central portion of the second upper source / drain layer 320B and a portion extending in the third direction (Z direction).

[0158] The first upper source / drain layer 310B of the semiconductor device 100 according to the implementation also includes a second side surface 310B_S2 extending in the third direction (Z direction), so that the ratio of the second upper source / drain layer 320B to the upper source / drain pattern 300B can be increased. That is, the ratio of the volume occupied by the second upper source / drain layer 320B to the volume of the upper source / drain trench 300BT can be increased. Therefore, the reliability of the semiconductor device 100 can be improved.

[0159] Figure 7 is a diagram showing the semiconductor device corresponding to Figure 2 A cross-sectional view of area A1.

[0160] Figure 7 The implementation shown in Figures 1 to 5 The implementation shown in FIG. 1 is substantially the same and therefore only the differences from the previous figures will be described.

[0161] In the present implementation, the shape of the upper source / drain pattern 300B is different from the previous implementation, and will be described below.

[0162] The top surface 300B_U of the upper source / drain pattern 300B according to the implementation can be located at a higher level than the top surface of the topmost upper channel pattern 140B. That is, the top surface 300B_U of the upper source / drain pattern 300B can be positioned farther away from the top surface of the substrate 101 than the top surface of the topmost upper channel pattern 140B. In other words, the top surface 300B_U of the upper source / drain pattern 300B can be located at a higher level than the bottom surface of the main gate structure 160M. Therefore, the upper source / drain pattern 300B can overlap with the plurality of upper channel patterns 140B and the upper gate structure 160B and the main gate structure 160M and the gate spacer 164 in the first direction (X direction). The upper source / drain pattern 300B can contact the gate spacer 164, but is not limited thereto.

[0163] In addition, the bottom surface 300B_B of the upper source / drain pattern 300B according to the implementation can be located at a level lower than the top surface of the intermediate dielectric isolation structure MDI. The bottom surface 300B_B of the upper source / drain pattern 300B can be located at a level lower than the bottom surface of the bottommost upper gate structure 160B. That is, the bottom surface 300B_B of the upper source / drain pattern 300B can be positioned closer to the top surface of the substrate 101 than the top surface of the intermediate dielectric isolation structure MDI. Therefore, the upper source / drain pattern 300B can overlap with the multiple upper channel patterns 140B and the upper gate structure 160B and the intermediate dielectric isolation structure MDI in the first direction (X direction). The upper source / drain pattern 300B can contact the intermediate dielectric isolation structure MDI, but is not limited to this.

[0164] exist Figure 7 , it is shown that the top surface 300B_U of the upper source / drain pattern 300B may be located at a higher level than the top surface of the topmost upper channel pattern 140B, and the bottom surface 300B_B of the upper source / drain pattern 300B may be located at a lower level than the top surface of the intermediate dielectric isolation structure MDI, but the present disclosure is not limited thereto. For example, the top surface 300B_U of the upper source / drain pattern 300B may be located at a higher level than the top surface of the topmost upper channel pattern 140B, and the bottom surface 300B_B of the upper source / drain pattern 300B may be located at substantially the same level as the top surface of the intermediate dielectric isolation structure MDI. Alternatively, a top surface 300B_U of the upper source / drain pattern 300B may be located at substantially the same level as a top surface of the topmost upper channel pattern 140B, and a bottom surface 300B_B of the upper source / drain pattern 300B may be located at a lower level than a top surface of the middle dielectric isolation structure MDI.

[0165] Figure 8 and Fig. 9 is corresponding to Figure 2 FIG. 4 is a cross-sectional view of a region A1 of a semiconductor device according to some implementations.

[0166] Figure 8 and Fig. 9 The implementation shown in Figures 1 to 5 The implementation shown in is substantially the same, and thus will not be described, but will be described in terms of differences. In this implementation, the shape of the second upper source / drain layer 320B is different from the previous implementation, and will be described below.

[0167] The top surface 320B_U of the second upper source / drain layer 320B according to the implementation may include a convex shape in a direction away from the top surface of the substrate 101. For example, a portion of the top surface 320B_U of the second upper source / drain layer 320B in contact with the interlayer insulating layer 190 may be convex in a direction away from the top surface of the substrate 101. Therefore, the second upper source / drain layer 320B may protrude from the top surface of the topmost upper channel pattern 140B. The second upper source / drain layer 320B may overlap with the main gate structure 160M and the gate spacer 164 in the first direction (X direction).

[0168] In addition, the bottom surface 320B_B of the second upper source / drain layer 320B according to the implementation may include a convex shape in the direction facing the substrate 101. For example, the bottom surface 320B_B of the second upper source / drain layer 320B in contact with the blocking structure 170 may be convex in the direction facing the substrate 101. Therefore, the second upper source / drain layer 320B may protrude downward from the bottom surface of the bottommost upper gate structure 160B. The second upper source / drain layer 320B may overlap with the intermediate dielectric isolation structure MDI in the first direction (X direction).

[0169] In this implementation, the second upper source / drain layer 320B may include a semiconductor material. For example, the second upper source / drain layer 320B may include the same material as the first upper source / drain layer 310B. In one example, the first upper source / drain layer 310B and the second upper source / drain layer 320B may include a semiconductor material, such as silicon (Si) or silicon germanium (SiGe).

[0170] In this case, the concentrations of the constituent materials of the first upper source / drain layer 310B and the second upper source / drain layer 320B may be different. For example, when the first upper source / drain layer 310B and the second upper source / drain layer 320B include silicon germanium (SiGe), the concentration of germanium (Ge) in the second upper source / drain layer 320B may be greater than the concentration of germanium (Ge) in the first upper source / drain layer 310B. In one example, the concentration of germanium (Ge) in the second upper source / drain layer 320B may be equal to or greater than 50at% and less than 60at%, but is not limited thereto. Within this range, when the second upper source / drain layer 320B is formed between the first upper source / drain layer 310B, the top surface 320B_U and the bottom surface 320B_B of the second upper source / drain layer 320B may have a convex shape.

[0171] In this implementation, the side 310B_S of the first upper source / drain layer 310B may have a convex shape from the sidewall 300BT_S of the upper source / drain trench 300BT. For example, the side 310B_S of the first upper source / drain layer 310B may have a rounded shape. In one example, the width of the central portion of the first upper source / drain layer 310B along the first direction (X direction) may be greater than the width of the top of the first upper source / drain layer 310B along the first direction (X direction) and the width of the bottom of the first upper source / drain layer 310B along the first direction (X direction).

[0172] On the other hand, when the top surface 320B_U and / or the bottom surface 320B_B of the second upper source / drain layer 320B have a convex shape, the width of the central portion of the first upper source / drain layer 310B along the first direction (X direction) may be equal to or greater than 10 nm and equal to or less than 13 nm. Here, the width of the central portion of the first upper source / drain layer 310B along the first direction (X direction) may be the maximum width of the first upper source / drain layer 310B along the first direction (X direction). Therefore, the first upper source / drain layers 310B may be spaced apart from each other or in contact with each other in the first direction (X direction).

[0173] For example, Figure 8 As shown, the maximum width of the first upper source / drain layer 310B along the first direction (X direction) can be less than half of the width of the upper source / drain trench 300BT along the first direction (X direction). Therefore, the first upper source / drain layer 310B can be spaced apart in the first direction (X direction). In one example, the first upper source / drain layer 310B located on one sidewall 300BT_S of the upper source / drain trench 300BT and the first upper source / drain layer 310B located on the other sidewall 300BT_S of the upper source / drain trench 300BT can be spaced apart in the first direction (X direction). In this implementation, the maximum width of the first upper source / drain layer 310B along the first direction (X direction) can be greater than the minimum spacing distance between the first upper source / drain layers 310B along the first direction (X direction). That is, the maximum width of the first upper source / drain layer 310B along the first direction (X direction) may be greater than the minimum width of the second upper source / drain layer 320B along the first direction (X direction).

[0174] Optionally, the first upper source / drain layers 310B may contact each other, such as Fig. 9As shown. For example, the first upper source / drain layer 310B located on one sidewall 300BT_S of the upper source / drain trench 300BT and the first upper source / drain layer 310B located on the other sidewall 300BT_S of the upper source / drain trench 300BT may contact each other. Therefore, the first upper source / drain layer 310B may include a recess 310B_C recessed from the central portion of the upper source / drain pattern 300B in the third direction (Z direction).

[0175] The recess 310B_C may be a portion where one side of the first upper source / drain layer 310B located on one sidewall 300BT_S of the upper source / drain trench 300BT is connected to one side of the first upper source / drain layer 310B located on the other sidewall 300BT_S of the upper source / drain trench 300BT. The recess 310B_C may be located in the central portion of the upper source / drain pattern 300B. The recess 310B_C may have a rounded shape toward the central portion of the upper source / drain pattern 300B.

[0176] exist Figure 8 and Fig. 9 , the top surface 320B_U and the bottom surface 320B_B of the second upper source / drain layer 320B are shown to have a convex shape, but the present disclosure is not limited thereto. For example, at least one of the top surface 320B_U and the bottom surface 320B_B of the second upper source / drain layer 320B may have a convex shape. In addition, as Figure 7 As shown in the implementation mode of FIG. 1 , the top surface 300B_U of the upper source / drain pattern 300B may be located at a higher level than the top surface of the topmost upper channel pattern 140B, and the bottom surface 300B_B of the upper source / drain pattern 300B may be located at a lower level than the top surface of the intermediate dielectric isolation structure MDI. As another example, the top surface 300B_U of the upper source / drain pattern 300B may be located at a higher level than the top surface of the topmost upper channel pattern 140B, and the bottom surface 300B_B of the upper source / drain pattern 300B may be located at substantially the same level as the top surface of the intermediate dielectric isolation structure MDI. In another example, a top surface 300B_U of the upper source / drain pattern 300B may be located at substantially the same level as a top surface of the topmost upper channel pattern 140B, and a bottom surface 300B_B of the upper source / drain pattern 300B may be located at a lower level than a top surface of the middle dielectric isolation structure MDI.

[0177] Fig.10 and Fig.11 is a diagram showing the semiconductor device corresponding to Figure 2 A cross-sectional view of area A1.

[0178] Fig.10 and Fig.11 The implementation shown is similar to Figures 1 to 5 The implementations shown are substantially the same and will therefore be described with respect to the differences.

[0179] In the present implementation, the shape of the upper source / drain pattern 300B is different from the previous implementation, and will be described below.

[0180] The side surface 310B_S of the first upper source / drain layer 310B may include a plurality of inclined surfaces inclined at a predetermined angle from the top surface of the substrate 101. For example, the first upper source / drain layer 310B may include a first inclined surface 310B_P1 that narrows in width along the first direction (X direction) as it moves away from the top surface of the substrate 101, and a second inclined surface 310B_P2 that widens in width along the first direction (X direction) as it moves away from the top surface of the substrate 101.

[0181] In this implementation, the first inclined surface 310B_P1 and the second inclined surface 310B_P2 of the first upper source / drain layer 310B may have different inclinations. For example, the first inclined surface 310B_P1 of the first upper source / drain layer 310B may be a side surface inclined at a predetermined angle to the top surface of the substrate 101 in one direction. In addition, the second inclined surface 310B_P2 of the first upper source / drain layer 310B may be a side surface inclined at a predetermined angle to the top surface of the substrate 101 in a different direction.

[0182] Therefore, the width of the first upper source / drain layer 310B along the first direction (X direction) may gradually increase from the upper and lower portions of the upper source / drain trench 300BT toward the central portion. In one example, the first width W1 of the central portion of the first upper source / drain layer 310B along the first direction (X direction) may be greater than the width of the top of the first upper source / drain layer 310B along the first direction (X direction) and the width of the bottom of the first upper source / drain layer 310B along the first direction (X direction). That is, the side 310B_S of the first upper source / drain layer 310B may have a convex shape from the sidewall 300BT_S of the upper source / drain trench 300BT. In one example, the first width W1 of the central portion of the first upper source / drain layer 310B along the first direction (X direction) may be equal to or greater than about 10nm and less than about 13nm. Within this range, the first upper source / drain layer 310B may include a plurality of inclined surfaces. Here, the first width W1 of the central portion of the first upper source / drain layer 310B along the first direction (X direction) may be the maximum width of the first upper source / drain layer 310B along the first direction (X direction). That is, according to the implementation, the first width W1 may represent the width of a portion where the first inclined surface 310B_P1 of the first upper source / drain layer 310B and the second inclined surface 310B_P2 of the first upper source / drain layer 310B meet along the first direction (X direction). The rest of the description of the first upper source / drain layer 310B is the same as Figures 1 to 5 The description of the implementation manner of the first upper source / drain layer 310B is substantially the same and thus will be omitted.

[0183] In this implementation, the second upper source / drain layer 320B may be located between the first upper source / drain layers 310B. The second upper source / drain layer 320B may fill the remaining portion after the first upper source / drain layer 310B is formed in the upper source / drain trench 300BT.

[0184] For example, Fig.10As shown, the side of the second upper source / drain layer 320B may have a shape complementary to the side of the first upper source / drain layer 310B. For example, the side of the second upper source / drain layer 320B may include a plurality of inclined surfaces corresponding to the first inclined surface 310B_P1 and the second inclined surface 310B_P2 of the first upper source / drain layer 310B. Therefore, the width of the second upper source / drain layer 320B along the first direction (X direction) may gradually decrease from the upper and lower parts of the upper source / drain trench 300BT toward the central part. In this case, the fourth width W4 of the central part of the second upper source / drain layer 320B along the first direction (X direction) may be the minimum width of the second upper source / drain layer 320B along the first direction (X direction). The description of the second upper source / drain layer 320B is the same as Figures 1 to 5 The description of the implementation manner of the second upper source / drain layer 320B is substantially the same and thus will be omitted.

[0185] Alternatively, if Fig.11 As shown, the second upper source / drain layer 320B may be located on the first upper source / drain layer 310B. Specifically, the second upper source / drain layer 320B may be conformally located on the first inclined surface 310B_P1 and the second inclined surface 310B_P2 of the first upper source / drain layer 310B. That is, the second upper source / drain layer 320B may be located on each of the first inclined surface 310B_P1 and the second inclined surface 310B_P2 of the first upper source / drain layer 310B. In this case, the second upper source / drain layer 320B located on one side and the second upper source / drain layer 320B located on the other side may be spaced apart in the first direction (X direction), but the present disclosure is not limited thereto. For example, the second upper source / drain layer 320B located on one side and the second upper source / drain layer 320B located on the other side may be connected to each other to form a whole.

[0186] In this implementation, the contact structure 180 may be located on the upper source / drain pattern 300B. The contact structure 180 may be electrically connected to the upper source / drain pattern 300B through the interlayer insulating layer 190. For example, Fig.10 As shown, the contact structure 180 may be positioned so that the upper source / drain pattern 300B is recessed to a predetermined depth. For example, the contact structure 180 may protrude within the second upper source / drain layer 320B. Fig.11As shown, the contact structure 180 may be located on the top surface of the second upper source / drain layer 320B. For example, the contact structure 180 may be located on the top surface of the second upper source / drain layer 320B located on one side and on the top surface of the second upper source / drain layer 320B located on the other side. In this case, even when the second upper source / drain layer 320B located on one side and the second upper source / drain layer 320B located on the other side are spaced apart in the first direction (X direction), the second upper source / drain layer 320B located on one side and the other side may be electrically connected by the contact structure 180.

[0187] The contact structure 180 may have an inclined side surface depending on the aspect ratio so that the width of the lower portion is narrower than the width of the upper portion, but the present disclosure is not limited thereto. The contact structure 180 according to this implementation may include a contact electrode 186, a first barrier layer 184 surrounding the contact electrode 186, and a first silicide film 182 located between the first barrier layer 184 and the upper source / drain pattern 300B. The description of the contact structure 180 according to this implementation is similar to that of Figures 1 to 5 The description of the implementation of the contact structure 180 is substantially the same and thus will be omitted.

[0188] Fig.12 Is the semiconductor device corresponding to Figure 2 A cross-sectional view of area A1.

[0189] Fig.12 The implementation shown in Fig.11 The implementations shown in are substantially the same and therefore will not be described, but will be described in terms of the differences.

[0190] The present embodiment is different from the previous embodiment in that a dummy source / drain pattern 400B is included, which will be described below.

[0191] The semiconductor device 100 includes a substrate 101, an active pattern 105 located on the substrate 101, a plurality of channel patterns 140 located on the active pattern 105, an intermediate dielectric isolation structure MDI located between the plurality of lower channel patterns 140A and the plurality of upper channel patterns 140B, a field insulation layer 110 located on the substrate 101, a gate structure 160 located on the active pattern 105, a lower source / drain pattern 300A and a dummy source / drain pattern 400B located on at least one side of the gate structure 160, and a blocking structure 170 located between the lower source / drain pattern 300A and the dummy source / drain pattern 400B.

[0192] Furthermore, in the semiconductor device 100 according to the implementation, the dummy source / drain pattern 400B may include a first dummy source / drain pattern 410B and a second dummy source / drain pattern 420B.

[0193] The dummy source / drain pattern 400B may be located on the lower source / drain pattern 300A. The dummy source / drain pattern 400B may be spaced apart from the lower source / drain pattern 300A in the third direction (Z direction). For example, the blocking structure 170 may be located between the dummy source / drain pattern 400B and the lower source / drain pattern 300A, and the dummy source / drain pattern 400B and the lower source / drain pattern 300A may be spaced apart by the blocking structure 170. Therefore, the dummy source / drain pattern 400B and the lower source / drain pattern 300A may be electrically insulated.

[0194] The dummy source / drain pattern 400B may be located at least one side of the upper gate structure 160B. For example, the dummy source / drain pattern 400B may be located at opposite sides of the upper gate structure 160B. The dummy source / drain pattern 400B may be connected to the plurality of upper channel patterns 140B.

[0195] The dummy source / drain pattern 400B may be located in the dummy source / drain trench 400BT. For example, the dummy source / drain pattern 400B may be located on one side and the other side of the dummy source / drain trench 400BT, respectively. The bottom surface of the dummy source / drain trench 400BT may be defined by the blocking structure 170, but is not limited thereto. The sidewall 400BT_S of the dummy source / drain trench 400BT may be defined by the plurality of upper channel patterns 140B and the plurality of upper gate structures 160B.

[0196] In this implementation, the dummy source / drain patterns 400B may be spaced apart in the first direction (X direction). For example, the dummy source / drain pattern 400B located on one side of the dummy source / drain trench 400BT and the dummy source / drain pattern 400B located on the other side of the dummy source / drain trench 400BT may be spaced apart in the first direction (X direction).

[0197] The dummy source / drain pattern 400B may include a first dummy source / drain pattern 410B and a second dummy source / drain pattern 420B.

[0198] The side of the first dummy source / drain pattern 410B may include a plurality of inclined surfaces inclined at a predetermined angle to the top surface of the substrate 101. For example, the first dummy source / drain pattern 410B may include a first inclined surface 410B_P1 and a second inclined surface 410B_P2, the first inclined surface 410B_P1 narrows in width along the first direction (X direction) as it moves away from the top surface of the substrate 101, and the second inclined surface 410B_P2 widens in width along the first direction (X direction) as it moves away from the top surface of the substrate 101. The first inclined surface 410B_P1 and the second inclined surface 410B_P2 of the first dummy source / drain pattern 410B may have different inclinations. Therefore, the width of the first dummy source / drain pattern 410B along the first direction (X direction) may gradually increase from the upper and lower portions of the dummy source / drain trench 400BT toward the central portion. The side of the first dummy source / drain pattern 410B may have a convex shape from the sidewall 400BT_S of the dummy source / drain trench 400BT.

[0199] According to the implementation, the second dummy source / drain pattern 420B may be located on the first dummy source / drain pattern 410B. Specifically, the second dummy source / drain pattern 420B may be conformally located on the first inclined surface 410B_P1 and the second inclined surface 410B_P2 of the first dummy source / drain pattern 410B. That is, the second dummy source / drain pattern 420B may be located on the first inclined surface 410B_P1 and the second inclined surface 410B_P2 of the corresponding first dummy source / drain pattern 410B. In this case, the second dummy source / drain pattern 420B located on one side and the second dummy source / drain pattern 420B located on the other side may be spaced apart in the first direction (X direction).

[0200] The contact structure 180 according to the implementation can be electrically connected to the lower source / drain pattern 300A through the interlayer insulating layer 190 and the barrier structure 170. The contact structure 180 can be located on the top surface of the second lower source / drain layer 320A. For example, the contact structure 180 can be positioned so that the lower source / drain pattern 300A is recessed to a predetermined depth. For example, the contact structure 180 can protrude within the second lower source / drain layer 320A.

[0201] In this implementation, the contact structure 180 may extend in the third direction (Z direction) between the dummy source / drain patterns 400B. The interlayer insulating layer 190 may be located between the contact structure 180 and the dummy source / drain patterns 400B. Therefore, the contact structure 180 and the dummy source / drain patterns 400B may not contact each other, and the contact structure 180 and the dummy source / drain patterns 400B may be electrically insulated from each other.

[0202] The contact structure 180 may have an inclined side surface depending on the aspect ratio so that the width of the lower portion is narrower than the width of the upper portion, but is not limited thereto. The contact structure 180 according to this implementation may include a contact electrode 186, a first barrier layer 184 surrounding the contact electrode 186, and a first silicide film 182 between the first barrier layer 184 and the lower source / drain pattern 300A. The description of the contact structure 180 according to this implementation is the same as that of Fig.11 The description of the implementation of the contact structure 180 is substantially the same and thus will be omitted.

[0203] In the following, further reference will be made to Figures 13 to 20 Describe semiconductor devices.

[0204] Fig.13 is the semiconductor device corresponding to the Figure 1 A cross-sectional view of the area taken along line III-III'.

[0205] Fig.13 The implementation shown in Figures 1 to 5 The implementations shown in are substantially the same and therefore will not be described, but will be described in terms of the differences.

[0206] In the present implementation, the shape of the lower source / drain pattern 300A is different from the previous implementation, and will be described below.

[0207] The lower source / drain pattern 300A of the semiconductor device 100 according to this implementation may include a portion located between the gate spacers 164 and a protrusion 300A_E located on the gate spacers 164 .

[0208] The protrusion 300A_E may be located at the top of the lower source / drain pattern 300A. The protrusion 300A_E may protrude from the center portion of the lower source / drain pattern 300A along the second direction (Y direction). That is, the protrusion 300A_E may protrude from the center portion of the lower source / drain pattern 300A toward the interlayer insulating layer 190. This may be due to the following process characteristics, in which the lower sacrificial layer 120A ( Fig.21 In the process of forming the lower source / drain trench 300AT by removing at least a portion of the plurality of lower channel patterns 140A and at least a portion of the first barrier pattern 171, the exposed portion at the top of the first barrier pattern 171 and the exposed portion at the top of the gate spacer 164 are removed together.

[0209] In this implementation, the gate spacer 164 may cover a portion of the side of the lower source / drain pattern 300A. For example, the gate spacer 164 may cover a portion of the side of the lower source / drain pattern 300A and may not cover the side of the protrusion 300A_E.

[0210] In this implementation, the first barrier pattern 171 may be located on the side of the gate spacer 164, on the side of the protrusion 300A_E, and on the top surface of the lower source / drain pattern 300A. That is, the first barrier pattern 171 may cover the side of the protrusion 300A_E. The first barrier pattern 171 may be located between the protrusion 300A_E and the interlayer insulating layer 190.

[0211] Fig.14 and Fig.15 Is the semiconductor device corresponding to Figure 2 A cross-sectional view of area A1.

[0212] Fig.14 and Fig.15 The implementation shown in Figures 1 to 5 The implementations shown in are substantially the same and therefore will not be described, but will be described in terms of the differences.

[0213] The present implementation differs from the previous implementation in that an air gap AG is included under the upper source / drain pattern 300B, which will be described below.

[0214] The semiconductor device 100 according to this implementation may further include an air gap AG between the blocking structure 170 and the upper source / drain pattern 300B.

[0215] For example, Fig.14 As shown, the air gap AG may be located between the second barrier pattern 172 and the second upper source / drain layer 320B. The air gap AG may be defined by the inner wall of the first barrier pattern 171, the top surface of the second barrier pattern 172, and the bottom surface of the second upper source / drain layer 320B. In this case, the top surface of the second barrier pattern 172 may be located at a level lower than the top surface 171_U of the first barrier pattern 171. That is, the top surface of the second barrier pattern 172 may be located closer to the top surface of the substrate 101 than the top surface 171_U of the first barrier pattern 171. Here, the top surface 171_U of the first barrier pattern 171 may refer to the top surface of the portion of the first barrier pattern 171 located between the intermediate dielectric isolation structure MDI and the second barrier pattern 172.

[0216] Alternatively, if Fig.15As shown, the air gap AG may be located between the first barrier pattern 171 and the second upper source / drain layer 320B. In this case, the barrier structure 170 may not include the second barrier pattern 172. That is, the air gap AG may be defined by the inner bottom surface and inner wall of the first barrier pattern 171 and the bottom surface of the second upper source / drain layer 320B.

[0217] In this implementation, the air gap AG may include a gas including air or a material used in a manufacturing process of the semiconductor device 100. In this implementation, the air gap AG may be formed by removing a portion or all of the second barrier pattern 172 in a process of forming the first barrier pattern 171 and the second barrier pattern 172 on the lower source / drain pattern 300A, and then removing at least a portion of the first barrier pattern 171 and the second barrier pattern 172 to form the barrier structure 170.

[0218] In this implementation, when the air gap AG is located on the blocking structure 170, the bottom surface of the second upper source / drain layer 320B may have a convex shape toward the substrate 101. For example, the bottom surface of the second upper source / drain layer 320B may have a rounded shape toward the substrate 101. This is because the second upper source / drain layer 320B may be formed in a portion of the space of the air gap AG in a process of forming the second upper source / drain layer 320B by using an epitaxial growth process using the plurality of upper channel patterns 140B as seeds.

[0219] Fig.16 and Fig.17 is the semiconductor device corresponding to the Figure 1 A cross-sectional view of the area taken along line I-I'.

[0220] Fig.16 and Fig.17 The implementation shown in Figures 1 to 5 The implementations shown in are substantially the same and thus will not be described, but will be described in terms of the differences.

[0221] This implementation differs from the previous implementation in that an inner gate spacer 168 is also included, which will be described below.

[0222] The semiconductor device 100 according to this implementation may further include an inner gate spacer 168 between the gate structure 160 and the source / drain pattern 300 .

[0223] The inner gate spacer 168 may be located on the side of the gate structure 160. The inner gate spacer 168 may be located between the gate structure 160 and the source / drain pattern 300. For example, Fig.16As shown, the inner gate spacer 168 may be located between the lower gate structure 160A and the lower source / drain pattern 300A, and may not be located between the upper gate structure 160B and the upper source / drain pattern 300B. Fig.17 As shown, the inner gate spacer 168 may be located between the lower gate structure 160A and the lower source / drain pattern 300A and between the upper gate structure 160B and the upper source / drain pattern 300B. The inner gate spacer 168 may not be located on the side of the main gate structure 160M.

[0224] The inner gate spacer 168 may be positioned side by side with the gate structure 160 between the plurality of channel patterns 140 adjacent in the third direction (Z direction). The inner gate spacer 168 may be in contact with the gate insulating films 162A and 162B. The gate structure 160 is spaced apart from the source / drain pattern 300 by the inner gate spacer 168 to be electrically isolated. The side of the inner gate spacer 168 facing the gate structure 160 may have a rounded shape that is convex toward the gate structure 160, but is not limited thereto. The inner gate spacer 168 may include silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant film, or a combination thereof.

[0225] Fig.18 is the semiconductor device corresponding to the Figure 1 A cross-sectional view of the area taken along line I-I'. Fig.19 is the semiconductor device corresponding to the Figure 1 A cross-sectional view of the area taken along line II-II'. Fig. 20 is the semiconductor device corresponding to the Figure 1 A cross-sectional view of the area taken along line III-III'.

[0226] Figures 18 to 20 The implementation shown in Figures 1 to 5 The implementations shown in are substantially the same and therefore will not be described, but will be described in terms of the differences.

[0227] The present implementation differs from the previous implementation in that it also includes a through-via structure 220, which will be described below.

[0228] The semiconductor device 100p may further include an upper insulating layer 192 on the contact structure 180, an upper wiring structure on the upper insulating layer 192, a lower wiring structure under the substrate 101, and a through via structure 220 between the source / drain pattern 300 and the lower wiring structure.

[0229] The upper insulating layer 192 may be located on the top surface of the capping layer 166, the top surface of the interlayer insulating layer 190, and the top surface of the contact structure 180. The upper insulating layer 192 may include the same material as the interlayer insulating layer 190. The upper insulating layer 192 may include, for example, silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON) and at least one of a low dielectric constant material.

[0230] The upper wiring structure may be located on and in the upper insulating layer 192. The upper wiring structure may include an upper wiring ML, an upper via VA, and an upper wiring insulating layer 193.

[0231] The upper wiring ML may be located on the upper insulating layer 192. The upper wiring ML may include metal (e.g., copper). The upper wiring ML may be electrically connected to the contact structure 180 through the upper via VA. The upper wiring insulating layer 193 may cover the upper wiring ML, and the upper wiring ML may be located within the upper wiring insulating layer 193. The upper wiring insulating layer 193 may include, for example, silicon oxide (SiO 2 ), at least one of silicon nitride (SiN), silicon nitride oxide (SiON) and a low dielectric constant film.

[0232] The lower wiring structure may be located on the bottom surface of the substrate 101. The lower wiring structure may be, for example, a power delivery network that supplies a voltage (eg, a power supply voltage) to the lower source / drain pattern 300A.

[0233] The lower wiring structure may include a lower wiring 195 and a lower wiring insulating layer 196 .

[0234] The lower wiring 195 may be located on the bottom surface of the substrate 101. The lower wiring 195 may include a metal (e.g., copper). The lower wiring 195 may be electrically connected to the through-via structure 220. The lower wiring insulating layer 196 may be located on the bottom surface of the substrate 101. The lower wiring insulating layer 196 may cover the lower wiring 195, and the lower wiring 195 may be located within the lower wiring insulating layer 196. The lower wiring insulating layer 196 may include, for example, silicon oxide (SiO 2 ), at least one of silicon nitride (SiN), silicon nitride oxide (SiON) and a low dielectric constant film.

[0235] The semiconductor device 100p according to the implementation may further include a bottom dielectric isolation structure BDI between the active patterns 105. The bottom dielectric isolation structure BDI may include substantially the same material as the middle dielectric isolation structure MDI, but is not limited thereto.

[0236] exist Fig.18 and Fig.19, the bottom dielectric isolation structure BDI is shown as being located between the active patterns 105, but is not limited thereto, and the bottom dielectric isolation structure BDI may also be located between the active pattern 105 and the lower gate structure 160A. Optionally, the semiconductor device 100p may not include the bottom dielectric isolation structure BDI. In this case, the substrate 101 may be made of an insulating substrate including an insulating material, and the active pattern 105 may be formed of an insulating pattern including an insulating material.

[0237] The through-path structure 220 may be located between the lower source / drain pattern 300A and the lower wiring structure. The through-path structure 220 may be connected to at least one lower source / drain pattern 300A. The through-path structure 220 may extend from the lower source / drain pattern 300A to the lower wiring structure in a third direction (Z direction). The top surface of the through-path structure 220 may be connected to the lower source / drain pattern 300A. In this implementation, the lower source / drain pattern 300A and the lower wiring structure may be electrically connected to each other via the through-path structure 220. That is, a voltage (e.g., a power supply voltage) may be applied to the lower source / drain pattern 300A from the lower wiring structure via the through-path structure 220.

[0238] The through via structure 220 may include a through via 226 , a second barrier layer 224 surrounding the through via 226 , and a second silicide film 222 between the second barrier layer 224 and the lower source / drain pattern 300A.

[0239] The through via 226 may include, for example, at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material. The second barrier layer 224 may include, for example, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN).

[0240] The second silicide film 222 may surround the portion of the through via 226 that protrudes into the lower source / drain pattern 300A. The second silicide film 222 may include a metal silicide. For example, the second silicide film 222 may include at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide. In an implementation, the number and arrangement of the conductive layers configuring the through via structure 220 may be changed. In some implementations, the second barrier layer 224 and / or the second silicide film 222 may be omitted.

[0241] Although not shown, the through via structure 220 may further include an insulating pad on an outer surface of the through via structure 220 for insulation from the substrate 101 .

[0242] In the following, reference will be made to Figure 21 to Figure 53A method of manufacturing a semiconductor device according to an implementation is described.

[0243] Figure 21 to Figure 53 is a cross-sectional view showing an example method of manufacturing a semiconductor device. In an implementation, Fig.21 , Fig.24 , Fig. 27 , Fig.30 , Fig.32 , Fig.34 , Fig.37 , Fig.39 , Fig.42 , Fig.44 , Fig.47 , Fig.50 and Fig.52 corresponds to along Figure 1 A cross-sectional view of a region taken along line II' illustrates a method of manufacturing a semiconductor device. Fig. 22 , Fig.25 , Fig.28 , Fig.35 , Fig.40 , Fig.48 , Fig.51 and Fig.53 corresponds to along Figure 1 A cross-sectional view of a region taken along line II-II' illustrates a method of manufacturing a semiconductor device according to an implementation. Fig.23 , Fig.26 , Fig.29 , Fig.31 , Fig.33 , Fig.36 , Fig.38 , Fig.41 , Fig.46 and Fig.49 corresponds to along Figure 1 A cross-sectional view of a region taken along line III-III' illustrates a method of manufacturing a semiconductor device according to an implementation. Fig.43 yes Fig.42 An enlarged cross-sectional view of area A2. Fig.45 yes Fig.44 An enlarged cross-sectional view of area A2 in FIG.

[0244] like Figure 21 to Figure 23 As shown, a sacrificial layer 120 , a plurality of lower channel patterns 140A, a middle semiconductor pattern 140S, and a plurality of upper channel patterns 140B may be formed on a substrate 101 , and a sacrificial gate structure 200 may be formed.

[0245] First, a sacrificial layer 120, the plurality of lower channel patterns 140A, the middle semiconductor pattern 140S, and the plurality of upper channel patterns 140B are formed on a substrate 101. The substrate 101 may be silicon on insulator (SOI) or bulk silicon. Alternatively, the substrate 101 may be a silicon substrate, or may include other materials such as silicon germanium (SiGe), silicon germanium on insulator (SGOI), indium antimonide, lead telluride compounds, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto.

[0246] The sacrificial layer 120 may be made of a material having an etching selectivity to the plurality of lower channel patterns 140A, the middle semiconductor pattern 140S, and the plurality of upper channel patterns 140B. The plurality of lower channel patterns 140A, the middle semiconductor pattern 140S, and the plurality of upper channel patterns 140B may include a material different from that of the sacrificial layer 120. For example, the plurality of lower channel patterns 140A, the middle semiconductor pattern 140S, and the plurality of upper channel patterns 140B may include silicon (Si), and the sacrificial layer 120 may include silicon germanium (SiGe), but the present disclosure is not limited thereto.

[0247] The sacrificial layer 120, the plurality of lower channel patterns 140A, and the plurality of upper channel patterns 140B may be formed by performing an epitaxial growth process using the substrate 101 as a seed. The number of the plurality of lower channel patterns 140A, the middle semiconductor patterns 140S, and the plurality of upper channel patterns 140B alternately stacked with the sacrificial layer 120 may vary in implementation.

[0248] Next, portions of the sacrificial layer 120 , portions of the plurality of lower channel patterns 140A, portions of the middle semiconductor pattern 140S, portions of the plurality of upper channel patterns 140B, and portions of the substrate 101 are removed to form an active structure, and a field insulating layer 110 may be formed.

[0249] The active structure may include alternately stacked sacrificial layers 120, the plurality of lower channel patterns 140A, the middle semiconductor patterns 140S, and the plurality of upper channel patterns 140B. In addition, the active structure may further include an active pattern 105 formed so that at least a portion of the substrate 101 is removed and protrudes from the top surface of the substrate 101. The active structure may extend in a first direction (X direction). The active structure may be spaced apart in a second direction (Y direction). Therefore, the opposite sides of the middle sacrificial layer 120B and the middle semiconductor pattern 140S may be exposed.

[0250] The field insulation layer 110 may be formed on a portion of the substrate 101 from which at least a portion of the substrate 101 has been removed. Thus, the active pattern 105 may be located on a side of the field insulation layer 110. A process of forming the field insulation layer 110 may include embedding an insulating material and then recessing the insulating material so that the active pattern 105 protrudes. Thus, a top surface of the field insulation layer 110 may be located at a lower level than a top surface of the active pattern 105, but the present disclosure is not limited thereto.

[0251] Next, a sacrificial gate structure 200 may be formed on the active structure. The sacrificial gate structure 200 may include a first sacrificial gate electrode 202 and a second sacrificial gate electrode 205 sequentially located on the plurality of upper channel patterns 140B and an initial capping layer 206. The first sacrificial gate electrode 202 may include, for example, silicon oxide (SiO 2 ), but the present disclosure is not limited thereto. The second sacrificial gate electrode 205 may include, for example, polysilicon, but the present disclosure is not limited thereto. The initial capping layer 206 may include, for example, silicon nitride, but the present disclosure is not limited thereto. Therefore, the opposite sides of the intermediate sacrificial layer 120B and the opposite sides of the intermediate semiconductor pattern 140S located between the sacrificial gate structures 200 may be exposed.

[0252] like Figure 24 to Figure 26 As shown, an intermediary dielectric isolation structure MDI may be formed, and a gate spacer 164 may be formed to cover the top surface and side surfaces of the sacrificial gate structure 200 and the active structure.

[0253] First, an intermediate dielectric isolation structure MDI can be formed by removing the intermediate sacrificial layer 120B and the intermediate semiconductor pattern 140S through the exposed intermediate sacrificial layer 120B and the relative sides of the intermediate semiconductor pattern 140S. The intermediate sacrificial layer 120B and the intermediate semiconductor pattern 140S have etching selectivity relative to the lower sacrificial layer 120A, the upper sacrificial layer 120C, the multiple lower channel patterns 140A and the multiple upper channel patterns 140B, and can therefore be selectively removed. The intermediate dielectric isolation structure MDI can be formed by filling the intermediate insulating pattern 210 in the area where the intermediate sacrificial layer 120B and the intermediate semiconductor pattern 140S have been removed. The intermediate insulating pattern 210 may include, for example, silicon oxide or silicon nitride. However, this method is not limited thereto. For example, the intermediate semiconductor pattern 140S may not be removed.

[0254] Subsequently, gate spacers 164 may be formed to cover opposite sidewalls and a top surface of sacrificial gate structure 200. Gate spacers 164 may be formed to have a uniform thickness along the top surface and side surfaces of sacrificial gate structure 200 and the active structure. Gate spacers 164 may cover a top surface of field insulation layer 110.

[0255] like Figure 27 to Figure 29 As shown, the first barrier pattern 171 may be formed by removing at least a portion of the gate spacer 164 and then removing portions of the plurality of upper channel patterns 140B, portions of the upper sacrificial layer 120C, and portions of the intermediate dielectric isolation structure MDI.

[0256] First, at least a portion of the gate spacer 164 may be removed. The process of removing at least a portion of the gate spacer 164 may be performed using a dry etching process. This may result in the removal of portions of the gate spacer 164 located on the top surface of the field insulation layer 110, on the top surface of the sacrificial gate structure 200, and on the top surface of the active structure. In this case, portions of the gate spacer 164 present on the side of the sacrificial gate structure 200 may be removed together, resulting in a reduced thickness.

[0257] Then, by using the sacrificial gate structure 200 as a mask, an upper recess region RCU may be formed by removing portions of the exposed upper sacrificial layer 120C, portions of the plurality of upper channel patterns 140B, and portions of the intermediate dielectric isolation structure MDI.

[0258] The upper recessed area RCU may extend through the exposed upper sacrificial layer 120C and the plurality of upper channel patterns 140B. The upper recessed area RCU may extend through at least a portion of the intermediate dielectric isolation structure MDI. In this implementation, in the cross-section along the first direction (X direction) and the third direction (Z direction), the lower width and the upper width of the upper recessed area RCU may be substantially equal, but the present disclosure is not limited thereto. For example, depending on the aspect ratio, the upper recessed area RCU may have an inclined side whose lower width is narrower than the upper width. Here, the upper recessed area RCU may refer to an area where a blocking structure 170 and an upper source / drain pattern 300B are formed in a later process.

[0259] Next, a first barrier pattern 171 may be formed to cover the sacrificial gate structure 200, the gate spacer 164, the active structure, and the upper recessed region RCU. The first barrier pattern 171 may be formed with a constant thickness along the top surface and side surfaces of the sacrificial gate structure 200, the top surface and side surfaces of the gate spacer 164, the top surface and side surfaces of the active structure, the side and bottom surfaces of the upper recessed region RCU, and the top surface of the field insulating layer 110. The first barrier pattern 171 may be formed along the top surface and side surfaces of the intermediate dielectric isolation structure MDI exposed by the upper recessed region RCU. The first barrier pattern 171 may include silicon oxide or silicon nitride, etc.

[0260] like Fig.30 and Fig.31As shown, the lower source / drain trench 300AT may be formed by removing a portion of the first barrier pattern 171 and removing portions of the plurality of lower channel patterns 140A, portions of the lower sacrificial layer 120A, and portions of the intermediate dielectric isolation structure MDI.

[0261] First, a portion of the first barrier pattern 171 located on the bottom surface of the upper recessed region RCU may be etched. The process of removing the first barrier pattern 171 may be performed using a dry etching process, but is not limited thereto. Subsequently, a lower source / drain trench 300AT extending in a third direction (Z direction) may be formed by removing a portion of the first barrier pattern 171 and removing at least a portion of the exposed intermediate dielectric isolation structure MDI, at least a portion of the plurality of lower channel patterns 140A, at least a portion of the lower sacrificial layer 120A, and at least a portion of the active pattern 105. The lower source / drain trench 300AT may be formed in the space between the opposing gate spacers 164.

[0262] In this implementation, if Fig.31 As shown, in the cross-sections along the second direction (Y direction) and the third direction (Z direction), the lower source / drain trench 300AT may have a trapezoidal shape that increases in width as it approaches the top surface of the substrate 101. That is, in the cross-sections along the second direction (Y direction) and the third direction (Z direction), the lower source / drain trench 300AT may include an inclined surface inclined to the top surface of the substrate 101. This may be due to the process characteristics in which the lower source / drain pattern 300A is formed in the space between the gate spacers 164 facing each other.

[0263] However, the present disclosure is not limited thereto, and in one example, the width of the lower source / drain pattern 300A along the second direction (Y direction) may be constant.

[0264] like Fig.32 and Fig.33 As shown, a lower source / drain pattern 300A may be formed in the lower source / drain trench 300AT.

[0265] The lower source / drain pattern 300A may be an epitaxial pattern formed by a selective epitaxial growth process using the active pattern 105 and the plurality of lower channel patterns 140A as seeds. Specifically, a first lower source / drain layer 310A may be formed along the inner wall and bottom surface of the lower source / drain trench 300AT, and a second lower source / drain layer 320A may be formed to fill the lower source / drain trench 300AT on the first lower source / drain layer 310A. Therefore, the lower source / drain pattern 300A may be in contact with the active pattern 105 and the plurality of lower channel patterns 140A.

[0266] In this implementation, the top surface of the lower source / drain pattern 300A may be located at a higher level than the top surface of the topmost lower sacrificial layer 120A. That is, the top surface of the lower source / drain pattern 300A may be positioned farther from the top surface of the substrate 101 than the top surface of the topmost lower sacrificial layer 120A. Therefore, a portion of the side of the lower source / drain pattern 300A may contact the intermediate dielectric isolation structure MDI. That is, the top surface of the lower source / drain pattern 300A may be located at a higher level than the bottom surface of the intermediate dielectric isolation structure MDI. However, the present disclosure is not limited thereto, and the top surface of the lower source / drain pattern 300A may be located at substantially the same level as the top surface of the topmost lower sacrificial layer 120A.

[0267] like Figure 34 to Figure 36 As shown, the first barrier pattern 171 may be further formed on the top surface and the side surface of the sacrificial gate structure 200 and within the upper recess region RCU.

[0268] Specifically, the first barrier pattern 171 may be further formed on the top surface of the lower source / drain pattern 300A exposed by the upper recessed region RCU, the side surfaces of the plurality of upper channel patterns 140B, and the side surfaces of the upper sacrificial layer 120C. For example, the first barrier pattern 171 may be further formed by depositing an insulating material along the top surface of the lower source / drain pattern 300A, the side surfaces of the plurality of upper channel patterns 140B, and the side surfaces of the upper sacrificial layer 120C. Therefore, the top surface of the lower source / drain pattern 300A may be covered by the first barrier pattern 171. In this case, the first barrier pattern 171 may be formed together on the side surfaces of the gate spacer 164, the top surface of the initial capping layer 206, and the top surface of the field insulating layer 110, but the present disclosure is not limited thereto.

[0269] like Fig.37 and Fig.38 As shown, the second barrier pattern 172 may be formed in a portion of the space of the upper recess area RCU.

[0270] For example, the second barrier pattern 172 may be formed on the first barrier pattern 171 located in the upper recessed region RCU. Therefore, the bottom surface and the side surface of the second barrier pattern 172 may be surrounded by the first barrier pattern 171. The process of forming the second barrier pattern 172 may be formed by etching at least a portion of the insulating material layer after forming the insulating material layer in the upper recessed region RCU. In this case, the second barrier pattern 172 may be formed together with the first barrier pattern 171 located on the field insulating layer 110.

[0271] In this implementation, the top surface of the second barrier pattern 172 may be substantially the same as the top surface of the intermediate dielectric isolation structure MDI, but is not limited thereto. Figure 7 In an implementation of FIG. 1 , a top surface of the second barrier pattern 172 may be located at a lower level than a top surface of the middle dielectric isolation structure MDI.

[0272] In this implementation, the top surface of the second barrier pattern 172 is shown as being flat, but is not limited thereto, for example, the top surface of the second barrier pattern 172 may have a convex shape toward the substrate 101. This shape may be formed by forming an insulating material layer on the first barrier pattern 171 and then removing at least a portion of the insulating material layer. In this case, as in Fig.14 As in the implementation manner of FIG. 1 , a space in which an air gap can be formed can be provided.

[0273] In addition, it is described in the implementation that the second barrier pattern 172 is formed on the first barrier pattern 171, but the present disclosure is not limited thereto. Fig.15 As in the implementation of , such a shape may be formed by forming an insulating material layer on the first barrier pattern 171 and then removing at least a portion of the insulating material layer so that the insulating material layer is completely removed.

[0274] like Figure 39 to Figure 41 As shown, at least a portion of the first barrier pattern 171 may be removed to form the barrier structure 170 .

[0275] For example, a portion of the exposed first barrier pattern 171 may be removed. That is, a portion of the first barrier pattern 171 located on the top surface of the preliminary capping layer 206 and the side of the gate spacer 164 may be removed. In this case, a portion of the first barrier pattern 171 located on the lower source / drain pattern 300A is not exposed by the second barrier pattern 172 and may not be etched. Therefore, a barrier structure 170 including the first barrier pattern 171 and the second barrier pattern 172 located on the lower source / drain pattern 300A may be formed.

[0276] In this case, a portion of the first barrier pattern 171 located on the side of the gate spacer 164 may remain. Fig.41 As shown, the first barrier pattern 171 may remain on the side of the gate spacer 164. However, the present disclosure is not limited thereto, and a portion of the first barrier pattern 171 located on the side of the gate spacer 164 may be completely removed.

[0277] In this implementation, an upper source / drain trench 300BT may be formed by forming a blocking structure 170 in the upper recessed region RCU. The bottom surface of the upper source / drain trench 300BT may be defined by the blocking structure 170. The sidewalls of the upper source / drain trench 300BT may be defined by the plurality of upper channel patterns 140B and the upper sacrificial layer 120C.

[0278] like Fig.42 and Fig.43 As shown, the first upper source / drain layer 310B may be formed on the sidewall 300BT_S of the upper source / drain trench 300BT.

[0279] Specifically, the first upper source / drain layer 310B may be formed on the sidewalls 300BT_S of the upper source / drain trench 300BT by using the opposite sides of the plurality of upper channel patterns 140B as seeds. Therefore, the first upper source / drain layer 310B positioned along the sidewalls 300BT_S of the upper source / drain trench 300BT may contact the plurality of upper channel patterns 140B.

[0280] In this implementation, the first upper source / drain layer 310B may not cover at least a portion of the bottom surface 300BT_B of the upper source / drain trench 300BT. For example, the first upper source / drain layer 310B may not be located on the bottom surface 300BT_B of the upper source / drain trench 300BT. This may be due to the process characteristics of the first upper source / drain layer 310B being formed by using the opposite side of the plurality of upper channel patterns 140B as a seed. That is, unlike the lower source / drain pattern 300A (which is a pattern formed using the top surface of the active pattern 105 and the opposite side of the plurality of lower channel patterns 140A as a seed), the upper source / drain pattern 300B may be a pattern formed using only the opposite side of the plurality of upper channel patterns 140B as a seed. Therefore, the first upper source / drain layer 310B may not cover at least a portion of the bottom surface 300BT_B of the upper source / drain trench 300BT.

[0281] In this implementation, the first upper source / drain layer 310B may be in contact with the multiple upper channel patterns 140B and the upper gate structure 160B. The first upper source / drain layer 310B may overlap with the multiple upper channel patterns 140B and the upper gate structure 160B in a first direction (X direction). In one example, an edge of the first upper source / drain layer 310B may be aligned with a top surface of the topmost upper channel pattern 140B. In addition, the first upper source / drain layer 310B may not overlap with the intermediate dielectric isolation structure MDI and the gate spacer 164 in the first direction (X direction) and the second direction (Y direction). However, the present disclosure is not limited thereto, and an additional inner gate spacer 168 may be located between the first upper source / drain layer 310B and the upper gate structure 160B, as Fig.17 The implementation method is shown in the following figure.

[0282] In this implementation, the side surface 310B_S of the first upper source / drain layer 310B may have a convex shape from the side wall 300BT_S of the upper source / drain trench 300BT. In one example, the side surface 310B_S of the first upper source / drain layer 310B may include a rounded curved surface convex from the side wall 300BT_S of the upper source / drain trench 300BT.

[0283] Therefore, the width of the first upper source / drain layer 310B along the first direction (X direction) may gradually increase from the upper and lower portions of the first upper source / drain layer 310B toward the central portion. For example, the first width W1 of the central portion of the first upper source / drain layer 310B along the first direction (X direction) may be greater than the second width W2 of the upper portion of the first upper source / drain layer 310B along the first direction (X direction). In addition, the first width W1 of the central portion of the first upper source / drain layer 310B along the first direction (X direction) may be greater than the third width W3 of the lower portion of the first upper source / drain layer 310B along the first direction (X direction). In this case, the first width W1 of the central portion of the first upper source / drain layer 310B along the first direction (X direction) may be the maximum width of the first upper source / drain layer 310B along the first direction (X direction). In one example, a first width W1 of a central portion of the first upper source / drain layer 310B along the first direction (X direction) may be equal to or greater than about 0 nm and less than about 10 nm.

[0284] In addition, the first angle θ1 formed by the side 310B_S of the first upper source / drain layer 310B and the sidewall 300BT_S of the upper source / drain trench 300BT may be 0° to 90°. In one example, the first angle θ1 formed by the side 310B_S of the first upper source / drain layer 310B and the sidewall 300BT_S of the upper source / drain trench 300BT may be 80° to 90°. Within this range, when the second upper source / drain layer 320B is formed between the first upper source / drain layers 310B, the second upper source / drain layer 320B may be formed to completely fill the upper source / drain trench 300BT.

[0285] In this implementation, the side 310B_S of the first upper source / drain layer 310B is shown as being curved, but the present disclosure is not limited thereto, and the side 310B_S of the first upper source / drain layer 310B may vary within this range to have a convex shape from the sidewall 300BT_S of the upper source / drain trench 300BT. Figure 6 As shown in the implementation of FIG. 3 , the side surface 310B_S of the first upper source / drain layer 310B may further include a side surface extending in the third direction (Z direction). Fig.10 and Fig.11 In an implementation manner, the side surface 310B_S of the first upper source / drain layer 310B may include a plurality of inclined surfaces.

[0286] The first upper source / drain layer 310B may include a semiconductor material. For example, the first upper source / drain layer 310B may include a semiconductor material such as silicon (Si) or silicon germanium (SiGe).

[0287] In this implementation, the first upper source / drain layer 310B may include impurities. For example, when the second transistor structure is p-type, the first upper source / drain layer 310B may include p-type impurities. In one example, the first upper source / drain layer 310B may include B, V, In, Ga, Al, or a combination thereof.

[0288] like Figures 44 to 46 As shown, a second upper source / drain layer 320B may be formed between the first upper source / drain layers 310B.

[0289] Specifically, the second upper source / drain layer 320B may fill the portion remaining after the first upper source / drain layer 310B is formed in the upper source / drain trench 300BT. For example, the second upper source / drain layer 320B may be formed on the blocking structure 170 defining the bottom surface 300BT_B of the upper source / drain trench 300BT. Therefore, the side of the second upper source / drain layer 320B may be formed to have a shape complementary to the side of the first upper source / drain layer 310B. For example, the side 310B_S of the first upper source / drain layer 310B may be formed to have a convex shape from the sidewall 300BT_S of the upper source / drain trench 300BT, and the side of the second upper source / drain layer 320B may be formed to have a shape convex toward the central portion of the second upper source / drain layer 320B.

[0290] In this implementation, the top surface 320B_U of the second upper source / drain layer 320B may be located at the same level as the top surface of the topmost upper channel pattern 140B among the plurality of upper channel patterns 140B. In addition, the top surface 320B_U of the second upper source / drain layer 320B may include a flat portion. However, the present disclosure is not limited thereto, and the top surface 320B_U of the second upper source / drain layer 320B may be located at a higher level than the top surface of the topmost upper channel pattern 140B among the plurality of upper channel patterns 140B, such as Figure 7 In addition, as shown in Figure 8 and Fig. 9 In an implementation manner, a bottom surface of the second upper source / drain layer 320B may have a convex shape toward the substrate 101 .

[0291] The second upper source / drain layer 320B may include a semiconductor material. For example, the second upper source / drain layer 320B may include the same material as the first upper source / drain layer 310B. In one example, the first upper source / drain layer 310B and the second upper source / drain layer 320B may include a semiconductor material such as silicon (Si) or silicon germanium (SiGe).

[0292] In this case, the concentrations of the constituent materials of the first upper source / drain layer 310B and the second upper source / drain layer 320B may be different. For example, when the first upper source / drain layer 310B and the second upper source / drain layer 320B include silicon germanium (SiGe), the concentration of germanium (Ge) in the second upper source / drain layer 320B may be greater than the concentration of germanium (Ge) in the first upper source / drain layer 310B. In one example, the concentration of germanium (Ge) in the second upper source / drain layer 320B may be equal to or greater than 60at% and less than 70at%, but the present disclosure is not limited thereto. Within this range, when the second upper source / drain layer 320B is formed between the first upper source / drain layer 310B, the second upper source / drain layer 320B may include a top surface 320B_U and a flat portion of the bottom surface. However, the present disclosure is not limited thereto, as in Figure 8 and Fig. 9 In an implementation manner, the germanium (Ge) concentration of the second upper source / drain layer 320B may be less than 60 at %.

[0293] In this implementation, the first upper source / drain layer 310B and / or the second upper source / drain layer 320B may be doped with impurities. For example, when the first transistor structure is p-type, the first upper source / drain layer 310B and / or the second upper source / drain layer 320B may include p-type impurities. In one example, the first upper source / drain layer 310B and the second upper source / drain layer 320B may include B, C, In, Ga, Al, or a combination thereof. In this case, the material of the impurities contained in the first upper source / drain layer 310B may be different from the material of the impurities contained in the second upper source / drain layer 320B. Optionally, the concentration of the impurities doped in the first upper source / drain layer 310B may be different from the concentration of the impurities doped in the second upper source / drain layer 320B. In this case, the concentration of the p-type impurities doped into the second upper source / drain layer 320B may be less than the concentration of the p-type impurities doped into the first upper source / drain layer 310B, but the present disclosure is not limited thereto.

[0294] like Figure 47 to Figure 49As shown, first, an interlayer insulating layer 190 may be formed on the upper source / drain pattern 300B. Subsequently, by removing the sacrificial gate structure 200 and removing the upper sacrificial layer 120C and the lower sacrificial layer 120A, a lower gate trench LR may be formed between the plurality of channel patterns 140 and an upper gate trench UR may be formed between the gate spacers 164 and on the uppermost upper channel 140B. In some implementations, the processes of removing the sacrificial gate structure 200, the upper sacrificial layer 120C, and the lower sacrificial layer 120A may occur simultaneously.

[0295] like Fig.50 and Fig.51 As shown, gate insulating films 162A and 162B can be formed in the lower gate trench LR, and a main gate insulating film 162M can be formed in the upper gate trench UR, gate electrodes 165A and 165B and a main gate electrode 165M can be formed, and a capping layer 166 can be formed on the main gate electrode 165M.

[0296] like Fig.52 and Fig.53 As shown, after forming a contact hole penetrating the interlayer insulating layer 190 to expose the upper source / drain pattern 300B, a contact structure 180 electrically connected to the upper source / drain pattern 300B while filling the contact hole may be formed. The contact structure 180 may be electrically connected to the upper source / drain pattern 300B through the interlayer insulating layer 190. The contact structure 180 may include a contact electrode 186, a first barrier layer 184 surrounding the contact electrode 186, and a first silicide film 182 between the first barrier layer 184 and the upper source / drain pattern 300B. Thus, the semiconductor device 100 according to the implementation may be manufactured.

[0297] Although the present disclosure contains many specific implementation details, these should not be interpreted as limitations on the scope of the claims. Certain features described in the present disclosure in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented in multiple implementations separately or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations and even initially claimed as such, one or more features from the combination may be removed from the combination in some cases, and the combination may be directed to a sub-combination or a variation of the sub-combination.

[0298] Although the implementation of the present disclosure has been described in detail, the scope of the present disclosure is not limited by the implementation. Various changes and modifications of the basic concept of the present disclosure defined in the appended claims by those skilled in the art should be interpreted as belonging to the scope of the present disclosure.

[0299] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0151704 filed in the Korean Intellectual Property Office on November 6, 2023, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, comprising: a plurality of lower channel patterns spaced apart from each other; a plurality of upper channel patterns spaced apart from each other on the plurality of lower channel patterns; a gate structure surrounding the plurality of lower channel patterns and the plurality of upper channel patterns; a lower source / drain trench located on one side of the plurality of lower channel patterns; an upper source / drain trench located on one side of the plurality of upper channel patterns; a lower source / drain pattern, located in the lower source / drain trench; as well as an upper source / drain pattern, comprising a first upper source / drain layer located at opposite sidewalls of the upper source / drain trench and a second upper source / drain layer located between the first upper source / drain layers, The first upper source / drain layer exposes at least a portion of a bottom surface of the upper source / drain trench.

2. The semiconductor device according to claim 1, wherein: The top surface of the second upper source / drain layer is flat, and A side surface of the first upper source / drain layer includes a curved surface.

3. The semiconductor device according to claim 2, wherein: The maximum width of the first upper source / drain layer is greater than 0 nm and less than 10 nm.

4. The semiconductor device according to claim 2, wherein the side surface of the first upper source / drain layer comprises: a first side surface extending from a sidewall of the upper source / drain trench and having a rounded shape; and The second side surface extends parallel to the sidewall of the upper source / drain trench.

5. The semiconductor device according to claim 4, wherein: An angle formed by the side surface of the first upper source / drain layer and the sidewall of the upper source / drain trench is between 80 degrees and 90 degrees.

6. The semiconductor device according to claim 2, wherein: The upper source / drain pattern includes silicon germanium, and The concentration of germanium contained in the second upper source / drain layer is equal to or greater than 60 at % and less than 70 at %.

7. The semiconductor device according to claim 1, wherein: A top surface of the second upper source / drain layer has a convex shape in a direction away from the lower source / drain pattern.

8. The semiconductor device according to claim 1, wherein: The first upper source / drain layer contacts the plurality of upper channel patterns, and The second upper source / drain layer is spaced apart from the plurality of upper channel patterns.

9. The semiconductor device according to claim 1, wherein: The side surface of the first upper source / drain layer includes a plurality of inclined surfaces having different inclinations.

10. The semiconductor device according to claim 1, wherein: The width of the first upper source / drain layer increases or remains the same from a lower portion of the upper source / drain trench toward a central portion of the upper source / drain trench.

11. The semiconductor device according to claim 1, further comprising: a blocking structure located between the lower source / drain pattern and the upper source / drain pattern, A bottom surface of the second upper source / drain layer contacts at least a portion of the blocking structure.

12. The semiconductor device according to claim 11, further comprising: an air gap between the blocking structure and the second upper source / drain layer, wherein the air gap overlaps the lower source / drain pattern in a vertical direction, and A bottom surface of the second upper source / drain layer has a convex shape toward the lower source / drain pattern.

13. A semiconductor device comprising: a plurality of upper channel patterns spaced apart from each other; a gate structure surrounding the plurality of upper channel patterns; an upper source / drain trench located on one side of the plurality of upper channel patterns; as well as an upper source / drain pattern including first upper source / drain layers protruding from opposite sidewalls of the upper source / drain trenches and a second upper source / drain layer located between the first upper source / drain layers, The width of the first upper source / drain layer gradually increases from the upper part and the lower part of the upper source / drain trench toward the central part of the upper source / drain trench.

14. The semiconductor device according to claim 13, wherein: The side surface of the first upper source / drain layer includes a curved surface, A top surface of the second upper source / drain layer is flat or has a convex shape.

15. The semiconductor device according to claim 14, wherein: The side surface of the first upper source / drain layer comprises: a first side extending from a sidewall of the upper source / drain trench and having a rounded shape; and The second side surface extends in a direction parallel to the sidewall of the upper source / drain trench.

16. A semiconductor device comprising: substrate; an active pattern, located on the substrate; a plurality of lower channel patterns spaced apart from each other on the active pattern; a plurality of upper channel patterns spaced apart from each other on the plurality of lower channel patterns; a gate structure surrounding the plurality of lower channel patterns and the plurality of upper channel patterns; a lower source / drain pattern located on one side of the plurality of lower channel patterns; an upper source / drain pattern located at one side of the plurality of upper channel patterns and comprising a first upper source / drain layer and a second upper source / drain layer; as well as a blocking structure located between the lower source / drain pattern and the upper source / drain pattern, wherein the first upper source / drain layer is located on two opposite sides of the second upper source / drain layer, and A width of the first upper source / drain layer along one direction gradually increases from an upper portion and a lower portion of the upper source / drain trench toward a central portion of the upper source / drain trench.

17. The semiconductor device according to claim 16, wherein: The side surface of the first upper source / drain layer comprises a rounded shape, and A top surface of the second upper source / drain layer is flat or has a convex shape.

18. The semiconductor device according to claim 17, wherein: The upper source / drain pattern comprises silicon germanium, The concentration of germanium contained in the second upper source / drain layer is greater than the concentration of germanium contained in the first upper source / drain layer, and The concentration of germanium contained in the second upper source / drain layer is equal to or greater than 60 at % and less than 70 at %.

19. The semiconductor device according to claim 17, wherein: A top surface of the second upper source / drain layer is positioned farther away from a top surface of the substrate than a top surface of a topmost upper channel pattern among the plurality of upper channel patterns, or the top surface of the second upper source / drain layer and the top surface of the topmost upper channel pattern are positioned to be spaced an equal distance apart from the top surface of the substrate.

20. The semiconductor device according to claim 16, wherein: The first upper source / drain layer exposes at least a portion of a top surface of the blocking structure.

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