Array substrate and display panel

Abstract

The invention provides an array substrate and a display panel. The array substrate comprises a substrate and a driving circuit layer arranged on the substrate. The driving circuit layer comprises at least one pixel driving circuit, the pixel driving circuit comprises a first thin film transistor, the first thin film transistor comprises a first active layer and at least one first grid electrode, the first active layer comprises a first channel region, and the first channel region is continuously arranged and is of a nonlinear structure on the whole; the orthographic projection of the first channel region on the substrate falls within the orthographic projection of the first gate on the substrate. In the array substrate, the stability of the first thin film transistor is enhanced, and the problem of pocking marks in a test is solved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular, to an array substrate and a display panel. Background Art

[0002] With the rapid development of display technology, display panels have been widely used in people's daily life and industrial production. From smartphones, tablets to large monitors, car displays, etc., the performance and reliability of display panels directly affect the user experience and the overall performance of the device. In actual use environments, display panels may face various complex conditions, among which high temperature and high humidity environments are one of the more common factors that have a significant impact on their performance. In order to evaluate the reliability and stability of display panels in high temperature and high humidity environments, the double 85 test came into being. After the double 85 test, there was a problem of pitting on the display panel, affecting the display effect. Summary of the invention

[0003] The present disclosure provides an array substrate and a display panel, which improve the stability of the first thin film transistor by setting the channel of the first thin film transistor into a non-linear continuous structure, thereby reducing the risk of pitting problems after 85 tests.

[0004] According to a first aspect of the present disclosure, an array substrate is provided, the array substrate comprising a substrate and a driving circuit layer arranged on the substrate. The driving circuit layer comprises at least one pixel driving circuit, the pixel driving circuit comprises a first thin film transistor, the first thin film transistor comprises a first active layer and at least one first gate, the first active layer comprises a first channel region, the first channel region is continuously arranged and has a non-linear structure as a whole, and the orthographic projection of the first channel region on the substrate falls within the orthographic projection of the first gate on the substrate.

[0005] In the above solution, the channel side length of the first thin film transistor is increased, thereby enhancing the stability of the first thin film transistor and reducing the offset of the Threshold Voltage (VTH) of the first thin film transistor, thereby improving the problem of pitting on the array substrate caused by the negative offset of VTH.

[0006] In a specific embodiment of the first aspect of the present disclosure, the orthographic projection of the first channel region on the substrate is U-shaped.

[0007] In the above solution, the U-shaped first channel region forms a U-shaped channel correspondingly, which can not only improve the stability of the first thin film transistor, but also improve the ability of the first thin film transistor to resist high-frequency electromagnetic interference.

[0008] In a specific embodiment of the first aspect of the present disclosure, a pattern of an orthographic projection of the first gate on the substrate includes a main body portion and an extension portion, and the extension portion extends from the bottom of the main body portion to the periphery of the main body portion.

[0009] In the above solution, the processing and manufacturing of the first thin film transistor is facilitated.

[0010] In a specific embodiment of the first aspect of the present disclosure, the orthographic projection of the main body portion on the substrate is U-shaped and coincides with the orthographic projection of the first channel region on the substrate, and the opening of the U-shaped main body portion corresponds to the bottom of the main body portion; or, the orthographic projection of the main body portion on the substrate is rectangular, and the orthographic projection of the first channel region on the substrate falls within the orthographic projection of the main body portion on the substrate.

[0011] Optionally, the shape of the orthographic projection of the extension portion on the substrate is a rectangle.

[0012] In a specific embodiment of the first aspect of the present disclosure, the array substrate also includes a light-emitting unit located on the side of the pixel driving circuit layer facing away from the substrate, the pixel driving circuit also includes a second thin film transistor for driving the light-emitting unit to emit light, the second thin film transistor includes a second active layer and a second gate, and the first thin film transistor is connected to the second gate of the second thin film transistor for initializing the second gate.

[0013] In a specific embodiment of the first aspect of the present disclosure, the second active layer includes a second channel region, and the length of the first channel region is greater than the length of the second channel region.

[0014] Optionally, a difference between the length of the first channel region and the length of the second channel region is A, and 0 μm<A≤21 μm.

[0015] In a specific embodiment of the first aspect of the present disclosure, the pixel driving circuit also includes a first scanning signal line and a first reference voltage line, the first thin film transistor includes a control end, a first path end and a second path end, the control end is connected to the first scanning signal line, the first path end is connected to the first reference voltage line, and the second path end is electrically connected to the second gate of the second thin film transistor.

[0016] In a specific embodiment of the first aspect of the present disclosure, the pixel driving circuit includes a power supply unit, a data writing unit, a driving unit and an initialization unit; the power supply unit is used to provide a power signal to the pixel driving circuit; the data writing unit is used to receive a scanning signal, and write and save the data signal into the driving unit according to the scanning signal; the driving unit is connected to the data writing unit and the power supply unit, and is used to receive the power signal and drive the light-emitting unit to emit light according to the data signal, and the second thin film transistor is part of the driving unit; the initialization unit is at least used to initialize the second gate of the second thin film transistor in the driving unit, and the first thin film transistor is part of the initialization unit.

[0017] In a specific embodiment of the first aspect of the present disclosure, the first thin film transistor is a low temperature polysilicon thin film transistor.

[0018] In the above solution, the design of the channel of the first thin film transistor can more effectively improve the problem of VTH offset or large offset caused by material problems of the low-temperature polysilicon thin film transistor.

[0019] Optionally, the first thin film transistor is a dual-gate transistor, so that the performance stability of the first thin film transistor is more effectively improved.

[0020] A second aspect of the present disclosure provides a display panel, which includes the array substrate in the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A cross-sectional view of an array substrate provided in accordance with an embodiment of the present disclosure.

[0022] Figure 2 A top view of the circuit structure of a common array substrate.

[0023] Figure 3 A top view of the circuit structure of an array substrate provided in one embodiment of the present disclosure.

[0024] Figure 4 An embodiment of the present disclosure provides Figure 1 An enlarged top view of the circuit structure at location A.

[0025] Figure 5 A top view of the circuit structure of an array substrate provided in one embodiment of the present disclosure.

[0026] Figure 6 An embodiment of the present disclosure provides Figure 1 Another enlarged top view of the circuit structure at A.

[0027] Figure 7 A cross-sectional view of another array substrate provided according to an embodiment of the present disclosure.

[0028] Figure 8 A circuit diagram of a pixel driving circuit of an array substrate provided in one embodiment of the present disclosure.

[0029] Fig. 9 A top view of the circuit structure of an array substrate provided in one embodiment of the present disclosure.

[0030] Fig.10 A top view of the circuit structure of an array substrate provided in another embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0032] The double 85 test, i.e., an environmental test at 85°C and 85% relative humidity, is designed to simulate the working state of the display panel under extreme conditions of high temperature and high humidity. Through this test, the performance of the display panel in such a harsh environment for a long time can be effectively tested, its reliability and life in actual use can be predicted, and the product can meet the needs of different users in various environments. For example, for outdoor advertising displays, industrial control terminals, and electronic equipment used in some special environments, the double 85 test can provide an important reference for the quality and stability of the product.

[0033] After the display panel performs specific operations in a dual 85 environment, such as continuous lighting, switching between different screens, loading specific images or video signals, etc., the performance of the display panel may change. After the aging test and the subsequent recovery stage, the pitting problem is particularly prominent. Specifically, a large number of pitting appeared on the surface of the display panel. Some of these pitting appeared as bright spots that continued to glow, some were dark spots that could not glow, and some appeared as spots with abnormal colors. These pitting seriously affected the display quality of the display panel and affected the user's normal viewing experience.

[0034] Through analysis, it is found that this is because the threshold voltage (VTH) of thin-film transistors (TFTs) in the display panel will shift negatively under the conditions of high-temperature light bias. Therefore, there is a problem of reliability failure of the display panel in the double 85 operation RA (85°C, 85% relative humidity) for 240 hours, such as the appearance of stippling problems. The threshold voltage (abbreviated as VTH) is a key electrical parameter. It refers to the critical voltage at which a conducting channel starts to form in the channel region of the TFT when the voltage applied between the gate and the source of the TFT, i.e., the gate-source voltage (abbreviated as VGS), reaches a certain value, enabling current to flow between the source and the drain. Simply put, when VGS < VTH, the TFT is in the off state and almost no current passes through; when VGS ≥ VTH, the TFT starts to conduct and current can flow from the source to the drain. Therefore, when VTH shifts negatively, it causes abnormal pixel charging or light emission, which will破坏 the uniformity of the display panel. Visually, this non-uniformity may be perceived as stippling. In addition, the negative shift of VTH may cause excessive local current density, which may result in local overheating. This will accelerate the aging of the organic light-emitting materials. In extreme cases, the change in the properties of these materials may cause微小 physical damage to the surface of the display panel,进而 forming stippling.

[0035] In view of this, embodiments of the present disclosure provide an array substrate and a display panel. The array substrate includes a substrate and a driving circuit layer disposed on the substrate. The driving circuit layer includes at least one pixel driving circuit, and the pixel driving circuit includes a first thin-film transistor. The first thin-film transistor includes a first active layer and at least one first gate. The first active layer includes a first channel region. The first channel region is continuously arranged and has an overall non-linear structure. The orthographic projection of the first channel region on the substrate falls within the orthographic projection of the first gate on the substrate. In this way, under the condition of the same layout size, the length of the carrier transmission path formed between the first channel region with a non-linear structure and the first gate becomes longer, that is, the length of the first channel region becomes larger. Thus, the ratio of the width to the length of the first channel region becomes smaller, providing a more stable transmission path for carriers, which is beneficial to stabilizing VTH, thereby reducing the risk of problems such as stippling in the display panel after the double 85 test, and进而 improving the reliability of the display panel.

[0036] In the following, the array substrate and the display panel in at least one embodiment of the present disclosure are described in conjunction with the accompanying drawings. In addition, as shown in the accompanying drawings, in at least one embodiment of the present disclosure, a spatial rectangular coordinate system is established with the surface where the array substrate is located as a reference to define the positions of the various film layers in the array substrate. In the spatial rectangular coordinate system, the X-axis and the Y-axis are parallel to the surface where the array substrate is located, and the Z-axis is perpendicular to the surface where the array substrate is located.

[0037] In an array substrate provided by an embodiment of the present disclosure, Figure 1 , Figure 3 As shown, the array substrate includes a substrate 100 and a driving circuit layer 200 disposed on the substrate 100. The substrate 100 may be a rigid substrate made of materials such as glass or plastic, or may be a flexible substrate made of materials such as polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC) or cellulose acetate propionate (CAP).

[0038] The driving circuit layer 200 includes at least one pixel driving circuit 200a, and the pixel driving circuit 200a includes a first thin film transistor T1. The first thin film transistor T1 includes a first active layer 210 and at least one first gate electrode 212. The first active layer 210 includes a first channel region 211, a first source region 213, and a first drain region 214. The first channel region 211 is located between the first source region 213 and the first drain region 214. The first channel region 211 is continuously arranged and has a non-linear structure as a whole. The orthographic projection of the first channel region 211 on the substrate 100 falls within the orthographic projection of the first gate electrode 212 on the substrate 100. The first channel region 211 and the first gate electrode 212 overlap in space, thereby forming a conductive channel, i.e., a channel.

[0039] When the first gate 212 applies an operating voltage, the first channel region 211 spatially overlapping the first gate 212 forms a conductive channel, allowing carriers to flow between the first source region 213 and the first drain region 214. Figure 2From the top view of the circuit structure of the common array substrate, it can be seen that the common first channel region 211' formed by the spatial overlap of the corresponding common first gate 212' and the common first active layer 210' in the common array substrate is a linear structure. However, the conductive channel, i.e., the channel, of the first channel region 211 of the non-linear structure in the present disclosure becomes longer, which is beneficial to the stability of the performance of the first thin film transistor T1. When the length of the first channel region 211 becomes longer, the corresponding channel length becomes longer, which reduces the influence of the electric field between the first source region 213 and the first drain region 214 on the first channel region 211, making the charge distribution in the first channel region 211 relatively stable, thereby reducing the drift of VTH, improving the stability of the first thin film transistor T1, and thus improving the problem of pitting on the array substrate due to the negative offset of VTH.

[0040] In addition, the first thin film transistor T1 further includes a first source electrode 213a and a first drain electrode 214a electrically connected to the first source region 213 and the first drain region 214 respectively, and the specific structures of the first source electrode 213a and the first drain electrode 214a can be designed according to actual needs, which will not be described in detail here.

[0041] In an array substrate provided in an embodiment of the present disclosure, Figure 3 and Figure 5 As shown, the first channel region 211 which is non-linear and continuously arranged as a whole has a U-shaped positive projection on the substrate 100. The first channel region 211 which is in a U-shaped structure as a whole can not only increase the channel length of the first thin film transistor T1, but also improve the uniformity of current distribution and enhance the resistance of the first thin film transistor T1 to high-frequency electromagnetic interference.

[0042] After defining the first channel region 211 in the first thin film transistor T1 , the embodiment of the present disclosure further defines the structure of the first gate 212 that forms a channel corresponding to the first channel region 211 , as follows.

[0043] In an array substrate provided in an embodiment of the present disclosure, the orthographic projection of the first gate 212 on the substrate 100 includes a main body 212a and an extension 212b, and the extension 212b extends from the bottom of the main body 212a to the periphery of the main body 212a.

[0044] In the array substrate provided in at least one embodiment of the present disclosure, the orthographic projection of the main body 212a on the substrate 100 is U-shaped and coincides with the orthographic projection of the first channel region 211 on the substrate 100, and the opening of the U-shaped main body 212a corresponds to the bottom of the main body 212a.

[0045] In the array substrate provided in at least another embodiment of the present disclosure, the orthographic projection of the main body 212a on the substrate 100 is a quasi-rectangular shape, and the orthographic projection of the first channel region 211 on the substrate 100 falls within the orthographic projection of the main body 212a on the substrate 100 .

[0046] In the array substrate provided in at least one embodiment of the present disclosure, the shape of the orthographic projection of the extension portion 212 b on the substrate 100 is a rectangle.

[0047] For example, Figure 1 and Figure 4 As shown, in the array substrate, the orthographic projection of the first channel region 211 of the first active layer 210 in the first thin film transistor T1 on the substrate 100 is U-shaped. The orthographic projection of the first gate electrode 212 corresponding to the first active layer 210 in the first thin film transistor T1 on the substrate 100 covers the U-shaped channel region. Specifically, the pattern of the first gate electrode 212 on the substrate 100 includes a main body 212a and an extension 212b. The orthographic projection of the main body 212a on the substrate 100 is U-shaped, and the extension 212b extends from the bottom of the main body 212a, that is, the opening of the U-shaped main body 212a to the periphery. The orthographic projection of the U-shaped main body 212a on the substrate 100 coincides with the orthographic projection of the U-shaped first channel region 211 on the substrate 100. The extension portion 212 b is rectangular and extends from the bottom of the U-shaped main portion 212 a to a direction away from the main portion 212 a . The extension portion 212 b does not overlap with the orthographic projection of the U-shaped first channel region 211 on the substrate 100 .

[0048] For example, Figure 1 and Figure 6 As shown, in the array substrate, the figure of the orthographic projection of the first gate 212 on the substrate 100 includes a main body 212a and an extension 212b. The figure of the orthographic projection of the main body 212a on the substrate 100 is a rectangular shape, that is, the overall outline of the figure of the orthographic projection of the main body 212a on the substrate 100 presents a rectangular or square shape, and at least one of the corresponding four corners is a 90° right angle, a circular arc angle, and a cut angle. The orthographic projection of the U-shaped first channel region 211 on the substrate 100 falls within the rectangular main body 212a. The figure of the orthographic projection of the extension 212b on the substrate 100 is a rectangle, extending from the bottom of the U-shaped main body 212a in a direction away from the main body 212a, and the extension 212b does not overlap with the orthographic projection of the U-shaped first channel region 211 on the substrate 100. Other structural descriptions can refer to the above embodiments, which will not be repeated here.

[0049] It should be noted that the structure of the array substrate in the present disclosure is not limited to the above examples and illustrations. For example, the figure of the orthographic projection of the first channel region 211 on the substrate 100 can also be a discount or a wavy line. The orthographic projection of the first gate 212 on the substrate 100 covers the orthographic projection of the first channel region 211 on the substrate 100, which can be designed into other structures according to actual needs. In addition, the array substrate also includes other film layers, such as a buffer layer arranged between the substrate 100 and the driving circuit layer 200. All of the above can be designed according to actual needs and will not be repeated here.

[0050] After introducing the structure of the first thin film transistor T1 in the array substrate in the embodiment of the present disclosure, the embodiment of the present disclosure further introduces the devices in the pixel driving circuit 200a that have a working relationship with the first thin film transistor T1, and the specific contents are as follows.

[0051] In an array substrate provided in an embodiment of the present disclosure, Figure 6 As shown, the array substrate further includes a pixel defining layer 400 and a light emitting unit 300 , and the pixel driving circuit 200 a includes a first thin film transistor T1 and a second thin film transistor T2 .

[0052] The light-emitting unit 300 is located on the side of the driving circuit layer 200 away from the substrate 100. The light-emitting unit 300 includes a first electrode 310, a light-emitting layer 320, and a second electrode 330 stacked on the substrate 100. The first electrode 310 is one of an anode or a cathode, and the corresponding second electrode 330 is one of a cathode or an anode. The pixel defining layer 400 is located on the side of the driving circuit layer 200 away from the substrate 100, and defines a pixel opening for exposing the first electrode 310 of the light-emitting unit 300, such as an anode.

[0053] The pixel driving circuit 200a includes a first thin film transistor T1 and a second thin film transistor T2. The second thin film transistor T2 is used to drive the light emitting unit 300 to emit light. The second thin film transistor T2 includes a second active layer 220 and a second gate electrode 222. The second active layer 220 includes a second source region 223, a second channel region 221 and a second drain region 224, and the second channel region 221 is located between the second source region 223 and the second drain region 224. Any one of the second source region 223 and the second drain region 224 is electrically connected to the anode of the light emitting unit 300 to achieve driving the light emitting unit 300 to emit light. The first thin film transistor T1 is connected to the second gate electrode 222 of the second thin film transistor T2 for initializing the second gate electrode 222. The second thin film transistor T2 also includes a second source electrode 223a electrically connected to the second source region 223 and a second source electrode 224a electrically connected to the second drain region 224.

[0054] The embodiment of the present disclosure does not specifically introduce the light-emitting layer 320, which can be designed according to the needs. For example, the light-emitting layer 320 can be a multi-layer structure. Specifically, the light-emitting layer 320 includes a stacked hole injection layer (Hole Inject Layer, HIL), a hole transport layer (Hole Transport Layer, HTL), a light-emitting material layer, an electron injection layer (Electron Inject Layer, EIL) and an electron transport layer (Electron Transport Layer, ETL). The above can be selected according to actual needs and will not be described in detail here.

[0055] In an array substrate provided in an embodiment of the present disclosure, Figure 3 , Figure 5 and Figure 7 As shown, the first channel region 211 of the first thin film transistor T1 is a non-linear continuous structure, the second channel region 221 of the second thin film transistor T2 is a linear continuous structure, and the length of the first channel region 211 is greater than the length of the second channel region 221, that is, the conductive channel of the first thin film transistor T1 is a non-linear continuous structure, the conductive channel of the second thin film transistor T2 is a linear continuous channel, and the length of the conductive channel of the first thin film transistor T1 is greater than the length of the conductive channel of the second thin film transistor T2.

[0056] In the array substrate provided in at least one embodiment of the present disclosure, the difference between the length of the first channel region 211 and the length of the second channel region 221 is A, and 0μm<A≤21μm. For example, the length of the second channel region 221 is 3μm, and the length of the first channel region 211 is any one of 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm, 17μm, 18μm, 19μm, 20μm, 21μm, 22μm, 23μm, and 24μm.

[0057] It should be noted that the length of the second channel region 221 is not limited to 3μm in the above example, and can also be set to be less than 3μm, such as 1μm, 2μm, or can be set to be greater than 3μm, such as 4μm, 5μm, 6μm, 7μm, etc. It can be specifically designed according to the requirements of the array substrate and will not be elaborated here.

[0058] Based on the above embodiments, in an array substrate provided in an embodiment of the present disclosure, the pixel driving circuit 200a may include any one of a 2T1C circuit, a 7T1C circuit, a 7T2C circuit, an 8T1C circuit, a 9T1C circuit, etc. Among them, the "2T1C circuit" refers to a pixel driving circuit 200a including two thin film transistors (T) and one capacitor (C) in the pixel driving circuit 200a, and other "7T1C circuits", "7T2C circuits", "9T1C circuits", etc. are analogous.

[0059] In an array substrate provided by an embodiment of the present disclosure, the pixel driving circuit 200a also includes a first scanning signal line and a first reference voltage line, and the first thin film transistor T1 includes a control end, a first path end and a second path end, the control end is connected to the first scanning signal line, the first path end is connected to the first reference voltage line, and the second path end is electrically connected to the second gate 222 of the second thin film transistor T2.

[0060] For ease of understanding, the following description is made by taking the pixel driving circuit 200 a as a 7T1C circuit as an example.

[0061] In an array substrate provided in an embodiment of the present disclosure, Figure 8 As shown, the array substrate includes a plurality of pixel driving circuits 200a and signal lines. The pixel driving circuit 200a includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, a sixth thin film transistor T6, a seventh thin film transistor T7 and a storage capacitor Cst, that is, the pixel driving circuit 200a has a 7T1C structure. The signal line includes a scan signal line Scan, a data line Data, a reference voltage line Vref, a high potential power supply voltage line Elvdd, a low potential power supply voltage line Elvss, etc. Specifically, each pixel driving circuit 200a includes a power supply unit, a data writing unit, a driving unit and an initialization unit.

[0062] The power supply unit is connected to the light-emitting enable signal line EM, and can receive the light-emitting enable signal EM through the light-emitting enable signal line EM. The light-emitting enable signal EM can indicate whether the current pixel driving circuit 200a emits light, so that the power supply unit can provide the power signal Vdd for the light-emitting element of the pixel driving circuit 200a according to the light-emitting enable signal EM.

[0063] Specifically, the power supply unit includes a fifth thin film transistor T5 and a sixth thin film transistor T6. The fifth gate of the fifth thin film transistor T5 is connected to the light-emitting enable signal line EM1, the fifth source of the fifth thin film transistor T5 is connected to the high potential power supply voltage line Elvdd, and the fifth drain of the fifth thin film transistor T5 is connected to the driving unit of the pixel driving circuit 200a. The sixth gate of the sixth thin film transistor T6 is connected to the light-emitting enable signal line EM1, the sixth source of the sixth thin film transistor T6 is connected to the driving unit of the pixel driving circuit 200a, and the sixth drain of the sixth thin film transistor T6 is connected to the light-emitting unit 300.

[0064] The data writing unit receives the scan signal Scan, so as to write the data signal Vdata into the driving unit of the pixel driving circuit 200 a and store it under the driving of the scan signal Scan.

[0065] Specifically, the data writing unit includes a third thin film transistor T3 and a fourth thin film transistor T4. The third gate of the third thin film transistor T3 is connected to the second scan signal line Scan2, the third source of the third thin film transistor T3 is connected to the initialization unit of the pixel driving circuit 200a, and the third drain of the third thin film transistor is connected to the driving unit of the pixel driving circuit 200a. The fourth gate of the fourth thin film transistor T4 is connected to the second scan signal line Scan2, the fourth source of the fourth thin film transistor T4 is connected to the first data line Data1, and the fourth drain of the fourth thin film transistor T4 is connected to the driving unit of the pixel driving circuit 200a.

[0066] The driving unit is connected to the data writing unit and the power supply unit, and is used for receiving the power signal Vdd and regulating the driving current according to the data signal Vdata, so as to drive the light emitting unit 300 to emit light.

[0067] Specifically, the driving unit includes a second thin film transistor T2, the second gate 222 of the second thin film transistor T2 is connected to the initialization unit of the pixel driving circuit 200a, the second source 223a of the second thin film transistor T2 is connected to the fourth drain of the fourth thin film transistor T4, and the second drain 224a of the second thin film transistor T2 is connected to the light emitting unit 300.

[0068] The initialization unit is connected to the reference signal line Vref, and is also connected to the light emitting unit 300 and the driving unit, and is used to initialize the second gate 222 of the second thin film transistor T2 in the driving unit and initialize the anode of the light emitting unit 300 .

[0069] Specifically, the initialization unit includes a first thin film transistor T1 and a seventh thin film transistor T7. The first thin film transistor T1 includes a first control terminal, i.e., a first gate electrode 212, a first path terminal, i.e., a first source electrode 213a electrically connected to the first source region 213, and a second path terminal, i.e., a first drain electrode 214a electrically connected to the first drain region 214. The first control terminal of the first thin film transistor T1 is connected to the first scan signal line Scan1, the first path terminal of the first thin film transistor T1 is connected to the first reference voltage line Vref1, and the second path terminal of the first thin film transistor T1 is connected to the second gate electrode 222 of the second thin film transistor T2, for initializing the second gate electrode 222 of the second thin film transistor T2. The seventh gate electrode of the seventh thin film transistor T7 is connected to the third scan signal line Scan3, the seventh source electrode of the seventh thin film transistor T7 is connected to the second reference voltage line Vref2, and the seventh drain electrode of the seventh thin film transistor T7 is connected to the light emitting unit 300, for initializing the anode of the light emitting unit 300.

[0070] In an array substrate provided in an embodiment of the present disclosure, Fig. 9 and Fig.10 As shown, the array substrate includes an active layer P-Si layer, a first metal layer M1, a second metal layer M2 and a third metal layer M3 stacked on a substrate 100, and the active layer includes at least an active layer of multiple thin film transistors. The first metal layer M1 includes at least the gates of multiple transistors, the first capacitor plate of the storage capacitor, and a plurality of scan signal lines Scan extending along the first direction, and a light-emitting enable signal line EM extending along the first direction. The second metal layer M2 includes at least the second capacitor plate of the storage capacitor and a reference voltage line Vref extending along the first direction. The third metal layer M3 includes at least the source and drain electrodes of multiple transistors, a plurality of data lines Data extending along the second direction, and a high potential power supply voltage line Elvdd extending along the second direction.

[0071] Specifically, the extension direction of the scan signal line Scan crosses the extension direction of the data line Data. For example, the extension direction of the scan signal line Scan is perpendicular to the extension direction of the data line Data. The scan signal line Scan extends along a first direction, such as a horizontal direction, and the data line Data extends along a second direction, such as a vertical direction. Other signal lines and peripheral circuits for driving are also provided on the first metal layer M1, the second metal layer M2, and the third metal layer M3, which are not described in detail here.

[0072] In the array substrate provided by the embodiment of the present disclosure, the first thin film transistor T1 is a low temperature polysilicon thin film transistor.

[0073] For example, Figure 7As shown, the first thin film transistor T1 , the second thin film transistor T2 , the third thin film transistor T3 , the fourth thin film transistor T4 , the fifth thin film transistor T5 , the sixth thin film transistor T6 , and the seventh thin film transistor T7 are low temperature polysilicon thin film transistors.

[0074] In the array substrate provided by at least one embodiment of the present disclosure, the first thin film transistor T1 is a dual-gate transistor.

[0075] For example, Figure 7 As shown, the first thin film transistor T1 and the third thin film transistor T3 are double-gate transistors.

[0076] An embodiment of the present disclosure further provides a display panel, which includes the array substrate in the above embodiment.

[0077] In an embodiment of the present disclosure, the display device may be an organic light emitting diode display device, a liquid crystal display device, an electronic paper display device, or the like.

[0078] For example, the display device in the embodiments of the present disclosure may be any product or component with a display function, such as a television, a digital camera, a mobile phone, a watch, a tablet computer, a laptop computer, a navigator, or the like.

[0079] It should be noted that the embodiments of the present disclosure do not describe all structures of the above display panel. To achieve the necessary functions of the display panel, those skilled in the art may set other structures according to specific application scenarios.

[0080] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. An array substrate, characterized in that: include: substrate; as well as A driving circuit layer, disposed on the substrate, the driving circuit layer comprising at least one pixel driving circuit, the pixel driving circuit comprising a first thin film transistor, the first thin film transistor comprising a first active layer and at least one first gate, the first active layer comprising a first channel region; The first channel regions are continuously arranged and are in a non-linear structure as a whole, and the orthographic projection of the first channel region on the substrate falls within the orthographic projection of the first gate on the substrate.

2. The array substrate according to claim 1, characterized in that: The orthographic projection of the first channel region on the substrate is U-shaped.

3. The array substrate according to claim 2, characterized in that: The orthographic projection of the first gate on the substrate includes a main body and an extension portion, and the extension portion extends from the bottom of the main body to the periphery of the main body.

4. The array substrate according to claim 3, characterized in that: The orthographic projection of the main body on the substrate is U-shaped and coincides with the orthographic projection of the first channel region on the substrate, and the opening of the U-shaped main body corresponds to the bottom of the main body; or, The orthographic projection of the main body on the substrate is a quasi-rectangular shape, and the orthographic projection of the first channel region on the substrate falls within the orthographic projection of the main body on the substrate; Preferably, the shape of the orthographic projection of the extension portion on the substrate is a rectangle.

5. The array substrate according to any one of claims 1 to 4, characterized in that: The array substrate also includes a light-emitting unit located on a side of the pixel driving circuit layer away from the substrate. The pixel driving circuit also includes a second thin film transistor for driving the light-emitting unit to emit light. The second thin film transistor includes a second active layer and a second gate. The first thin film transistor is connected to the second gate of the second thin film transistor for initializing the second gate.

6. The array substrate according to claim 5, characterized in that: The second active layer includes a second channel region, and the length of the first channel region is greater than the length of the second channel region; Preferably, a difference between the length of the first channel region and the length of the second channel region is A, and 0 μm<A≤21 μm.

7. The array substrate according to claim 5, characterized in that: The pixel driving circuit also includes a first scanning signal line and a first reference voltage line, the first thin film transistor includes a control end, a first path end and a second path end, the control end is connected to the first scanning signal line, the first path end is connected to the first reference voltage line, and the second path end is electrically connected to the second gate of the second thin film transistor.

8. The array substrate according to claim 7, characterized in that: The pixel driving circuit includes a power supply unit, a data writing unit, a driving unit and an initialization unit, wherein: The power supply unit is used to provide a power signal to the pixel driving circuit; The data writing unit is used to receive a scanning signal, and write a data signal into the driving unit and save it according to the scanning signal; The driving unit is connected to the data writing unit and the power supply unit, and is used to receive the power signal and drive the light emitting unit to emit light according to the data signal, and the second thin film transistor belongs to the driving unit; The initialization unit is at least used to initialize the second gate of the second thin film transistor in the driving unit, wherein the first thin film transistor is part of the initialization unit.

9. The array substrate according to claim 1, characterized in that: The first thin film transistor is a low temperature polysilicon thin film transistor; Preferably, the first thin film transistor is a dual-gate transistor.

10. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 9.

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