ESD protection device with SCR structure

Abstract

The invention provides an ESD (Electro-Static Discharge) protection device with an SCR (Selective Catalytic Reduction) structure, in the ESD protection device, a first floating heavily doped region and a second floating heavily doped region are respectively introduced between two side edges of a first well region and a substrate, and a third floating heavily doped region and a fourth floating heavily doped region are respectively introduced between the inner side edge of a second well region and the substrate, the floating heavily doped region I, the floating heavily doped region III and the first silicide barrier layer connected with the cathode of the power supply form a parasitic diode, and similarly, the floating heavily doped region II, the floating heavily doped region IV and the second silicide barrier layer connected with the cathode of the power supply form a parasitic diode, the introduced floating heavily doped region III and the introduced floating heavily doped region IV are respectively a part of the base electrode of the parasitic PNP triode; the first floating heavily doped region and the second floating heavily doped region are respectively a part of the base electrode of the NPN triode, so that the base electrode is heavily doped, the common emitter amplification coefficient beta of a bipolar junction transistor (BJT) can be reduced, and the maintaining voltage of the SCR structure is effectively improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to an ESD protection device with an SCR structure. Background Art

[0002] In the field of high-voltage electrostatic protection, devices such as PNP transistors, diodes, LDMOS devices or SCR (Silicon Controlled Rectifier) ​​devices are often used. Among them, devices such as PNP transistors, diodes and LDMOS devices have a higher holding voltage, but the ESD (electrostatic discharge) protection capability per unit area is weak; while the SCR device has a strong ESD protection capability per unit area, but the holding voltage (Vh) is low and latch-up is prone to occur, which seriously limits the application of SCR devices in the field of high-voltage electrostatic protection. Summary of the invention

[0003] The present application provides an ESD protection device with an SCR structure, which can solve the problem that the conventional ESD protection device with an SCR structure has a low maintenance voltage and is prone to latch-up.

[0004] The embodiment of the present application provides an ESD protection device with an SCR structure, including: substrate; A well region 1 of a first conductivity type, the well region 1 being located in the substrate; A second well region of a second conductivity type, the second well region being located in the substrate and surrounding the first well region; An internal heavily doped region 1, an internal heavily doped region 2 and an internal heavily doped region 3 of a first conductivity type, wherein the internal heavily doped region 1 is located in the well region 1, and the internal heavily doped region 2 and the internal heavily doped region 3 are located at both sides of the internal heavily doped region 1 and are both located in the well region 2; An internal heavily doped region 4, an internal heavily doped region 5 and an internal heavily doped region 6 of the second conductivity type, wherein the internal heavily doped region 4 and the internal heavily doped region 5 are located at both sides of the internal heavily doped region 1 and are both located in the well region 1, and the internal heavily doped region 6 is located in the well region 2 and is arranged around the internal heavily doped region 2 and the internal heavily doped region 3; A floating heavily doped region 1 and a floating heavily doped region 2 of a first conductivity type, wherein the floating heavily doped region 1 is located at the fourth side of the internal heavily doped region away from the internal heavily doped region 1, and the floating heavily doped region 1 spans the left edge of the well region 1 and the substrate; the floating heavily doped region 2 is located at the fifth side of the internal heavily doped region away from the internal heavily doped region 1, and the floating heavily doped region 2 spans the right edge of the well region 1 and the substrate; a floating heavily doped region three and a floating heavily doped region four of the second conductivity type, wherein the floating heavily doped region three is located on the side of the internal heavily doped region two away from the internal heavily doped region six, and the floating heavily doped region three spans the inner edge of the well region two and the substrate; the floating heavily doped region four is located on the side of the internal heavily doped region three away from the internal heavily doped region six, and the floating heavily doped region four spans the inner edge of the well region two and the substrate; A plurality of shallow trench isolation structures, some of which are located in the well region 1 and are used to isolate different internal heavily doped regions and / or floating heavily doped regions; the remaining shallow trench isolation structures are located in the well region 2 and are used to isolate different internal heavily doped regions and / or floating heavily doped regions; A first silicide barrier layer, wherein the first silicide barrier layer covers the substrate between the first floating heavily doped region and the third floating heavily doped region; A second silicide barrier layer, wherein the second silicide barrier layer covers the substrate between the second floating heavily doped region and the fourth floating heavily doped region; Among them, the internal heavily doped region two, the internal heavily doped region three and the internal heavily doped region six are all connected to the anode of the external power supply; the internal heavily doped region one, the internal heavily doped region four, the internal heavily doped region five, the first silicide barrier layer and the second silicide barrier layer are all connected to the cathode of the external power supply.

[0005] Optionally, in the ESD protection device with an SCR structure, the substrate includes: a base and an epitaxial layer located on the base, the well region one and the well region two are both located in the epitaxial layer, the floating heavily doped region one spans the left edge of the well region one and the epitaxial layer, the floating heavily doped region two spans the right edge of the well region one and the epitaxial layer, the floating heavily doped region three spans the inner edge of the well region two and the epitaxial layer, and the floating heavily doped region four spans the inner edge of the well region two and the epitaxial layer.

[0006] Optionally, in the ESD protection device with the SCR structure, the ESD protection device with the SCR structure further includes: a buried layer of the second conductivity type, the buried layer is located in the substrate and a front side of the buried layer contacts a back side of the epitaxial layer.

[0007] Optionally, in the ESD protection device with the SCR structure, the ESD protection device with the SCR structure further includes: a deep well of the second conductivity type, the deep well is located at the bottom of the epitaxial layer and the back side of the deep well contacts the front side of the substrate.

[0008] Optionally, in the ESD protection device with the SCR structure, the ESD protection device with the SCR structure also includes: a buried layer of the second conductivity type and a deep well of the second conductivity type, the buried layer is located in the substrate and the front side of the buried layer contacts the back side of the epitaxial layer, and the deep well is located in the epitaxial layer and at the bottom of the well region two.

[0009] Optionally, in the ESD protection device with the SCR structure, the conductivity type of the doped ions in the substrate is the first conductivity type, and the conductivity type of the doped ions in the epitaxial layer is the first conductivity type.

[0010] Optionally, in the ESD protection device with the SCR structure, the materials of the first silicide barrier layer and the second silicide barrier layer are both polysilicon.

[0011] Optionally, in the ESD protection device with the SCR structure, the first conductivity type is P type; and the second conductivity type is N type.

[0012] The technical solution of this application has at least the following advantages: The present application introduces a floating heavily doped region 1 and a floating heavily doped region 2 between the two side edges of the well region 1 and the substrate, and introduces a floating heavily doped region 3 and a floating heavily doped region 4 between the inner edge of the well region 2 and the substrate, respectively. The first silicide barrier layer between the floating heavily doped region 1 and the floating heavily doped region 3 is connected to the power cathode, and the second silicide barrier layer between the floating heavily doped region 2 and the floating heavily doped region 4 is connected to the power cathode. At this time, the floating heavily doped region 1, the floating heavily doped region 3 and the first silicide barrier layer form a parasitic diode. Similarly, the floating heavily doped region 2, The floating heavily doped region four and the second silicide barrier layer form a parasitic diode, wherein the SCR structure is formed by coupling the PNP transistor (P+ / NW / PW) and the NPN transistor (NW / PW / N+), the introduced floating heavily doped region three (N+) is a part of the base of the parasitic PNP transistor; the introduced floating heavily doped region one (P+) is a part of the base of the NPN transistor, which respectively results in heavy doping of the bases of the PNP and NPN transistors, reducing the common emitter amplification factor β of the BJT (bipolar transistor), thereby effectively improving the holding voltage of the SCR structure. Since the ESD protection device provided in the present application is an axisymmetric structure (the center line of the internal heavily doped region one is the axis of symmetry), similarly, the floating heavily doped region four (N+) introduced on the right is part of the base of the parasitic PNP transistor; the introduced floating heavily doped region two (P+) is part of the base of the NPN transistor, which respectively leads to heavy doping of the bases of the PNP and NPN transistors, reducing the common emitter amplification factor β of the BJT (bipolar transistor), thereby effectively improving the holding voltage of the SCR structure.

[0013] Furthermore, in the advanced process, the first silicide barrier layer and the second silicide barrier layer can prevent the floating heavily doped region one and the floating heavily doped region three (the floating heavily doped region two and the floating heavily doped region four) from short-circuiting due to the metal silicide process. At the same time, the breakdown voltage of the SCR device can be controlled by adjusting the lateral width of the first silicide barrier layer between the floating heavily doped region one and the floating heavily doped region three and the lateral width of the second silicide barrier layer between the floating heavily doped region two and the floating heavily doped region four. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0015] Figure 1 is a structural schematic diagram of an ESD protection device with an SCR structure according to a first embodiment of the present invention; Figure 2 Schematic diagram of the working principle of the ESD protection device according to the first embodiment of the present invention; Figure 3 is a schematic diagram of the relationship between the breakdown voltage and the lateral width of the first / second silicide barrier layer according to the first embodiment of the present invention; Figure 4 It is a schematic diagram of a TLP test curve of the SCR structure inside the ESD protection device when the lateral widths of the first silicide barrier layer and the second silicide barrier layer are both 0.2 μm according to the first embodiment of the present invention; Figure 5 is a schematic structural diagram of an ESD protection device with an SCR structure according to a second embodiment of the present invention; Figure 6 is a schematic structural diagram of an ESD protection device with an SCR structure according to a third embodiment of the present invention; Figure 7 is a schematic structural diagram of an ESD protection device with an SCR structure according to a fourth embodiment of the present invention; The reference numerals are described as follows: 10-substrate, 11-well region 1, 12-well region 2, 13-base, 14-epitaxial layer, 15-buried layer, 16-deep well; 21-internal heavily doped region 1, 22-internal heavily doped region 2, 23-internal heavily doped region 3, 24-internal heavily doped region 4, 25-internal heavily doped region 5, 26-internal heavily doped region 6; 31- floating heavily doped region 1, 32- floating heavily doped region 2, 33- floating heavily doped region 3, 34- floating heavily doped region 4; 40- shallow trench isolation structure; 51 - a first silicide barrier layer, 52 - a second silicide barrier layer. DETAILED DESCRIPTION

[0016] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0017] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0018] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0019] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. Embodiment 1

[0020] Embodiment 1 of the present application provides an ESD protection device with an SCR structure, referring to Figure 1 , Figure 1 : is a schematic diagram of the structure of an ESD protection device with an SCR structure according to a first embodiment of the present invention, wherein the ESD protection device with an SCR structure comprises: Substrate 10; A well region 11 of a first conductivity type, the well region 11 is in a strip shape, and the well region 11 is located in the substrate 10; A second well region 12 of a second conductivity type, wherein the second well region 12 is ring-shaped, is located in the substrate 10 and is disposed around the first well region 11; An internal heavily doped region 1 21, an internal heavily doped region 22 and an internal heavily doped region 3 23 of a first conductivity type, wherein the internal heavily doped region 1 21 is located in the well region 1 11, and the internal heavily doped region 2 22 and the internal heavily doped region 3 23 are located on both sides of the internal heavily doped region 1 21 (the internal heavily doped region 2 22 and the internal heavily doped region 3 23 are located on both sides of the well region 1 11) and are both located in the well region 2 12; An internal heavily doped region 24, an internal heavily doped region 25 and an internal heavily doped region 26 of the second conductivity type, wherein the internal heavily doped region 24 and the internal heavily doped region 25 are located on both sides of the internal heavily doped region 1 21 and are both located in the well region 1 11, the internal heavily doped region 6 26 is located in the well region 2 12 and the internal heavily doped region 6 26 is arranged around the internal heavily doped region 2 22 and the internal heavily doped region 3 23; wherein the internal heavily doped region 1 21, the internal heavily doped region 2 22, the internal heavily doped region 3 23, the internal heavily doped region 24, the internal heavily doped region 5 25 and the internal heavily doped region 6 26 are all in strip shape; A floating heavily doped region 1 31 and a floating heavily doped region 2 32 of the first conductivity type, wherein the floating heavily doped region 1 31 is located on the side of the internal heavily doped region 4 24 away from the internal heavily doped region 1 21, and the floating heavily doped region 1 31 spans the left edge of the well region 1 11 and the substrate 10; the floating heavily doped region 2 32 is located on the side of the internal heavily doped region 5 25 away from the internal heavily doped region 1 21, and the floating heavily doped region 2 32 spans the right edge of the well region 1 11 and the substrate 10; a floating heavily doped region three 33 and a floating heavily doped region four 34 of the second conductivity type, wherein the floating heavily doped region three 33 is located on the side of the internal heavily doped region two 22 away from the internal heavily doped region six 26, and the floating heavily doped region three 33 spans the inner edge of the well region two 12 and the substrate 10; the floating heavily doped region four 34 is located on the side of the internal heavily doped region three 23 away from the internal heavily doped region six 26, and the floating heavily doped region four 34 spans the inner edge of the well region two 12 and the substrate 10; wherein the floating heavily doped region one 31, the floating heavily doped region two 32, the floating heavily doped region three 33 and the floating heavily doped region four 34 are all in strip shape; A plurality of shallow trench isolation structures 40, wherein a portion of the shallow trench isolation structures 40 are respectively located in the well region 11, and are respectively used for isolation between the floating heavily doped region 1 31, the internal heavily doped region 4 24, the internal heavily doped region 1 21, the internal heavily doped region 5 25, and the floating heavily doped region 2 32; the remaining portion of the shallow trench isolation structures 40 are located in the well region 2 12, and are respectively used for isolation between the internal heavily doped region 6 26, the internal heavily doped region 22, and the floating heavily doped region 3 33, and are respectively used for isolation between the internal heavily doped region 6 26, the internal heavily doped region 3 23, and the floating heavily doped region 4 34; A first silicide barrier layer 51, wherein the first silicide barrier layer 51 covers the substrate 10 between the floating heavily doped region 1 31 and the floating heavily doped region 3 33; A second silicide barrier layer 52, wherein the second silicide barrier layer 52 covers the substrate 10 between the second floating heavily doped region 32 and the fourth floating heavily doped region 34; Among them, the internal heavily doped region two 22, the internal heavily doped region three 23 and the internal heavily doped region six 26 are all connected to the anode (High) of the external power supply; the internal heavily doped region one 21, the internal heavily doped region four 24, the internal heavily doped region five 25, the first silicide barrier layer 51 and the second silicide barrier layer 52 are all connected to the cathode (Low) of the external power supply.

[0021] It is worth noting that the ESD protection device provided in the present application is an axisymmetric structure, wherein the center line of the internal heavily doped region 21 is the axis of symmetry.

[0022] In this embodiment, the first conductivity type is P type; the second conductivity type is N type.

[0023] Furthermore, the conductivity type of the doped ions in the substrate 10 is the first conductivity type (P type).

[0024] In this embodiment, the substrate 10 may be referred to as PSUB; The well region 11 may be referred to as PW; Well region 2 12 may be referred to as NW; The internal heavily doped region 1 21 , the internal heavily doped region 22 , and the internal heavily doped region 3 23 may be referred to as P+; The internal heavily doped region four 24, the internal heavily doped region five 25 and the internal heavily doped region six 26 may be referred to as N+ for short; The floating heavily doped region 1 31 and the floating heavily doped region 2 32 may be referred to as P+; The floating heavily doped region three 33 and the floating heavily doped region four 34 may be referred to as N+ for short.

[0025] In the present application, by introducing a floating heavily doped region 1 and a floating heavily doped region 2 between the two side edges of the well region 1 and the substrate, and introducing a floating heavily doped region 3 and a floating heavily doped region 4 between the inner edge of the well region 2 and the substrate, the first silicide barrier layer between the floating heavily doped region 1 and the floating heavily doped region 3 is connected to the power cathode, and the second silicide barrier layer between the floating heavily doped region 2 and the floating heavily doped region 4 is connected to the power cathode. At this time, reference Figure 2 , Figure 2 It is a schematic diagram of the working principle of the ESD protection device of the first embodiment of the present invention. The floating heavily doped region one, the floating heavily doped region three and the first silicide barrier layer form a parasitic diode. Similarly, the floating heavily doped region two, the floating heavily doped region four and the second silicide barrier layer form a parasitic diode. Among them, the SCR structure is formed by coupling the PNP transistor (P+ / NW / PW) and the NPN transistor (NW / PW / N+). The introduced floating heavily doped region three (N+) is a part of the parasitic PNP transistor base; the introduced floating heavily doped region one (P+) is a part of the NPN transistor base, which respectively causes the bases of the PNP and NPN transistors to be heavily doped, thereby reducing the common emitter amplification factor β of the BJT (bipolar transistor), thereby effectively improving the holding voltage of the SCR structure. Since the ESD protection device provided in the present application is an axisymmetric structure (the center line of the internal heavily doped region one is the axis of symmetry), similarly, the floating heavily doped region four (N+) introduced on the right is part of the base of the parasitic PNP transistor; the introduced floating heavily doped region two (P+) is part of the base of the NPN transistor, which respectively leads to heavy doping of the bases of the PNP and NPN transistors, reducing the common emitter amplification factor β of the BJT (bipolar transistor), thereby effectively improving the holding voltage of the SCR structure.

[0026] Preferably, the first silicide barrier layer 51 and the second silicide barrier layer 52 are both made of polysilicon.

[0027] In the advanced process, the first silicide barrier layer and the second silicide barrier layer can prevent the floating heavily doped region one and the floating heavily doped region three (the floating heavily doped region two and the floating heavily doped region four) from short circuiting due to the metal silicide process. At the same time, the breakdown voltage of the SCR device can be controlled by adjusting the lateral width S of the first silicide barrier layer between the floating heavily doped region one and the floating heavily doped region three and the lateral width of the second silicide barrier layer between the floating heavily doped region two and the floating heavily doped region four.

[0028] refer to Figure 3 and Figure 4 , Figure 3 is a schematic diagram of the relationship between the breakdown voltage and the lateral width of the first / second silicide barrier layer according to the first embodiment of the present invention, Figure 4The figure is a schematic diagram of a TLP test curve of an SCR structure inside an ESD protection device when the lateral widths of the first silicide barrier layer and the second silicide barrier layer of the first embodiment of the present invention are both 0.2 μm. The TLP test (Transmission Line Pulse) is a conventional research and test method for electrostatic discharge protection technology of integrated circuits. The DC (direct current) test and TLP test data show that: Figure 3 The voltage breakdown test of the first / second silicide barrier layer with a lateral width S of 0.2μm, 0.3μm, 0.4μm, and 0.5μm is shown. The ESD protection device structure provided by the present application can flexibly adjust the breakdown voltage of the device by adjusting the lateral width S of the first silicide barrier layer between the floating heavily doped region 1 and the floating heavily doped region 3 and the lateral width of the second silicide barrier layer between the floating heavily doped region 2 and the floating heavily doped region 4. Further, refer to Figure 4 When the lateral width S of the first / second silicide barrier layer is 0.2 μm, its maintenance voltage Vh is greater than 15.6 V and close to the turn-on voltage (also called ESD trigger voltage) Vt1, where the turn-on voltage Vt1 = 17.4 V. The ESD protection device structure provided in the present application can be used as 7V~12V ESD protection, and there is basically no latch-up risk.

[0029] Furthermore, the ESD protection device with an SCR structure may also include: a substrate lead-out doping region (not shown), the substrate lead-out doping region surrounds the periphery of the internal heavily doped region six 26, the conductivity type of the doped ions in the substrate lead-out doping region is the same as the doping type of the substrate, and the substrate lead-out doping region is used to lead out the bottom substrate (PSUB). Embodiment 2

[0030] Embodiment 2 of the present application provides an ESD protection device with an SCR structure, referring to Figure 5 , Figure 5 It is a structural schematic diagram of an ESD protection device with an SCR structure according to a second embodiment of the present invention, wherein the ESD protection device with an SCR structure includes: a substrate 10, a well region 11 of a first conductivity type, a well region 12 of a second conductivity type, an internal heavily doped region 1 21 of a first conductivity type, an internal heavily doped region 2 22 and an internal heavily doped region 3 23, an internal heavily doped region 4 24 of a second conductivity type, an internal heavily doped region 5 25 and an internal heavily doped region 6 26, a floating heavily doped region 1 31 and a floating heavily doped region 2 32 of a first conductivity type, a floating heavily doped region 3 33 and a floating heavily doped region 4 34 of a second conductivity type, a plurality of shallow trench isolation structures 40, a first silicide barrier layer 51 and a second silicide barrier layer 52.

[0031] in, The well region 11 is in a strip shape, and the well region 11 is located in the substrate 10; The second well region 12 is ring-shaped, and the second well region 12 is located in the substrate 10 and is arranged around the first well region 11; The internal heavily doped region 1 21 is located in the well region 1 11, the internal heavily doped region 2 22 and the internal heavily doped region 3 23 are located on both sides of the internal heavily doped region 1 21 (the internal heavily doped region 2 22 and the internal heavily doped region 3 23 are located on both sides of the well region 1 11) and are both located in the well region 2 12; The internal heavily doped region four 24 and the internal heavily doped region five 25 are located at both sides of the internal heavily doped region one 21 and are both located in the well region one 11, the internal heavily doped region six 26 is located in the well region two 12 and the internal heavily doped region six 26 is arranged around the internal heavily doped region two 22 and the internal heavily doped region three 23; wherein the internal heavily doped region one 21, the internal heavily doped region two 22, the internal heavily doped region three 23, the internal heavily doped region four 24, the internal heavily doped region five 25 and the internal heavily doped region six 26 are all in strip shape; The floating heavily doped region 1 31 is located at the side of the internal heavily doped region 4 24 away from the internal heavily doped region 1 21, and the floating heavily doped region 1 31 spans the left edge of the well region 1 11 and the substrate 10; the floating heavily doped region 2 32 is located at the side of the internal heavily doped region 5 25 away from the internal heavily doped region 1 21, and the floating heavily doped region 2 32 spans the right edge of the well region 1 11 and the substrate 10; The floating heavily doped region three 33 is located at the side of the internal heavily doped region two 22 away from the internal heavily doped region six 26, and the floating heavily doped region three 33 spans the inner edge of the well region two 12 and the substrate 10; the floating heavily doped region four 34 is located at the side of the internal heavily doped region three 23 away from the internal heavily doped region six 26, and the floating heavily doped region four 34 spans the inner edge of the well region two 12 and the substrate 10; wherein the floating heavily doped region one 31, the floating heavily doped region two 32, the floating heavily doped region three 33 and the floating heavily doped region four 34 are all in strip shape; Part of the shallow trench isolation structure 40 is located in the well region 11, and is used for isolation between the floating heavily doped region 1 31, the internal heavily doped region 4 24, the internal heavily doped region 1 21, the internal heavily doped region 5 25, and the floating heavily doped region 2 32; the remaining part of the shallow trench isolation structure 40 is located in the well region 2 12, and is used for isolation between the internal heavily doped region 6 26, the internal heavily doped region 2 22, and the floating heavily doped region 3 33, and is used for isolation between the internal heavily doped region 6 26, the internal heavily doped region 3 23, and the floating heavily doped region 4 34; The first silicide barrier layer 51 covers the substrate 10 between the floating heavily doped region 1 31 and the floating heavily doped region 3 33 ; The second silicide barrier layer 52 covers the substrate 10 between the second floating heavily doped region 32 and the fourth floating heavily doped region 34; Among them, the internal heavily doped region two 22, the internal heavily doped region three 23 and the internal heavily doped region six 26 are all connected to the anode (High) of the external power supply; the internal heavily doped region one 21, the internal heavily doped region four 24, the internal heavily doped region five 25, the first silicide barrier layer 51 and the second silicide barrier layer 52 are all connected to the cathode (Low) of the external power supply.

[0032] In this embodiment, the first conductivity type is P type; the second conductivity type is N type.

[0033] Furthermore, the substrate 10 includes: a base 13 and an epitaxial layer 14 located on the base 13, the well region 11 and the well region 2 12 are both located in the epitaxial layer 14, the floating heavily doped region 1 31 spans the left edge of the well region 1 11 and the epitaxial layer 14, the floating heavily doped region 2 32 spans the right edge of the well region 1 11 and the epitaxial layer 14, the floating heavily doped region 3 33 spans the inner edge of the well region 2 12 and the epitaxial layer 14, and the floating heavily doped region 4 34 spans the inner edge of the well region 2 12 and the epitaxial layer 14.

[0034] In this embodiment, the conductivity type of the doped ions in the substrate 13 is the first conductivity type, and the conductivity type of the doped ions in the epitaxial layer 14 is the first conductivity type.

[0035] Preferably, the ESD protection device with the SCR structure may further include: a buried layer (NBL) 15 of the second conductivity type, wherein the buried layer 15 is located in the substrate 13 and a front surface of the buried layer 15 contacts a back surface of the epitaxial layer 14 .

[0036] In the present application, the working principle of the ESD protection device of the second embodiment of the present application is the same as the working principle of the ESD protection device of the first embodiment, by respectively introducing a floating heavily doped region one and a floating heavily doped region two between the two side edges of the well region one and the substrate, and respectively introducing a floating heavily doped region three and a floating heavily doped region four between the inner edge of the well region two and the substrate, the first silicide barrier layer between the floating heavily doped region one and the floating heavily doped region three is connected to the power cathode, and the second silicide barrier layer between the floating heavily doped region two and the floating heavily doped region four is connected to the power cathode. At this time, the floating heavily doped region one, the floating heavily doped region three and the first silicide barrier layer are connected to the power cathode. The barrier layer forms a parasitic diode. Similarly, the floating heavily doped region two, the floating heavily doped region four and the second silicide barrier layer form a parasitic diode, wherein the SCR structure is formed by coupling the PNP transistor (P+ / NW / PW) and the NPN transistor (NW / PW / N+), the introduced floating heavily doped region three (N+) is part of the parasitic PNP transistor base; the introduced floating heavily doped region one (P+) is part of the NPN transistor base, which respectively leads to heavy doping of the bases of the PNP and NPN transistors, reducing the common emitter amplification factor β of the BJT (bipolar transistor), thereby effectively improving the holding voltage of the SCR structure. Since the ESD protection device provided in the present application is an axisymmetric structure (the center line of the internal heavily doped region one is the axis of symmetry), similarly, the floating heavily doped region four (N+) introduced on the right is part of the base of the parasitic PNP transistor; the introduced floating heavily doped region two (P+) is part of the base of the NPN transistor, which respectively leads to heavy doping of the bases of the PNP and NPN transistors, reducing the common emitter amplification factor β of the BJT (bipolar transistor), thereby effectively improving the holding voltage of the SCR structure.

[0037] Furthermore, in the advanced process, the first silicide barrier layer and the second silicide barrier layer can prevent the floating heavily doped region one and the floating heavily doped region three (the floating heavily doped region two and the floating heavily doped region four) from short-circuiting due to the metal silicide process. At the same time, the breakdown voltage of the SCR device can be controlled by adjusting the lateral width of the first silicide barrier layer between the floating heavily doped region one and the floating heavily doped region three and the lateral width of the second silicide barrier layer between the floating heavily doped region two and the floating heavily doped region four.

[0038] Among them, the parts not described in this embodiment 2 can refer to the embodiment 1 accordingly, and this embodiment 2 will not be repeated. Embodiment 3

[0039] Embodiment 3 of the present application provides an ESD protection device with an SCR structure, referring to Figure 6 , Figure 6It is a structural schematic diagram of an ESD protection device with an SCR structure according to embodiment three of the present invention, wherein the ESD protection device with an SCR structure includes: a substrate 10, a well region 11 of a first conductivity type, a well region 12 of a second conductivity type, an internal heavily doped region 1 21 of a first conductivity type, an internal heavily doped region 2 22 and an internal heavily doped region 3 23, an internal heavily doped region 4 24 of a second conductivity type, an internal heavily doped region 5 25 and an internal heavily doped region 6 26, a floating heavily doped region 1 31 and a floating heavily doped region 2 32 of a first conductivity type, a floating heavily doped region 3 33 and a floating heavily doped region 4 34 of a second conductivity type, a plurality of shallow trench isolation structures 40, a first silicide barrier layer 51 and a second silicide barrier layer 52.

[0040] in, The well region 11 is in a strip shape, and the well region 11 is located in the substrate 10; The second well region 12 is ring-shaped, and the second well region 12 is located in the substrate 10 and is arranged around the first well region 11; The internal heavily doped region 1 21 is located in the well region 1 11, the internal heavily doped region 2 22 and the internal heavily doped region 3 23 are located on both sides of the internal heavily doped region 1 21 (the internal heavily doped region 2 22 and the internal heavily doped region 3 23 are located on both sides of the well region 1 11) and are both located in the well region 2 12; The internal heavily doped region four 24 and the internal heavily doped region five 25 are located at both sides of the internal heavily doped region one 21 and are both located in the well region one 11, the internal heavily doped region six 26 is located in the well region two 12 and the internal heavily doped region six 26 is arranged around the internal heavily doped region two 22 and the internal heavily doped region three 23; wherein the internal heavily doped region one 21, the internal heavily doped region two 22, the internal heavily doped region three 23, the internal heavily doped region four 24, the internal heavily doped region five 25 and the internal heavily doped region six 26 are all in strip shape; The floating heavily doped region 1 31 is located at the side of the internal heavily doped region 4 24 away from the internal heavily doped region 1 21, and the floating heavily doped region 1 31 spans the left edge of the well region 1 11 and the substrate 10; the floating heavily doped region 2 32 is located at the side of the internal heavily doped region 5 25 away from the internal heavily doped region 1 21, and the floating heavily doped region 2 32 spans the right edge of the well region 1 11 and the substrate 10; The floating heavily doped region three 33 is located at the side of the internal heavily doped region two 22 away from the internal heavily doped region six 26, and the floating heavily doped region three 33 spans the inner edge of the well region two 12 and the substrate 10; the floating heavily doped region four 34 is located at the side of the internal heavily doped region three 23 away from the internal heavily doped region six 26, and the floating heavily doped region four 34 spans the inner edge of the well region two 12 and the substrate 10; wherein the floating heavily doped region one 31, the floating heavily doped region two 32, the floating heavily doped region three 33 and the floating heavily doped region four 34 are all in strip shape; Part of the shallow trench isolation structure 40 is located in the well region 11, and is used for isolation between the floating heavily doped region 1 31, the internal heavily doped region 4 24, the internal heavily doped region 1 21, the internal heavily doped region 5 25, and the floating heavily doped region 2 32; the remaining part of the shallow trench isolation structure 40 is located in the well region 2 12, and is used for isolation between the internal heavily doped region 6 26, the internal heavily doped region 2 22, and the floating heavily doped region 3 33, and is used for isolation between the internal heavily doped region 6 26, the internal heavily doped region 3 23, and the floating heavily doped region 4 34; The first silicide barrier layer 51 covers the substrate 10 between the floating heavily doped region 1 31 and the floating heavily doped region 3 33 ; The second silicide barrier layer 52 covers the substrate 10 between the second floating heavily doped region 32 and the fourth floating heavily doped region 34; Among them, the internal heavily doped region two 22, the internal heavily doped region three 23 and the internal heavily doped region six 26 are all connected to the anode (High) of the external power supply; the internal heavily doped region one 21, the internal heavily doped region four 24, the internal heavily doped region five 25, the first silicide barrier layer 51 and the second silicide barrier layer 52 are all connected to the cathode (Low) of the external power supply.

[0041] In this embodiment, the first conductivity type is P type; the second conductivity type is N type.

[0042] Furthermore, the substrate 10 includes: a base 13 and an epitaxial layer 14 located on the base 13, the well region 11 and the well region 2 12 are both located in the epitaxial layer 14, the floating heavily doped region 1 31 spans the left edge of the well region 1 11 and the epitaxial layer 14, the floating heavily doped region 2 32 spans the right edge of the well region 1 11 and the epitaxial layer 14, the floating heavily doped region 3 33 spans the inner edge of the well region 2 12 and the epitaxial layer 14, and the floating heavily doped region 4 34 spans the inner edge of the well region 2 12 and the epitaxial layer 14.

[0043] In this embodiment, the conductivity type of the doped ions in the substrate 13 is the first conductivity type, and the conductivity type of the doped ions in the epitaxial layer 14 is the first conductivity type.

[0044] Furthermore, the ESD protection device with the SCR structure may further include: a deep well (DNW) 16 of the second conductivity type, wherein the deep well 16 is located at the bottom of the epitaxial layer 14 and the back surface of the deep well 16 contacts the front surface of the substrate 13 .

[0045] In the present application, the working principle of the ESD protection device of the third embodiment of the present application is the same as the working principle of the ESD protection device of the first embodiment, by respectively introducing a floating heavily doped region one and a floating heavily doped region two between the two side edges of the well region one and the substrate, and respectively introducing a floating heavily doped region three and a floating heavily doped region four between the inner edge of the well region two and the substrate, the first silicide barrier layer between the floating heavily doped region one and the floating heavily doped region three is connected to the power cathode, and the second silicide barrier layer between the floating heavily doped region two and the floating heavily doped region four is connected to the power cathode. At this time, the floating heavily doped region one, the floating heavily doped region three and the first silicide barrier layer are connected to the power cathode. The barrier layer forms a parasitic diode. Similarly, the floating heavily doped region two, the floating heavily doped region four and the second silicide barrier layer form a parasitic diode, wherein the SCR structure is formed by coupling the PNP transistor (P+ / NW / PW) and the NPN transistor (NW / PW / N+), the introduced floating heavily doped region three (N+) is part of the parasitic PNP transistor base; the introduced floating heavily doped region one (P+) is part of the NPN transistor base, which respectively leads to heavy doping of the bases of the PNP and NPN transistors, reducing the common emitter amplification factor β of the BJT (bipolar transistor), thereby effectively improving the holding voltage of the SCR structure. Since the ESD protection device provided in the present application is an axisymmetric structure (the center line of the internal heavily doped region one is the axis of symmetry), similarly, the floating heavily doped region four (N+) introduced on the right is part of the base of the parasitic PNP transistor; the introduced floating heavily doped region two (P+) is part of the base of the NPN transistor, which respectively leads to heavy doping of the bases of the PNP and NPN transistors, reducing the common emitter amplification factor β of the BJT (bipolar transistor), thereby effectively improving the holding voltage of the SCR structure.

[0046] Furthermore, in the advanced process, the first silicide barrier layer and the second silicide barrier layer can prevent the floating heavily doped region one and the floating heavily doped region three (the floating heavily doped region two and the floating heavily doped region four) from short-circuiting due to the metal silicide process. At the same time, the breakdown voltage of the SCR device can be controlled by adjusting the lateral width of the first silicide barrier layer between the floating heavily doped region one and the floating heavily doped region three and the lateral width of the second silicide barrier layer between the floating heavily doped region two and the floating heavily doped region four.

[0047] Among them, the parts not described in this embodiment three can refer to the embodiment one accordingly, and this embodiment three will not be repeated. Embodiment 4

[0048] Embodiment 4 of the present application provides an ESD protection device with an SCR structure, referring to Figure 7 , Figure 7 It is a structural schematic diagram of an ESD protection device with an SCR structure according to a fourth embodiment of the present invention, wherein the ESD protection device with an SCR structure includes: a substrate 10, a well region 11 of a first conductivity type, a well region 12 of a second conductivity type, an internal heavily doped region 1 21 of a first conductivity type, an internal heavily doped region 2 22 and an internal heavily doped region 3 23, an internal heavily doped region 4 24 of a second conductivity type, an internal heavily doped region 5 25 and an internal heavily doped region 6 26, a floating heavily doped region 1 31 and a floating heavily doped region 2 32 of a first conductivity type, a floating heavily doped region 3 33 and a floating heavily doped region 4 34 of a second conductivity type, a plurality of shallow trench isolation structures 40, a first silicide barrier layer 51 and a second silicide barrier layer 52.

[0049] in, The well region 11 is in a strip shape, and the well region 11 is located in the substrate 10; The second well region 12 is ring-shaped, and the second well region 12 is located in the substrate 10 and is arranged around the first well region 11; The internal heavily doped region 1 21 is located in the well region 1 11, the internal heavily doped region 2 22 and the internal heavily doped region 3 23 are located on both sides of the internal heavily doped region 1 21 (the internal heavily doped region 2 22 and the internal heavily doped region 3 23 are located on both sides of the well region 1 11) and are both located in the well region 2 12; The internal heavily doped region four 24 and the internal heavily doped region five 25 are located at both sides of the internal heavily doped region one 21 and are both located in the well region one 11, the internal heavily doped region six 26 is located in the well region two 12 and the internal heavily doped region six 26 is arranged around the internal heavily doped region two 22 and the internal heavily doped region three 23; wherein the internal heavily doped region one 21, the internal heavily doped region two 22, the internal heavily doped region three 23, the internal heavily doped region four 24, the internal heavily doped region five 25 and the internal heavily doped region six 26 are all in strip shape; The floating heavily doped region 1 31 is located at the side of the internal heavily doped region 4 24 away from the internal heavily doped region 1 21, and the floating heavily doped region 1 31 spans the left edge of the well region 1 11 and the substrate 10; the floating heavily doped region 2 32 is located at the side of the internal heavily doped region 5 25 away from the internal heavily doped region 1 21, and the floating heavily doped region 2 32 spans the right edge of the well region 1 11 and the substrate 10; The floating heavily doped region three 33 is located at the side of the internal heavily doped region two 22 away from the internal heavily doped region six 26, and the floating heavily doped region three 33 spans the inner edge of the well region two 12 and the substrate 10; the floating heavily doped region four 34 is located at the side of the internal heavily doped region three 23 away from the internal heavily doped region six 26, and the floating heavily doped region four 34 spans the inner edge of the well region two 12 and the substrate 10; wherein the floating heavily doped region one 31, the floating heavily doped region two 32, the floating heavily doped region three 33 and the floating heavily doped region four 34 are all in strip shape; Part of the shallow trench isolation structure 40 is located in the well region 11, and is used for isolation between the floating heavily doped region 1 31, the internal heavily doped region 4 24, the internal heavily doped region 1 21, the internal heavily doped region 5 25, and the floating heavily doped region 2 32; the remaining part of the shallow trench isolation structure 40 is located in the well region 2 12, and is used for isolation between the internal heavily doped region 6 26, the internal heavily doped region 2 22, and the floating heavily doped region 3 33, and is used for isolation between the internal heavily doped region 6 26, the internal heavily doped region 3 23, and the floating heavily doped region 4 34; The first silicide barrier layer 51 covers the substrate 10 between the floating heavily doped region 1 31 and the floating heavily doped region 3 33 ; The second silicide barrier layer 52 covers the substrate 10 between the second floating heavily doped region 32 and the fourth floating heavily doped region 34; Among them, the internal heavily doped region two 22, the internal heavily doped region three 23 and the internal heavily doped region six 26 are all connected to the anode (High) of the external power supply; the internal heavily doped region one 21, the internal heavily doped region four 24, the internal heavily doped region five 25, the first silicide barrier layer 51 and the second silicide barrier layer 52 are all connected to the cathode (Low) of the external power supply.

[0050] In this embodiment, the first conductivity type is P type; the second conductivity type is N type.

[0051] Furthermore, the substrate 10 includes: a base 13 and an epitaxial layer 14 located on the base 13, the well region 11 and the well region 2 12 are both located in the epitaxial layer 14, the floating heavily doped region 1 31 spans the left edge of the well region 1 11 and the epitaxial layer 14, the floating heavily doped region 2 32 spans the right edge of the well region 1 11 and the epitaxial layer 14, the floating heavily doped region 3 33 spans the inner edge of the well region 2 12 and the epitaxial layer 14, and the floating heavily doped region 4 34 spans the inner edge of the well region 2 12 and the epitaxial layer 14.

[0052] In this embodiment, the conductivity type of the doped ions in the substrate 13 is the first conductivity type, and the conductivity type of the doped ions in the epitaxial layer 14 is the first conductivity type.

[0053] Furthermore, the ESD protection device with an SCR structure may also include: a buried layer 15 of a second conductivity type and a deep well 16 of a second conductivity type, wherein the buried layer 15 is located in the substrate 13 and the front side of the buried layer 15 contacts the back side of the epitaxial layer 14, and the deep well 16 is located in the epitaxial layer 14 and at the bottom of the well region 2 12.

[0054] In the present application, the working principle of the ESD protection device of the fourth embodiment of the present application is the same as the working principle of the ESD protection device of the first embodiment, by respectively introducing a floating heavily doped region one and a floating heavily doped region two between the two side edges of the well region one and the substrate, and respectively introducing a floating heavily doped region three and a floating heavily doped region four between the inner edge of the well region two and the substrate, the first silicide barrier layer between the floating heavily doped region one and the floating heavily doped region three is connected to the power cathode, and the second silicide barrier layer between the floating heavily doped region two and the floating heavily doped region four is connected to the power cathode. At this time, the floating heavily doped region one, the floating heavily doped region three and the first silicide barrier layer are connected to the power cathode. The barrier layer forms a parasitic diode. Similarly, the floating heavily doped region two, the floating heavily doped region four and the second silicide barrier layer form a parasitic diode, wherein the SCR structure is formed by coupling the PNP transistor (P+ / NW / PW) and the NPN transistor (NW / PW / N+), the introduced floating heavily doped region three (N+) is part of the parasitic PNP transistor base; the introduced floating heavily doped region one (P+) is part of the NPN transistor base, which respectively leads to heavy doping of the bases of the PNP and NPN transistors, reducing the common emitter amplification factor β of the BJT (bipolar transistor), thereby effectively improving the holding voltage of the SCR structure. Since the ESD protection device provided in the present application is an axisymmetric structure (the center line of the internal heavily doped region one is the axis of symmetry), similarly, the floating heavily doped region four (N+) introduced on the right is part of the base of the parasitic PNP transistor; the introduced floating heavily doped region two (P+) is part of the base of the NPN transistor, which respectively leads to heavy doping of the bases of the PNP and NPN transistors, reducing the common emitter amplification factor β of the BJT (bipolar transistor), thereby effectively improving the holding voltage of the SCR structure.

[0055] Furthermore, in the advanced process, the first silicide barrier layer and the second silicide barrier layer can prevent the floating heavily doped region one and the floating heavily doped region three (the floating heavily doped region two and the floating heavily doped region four) from short-circuiting due to the metal silicide process. At the same time, the breakdown voltage of the SCR device can be controlled by adjusting the lateral width of the first silicide barrier layer between the floating heavily doped region one and the floating heavily doped region three and the lateral width of the second silicide barrier layer between the floating heavily doped region two and the floating heavily doped region four.

[0056] Among them, the parts not described in this embodiment 4 can refer to the embodiment 1 accordingly, and this embodiment 4 will not be repeated.

[0057] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. An ESD protection device with an SCR structure, characterized in that: include: substrate; A well region 1 of a first conductivity type, the well region 1 being located in the substrate; A second well region of a second conductivity type, the second well region being located in the substrate and surrounding the first well region; An internal heavily doped region 1, an internal heavily doped region 2 and an internal heavily doped region 3 of a first conductivity type, wherein the internal heavily doped region 1 is located in the well region 1, and the internal heavily doped region 2 and the internal heavily doped region 3 are located at both sides of the internal heavily doped region 1 and are both located in the well region 2; An internal heavily doped region 4, an internal heavily doped region 5 and an internal heavily doped region 6 of the second conductivity type, wherein the internal heavily doped region 4 and the internal heavily doped region 5 are located at both sides of the internal heavily doped region 1 and are both located in the well region 1, and the internal heavily doped region 6 is located in the well region 2 and is arranged around the internal heavily doped region 2 and the internal heavily doped region 3; A floating heavily doped region 1 and a floating heavily doped region 2 of a first conductivity type, wherein the floating heavily doped region 1 is located at the fourth side of the internal heavily doped region away from the internal heavily doped region 1, and the floating heavily doped region 1 spans the left edge of the well region 1 and the substrate; the floating heavily doped region 2 is located at the fifth side of the internal heavily doped region away from the internal heavily doped region 1, and the floating heavily doped region 2 spans the right edge of the well region 1 and the substrate; a floating heavily doped region three and a floating heavily doped region four of the second conductivity type, wherein the floating heavily doped region three is located on the side of the internal heavily doped region two away from the internal heavily doped region six, and the floating heavily doped region three spans the inner edge of the well region two and the substrate; the floating heavily doped region four is located on the side of the internal heavily doped region three away from the internal heavily doped region six, and the floating heavily doped region four spans the inner edge of the well region two and the substrate; A plurality of shallow trench isolation structures, some of which are located in the well region 1 and are used to isolate different internal heavily doped regions and / or floating heavily doped regions; the remaining shallow trench isolation structures are located in the well region 2 and are used to isolate different internal heavily doped regions and / or floating heavily doped regions; A first silicide barrier layer, wherein the first silicide barrier layer covers the substrate between the first floating heavily doped region and the third floating heavily doped region; A second silicide barrier layer, wherein the second silicide barrier layer covers the substrate between the second floating heavily doped region and the fourth floating heavily doped region; Among them, the internal heavily doped region two, the internal heavily doped region three and the internal heavily doped region six are all connected to the anode of the external power supply; the internal heavily doped region one, the internal heavily doped region four, the internal heavily doped region five, the first silicide barrier layer and the second silicide barrier layer are all connected to the cathode of the external power supply.

2. The ESD protection device with SCR structure according to claim 1, characterized in that: The substrate includes: a base and an epitaxial layer located on the base, the well region 1 and the well region 2 are both located in the epitaxial layer, the floating heavily doped region 1 spans the left edge of the well region 1 and the epitaxial layer, the floating heavily doped region 2 spans the right edge of the well region 1 and the epitaxial layer, the floating heavily doped region 3 spans the inner edge of the well region 2 and the epitaxial layer, and the floating heavily doped region 4 spans the inner edge of the well region 2 and the epitaxial layer.

3. The ESD protection device with SCR structure according to claim 2, characterized in that: The ESD protection device with the SCR structure further includes: a buried layer of a second conductivity type, the buried layer is located in the substrate and a front surface of the buried layer contacts a back surface of the epitaxial layer.

4. The ESD protection device with SCR structure according to claim 2, characterized in that: The ESD protection device with the SCR structure further includes: a deep well of the second conductivity type, the deep well is located at the bottom of the epitaxial layer and the back side of the deep well contacts the front side of the substrate.

5. The ESD protection device with SCR structure according to claim 2, characterized in that: The ESD protection device with an SCR structure further includes: a buried layer of a second conductivity type and a deep well of a second conductivity type, wherein the buried layer is located in the substrate and a front side of the buried layer contacts a back side of the epitaxial layer, and the deep well is located in the epitaxial layer and at the bottom of the well region two.

6. The ESD protection device with SCR structure according to claim 2, characterized in that: The conductivity type of the doped ions in the substrate is the first conductivity type, and the conductivity type of the doped ions in the epitaxial layer is the first conductivity type.

7. The ESD protection device with SCR structure according to claim 1, characterized in that: The first silicide barrier layer and the second silicide barrier layer are both made of polysilicon.

8. The ESD protection device with an SCR structure according to any one of claims 1 to 7, characterized in that: The first conductivity type is P type; the second conductivity type is N type.

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