ESD protection device

Abstract

The invention provides an ESD (Electro-Static Discharge) protection device, which is characterized in that a functional region of the ESD device is prepared in the same active region, and specifically, an internal well region I or an annular well region NW / an internal well region II PW / a peripheral heavily doped region N + / an internal heavily doped region P + is arranged in the same active region; in order to prevent the short circuit between the anode High and the cathode Low caused by the metal silicide in the advanced process, the metal silicide barrier layer is adopted for isolation, and the metal silicide is prevented from being formed between the anode and the cathode. In the ESD protection device provided by the invention, a shallow trench isolation structure is not arranged on a path for discharging an ESD current, that is, the ESD current does not need to bypass the shallow trench isolation structure like a traditional ESD device, so that the ESD current has a shorter current path, that is, the on resistance of the device is smaller, the effective area of ESD protection is wider, and the ESD protection efficiency is improved. Therefore, the performance of the ESD protection device with the PNP structure can be fully exerted.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to an ESD protection device. Background Art

[0002] ESD (electrostatic discharge) devices with PNP structure play an important role in the field of electrostatic protection. Due to their high holding voltage (Vh) characteristics, there is basically no latch-up risk and they are often used for electrostatic protection of high-voltage ports.

[0003] However, in traditional ESD devices with a PNP structure, the on-resistance of the high-voltage PNP transistor is large, and the limit capability exceeds the ESD design window. Specifically, the PNP failure voltage is greater than the internal failure voltage, the effective area of ​​​​the ESD protection is small, and the full performance of the PNP cannot be exerted. That is, even if the ESD device with a PNP structure is turned on to discharge the ESD current, it cannot exert its limit performance, and the internal device or circuit fails due to static electricity. Summary of the invention

[0004] The present application provides an ESD protection device, which can solve the problem of large on-resistance of a traditional ESD device with a PNP structure.

[0005] The embodiment of the present application provides an ESD protection device, including: substrate; At least one first conductivity type internal well region 1, the internal well region 1 being spaced apart and located in the substrate; A plurality of second conductive type internal well regions 2, the internal well regions 2 being spaced apart in the substrate and respectively located between two adjacent internal well regions 1; A ring-shaped well region of a first conductivity type, the ring-shaped well region being located in the substrate and surrounding the outermost inner well region 2; a substrate lead-out well region of a second conductivity type, the substrate lead-out well region being located in the substrate and surrounding the annular well region; A plurality of second conductivity type internal heavily doped regions, the internal heavily doped regions being located in the first internal well region, the second internal well region and the annular well region; A peripheral heavily doped region of a first conductivity type, the peripheral heavily doped region being located in the annular well region, the peripheral heavily doped region being arranged around the inner heavily doped region in the annular well region and being spaced apart from the inner heavily doped region in the annular well region; A substrate lead-out heavily doped region of a second conductivity type, wherein the substrate lead-out heavily doped region is located in the substrate lead-out well region; A plurality of shallow trench isolation structures, at least one of the shallow trench isolation structures is located in the annular well region and between the peripheral heavily doped region and the internal heavily doped region in the annular well region, and at least one of the shallow trench isolation structures is located between the peripheral heavily doped region and the substrate lead-out heavily doped region; A metal silicide barrier layer, wherein the metal silicide barrier layer covers surfaces of the substrate, the annular well region, the first inner well region, and the second inner well region between all the inner heavily doped regions; Among them, the peripheral heavily doped region, the internal heavily doped region in the annular well region and the internal heavily doped region in the internal well region one are connected to the anode of an external power supply, and the internal heavily doped region in the internal well region two and the substrate lead-out heavily doped region are connected to the cathode of an external power supply, wherein a shallow trench isolation structure is not arranged on the path for discharging ESD current in the substrate.

[0006] Optionally, in the ESD protection device, the staggered internal well region 1 and the internal well region 2 are an axially symmetrical structure, wherein the central axis of the axially symmetrical structure is one of the internal well regions 1, and the outermost portion of the axially symmetrical structure is two of the internal well regions 2.

[0007] Optionally, in the ESD protection device, the substrate includes: a base and an epitaxial layer located on the base, and the internal well region 1, the internal well region 2, the annular well region and the substrate lead-out well region are all located in the epitaxial layer.

[0008] Optionally, in the ESD protection device, the ESD protection device further includes: a buried layer of the first conductive type, the buried layer is located in the substrate and the front side of the buried layer contacts the bottom surface of the internal well region 1 in the epitaxial layer and the bottom surface of the annular well region.

[0009] Optionally, in the ESD protection device, the ESD protection device further includes: a deep well of the first conductivity type, the deep well being located at the bottom of the epitaxial layer and contacting the bottom surface of the internal well region 1 in the epitaxial layer and the bottom surface of the annular well region.

[0010] Optionally, in the ESD protection device, the ESD protection device also includes: a buried layer of the first conductivity type and a deep well of the first conductivity type, the deep well being located at the bottom of the epitaxial layer and contacting the bottom surface of an internal well region 1 in the epitaxial layer and the bottom surface of the annular well region, the buried layer being located in the substrate and the front surface of the buried layer contacting the bottom surface of the deep well in the epitaxial layer.

[0011] Optionally, in the ESD protection device, the conductivity type of the doped ions in the substrate is the second conductivity type.

[0012] Optionally, in the ESD protection device, the first conductivity type is N-type; and the second conductivity type is P-type.

[0013] The technical solution of this application has at least the following advantages: The present application provides an ESD protection device. The present application prepares the functional areas of the ESD device in the same active area. Specifically, by setting the internal well area one or the annular well area NW / internal well area two PW / peripheral heavily doped area N+ / internal heavily doped area P+ in the same active area, in order to prevent the metal silicide in the advanced process from causing a short circuit between the anode High and the cathode Low, a metal silicide barrier layer is used for isolation to prevent the formation of metal silicide between the anode and the cathode. In the ESD protection device provided by the present application, there is no shallow trench isolation structure on the path of discharging the ESD current, that is, the ESD current does not need to bypass the shallow trench isolation structure like the traditional ESD device, so that the ESD current has a shorter current path, that is, the on-resistance of the device is smaller, and the effective area of ​​ESD protection is wider, so that the performance of the ESD protection device with a PNP structure can be fully utilized. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0015] Figure 1 is a schematic structural diagram of an ESD protection device according to a first embodiment of the present invention; Figure 2 Schematic diagram of the working principle of the ESD protection device according to the first embodiment of the present invention; Figure 3 It is a schematic diagram comparing TLP test curves of a conventional ESD protection device with a PNP structure according to Embodiment 1 of the present invention and the ESD protection device provided by the present application; Figure 4 is a schematic structural diagram of an ESD protection device according to a second embodiment of the present invention; Figure 5 is a schematic structural diagram of an ESD protection device according to a third embodiment of the present invention; Figure 6 is a schematic structural diagram of an ESD protection device according to a fourth embodiment of the present invention; The reference numerals are described as follows: 10-substrate, 71-base, 72-epitaxial layer; 11-internal well region 1, 12-internal well region 2, 13-annular well region, 14-substrate lead-out well region, 15-buried layer, 16-deep well; 20 - internal heavily doped region, 30 - peripheral heavily doped region, 40 - substrate lead-out heavily doped region, 50 - shallow trench isolation structure, 60 - metal silicide barrier layer. DETAILED DESCRIPTION

[0016] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0017] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0018] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0019] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. Embodiment 1

[0020] The present application embodiment provides an ESD protection device, referring to Figure 1 , Figure 1 : is a schematic diagram of the structure of an ESD protection device according to Embodiment 1 of the present invention, the ESD protection device comprises: Substrate 10; At least one first conductivity type internal well region 11, wherein the internal well region 11 is spaced apart and located in the substrate 10; A plurality of second conductive type internal well regions 12, wherein the second internal well regions 12 are spaced apart in the substrate 10 and are respectively located between two adjacent ones of the first internal well regions 11; A first conductivity type annular well region 13, the annular well region 13 is located in the substrate 10 and surrounds the outermost inner well region 2 12; A substrate lead-out well region 14 of a second conductivity type, wherein the substrate lead-out well region 14 is located in the substrate 10 and surrounds the annular well region 13; A plurality of second conductivity type internal heavily doped regions 20, wherein the internal heavily doped regions 20 are located in the internal well region 11, the internal well region 2 12 and the annular well region 13; A peripheral heavily doped region 30 of a first conductivity type, the peripheral heavily doped region 30 being located in the annular well region 13, the peripheral heavily doped region 30 being arranged around the inner heavily doped region 20 in the annular well region 13 and being spaced apart from the inner heavily doped region 20 in the annular well region 13; A substrate lead-out heavily doped region 40 of a second conductivity type, wherein the substrate lead-out heavily doped region 40 is located in the substrate lead-out well region 14; A plurality of shallow trench isolation structures 50, at least one of the shallow trench isolation structures 50 is located in the annular well region 13 and between the peripheral heavily doped region 30 and the internal heavily doped region 20 in the annular well region 13, and at least one of the shallow trench isolation structures 50 is located between the peripheral heavily doped region 30 and the substrate lead-out heavily doped region 40; A metal silicide barrier layer 60, wherein the metal silicide barrier layer 60 covers surfaces of the substrate 10, the annular well region 13, the inner well region 11 and the inner well region 2 12 between all the inner heavily doped regions 20; Among them, the peripheral heavily doped region 30, the internal heavily doped region 20 in the annular well region 13 and the internal heavily doped region 20 in the internal well region 11 are connected to the anode (High) of the external power supply, and the internal heavily doped region 20 in the internal well region 2 12 and the substrate lead-out heavily doped region 40 are connected to the cathode (Low) of the external power supply, wherein no shallow trench isolation structure is set on the path for discharging the ESD current in the substrate, that is, no shallow trench isolation structure is set between the internal heavily doped region 20 connected to the anode and the internal heavily doped region 20 connected to the cathode.

[0021] Preferably, the internal well region 11 and the internal well region 2 12 are both strip-shaped, and the annular well region 13 and the substrate lead-out well region 14 are both ring-shaped; further, the internal heavily doped region 20 is strip-shaped, and the peripheral heavily doped region 30 and the substrate lead-out heavily doped region 40 are both ring-shaped.

[0022] In this embodiment, the internal well region one (NW) 11 or the annular well region (NW) 13 / the internal well region two (PW) 12 / the peripheral heavily doped region N+30 / the internal heavily doped region P+20 are located in the same active area, that is, the internal well region one (NW) 11 or the annular well region (NW) 13 / the internal well region two (PW) 12 / the peripheral heavily doped region N+30 / the internal heavily doped region P+20 are located in the same active area of ​​the functional area for preparing the ESD device.

[0023] Preferably, the staggered internal well region 1 1 and the internal well region 2 12 are an axisymmetric structure, wherein the central axis of the symmetrical structure is one of the internal well regions 11 , and the outermost part of the symmetrical structure is the two internal well regions 2 12 .

[0024] refer to Figure 1 In this embodiment, the ESD protection device includes: an internal well region 11 and two internal well regions 12 as an example, and the two internal well regions 12 are respectively arranged on both sides of the internal well region 11.

[0025] Furthermore, the conductivity type of the doped ions in the substrate 10 is the second conductivity type.

[0026] In this embodiment, the first conductivity type is N type; the second conductivity type is P type. The substrate 10 can be referred to as Psub; the internal well region 11 and the ring well region can be referred to as NW; the internal well region 2 12 and the substrate lead-out well region 14 can be referred to as PW; the internal heavily doped region 20 and the substrate lead-out heavily doped region 40 can be referred to as P+; and the peripheral heavily doped region 30 can be referred to as N+.

[0027] Preferably, the metal silicide blocking layer (SAB) 60 may be stacked silicon dioxide and silicon nitride, wherein silicon nitride is stacked on silicon dioxide.

[0028] refer to Figure 2 , Figure 2 This is a schematic diagram of the working principle of the ESD protection device of the first embodiment of the present invention. In the present application, an internal well region NW or an annular well region NW / internal well region PW / peripheral heavily doped region N+ / internal heavily doped region P+ are set in the same active region, wherein the internal heavily doped region (P+) 20-annular well region (NW) 13-internal well region 2 (PW) 12 / internal heavily doped region (P+) 20 constitutes a PNP transistor, and the internal heavily doped region (P+) 20 / internal well region 2 (PW)-internal well region 1 (NW) 11-internal well region 2 (PW) 12 also constitutes a PNP transistor. Further, as Figure 2As shown, in order to prevent the metal silicide in the advanced process from causing a short circuit between the anode High and the cathode Low, a metal silicide barrier layer is used for isolation to prevent the formation of metal silicide on the substrate surface between the anode and the cathode. In the ESD protection device provided by the present application, there is no shallow trench isolation structure on the path of discharging the ESD current, that is, the ESD current does not need to bypass the shallow trench isolation structure like a traditional ESD device, so that the ESD current has a shorter current path, that is, the on-resistance of the device is smaller, and the effective area of ​​ESD protection is wider, so that the performance of the ESD protection device with a PNP structure can be fully utilized.

[0029] refer to Figure 3 , Figure 3 It is a schematic diagram comparing the TLP test curves of the traditional ESD protection device with a PNP structure in Example 1 of the present invention and the ESD protection device provided in the present application. Under the same size, the on-resistance of the ESD protection device provided in the present application is significantly smaller than the on-resistance of the traditional ESD protection device with a PNP structure, and the effective area that can be used for ESD protection is wider and the performance is better. Embodiment 2

[0030] Embodiment 2 of the present application provides an ESD protection device, referring to Figure 4 , Figure 4 : is a schematic diagram of the structure of an ESD protection device according to the second embodiment of the present invention, the ESD protection device comprises: Substrate 10; At least one first conductivity type internal well region 11, wherein the internal well region 11 is spaced apart and located in the substrate 10; A plurality of second conductive type internal well regions 12, wherein the second internal well regions 12 are spaced apart in the substrate 10 and are respectively located between two adjacent ones of the first internal well regions 11; A first conductivity type annular well region 13, the annular well region 13 is located in the substrate 10 and surrounds the outermost inner well region 2 12; A substrate lead-out well region 14 of a second conductivity type, wherein the substrate lead-out well region 14 is located in the substrate 10 and surrounds the annular well region 13; A plurality of second conductivity type internal heavily doped regions 20, wherein the internal heavily doped regions 20 are located in the internal well region 11, the internal well region 2 12 and the annular well region 13; A peripheral heavily doped region 30 of a first conductivity type, the peripheral heavily doped region 30 being located in the annular well region 13, the peripheral heavily doped region 30 being arranged around the inner heavily doped region 20 in the annular well region 13 and being spaced apart from the inner heavily doped region 20 in the annular well region 13; A substrate lead-out heavily doped region 40 of a second conductivity type, wherein the substrate lead-out heavily doped region 40 is located in the substrate lead-out well region 14; A plurality of shallow trench isolation structures 50, at least one of the shallow trench isolation structures 50 is located in the annular well region 13 and between the peripheral heavily doped region 30 and the internal heavily doped region 20 in the annular well region 13, and at least one of the shallow trench isolation structures 50 is located between the peripheral heavily doped region 30 and the substrate lead-out heavily doped region 40; A metal silicide barrier layer 60, wherein the metal silicide barrier layer 60 covers surfaces of the substrate 10, the annular well region 13, the inner well region 11 and the inner well region 2 12 between all the inner heavily doped regions 20; Among them, the peripheral heavily doped region 30, the internal heavily doped region 20 in the annular well region 13 and the internal heavily doped region 20 in the internal well region 11 are connected to the anode (High) of the external power supply, and the internal heavily doped region 20 in the internal well region 2 12 and the substrate lead-out heavily doped region 40 are connected to the cathode (Low) of the external power supply, wherein no shallow trench isolation structure is set on the path for discharging the ESD current in the substrate, that is, no shallow trench isolation structure is set between the internal heavily doped region 20 connected to the anode and the internal heavily doped region 20 connected to the cathode.

[0031] Furthermore, the substrate 10 includes: a base 71 and an epitaxial layer 72 located on the base 71 , and the internal well region 1 11 , the internal well region 2 12 , the annular well region 13 and the substrate lead-out well region 14 are all located in the epitaxial layer 72 .

[0032] Preferably, the ESD protection device also includes: a buried layer 15 of a first conductive type, the buried layer 15 is located in the substrate 71 and the front side of the buried layer 15 contacts the bottom surface of the internal well region 11 in the epitaxial layer 72 and the bottom surface of the annular well region 13, wherein the buried layer 15 plays an isolation role.

[0033] Preferably, the staggered internal well region 1 1 and the internal well region 2 12 are an axisymmetric structure, wherein the central axis of the symmetrical structure is one of the internal well regions 11 , and the outermost part of the symmetrical structure is the two internal well regions 2 12 .

[0034] refer to Figure 4 In this embodiment, the ESD protection device includes: an internal well region 11 and two internal well regions 12 as an example, and the two internal well regions 12 are respectively arranged on both sides of the internal well region 11.

[0035] Furthermore, the conductivity types of the doped ions in the substrate 71 and the epitaxial layer 72 are both the second conductivity type.

[0036] In this embodiment, the first conductivity type is N type; the second conductivity type is P type. The substrate 10 and the base 71 can be referred to as Psub; the internal well region 11 and the annular well region can be referred to as NW; the internal well region 2 12 and the substrate lead well region 14 can be referred to as PW; the internal heavily doped region 20 and the substrate lead heavily doped region 40 can be referred to as P+; the peripheral heavily doped region 30 can be referred to as N+, the epitaxial layer can be referred to as PEPI; the buried layer 15 can be referred to as NBL; and the deep well can be referred to as DNW.

[0037] In the present application, the working principle of the ESD protection device of the second embodiment of the present application is the same as the working principle of the ESD protection device of the first embodiment. In the present embodiment, an internal well region NW or an annular well region NW / internal well region PW / peripheral heavily doped region N+ / internal heavily doped region P+ is set in the same active area, wherein the internal heavily doped region (P+) 20-annular well region (NW) 13-internal well region 2 (PW) 12 / internal heavily doped region (P+) 20 constitutes a PNP triode, and the internal heavily doped region (P+) 20 / internal well region 2 (PW)-internal well region 1 (NW) 11-internal well region 2 (PW) 12 also constitutes a PNP triode. Further, in order to prevent the metal silicide in the advanced process from causing a short circuit between the anode High and the cathode Low, a metal silicide barrier layer is used for isolation to prevent the formation of metal silicide on the substrate surface between the anode and the cathode. In the ESD protection device provided in this embodiment, no shallow trench isolation structure is set on the path for discharging the ESD current, that is, the ESD current does not need to bypass the shallow trench isolation structure like a traditional ESD device, so that the ESD current has a shorter current path, that is, the on-resistance of the device is smaller and the effective area of ​​​​the ESD protection is wider, so that the performance of the ESD protection device with a PNP structure can be fully utilized.

[0038] Among them, the parts not described in this embodiment 2 can refer to the embodiment 1 accordingly, and this embodiment 2 will not be repeated. Embodiment 3

[0039] Embodiment 3 of the present application provides an ESD protection device, referring to Figure 5 , Figure 5 : is a schematic diagram of the structure of an ESD protection device according to Embodiment 3 of the present invention, wherein the ESD protection device comprises: Substrate 10; At least one first conductivity type internal well region 11, wherein the internal well region 11 is spaced apart and located in the substrate 10; A plurality of second conductive type internal well regions 12, wherein the second internal well regions 12 are spaced apart in the substrate 10 and are respectively located between two adjacent ones of the first internal well regions 11; A first conductivity type annular well region 13, the annular well region 13 is located in the substrate 10 and surrounds the outermost inner well region 2 12; A substrate lead-out well region 14 of a second conductivity type, wherein the substrate lead-out well region 14 is located in the substrate 10 and surrounds the annular well region 13; A plurality of second conductivity type internal heavily doped regions 20, wherein the internal heavily doped regions 20 are located in the internal well region 11, the internal well region 2 12 and the annular well region 13; A peripheral heavily doped region 30 of a first conductivity type, the peripheral heavily doped region 30 being located in the annular well region 13, the peripheral heavily doped region 30 being arranged around the inner heavily doped region 20 in the annular well region 13 and being spaced apart from the inner heavily doped region 20 in the annular well region 13; A substrate lead-out heavily doped region 40 of a second conductivity type, wherein the substrate lead-out heavily doped region 40 is located in the substrate lead-out well region 14; A plurality of shallow trench isolation structures 50, at least one of the shallow trench isolation structures 50 is located in the annular well region 13 and between the peripheral heavily doped region 30 and the internal heavily doped region 20 in the annular well region 13, and at least one of the shallow trench isolation structures 50 is located between the peripheral heavily doped region 30 and the substrate lead-out heavily doped region 40; A metal silicide barrier layer 60, wherein the metal silicide barrier layer 60 covers surfaces of the substrate 10, the annular well region 13, the inner well region 11 and the inner well region 2 12 between all the inner heavily doped regions 20; Among them, the peripheral heavily doped region 30, the internal heavily doped region 20 in the annular well region 13 and the internal heavily doped region 20 in the internal well region 11 are connected to the anode (High) of the external power supply, and the internal heavily doped region 20 in the internal well region 2 12 and the substrate lead-out heavily doped region 40 are connected to the cathode (Low) of the external power supply, wherein no shallow trench isolation structure is set on the path for discharging the ESD current in the substrate, that is, no shallow trench isolation structure is set between the internal heavily doped region 20 connected to the anode and the internal heavily doped region 20 connected to the cathode.

[0040] Furthermore, the substrate 10 includes: a base 71 and an epitaxial layer 72 located on the base 71 , and the internal well region 1 11 , the internal well region 2 12 , the annular well region 13 and the substrate lead-out well region 14 are all located in the epitaxial layer 72 .

[0041] Preferably, the ESD protection device also includes: a deep well 16 of the first conductive type, the deep well 16 is located at the bottom of the epitaxial layer 72 and contacts the bottom surface of the internal well region 11 in the epitaxial layer 72 and the bottom surface of the annular well region 13, wherein the deep well 16 plays an isolation role.

[0042] Preferably, the staggered internal well region 1 1 and the internal well region 2 12 are an axisymmetric structure, wherein the central axis of the symmetrical structure is one of the internal well regions 11 , and the outermost part of the symmetrical structure is the two internal well regions 2 12 .

[0043] refer to Figure 5 In this embodiment, the ESD protection device includes: an internal well region 11 and two internal well regions 12 as an example, and the two internal well regions 12 are respectively arranged on both sides of the internal well region 11.

[0044] Furthermore, the conductivity types of the doped ions in the substrate 71 and the epitaxial layer 72 are both the second conductivity type.

[0045] In this embodiment, the first conductivity type is N type; the second conductivity type is P type. The substrate 10 and the base 71 can be referred to as Psub; the internal well region 11 and the annular well region can be referred to as NW; the internal well region 2 12 and the substrate lead well region 14 can be referred to as PW; the internal heavily doped region 20 and the substrate lead heavily doped region 40 can be referred to as P+; the peripheral heavily doped region 30 can be referred to as N+, the epitaxial layer can be referred to as PEPI; the buried layer 15 can be referred to as NBL; and the deep well can be referred to as DNW.

[0046] In the present application, the working principle of the ESD protection device of the third embodiment of the present application is the same as the working principle of the ESD protection device of the first embodiment. In the present embodiment, an internal well region NW or an annular well region NW / internal well region PW / peripheral heavily doped region N+ / internal heavily doped region P+ is set in the same active area, wherein the internal heavily doped region (P+) 20-annular well region (NW) 13-internal well region 2 (PW) 12 / internal heavily doped region (P+) 20 constitutes a PNP triode, and the internal heavily doped region (P+) 20 / internal well region 2 (PW)-internal well region 1 (NW) 11-internal well region 2 (PW) 12 also constitutes a PNP triode. Further, in order to prevent the metal silicide in the advanced process from causing a short circuit between the anode High and the cathode Low, a metal silicide barrier layer is used for isolation to prevent the formation of metal silicide on the substrate surface between the anode and the cathode. In the ESD protection device provided in this embodiment, no shallow trench isolation structure is set on the path for discharging the ESD current, that is, the ESD current does not need to bypass the shallow trench isolation structure like a traditional ESD device, so that the ESD current has a shorter current path, that is, the on-resistance of the device is smaller and the effective area of ​​​​the ESD protection is wider, so that the performance of the ESD protection device with a PNP structure can be fully utilized.

[0047] Among them, the parts not described in this embodiment three can refer to the embodiment one accordingly, and this embodiment three will not be repeated. Embodiment 4

[0048] Embodiment 4 of the present application provides an ESD protection device, referring to Figure 6 , Figure 6 : is a schematic diagram of the structure of an ESD protection device according to a fourth embodiment of the present invention, wherein the ESD protection device comprises: Substrate 10; At least one first conductivity type internal well region 11, wherein the internal well region 11 is spaced apart and located in the substrate 10; A plurality of second conductive type internal well regions 12, wherein the second internal well regions 12 are spaced apart in the substrate 10 and are respectively located between two adjacent ones of the first internal well regions 11; A first conductivity type annular well region 13, the annular well region 13 is located in the substrate 10 and surrounds the outermost inner well region 2 12; A substrate lead-out well region 14 of a second conductivity type, wherein the substrate lead-out well region 14 is located in the substrate 10 and surrounds the annular well region 13; A plurality of second conductivity type internal heavily doped regions 20, wherein the internal heavily doped regions 20 are located in the internal well region 11, the internal well region 2 12 and the annular well region 13; A peripheral heavily doped region 30 of a first conductivity type, the peripheral heavily doped region 30 being located in the annular well region 13, the peripheral heavily doped region 30 being arranged around the inner heavily doped region 20 in the annular well region 13 and being spaced apart from the inner heavily doped region 20 in the annular well region 13; A substrate lead-out heavily doped region 40 of a second conductivity type, wherein the substrate lead-out heavily doped region 40 is located in the substrate lead-out well region 14; A plurality of shallow trench isolation structures 50, at least one of the shallow trench isolation structures 50 is located in the annular well region 13 and between the peripheral heavily doped region 30 and the internal heavily doped region 20 in the annular well region 13, and at least one of the shallow trench isolation structures 50 is located between the peripheral heavily doped region 30 and the substrate lead-out heavily doped region 40; A metal silicide barrier layer 60, wherein the metal silicide barrier layer 60 covers surfaces of the substrate 10, the annular well region 13, the inner well region 11 and the inner well region 2 12 between all the inner heavily doped regions 20; Among them, the peripheral heavily doped region 30, the internal heavily doped region 20 in the annular well region 13 and the internal heavily doped region 20 in the internal well region 11 are connected to the anode (High) of the external power supply, and the internal heavily doped region 20 in the internal well region 2 12 and the substrate lead-out heavily doped region 40 are connected to the cathode (Low) of the external power supply, wherein no shallow trench isolation structure is set on the path for discharging the ESD current in the substrate, that is, no shallow trench isolation structure is set between the internal heavily doped region 20 connected to the anode and the internal heavily doped region 20 connected to the cathode.

[0049] Furthermore, the substrate 10 includes: a base 71 and an epitaxial layer 72 located on the base 71 , and the internal well region 1 11 , the internal well region 2 12 , the annular well region 13 and the substrate lead-out well region 14 are all located in the epitaxial layer 72 .

[0050] Preferably, the ESD protection device also includes: a buried layer 15 of the first conductive type and a deep well 16 of the first conductive type, the deep well 15 is located at the bottom of the epitaxial layer 72 and contacts the bottom surface of the internal well region 11 in the epitaxial layer 72 and the bottom surface of the annular well region 13, the buried layer 15 is located in the substrate 71 and the front surface of the buried layer 15 contacts the bottom surface of the deep well 16 in the epitaxial layer 72, wherein the buried layer 15 and the deep well 16 both play an isolation role.

[0051] Preferably, the staggered internal well region 1 1 and the internal well region 2 12 are an axisymmetric structure, wherein the central axis of the symmetrical structure is one of the internal well regions 11 , and the outermost part of the symmetrical structure is the two internal well regions 2 12 .

[0052] refer to Figure 6 In this embodiment, the ESD protection device includes: an internal well region 11 and two internal well regions 12 as an example, and the two internal well regions 12 are respectively arranged on both sides of the internal well region 11.

[0053] Furthermore, the conductivity types of the doped ions in the substrate 71 and the epitaxial layer 72 are both the second conductivity type.

[0054] In this embodiment, the first conductivity type is N type; the second conductivity type is P type. The substrate 10 and the base 71 can be referred to as Psub; the internal well region 11 and the annular well region can be referred to as NW; the internal well region 2 12 and the substrate lead well region 14 can be referred to as PW; the internal heavily doped region 20 and the substrate lead heavily doped region 40 can be referred to as P+; the peripheral heavily doped region 30 can be referred to as N+, the epitaxial layer can be referred to as PEPI; the buried layer 15 can be referred to as NBL; and the deep well can be referred to as DNW.

[0055] In the present application, the working principle of the ESD protection device of the fourth embodiment of the present application is the same as the working principle of the ESD protection device of the first embodiment. In the present embodiment, an internal well region NW or an annular well region NW / internal well region PW / peripheral heavily doped region N+ / internal heavily doped region P+ is set in the same active area, wherein the internal heavily doped region (P+) 20-annular well region (NW) 13-internal well region 2 (PW) 12 / internal heavily doped region (P+) 20 constitutes a PNP triode, and the internal heavily doped region (P+) 20 / internal well region 2 (PW)-internal well region 1 (NW) 11-internal well region 2 (PW) 12 also constitutes a PNP triode. Further, in order to prevent the metal silicide in the advanced process from causing a short circuit between the anode High and the cathode Low, a metal silicide barrier layer is used for isolation to prevent the formation of metal silicide on the substrate surface between the anode and the cathode. In the ESD protection device provided in this embodiment, no shallow trench isolation structure is set on the path for discharging the ESD current, that is, the ESD current does not need to bypass the shallow trench isolation structure like a traditional ESD device, so that the ESD current has a shorter current path, that is, the on-resistance of the device is smaller and the effective area of ​​​​the ESD protection is wider, so that the performance of the ESD protection device with a PNP structure can be fully utilized.

[0056] Among them, the parts not described in this embodiment 4 can refer to the embodiment 1 accordingly, and this embodiment 4 will not be repeated.

[0057] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. An ESD protection device, characterized in that: include: substrate; At least one first conductivity type internal well region 1, the internal well region 1 being spaced apart and located in the substrate; A plurality of second conductive type internal well regions 2, the internal well regions 2 being spaced apart in the substrate and respectively located between two adjacent internal well regions 1; A ring-shaped well region of a first conductivity type, the ring-shaped well region being located in the substrate and surrounding the outermost inner well region 2; a substrate lead-out well region of a second conductivity type, the substrate lead-out well region being located in the substrate and surrounding the annular well region; A plurality of second conductivity type internal heavily doped regions, the internal heavily doped regions being located in the first internal well region, the second internal well region and the annular well region; A peripheral heavily doped region of a first conductivity type, the peripheral heavily doped region being located in the annular well region, the peripheral heavily doped region being arranged around the inner heavily doped region in the annular well region and being spaced apart from the inner heavily doped region in the annular well region; A substrate lead-out heavily doped region of a second conductivity type, wherein the substrate lead-out heavily doped region is located in the substrate lead-out well region; A plurality of shallow trench isolation structures, at least one of the shallow trench isolation structures is located in the annular well region and between the peripheral heavily doped region and the internal heavily doped region in the annular well region, and at least one of the shallow trench isolation structures is located between the peripheral heavily doped region and the substrate lead-out heavily doped region; A metal silicide barrier layer, wherein the metal silicide barrier layer covers surfaces of the substrate, the annular well region, the first inner well region, and the second inner well region between all the inner heavily doped regions; Among them, the peripheral heavily doped region, the internal heavily doped region in the annular well region and the internal heavily doped region in the internal well region one are connected to the anode of an external power supply, and the internal heavily doped region in the internal well region two and the substrate lead-out heavily doped region are connected to the cathode of an external power supply, wherein a shallow trench isolation structure is not arranged on the path for discharging ESD current in the substrate.

2. The ESD protection device according to claim 1, characterized in that: The staggered internal well region 1 and the internal well region 2 are an axisymmetric structure, wherein the central axis of the axisymmetric structure is one of the internal well regions 1, and the outermost periphery of the axisymmetric structure is two of the internal well regions 2.

3. The ESD protection device according to claim 1, characterized in that: The substrate comprises: a base and an epitaxial layer located on the base, and the first internal well region, the second internal well region, the annular well region and the substrate lead-out well region are all located in the epitaxial layer.

4. The ESD protection device according to claim 3, characterized in that: The ESD protection device further includes: a buried layer of a first conductivity type, the buried layer is located in the substrate and a front surface of the buried layer contacts a bottom surface of the inner well region 1 in the epitaxial layer and a bottom surface of the annular well region.

5. The ESD protection device according to claim 3, characterized in that: The ESD protection device further includes: a deep well of the first conductivity type, the deep well being located at the bottom of the epitaxial layer and contacting the bottom surface of the inner well region 1 in the epitaxial layer and the bottom surface of the annular well region.

6. The ESD protection device according to claim 3, characterized in that: The ESD protection device also includes: a buried layer of the first conductive type and a deep well of the first conductive type, the deep well being located at the bottom of the epitaxial layer and in contact with the bottom surface of an internal well region 1 in the epitaxial layer and the bottom surface of the annular well region, the buried layer being located in the substrate and the front surface of the buried layer in contact with the bottom surface of the deep well in the epitaxial layer.

7. The ESD protection device according to claim 1, characterized in that: The conductivity type of the doped ions in the substrate is the second conductivity type.

8. The ESD protection device according to any one of claims 1 to 7, characterized in that: The first conductivity type is N type; the second conductivity type is P type.

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