Method for reducing process cost of CIS product

Abstract

The invention provides a method for reducing the process cost of a CIS product. The method comprises the following steps: providing a substrate, forming an ion implantation protection layer on the substrate, forming a photoresist layer on the ion implantation protection layer, opening the photoresist layer through photoetching to define an implantation region of a deep N well, then performing ion implantation to form the deep N well, and removing the photoresist layer; forming a hard mask layer on the ion implantation protection layer, and forming shallow trenches on the hard mask layer, the ion implantation protection layer below the hard mask layer and the substrate by using photoetching and etching methods; forming a linear oxide layer on the surface of the shallow trench on the substrate by using a furnace tube thermal oxidation method, and meanwhile, annealing and repairing the damage of deep N well ion implantation in the step; forming shallow trench isolation for filling the shallow trench by using a deposition and grinding method, and removing the hard mask layer; and subsequent manufacturing of the CMOS image sensor is carried out. According to the invention, the process cost caused by ISSG is reduced, and the defect of silicon damage caused by DDN annealing is avoided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for reducing the process cost of CIS products. Background Art

[0002] Theoretically, CMOS image sensors do not generate photocurrent when there is no light. However, during the manufacturing process of CIS products, due to the influence of factors such as metal contamination, process fluctuations, and raw material changes, pixels will generate charges when there is no light, and the accumulation of charges will generate dark current. For a pixel unit, if its dark current value exceeds the photocurrent generated by capturing photoelectrons, the pixel will be considered as white noise. Therefore, white noise is a pixel unit with excessive dark current.

[0003] In the manufacturing process, factors that affect white noise are:

[0004] 1. Heavy metal ion pollution; 2. Etching plasma charging leads to gate leakage; 3. Ion implantation leads to lattice damage.

[0005] The first two require improvements in raw materials, equipment, substrate impurity removal, etc., which are relatively complex and costly. For lattice damage caused by ion implantation, high-temperature annealing can be used to repair the damage, effectively improving white noise.

[0006] In the existing technology, DDN IMP (double diffused N-well ion implantation) + DDN furnace annealing is performed after the active area is formed. Currently, high-end CIS products have advanced the DDN IMP + DDN furnace annealing to before the pad oxide (PAD oxide) is formed in the active area. The heat in the active area process can be used to further repair the lattice damage caused by high-energy implantation (including furnace pad oxide / nitride layer deposition, STI linear oxide layer, HARP annealing and post-STI CMP annealing).

[0007] In order to solve the above problems, it is necessary to propose a new method to reduce the process cost of CIS products. Summary of the invention

[0008] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for reducing the process cost of CIS products, so as to solve the problem of high process cost of CIS products in the prior art.

[0009] To achieve the above-mentioned object and other related objects, the present invention provides a method for reducing the process cost of CIS products, comprising:

[0010] Step 1, providing a substrate, on which an ion implantation protection layer is formed, forming a photoresist layer on the ion implantation protection layer, photolithography opening the photoresist layer to define an implantation region of a deep N well, then performing ion implantation to form a deep N well, and removing the photoresist layer;

[0011] Step 2: forming a hard mask layer on the ion implantation protection layer, and forming shallow trenches on the hard mask layer, the ion implantation protection layer thereunder, and the substrate by photolithography and etching methods;

[0012] Step 3: forming a linear oxide layer on the surface of the shallow groove on the substrate by a furnace tube thermal oxidation method, and at the same time, annealing is performed in this step to repair the damage caused by the deep N-well ion implantation;

[0013] Step 4: forming a shallow trench isolation filling the shallow trench by deposition and grinding, and removing the hard mask layer;

[0014] Step 5: Proceed to manufacture the subsequent CMOS image sensor.

[0015] Preferably, step one further comprises the step of forming an alignment mark on the substrate before forming the deep N well.

[0016] Preferably, the ion implantation protection layer in step one is a pad oxide layer.

[0017] Preferably, the material of the hard mask layer in step 2 is silicon nitride.

[0018] Preferably, the etching method in step 2 is dry etching.

[0019] Preferably, the grinding method in step 4 is chemical mechanical planarization grinding.

[0020] Preferably, in step four, the hard mask layer is removed by wet etching.

[0021] Preferably, the subsequent manufacturing of the CMOS image sensor in step five includes: forming a P-type shallow doped region in the substrate region at the upper portion of the deep N-well.

[0022] Preferably, the subsequent manufacturing of the CMOS image sensor in step five includes: performing ion implantation of pixel units; forming a gate structure; forming sidewalls located on both sides of the gate structure; and forming a metal interconnection structure.

[0023] As described above, the method of reducing the process cost of CIS products of the present invention has the following beneficial effects:

[0024] For CIS high-end products with DDN advance solution, the present invention skips DDN furnace annealing and changes STI linear oxide layer ISSG (in-situ steam generation) to furnace linear oxide layer + annealing (combined into one process), and uses this annealing to repair the lattice damage caused by DDN ion implantation, thereby reducing the process cost caused by ISSG and avoiding silicon damage defects caused by DDN annealing. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Shown is a schematic diagram of the process flow of the present invention;

[0026] Figure 2 It is a schematic diagram showing the formation of an alignment mark according to the present invention;

[0027] Figure 3 It is a schematic diagram showing the ion implantation of the deep N-well of the present invention;

[0028] Figure 4 Shown is a schematic diagram of forming a shallow trench according to the present invention;

[0029] Figure 5 Shown is a schematic diagram of forming a linear oxide layer according to the present invention;

[0030] Figure 6 It is a schematic diagram of forming shallow trench isolation according to the present invention;

[0031] Figure 7 Shown is a schematic diagram of forming a CMOS image sensor according to the present invention. DETAILED DESCRIPTION

[0032] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0033] See also Figure 1 The present invention provides a method for reducing the process cost of CIS products, comprising:

[0034] Step 1: Provide a substrate 101, on which an ion implantation protection layer 102 is formed, and a photoresist layer 104 is formed on the ion implantation protection layer 102. The photoresist layer 104 is opened by photolithography to define an implantation region of a deep N well 109, and then ion implantation is performed to form the deep N well 109, skipping the DDN furnace annealing step to form a substrate 101. Figure 3 The structure shown, the photoresist layer 104 is removed;

[0035] In some embodiments, step 1 further includes forming an alignment mark 103 on the substrate 101 before forming the deep N well 109. Figure 2 Specifically, the alignment mark 103 can be formed on the substrate 101 by photolithography and etching.

[0036] In some embodiments, the ion implantation protection layer 102 in step 1 is a pad oxide layer.

[0037] Step 2: forming a hard mask layer 105 on the ion implantation protection layer 102, and forming shallow trenches on the hard mask layer 105 and the ion implantation protection layer 102 and the substrate 101 thereunder by photolithography and etching, so as to form a Figure 4 The structure shown;

[0038] In some embodiments, the material of the hard mask layer 105 in step 2 is silicon nitride.

[0039] In some embodiments, the etching method in step 2 is dry etching.

[0040] Step 3: A linear oxide layer 107 is formed on the surface of the shallow groove on the substrate 101 by using a furnace thermal oxidation method. At the same time, annealing is performed in this step to repair the damage caused by ion implantation in the deep N well 109, forming a linear oxide layer 107. Figure 5 The structure shown in FIG. 1 shows a structure in which the STI linear oxide layer 107 ISSG (in-situ steam generation) is changed to a furnace linear oxide layer 107 + annealing (combined into one process) and the defect problem of silicon damage is avoided.

[0041] Step 4: forming a shallow trench isolation 108 filling the shallow trench by a deposition and grinding method, that is, depositing a shallow trench isolation 108 material, and then grinding it onto the hard mask layer 105, removing the hard mask layer 105, and forming Figure 6 The structure shown;

[0042] In some embodiments, the polishing method in step 4 is chemical mechanical planarization polishing.

[0043] In some embodiments, in step 4, the hard mask layer 105 is removed by wet etching.

[0044] Step 5: Proceed to manufacture the subsequent CMOS image sensor.

[0045] In some embodiments, the subsequent manufacturing of the CMOS image sensor in step five includes: forming a P-type shallow doped region 110 in the substrate 101 region at the upper portion of the deep N well 109 , that is, forming a DDN structure (double diffused N well).

[0046] In some embodiments, the subsequent manufacturing of the CMOS image sensor in step five includes: performing ion implantation of the pixel unit; forming a gate structure; forming sidewalls on both sides of the gate structure, forming a Figure 7 The structure shown; forming a metal interconnect structure.

[0047] In some embodiments, the subsequent manufacturing of the CMOS image sensor in step five includes: forming a P-type shallow doped region in the substrate 101 at the upper portion of the deep N well 109 .

[0048] In some embodiments, the subsequent manufacturing of the CMOS image sensor in step five includes: performing ion implantation of pixel units; forming a gate structure; forming sidewalls on both sides of the gate structure; and forming a metal interconnection structure.

[0049] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0050] In summary, for the CIS high-end products of the DDN advance solution, the present invention skips the DDN furnace tube annealing, and changes the STI linear oxide layer ISSG (in-situ steam generation) to the furnace tube linear oxide layer + annealing (combined into one process), and uses the annealing to repair the lattice damage caused by DDN ion implantation, thereby reducing the process cost caused by ISSG and avoiding the silicon damage defects caused by DDN annealing. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0051] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for reducing the process cost of CIS products, characterized in that: At least: Step 1, providing a substrate, on which an ion implantation protection layer is formed, forming a photoresist layer on the ion implantation protection layer, photolithography opening the photoresist layer to define an implantation region of a deep N well, then performing ion implantation to form a deep N well, and removing the photoresist layer; Step 2: forming a hard mask layer on the ion implantation protection layer, and forming shallow trenches on the hard mask layer, the ion implantation protection layer thereunder, and the substrate by photolithography and etching methods; Step 3: forming a linear oxide layer on the surface of the shallow groove on the substrate by a furnace tube thermal oxidation method, and at the same time, annealing is performed in this step to repair the damage caused by the deep N-well ion implantation; Step 4: forming a shallow trench isolation filling the shallow trench by deposition and grinding, and removing the hard mask layer; Step 5: Proceed to manufacture the subsequent CMOS image sensor.

2. The method for reducing the process cost of CIS products according to claim 1, characterized in that: Step 1 also includes the step of forming an alignment mark on the substrate before forming the deep N well.

3. The method for reducing the process cost of CIS products according to claim 1, characterized in that: The ion implantation protection layer in step 1 is a pad oxide layer.

4. The method for reducing the process cost of CIS products according to claim 1, characterized in that: The material of the hard mask layer in step 2 is silicon nitride.

5. The method for reducing the process cost of CIS products according to claim 1, characterized in that: The etching method in step 2 is dry etching.

6. The method for reducing the process cost of CIS products according to claim 1, characterized in that: The grinding method in step 4 is chemical mechanical planarization grinding.

7. The method for reducing the process cost of CIS products according to claim 1, characterized in that: In step 4, the hard mask layer is removed by wet etching.

8. The method for reducing the process cost of CIS products according to claim 1, characterized in that: The subsequent manufacturing of the CMOS image sensor in step five includes: forming a P-type shallow doped region in the substrate region at the upper portion of the deep N-well.

9. The method for reducing the process cost of CIS products according to claim 1, characterized in that: The subsequent manufacturing of the CMOS image sensor in step five includes: performing ion implantation of pixel units; forming a gate structure; forming sidewalls located on both sides of the gate structure; and forming a metal interconnection structure.

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