CMOS image sensor and manufacturing method thereof

Abstract

The invention discloses a CMOS image sensor. An N-type region of a photodiode includes a first region block and a second region block adjoining a first side of a first gate structure of a transfer transistor. The second area block comprises a bottom edge, a top edge and a bevel edge. The bottom edge and the top edge both extend in the second direction, the bottom edge is adjacent to the first side of the first area block, and the bottom edge has a first width; the distance between the top edge and the bottom edge is a first length, and the top edge has a second width. The bevel edge is connected with corresponding end points of the bottom edge and the top edge; a first included angle is formed between the bevel edge and the first direction from the source region to the drain region of the transfer transistor. The first width is greater than the second width, and the first included angle is greater than zero degree; and in the direction from the top edge to the bottom edge, the width of the second region block is gradually increased, and an internal potential distribution adjusting structure of the N-type region is formed. The invention further discloses a manufacturing method of the CMOS image sensor. According to the invention, the transfer speed of photo-induced electrons can be increased, and the image lag phenomenon is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a CMOS image sensor. The present invention also relates to a manufacturing method of the CMOS image sensor. Background Art

[0002] CMOS image sensor (CIS) is an image sensor technology mainly used in smartphones, digital cameras, security equipment and some high-end scientific applications. Photodiode (PD) is mainly used in the field of electronic imaging due to its advantages such as low noise, high quantum efficiency and low dark current, and has always been the preferred technology for CIS. The charge transfer process is a key performance parameter of PD. High charge transfer speed and low image hysteresis play a very important role in advanced applications such as ultra-high-speed imaging. The charge transfer in the PD we are currently developing is driven by a variety of coupling processes, including self-induced drift, fringe field and thermal diffusion. For large PDs with a "flat" potential distribution in the central area, diffusion is the main factor, and the charge transfer time is proportional to the square of the distance. However, the slow movement of carriers based on a single diffusion increases the probability of image hysteresis effect. Therefore, improving the electron transfer rate has become the key to improving product competitiveness.

[0003] like Figure 1 , which is a schematic plan view of a photodiode of an existing CMOS image sensor; a pixel region of the CMOS image sensor includes a plurality of pixel units, each of which includes: a photodiode, a transfer transistor and a floating diffusion region 104 (FD).

[0004] The transfer transistor includes a gate structure 103 , an N-type region 102 of the photodiode is located on a first side of the gate structure 103 and serves as a source region of the transfer transistor, and a floating diffusion region 104 is located on a second side of the gate structure 103 and serves as a drain region of the transfer transistor.

[0005] Depend on Figure 1 As shown, the main structure of the N-type region 102 is a square structure.

[0006] like Figure 2 FIG. 1 is a schematic diagram of the transfer of photogenerated electrons of a photodiode of an existing CMOS image sensor; and Figure 1 Compared to the structure shown, Figure 2 The main structure of the N-type region 102 in FIG. 1 is also a square structure, but the two top corners of the square structure away from the gate structure 103 are rounded.

[0007] After the photodiode is exposed to light, photogenerated electrons 105 are generated. When the gate voltage of the gate structure 103 is greater than the threshold voltage, the source and drain of the transfer transistor are turned on, and the photogenerated electrons 105 are transferred to the floating diffusion region 104 along the arrow line direction shown by the dotted line 106 .

[0008] Depend on Figure 2 As shown, the potential distribution in the central area of ​​the N-type region 102 is flat, and the photogenerated electrons 105 are mainly transferred by diffusion. The time of diffusion transfer is inversely proportional to the square of the distance. Therefore, the farther the distance from the first side of the gate structure 104, the longer the time required for the transfer of the photogenerated electrons 105, which will increase the probability of the image lag effect. Summary of the invention

[0009] The technical problem to be solved by the present invention is to provide a CMOS image sensor which can increase the transfer speed of photogenerated electrons, thereby improving the image hysteresis phenomenon. To this end, the present invention also provides a method for manufacturing the CMOS image sensor.

[0010] In order to solve the above technical problem, the pixel area of ​​the CMOS image sensor provided by the present invention includes a plurality of pixel units, each of which includes: a photodiode, a transfer transistor and a floating diffusion area.

[0011] The transfer transistor comprises a first gate structure, the N-type region of the photodiode is located at a first side of the first gate structure and serves as a source region of the transfer transistor, and the floating diffusion region is located at a second side of the first gate structure and serves as a drain region of the transfer transistor.

[0012] The first direction is the direction from the source region to the drain region, and the second direction is the extension direction of the first gate structure, and the second direction is perpendicular to the first direction.

[0013] On the planes of the first direction and the second direction, the N-type region includes a first area block and a second area block.

[0014] The second side of the first region block is adjacent to the first side of the first gate structure, and the width of the first region block in the second direction remains unchanged.

[0015] The second area block includes: a bottom edge, a top edge and a hypotenuse.

[0016] The bottom edge and the top edge both extend along the second direction, the bottom edge is adjacent to the first side of the first area block, and the bottom edge has a first width; the spacing between the top edge and the bottom edge is a first length, and the top edge has a second width.

[0017] The hypotenuse connects the corresponding endpoints of the bottom edge and the top edge; and a first angle is formed between the hypotenuse and the first direction.

[0018] The second width is greater than or equal to zero, the first width is greater than the second width, and the first angle is greater than zero degrees; in the direction from the top edge to the bottom edge, the width of the second area block gradually increases and forms an internal potential distribution adjustment structure of the N-type region, and the sizes of the first width and the first angle meet the requirements of the potential difference between the top edge and the bottom edge.

[0019] A further improvement is that the second area block is a trapezoid or a triangle.

[0020] A further improvement is that the second area block is a combination structure of a plurality of trapezoids, the bottom sides of the trapezoids in the N-type region are aligned and connected together, and there are intervals between the top sides of the trapezoids.

[0021] The total area of ​​each of the trapezoids in the N-type region meets the requirement of FWC.

[0022] A further improvement is that the structural parameters of the trapezoids in the N-type region are the same.

[0023] A further improvement is that the second area block is a combination structure of multiple triangles, the bottom sides of the triangles in the N-type region are aligned and connected together, the top sides of the triangles are vertices and there are intervals between the vertices.

[0024] The total area of ​​each of the triangles in the N-type region meets the requirement of FWC.

[0025] A further improvement is that the structural parameters of the triangles in the N-type region are the same.

[0026] A further improvement is that the N-type region is an N-type ion implantation region formed in a P-type semiconductor substrate; and the P-type region of the photodiode is composed of the P-type semiconductor substrate located at the bottom of the N-type region.

[0027] A further improvement is that the first gate structure is a planar gate or a trench gate.

[0028] To solve the above technical problem, in the manufacturing method of the CMOS image sensor provided by the present invention, the pixel area of ​​the CMOS image sensor includes a plurality of pixel units, each of which includes: a photodiode, a transfer transistor and a floating diffusion area.

[0029] The transfer transistor comprises a first gate structure, the N-type region of the photodiode is located at a first side of the first gate structure and serves as a source region of the transfer transistor, and the floating diffusion region is located at a second side of the first gate structure and serves as a drain region of the transfer transistor.

[0030] The first direction is the direction from the source region to the drain region, and the second direction is the extension direction of the first gate structure, and the second direction is perpendicular to the first direction.

[0031] The step of forming the N-type region comprises:

[0032] The formation area of ​​the N-type region is defined by photolithography. On the planes of the first direction and the second direction, the N-type region includes a first area block and a second area block.

[0033] The second side of the first region block is adjacent to the first side of the first gate structure, and the width of the first region block in the second direction remains unchanged.

[0034] The second area block includes: a bottom edge, a top edge and a hypotenuse.

[0035] The bottom edge and the top edge both extend along the second direction, the bottom edge is adjacent to the first side of the first area block, and the bottom edge has a first width; the spacing between the top edge and the bottom edge is a first length, and the top edge has a second width.

[0036] The hypotenuse connects the corresponding endpoints of the bottom edge and the top edge; and a first angle is formed between the hypotenuse and the first direction.

[0037] The second width is greater than or equal to zero, the first width is greater than the second width, and the first angle is greater than zero degrees; in the direction from the top edge to the bottom edge, the width of the second area block gradually increases and forms an internal potential distribution adjustment structure of the N-type region, and the sizes of the first width and the first angle meet the requirements of the potential difference between the top edge and the bottom edge.

[0038] N-type ion implantation is performed to form the N-type region in the P-type semiconductor substrate, and the P-type region of the photodiode is composed of the P-type semiconductor substrate located at the bottom of the N-type region.

[0039] A further improvement is that the second area block is a trapezoid or a triangle.

[0040] A further improvement is that the second area block is a combination structure of a plurality of trapezoids, the bottom sides of the trapezoids in the N-type region are aligned and connected together, and there are intervals between the top sides of the trapezoids.

[0041] The total area of ​​each of the trapezoids in the N-type region meets the requirement of FWC.

[0042] A further improvement is that the structural parameters of the trapezoids in the N-type region are the same.

[0043] A further improvement is that the second area block is a combination structure of multiple triangles, the bottom sides of the triangles in the N-type region are aligned and connected together, the top sides of the triangles are vertices and there are intervals between the vertices.

[0044] The total area of ​​each of the triangles in the N-type region meets the requirement of FWC.

[0045] A further improvement is that the structural parameters of the triangles in the N-type region are the same.

[0046] A further improvement is that the first gate structure is a planar gate or a trench gate.

[0047] The present invention makes a special arrangement for the planar structure of the N-type region. The second area block includes a bottom edge, a top edge and a hypotenuse. The first width of the bottom edge, the second width of the top edge and the first angle of the hypotenuse can be set in advance according to the need to improve the electric potential in the direction from the top edge to the bottom edge, so that the sizes of the first width and the first angle meet the requirements of the electric potential difference between the top edge and the bottom edge, thereby increasing the transfer speed of photogenerated electrons and making the transfer speed of photogenerated electrons meet the requirements, thereby improving the image lag phenomenon.

[0048] Compared with the existing structure, the area of ​​the N-type region of the present invention is reduced to a certain extent. The present invention can increase the transfer speed of photogenerated electrons while ensuring that the area of ​​the entire pixel unit remains unchanged.

[0049] The present invention can set the second area block of the N-type region step by step according to the need to improve the transfer speed of photogenerated electrons, that is, even if the first width is continuously reduced and the first angle is continuously increased, when the planar structure of the N-type region is converted from a trapezoid to a triangle, the potential difference along the first direction inside the N-type region can be increased to the maximum, and the internal electric field strength can also be increased to the maximum, so that the transfer speed of the photogenerated electrons can be increased to the best extent, and it is beneficial to completely transfer the photogenerated electrons in the area of ​​the N-type region away from the side of the transfer transistor to the floating diffusion region, and the defect that the electrons cannot be completely extracted due to too many electrons can be prevented.

[0050] In addition, since the first width is continuously reduced and the first angle is continuously increased, the area of ​​the corresponding trapezoid or triangle is continuously reduced. The present invention can further set the second area block of the N-type region to a combined structure including multiple trapezoids or multiple triangles. In this way, the structural characteristics of the trapezoid or triangle can be used to improve the transfer speed of photogenerated electrons, and the area of ​​the entire N-type region can be made large enough by using the sum of the areas of multiple trapezoids or multiple triangles, so that the full well capacity of the device can meet the requirements of FWC, which can be well applied to pixels of larger sizes.

[0051] In addition, the implantation energy and implantation dose of the ion implantation in the N-type region of the present invention can be the same as those of the existing structure. Therefore, under the condition of keeping the process parameters of the ion implantation in the N-type region unchanged, the present invention can improve the internal potential distribution of the N-type region and improve the transfer rate of photogenerated electrons only by improving the planar structure of the N-type region. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0053] Figure 1 is a plan view schematic diagram of a photodiode of an existing CMOS image sensor;

[0054] Figure 2 It is a schematic diagram of the transfer of photogenerated electrons of the photodiode of the existing CMOS image sensor;

[0055] Figure 3 is a plan view schematic diagram of a first photodiode of a CMOS image sensor according to an embodiment of the present invention;

[0056] Figure 4 is a plan view schematically showing a second photodiode of a CMOS image sensor according to an embodiment of the present invention;

[0057] Figure 5 is a plan view schematic diagram of a third photodiode of a CMOS image sensor according to an embodiment of the present invention;

[0058] Figure 6 yes Figure 1 The existing CMOS image sensor shown and Figures 3 to 5 The distribution curves of the internal potentials of three photodiodes of the CMOS image sensor according to the embodiment of the present invention in the X direction are shown;

[0059] Figure 7 FIG. 1 is a plan view of a photodiode of a CMOS image sensor according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0060] like Figure 3 , which is a plan view of a first type of photodiode of a CMOS image sensor according to an embodiment of the present invention; the pixel region of the CMOS image sensor according to the embodiment of the present invention includes a plurality of pixel units, each of which includes: a photodiode, a transfer transistor and a floating diffusion region 204.

[0061] The transfer transistor includes a first gate structure 203, the N-type region 202 of the photodiode is located on a first side of the first gate structure 203 and serves as a source region of the transfer transistor, and the floating diffusion region 204 is located on a second side of the first gate structure 203 and serves as a drain region of the transfer transistor.

[0062] In the embodiment of the present invention, the first gate structure 203 is a trench gate. In other embodiments, the first gate structure 203 may be a planar gate.

[0063] The N-type region 202 is an N-type ion implantation region formed in a P-type semiconductor substrate; the P-type region of the photodiode is composed of the P-type semiconductor substrate located at the bottom of the N-type region 202 .

[0064] The first direction is the direction from the source region to the drain region, and the second direction is the extension direction of the first gate structure 203 , and the second direction is perpendicular to the first direction. Figure 3 , the first direction is the X direction, and the second direction is the Y direction.

[0065] On the planes of the first direction and the second direction, the N-type region 202 includes a first area block 2021 and a second area block 2022 .

[0066] The second side of the first region block 2021 is adjacent to the first side of the first gate structure 203 , and the width of the first region block 2021 in the second direction remains unchanged.

[0067] The second area block 2022 includes a bottom edge 301 , a top edge 302 and a hypotenuse 303 .

[0068] The bottom edge 301 and the top edge 302 both extend along the second direction, the bottom edge 301 is adjacent to the first side of the first area block 2021, and the bottom edge 301 has a first width W; the spacing between the top edge 302 and the bottom edge 301 is a first length L, and the top edge 302 has a second width.

[0069] The hypotenuse 303 connects the corresponding endpoints of the bottom edge 301 and the top edge 302 ; a first angle α is formed between the hypotenuse 303 and the first direction.

[0070] The second width is greater than or equal to zero, the first width W is greater than the second width, and the first angle α is greater than zero degrees; from the top edge 302 to the bottom edge 301, the width of the second area block 2022 gradually increases and forms an internal potential distribution adjustment structure of the N-type region 202, and the magnitudes of the first width W and the first angle α meet the requirements of the potential difference between the top edge 302 and the bottom edge 301. Figure 3 As shown, after the first width W, the first angle α and the first length L are determined, the second width is also determined. Therefore, it is only necessary to adjust the size of the first width W and the first angle α to adjust the potential difference between the top edge 302 and the bottom edge 301.

[0071] In the embodiment of the present invention, since the first regional block 2021 is close to the first gate structure 203, the transfer distance of the photogenerated carriers inside the first regional block 2021 is relatively short, and the rapid transfer of the photogenerated carriers inside the first regional block 2021 can be achieved without special setting of the first regional block 2021.

[0072] Depend on Figure 3 As shown, in the first structure of the embodiment of the present invention, the second area block 2022 is a trapezoid.

[0073] In order to adjust the potential difference between the top edge 302 and the bottom edge 301, the trapezoidal parameters of the second area block 2022 can be set according to the required potential difference requirements. Under the condition that the first length L remains unchanged, the trapezoidal parameters of the second area block 2022 can be expressed by the first width W and the first angle α. Figure 4 The trapezoidal parameters of the second region block 2022 of the second photodiode of the CMOS image sensor according to the embodiment of the present invention and Figure 5 The trapezoidal parameters of the second area block 2022 of the third photodiode of the CMOS image sensor according to the embodiment of the present invention are shown as follows: The relationship between the trapezoidal parameters of the second area block 2022 and the potential difference between the top side 302 and the bottom side 301 is further described:

[0074] like Figure 4 As shown, and Figure 3 In comparison, the first width W is reduced, and the first angle α remains unchanged, so it can be deduced that the second width will also be reduced.

[0075] like Figure 5 As shown, and Figure 4 In comparison, the first width W remains unchanged, and the first angle α is reduced, and it can be deduced that the second width will also be reduced.

[0076] like Figure 6 As shown, Figure 1 The existing CMOS image sensor shown and Figures 3 to 5 The distribution curves of the internal potentials of the three photodiodes of the CMOS image sensor according to the embodiment of the present invention in the X direction are shown; wherein, Figure 3 The first width W of the corresponding embodiment of the present invention is equal to Figure 1 The width of the N-type region of the photodiode of the existing CMOS image sensor, the first length L is equal to Figure 1 The length of the N-type region of the photodiode in the conventional CMOS image sensor.

[0077] Figure 6 In the example, curve 401 corresponds to Figure 1 The internal potential distribution curve of the photodiode of the conventional CMOS image sensor is shown, and the curve 402 corresponds to Figure 3 The internal potential distribution curve of the first photodiode of the embodiment of the present invention is shown, and the curve 403 corresponds to Figure 3 The internal potential distribution curve of the second photodiode of the embodiment of the present invention is shown, and the curve 404 corresponds to Figure 3 The internal potential distribution curve of the third photodiode of the embodiment of the present invention is shown.

[0078] It can be seen from the curve 401 that the potential changes gradually from left to right in the built-in electric field, the photogenerated electrons transfer slowly, and the potential changes slowly.

[0079] It can be seen from curve 402 that Figure 3 The PD profile of the first structure of the embodiment of the present invention is set to an inclination angle α at a position far away from the TX region, i.e., the low-voltage gate structure 203. Compared with the curve 401, it can be seen that the potential of the curve 402 from left to right changes significantly.

[0080] It can be seen from curve 403 that Figure 4 The second structure of the embodiment of the present invention shown in the figure is based on the first structure of the embodiment of the present invention, while keeping the tilt angle α unchanged, reducing the PD width W (W↓), which can further increase the potential difference range of the built-in electric field from left to right.

[0081] It can be seen from curve 404 that Figure 5 The third structure of the embodiment of the present invention shown in the figure keeps the PD width W unchanged on the basis of the second structure of the embodiment of the present invention, increases the tilt angle α (α↓), and can increase the potential distribution of the built-in electric field to the maximum.

[0082] Therefore, by comparing the curves 401 to 404 , it can be concluded that the larger the inclination angle α is, the narrower the PD width W is, resulting in a larger potential distribution difference within the PD and faster acceleration of electrons by the electric field, thereby improving the image lag phenomenon.

[0083] It can be seen that from curve 401 to curve 404, the rate of change of the potential inside the photodiode increases successively, so that the potential difference on both sides of the photodiode increases successively. Since the electric field strength is the ratio of the potential to the distance, the greater the potential difference, the greater the internal electric field strength, the greater the electric field strength, the greater the force on the photogenerated carriers, and finally the transfer rate of the photogenerated electrons can be increased.

[0084] At the same time, comparison Figures 3 to 5 As can be seen from the structure shown in the figure, the areas of the three photodiodes in the embodiment of the present invention will decrease successively and are all smaller than Figure 1The area of ​​the existing photodiode is shown. If the area of ​​the photodiode is reduced, the FWC will be reduced. Therefore, in the embodiment of the present invention, the trapezoidal parameters of the N-type region of the photodiode can be selected as required, and the area of ​​the N-type region is made as large as possible while ensuring that the transfer rate of the photogenerated electrons meets the requirements, so that the FWC meets the requirements.

[0085] A further improvement of the embodiment of the present invention is that the second area block 2022 is a triangle. Compared with the trapezoid, in the triangle, the top edge 302 is reduced to a vertex. The triangular structure can further improve the transfer rate of photogenerated electrons. However, the area of ​​the N-type region is further reduced.

[0086] A further improvement of the embodiment of the present invention is that the second area block 2022 is a combination structure of multiple trapezoids, the bottom sides 301 of the trapezoids of the N-type region 202 are aligned and connected together, and there are intervals between the top sides 302 of the trapezoids.

[0087] The total area of ​​each of the trapezoids of the N-type region 202 meets the FWC requirement. At this time, the transfer rate of photogenerated electrons and the FWC can be adjusted independently, so that the transfer rate of photogenerated electrons and the FWC meet the requirements at the same time.

[0088] Preferably, the structural parameters of the trapezoids of the N-type region 202 are the same.

[0089] like Figure 7 As shown, it is a plan schematic diagram of the photodiode of the CMOS image sensor of a preferred embodiment of the present invention; the second area block 2022 is a combination structure of multiple triangles, the bottom edges 301 of each of the triangles in the N-type region 202 are aligned and connected together, the top edges 302 of each of the triangles are vertices 302a and there are intervals between each of the vertices 302a.

[0090] The total area of ​​each of the triangles in the N-type region 202 meets the requirement of FWC.

[0091] The structural parameters of the triangles in the N-type region 202 are the same.

[0092] Depend on Figure 7 As shown, the N-type region 202 is a comb-shaped structure, which can optimize the transfer rate of photogenerated electrons and meet the requirements of FWC at the same time.

[0093] The embodiment of the present invention makes special arrangements for the planar structure of the N-type region 202. The second area block 2022 includes a bottom edge 301, a top edge 302, and a hypotenuse 303. The first width W of the bottom edge 301, the second width of the top edge 302, and the first angle α of the hypotenuse 303 can be set in advance according to the need to improve the electric potential in the direction from the top edge 302 to the bottom edge 301, so that the sizes of the first width W and the first angle α meet the requirements of the electric potential difference between the top edge 302 and the bottom edge 301, thereby increasing the transfer speed of photogenerated electrons and making the transfer speed of photogenerated electrons meet the requirements, thereby improving the image lag phenomenon.

[0094] Compared with the existing structure, the area of ​​the N-type region 202 in the embodiment of the present invention is reduced to a certain extent. The embodiment of the present invention can increase the transfer speed of photogenerated electrons while ensuring that the area of ​​the entire pixel unit remains unchanged.

[0095] The embodiment of the present invention can set the second area block 2022 of the N-type region 202 step by step according to the need to improve the transfer speed of photogenerated electrons. That is, even if the first width W is continuously reduced and the first angle α is continuously increased, when the planar structure of the N-type region 202 is transformed from a trapezoid into a triangle, the potential difference along the first direction inside the N-type region 202 can be increased to the maximum, and the internal electric field strength can also be increased to the maximum, so that the transfer speed of the photogenerated electrons can be increased to the best extent, and it is beneficial to completely transfer the photogenerated electrons in the area of ​​the N-type region 202 away from the side of the transfer transistor to the floating diffusion region 204, and the defect that the electrons cannot be completely extracted due to too many electrons can be prevented.

[0096] In addition, since the first width W is continuously reduced and the first angle α is continuously increased, the area of ​​the corresponding trapezoid or triangle is continuously reduced. In the embodiment of the present invention, the second area block 2022 of the N-type region 202 can be further set to a combined structure including multiple trapezoids or multiple triangles. In this way, the structural characteristics of the trapezoid or triangle can be used to improve the transfer speed of photogenerated electrons, and the area of ​​the entire N-type region 202 can be made large enough by using the sum of the areas of multiple trapezoids or multiple triangles, so that the full well capacity of the device can meet the requirements of FWC, which can be well applied to pixels of larger sizes.

[0097] In addition, the implantation energy and implantation dose of the ion implantation in the N-type region 202 of the embodiment of the present invention can be the same as those of the existing structure. Therefore, under the condition of keeping the process parameters of the ion implantation in the N-type region 202 unchanged, the embodiment of the present invention can improve the internal potential distribution of the N-type region 202 and improve the transfer rate of photogenerated electrons only by improving the planar structure of the N-type region 202.

[0098] In order to increase the charge transfer speed, the embodiment of the present invention achieves low image lag by optimizing the PD structure and its potential distribution. Compared with the existing traditional diffusion-based method, the lateral electric field with a large potential difference is constructed in the PD, which leads to a significant acceleration of charge collection. The PD structure design of the embodiment of the present invention plays a vital reference role in the future design of faster and clearer image effects.

[0099] The electron transfer speed of the PD in the CIS image sensor of the embodiment of the present invention is optimized, which can further increase the speed of photogenerated electron transfer to the FD, suppress image lag, and improve image imaging performance. In theory, photogenerated electrons transfer along places with high potential, but if the electric field has a weak ability to accelerate electrons within a spatial range with a small potential change, the electron transfer rate in the PD is reduced, further forming the phenomenon of image lag. The combed PD structure in the preferred embodiment of the present invention can make a significant difference in the potential change of the built-in electric field of the PD, so that electrons can be transferred to the FD as quickly as possible and pixel transmission and reading are performed, so that the image is formed more quickly.

[0100] Embodiments of the present invention Figures 3 to 5 Under the conditions of various corresponding PD shape designs, in order to obtain a faster transmission rate, part of the FWC area will inevitably be sacrificed, resulting in the loss of the final image. Therefore, it is necessary to comprehensively consider the pros and cons and design a PD morphology with reduced pixel size and fast electron transmission under the condition of ensuring the required FWC. At this time, Figure 7 The PD shape of the preferred embodiment of the present invention is shown as follows:

[0101] Under the condition of constant α, the large area PD is divided into several triangular pyramids (W↓), which can further increase the built-in potential difference and improve the electron transfer rate;

[0102] The photogenerated electrons in the PD far from the TX region, i.e., the first gate structure 203, can be further completely transferred to the FD to prevent the electrons from being completely extracted due to excessive electrons;

[0103] In order to ensure that the image is fully formed and sufficient FWC is required, a larger pixel size is used.

[0104] The embodiments of the present invention are mainly aimed at the design of reducing image hysteresis of CMOS image sensors, and utilize changes in PD morphology and potential distribution to enable photogenerated electrons to be transferred to FD at the fastest speed, thereby accelerating image reading.

[0105] In the manufacturing method of the CMOS image sensor according to the embodiment of the present invention, as follows Figure 3 As shown, the pixel area of ​​the CMOS image sensor includes a plurality of pixel units, each of which includes: a photodiode, a transfer transistor and a floating diffusion area 204 .

[0106] The transfer transistor includes a first gate structure 203, the N-type region 202 of the photodiode is located on a first side of the first gate structure 203 and serves as a source region of the transfer transistor, and the floating diffusion region 204 is located on a second side of the first gate structure 203 and serves as a drain region of the transfer transistor.

[0107] In the method of the embodiment of the present invention, the first gate structure 203 is a trench gate. In other embodiments, the first gate structure 203 can also be a planar gate.

[0108] The first direction is the direction from the source region to the drain region, and the second direction is the extension direction of the first gate structure 203 , and the second direction is perpendicular to the first direction.

[0109] The steps of forming the N-type region 202 include:

[0110] The formation area of ​​the N-type region 202 is defined by photolithography. On the planes of the first direction and the second direction, the N-type region 202 includes a first area block 2021 and a second area block 2022 .

[0111] The second side of the first region block 2021 is adjacent to the first side of the first gate structure 203 , and the width of the first region block 2021 in the second direction remains unchanged.

[0112] The second area block 2022 includes a bottom edge 301 , a top edge 302 and a hypotenuse 303 .

[0113] The bottom edge 301 and the top edge 302 both extend along the second direction, the bottom edge 301 is adjacent to the first side of the first area block 2021, and the bottom edge 301 has a first width W; the spacing between the top edge 302 and the bottom edge 301 is a first length L, and the top edge 302 has a second width.

[0114] The hypotenuse 303 connects the corresponding endpoints of the bottom edge 301 and the top edge 302 ; a first angle α is formed between the hypotenuse 303 and the first direction.

[0115] The second width is greater than or equal to zero, the first width W is greater than the second width, and the first angle α is greater than zero degrees; from the top edge 302 to the bottom edge 301, the width of the second area block 2022 gradually increases and forms an internal potential distribution adjustment structure of the N-type region 202, and the magnitudes of the first width W and the first angle α meet the requirements of the potential difference between the top edge 302 and the bottom edge 301. Figure 3As shown, after the first width W, the first angle α and the first length L are determined, the second width is also determined. Therefore, it is only necessary to adjust the size of the first width W and the first angle α to adjust the potential difference between the top edge 302 and the bottom edge 301.

[0116] N-type ion implantation is performed to form the N-type region 202 in the P-type semiconductor substrate. The P-type region of the photodiode is composed of the P-type semiconductor substrate located at the bottom of the N-type region 202 .

[0117] In the embodiment method of the present invention, since the first area block 2021 is close to the first gate structure 203, the transfer distance of the photogenerated carriers inside the first area block 2021 is relatively short, and the rapid transfer of the photogenerated carriers inside the first area block 2021 can be achieved without special setting of the first area block 2021.

[0118] The method of the embodiment of the present invention can form various photodiode structures of the embodiment of the present invention, including Figure 3 , Figure 4 , Figure 5 and Figure 7 Various photodiode structures are shown.

[0119] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A CMOS image sensor, characterized in that: The pixel area of ​​the CMOS image sensor includes a plurality of pixel units, each of which includes: a photodiode, a transfer transistor and a floating diffusion area; The transfer transistor comprises a first gate structure, the N-type region of the photodiode is located on a first side of the first gate structure and serves as a source region of the transfer transistor, and the floating diffusion region is located on a second side of the first gate structure and serves as a drain region of the transfer transistor; The first direction is the direction from the source region to the drain region, and the second direction is the extension direction of the first gate structure and the second direction is perpendicular to the first direction; On the planes of the first direction and the second direction, the N-type region includes a first area block and a second area block; The second side of the first area block is adjacent to the first side of the first gate structure, and the width of the first area block in the second direction remains unchanged; The second area block includes: a bottom edge, a top edge and a bevel edge; The bottom edge and the top edge both extend along the second direction, the bottom edge is adjacent to the first side of the first area block, and the bottom edge has a first width; the spacing between the top edge and the bottom edge is a first length, and the top edge has a second width; The hypotenuse connects the end points corresponding to the bottom edge and the top edge; a first angle is formed between the hypotenuse and the first direction; The second width is greater than or equal to zero, the first width is greater than the second width, and the first angle is greater than zero degrees; in the direction from the top edge to the bottom edge, the width of the second area block gradually increases and forms an internal potential distribution adjustment structure of the N-type region, and the sizes of the first width and the first angle meet the requirements of the potential difference between the top edge and the bottom edge.

2. The CMOS image sensor according to claim 1, wherein: The second area block is a trapezoid or a triangle.

3. The CMOS image sensor according to claim 1, wherein: The second area block is a combination structure of a plurality of trapezoids, the bottom sides of the trapezoids in the N-type region are aligned and connected together, and there is a gap between the top sides of the trapezoids; The total area of ​​each of the trapezoids in the N-type region meets the requirement of FWC.

4. The CMOS image sensor according to claim 3, wherein: The structural parameters of the trapezoids in the N-type region are the same.

5. The CMOS image sensor according to claim 1, wherein: The second area block is a combination structure of a plurality of triangles, the bottom sides of the triangles in the N-type region are aligned and connected together, the top sides of the triangles are vertices, and there are intervals between the vertices; The total area of ​​each of the triangles in the N-type region meets the requirement of FWC.

6. The CMOS image sensor according to claim 5, wherein: The structural parameters of the triangles in the N-type region are the same.

7. The CMOS image sensor according to claim 1, wherein: The N-type region is an N-type ion implantation region formed in a P-type semiconductor substrate; the P-type region of the photodiode is composed of the P-type semiconductor substrate located at the bottom of the N-type region.

8. The CMOS image sensor according to claim 1, wherein: The first gate structure is a planar gate or a trench gate.

9. A method for manufacturing a CMOS image sensor, characterized in that: The pixel area of ​​the CMOS image sensor includes a plurality of pixel units, each of which includes: a photodiode, a transfer transistor and a floating diffusion area; The transfer transistor comprises a first gate structure, the N-type region of the photodiode is located on a first side of the first gate structure and serves as a source region of the transfer transistor, and the floating diffusion region is located on a second side of the first gate structure and serves as a drain region of the transfer transistor; The first direction is the direction from the source region to the drain region, and the second direction is the extension direction of the first gate structure and the second direction is perpendicular to the first direction; The step of forming the N-type region comprises: Photolithography defines a formation area of ​​the N-type region, where the N-type region includes a first area block and a second area block on a plane in the first direction and the second direction; The second side of the first area block is adjacent to the first side of the first gate structure, and the width of the first area block in the second direction remains unchanged; The second area block includes: a bottom edge, a top edge and a bevel edge; The bottom edge and the top edge both extend along the second direction, the bottom edge is adjacent to the first side of the first area block, and the bottom edge has a first width; the spacing between the top edge and the bottom edge is a first length, and the top edge has a second width; The hypotenuse connects the end points corresponding to the bottom edge and the top edge; a first angle is formed between the hypotenuse and the first direction; The second width is greater than or equal to zero, the first width is greater than the second width, and the first angle is greater than zero degrees; in the direction from the top edge to the bottom edge, the width of the second region block gradually increases and forms an internal potential distribution adjustment structure of the N-type region, and the magnitudes of the first width and the first angle meet the requirements of the potential difference between the top edge and the bottom edge; N-type ion implantation is performed to form the N-type region in the P-type semiconductor substrate, and the P-type region of the photodiode is composed of the P-type semiconductor substrate located at the bottom of the N-type region.

10. The method for manufacturing a CMOS image sensor according to claim 9, wherein: The second area block is a trapezoid or a triangle.

11. The method for manufacturing a CMOS image sensor according to claim 9, wherein: The second area block is a combination structure of a plurality of trapezoids, the bottom sides of the trapezoids in the N-type region are aligned and connected together, and there is a gap between the top sides of the trapezoids; The total area of ​​each of the trapezoids in the N-type region meets the requirement of FWC.

12. The method for manufacturing a CMOS image sensor according to claim 11, wherein: The structural parameters of the trapezoids in the N-type region are the same.

13. The method for manufacturing a CMOS image sensor according to claim 9, wherein: The second area block is a combination structure of a plurality of triangles, the bottom sides of the triangles in the N-type region are aligned and connected together, the top sides of the triangles are vertices, and there are intervals between the vertices; The total area of ​​each of the triangles in the N-type region meets the requirement of FWC.

14. The method for manufacturing a CMOS image sensor according to claim 13, wherein: The structural parameters of the triangles in the N-type region are the same.

15. The method for manufacturing a CMOS image sensor according to claim 9, wherein: The first gate structure is a planar gate or a trench gate.

Images