High-temperature-resistant LED chip, preparation method thereof and display screen

Abstract

The invention discloses a high-temperature-resistant LED chip, a preparation method of the high-temperature-resistant LED chip and a display screen, and relates to the field of LED manufacturing. The preparation method comprises the steps of etching an epitaxial wafer to form a conductive step; forming a first photoresist layer and a second photoresist layer; forming a photoresist opening; evaporating a reflecting layer and a bonding wire layer; removing the first photoresist layer and the second photoresist layer; and forming a passivation layer and opening a hole. The photoresist opening comprises a first opening and a second opening, and the side wall of the cross section of the first opening comprises a first straight line section; the side wall of the cross section of the second opening comprises a second straight line section; included angles between the first straight line segment and the surface of the epitaxial wafer and between the second straight line segment and the surface of the epitaxial wafer are alpha 1 and alpha 2, and alpha 2-alpha 1 is greater than or equal to 65 degrees; included angles between the side wall of the reflecting layer and the surface of the epitaxial wafer and between the side wall of the bonding wire layer and the surface of the epitaxial wafer are beta1 and beta2; beta2-beta1 > = 60 degrees. The distance between the side wall of the bonding wire layer and the side wall of the reflecting layer is greater than or equal to 2 microns; by implementing the invention, the high-temperature resistance of the LED chip can be improved, and the reliability of the LED chip can be improved.

Description

Technical Field

[0001] The present invention relates to the field of LED manufacturing, and in particular to a high temperature resistant LED chip and a preparation method thereof, and a display screen. Background Art

[0002] In recent years, the market for display screens based on red, green and blue LED chips has expanded rapidly, and the demand is strong. Such LED chips used in display screens need to be used outdoors in different regions and environments, which places high demands on their high temperature resistance. Furthermore, as LED chips used in display screens are gradually miniaturized, more and more LED chips are integrated into a single display screen device, and the heat generated is also increasing, which in turn places higher demands on the high temperature resistance of a single LED chip.

[0003] On the other hand, in traditional LED chips, the electrodes generally include a reflective layer (usually Al) and a wire bonding layer (usually Au). Al metal easily expands at high temperatures and comes into contact with Au, which then reacts to form an Al-Au alloy. This alloy is a brittle solid solution and is prone to failure during use. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a high temperature resistant LED chip and a preparation method thereof, which has strong high temperature resistance and high reliability.

[0005] Another technical problem to be solved by the present invention is to provide a display screen with high reliability.

[0006] In order to solve the above technical problems, the present invention provides a method for preparing a high temperature resistant LED chip, which comprises the following steps: S1. Providing an epitaxial wafer; wherein the epitaxial wafer comprises a substrate and a first semiconductor layer, an active layer, and a second semiconductor layer sequentially stacked on the substrate; S2, etching the epitaxial wafer to form a conductive step; S3, forming a first photoresist layer on the epitaxial wafer obtained in step S2; S4, forming a second photoresist layer on the first photoresist layer; S5, exposing and developing the epitaxial wafer obtained in step S4, removing the first photoresist layer and the second photoresist layer in the preset area, and forming a photoresist opening; the photoresist opening includes a first opening and a second opening arranged in sequence from bottom to top, the side wall of the cross section of the first opening includes at least a first arc segment and a first straight line segment connected thereto; the side wall of the cross section of the second opening includes at least a second arc segment and a second straight line segment connected thereto; the angle between the first straight line segment and the surface of the epitaxial wafer is α1, the angle between the second straight line segment and the surface of the epitaxial wafer is α2, and α2-α1≥65°; S6, vapor deposition on the epitaxial wafer obtained in step S5, forming a reflective layer on the second photoresist layer and in the photoresist opening; the reflective layer includes a reflective sublayer and a protective layer covering the reflective sublayer; the angle between the side wall of the reflective layer in the photoresist opening and the surface of the epitaxial wafer is β1; S7, vapor deposition on the epitaxial wafer obtained in step S6, forming a wire bonding layer on the reflective layer; the angle between the side wall of the wire bonding layer located in the photoresist opening and the surface of the epitaxial wafer is β2, β2-β1≥60°; and there is a preset distance L between the side wall of the wire bonding layer located in the photoresist opening and the side wall of the reflective layer located in the photoresist opening, L≥2μm; S8, removing the first photoresist layer, the second photoresist layer, and the reflective layer and the bonding wire layer thereon; S9, forming a passivation layer on the epitaxial wafer obtained in step S8, and forming a wire bonding hole above the wire bonding layer, so as to obtain a finished high temperature resistant LED chip.

[0007] As an improvement of the above technical solution, the first photoresist layer is formed by a first photoresist, and the second photoresist layer is formed by a second photoresist; the viscosity of the first photoresist is less than the viscosity of the second photoresist; The thickness of the first photoresist layer is smaller than the thickness of the second photoresist layer.

[0008] As an improvement of the above technical solution, the first photoresist is a negative photoresist having a viscosity of 40-60 cP; The second photoresist is a negative photoresist having a viscosity of 80-100 cP; The thickness of the first photoresist layer is 1 / 3 to 1 / 2 of the thickness of the second photoresist layer.

[0009] As an improvement of the above technical solution, the reflective sublayer is an Al layer with a thickness of 1200-3000Å; The protective layer comprises a Ti layer, a first Pt layer, a Ni layer and a second Pt layer stacked sequentially on the reflective sublayer, the Ti layer has a thickness of 1000-2000Å, the first Pt layer has a thickness of 500-1000Å, the Ni layer has a thickness of 1000-2000Å, and the second Pt layer has a thickness of 500-1000Å; The bonding wire layer is an Au layer, and its thickness is 15000-20000Å; The passivation layer is Al 2 O 3 layer, with a thickness of 600~1200Å.

[0010] As an improvement of the above technical solution, in step S6, when evaporating the reflective layer, the metal beam has a first angle with the surface of the epitaxial wafer; In step S7, when the protective layer is evaporated, the metal beam has a second angle with the surface of the epitaxial wafer; The second angle is less than the first angle.

[0011] As an improvement of the above technical solution, the first angle is 40°~50°, and the second angle is 30°~35°.

[0012] As an improvement of the above technical solution, the value range of α1 is 15°~30°, and the value range of α2 is 85°~90°; The value range of β1 is 20°~40°, and the value range of β2 is 80°~88°; The value range of L is 2~4μm; The thickness of the first photoresist layer is 1-3 μm, and the thickness of the second photoresist layer is 5-10 μm.

[0013] As an improvement of the above technical solution, step S5 includes: S51, using an exposure light source with a wavelength of 280-350 nm to expose the epitaxial wafer obtained in step S4 for 5-15 seconds, with a light intensity of 100-150 mJ / cm 2 ; S52: Expose the epitaxial wafer obtained in step S51 for 3-5 seconds using an exposure light source with a wavelength of 310-380 nm and a light intensity of 150-200 mJ / cm 2 ; S53, spraying the epitaxial wafer obtained in step S52 with a developer having a pressure of 0.5-0.9 bar for 30-40 seconds; wherein the temperature of the developer is 18-20° C.; S54, spraying the epitaxial wafer obtained in step S53 with a developer having a pressure of 1 to 1.3 bar for 50 to 90 seconds; wherein the temperature of the developer is 25 to 28° C.; S55, baking the epitaxial wafer obtained in step S54 at 100-110°C for 40-100s, then baking at 120-140°C for 5-10min, and finally baking at 115-125°C for 5-10min.

[0014] Correspondingly, the present invention also discloses a high temperature resistant LED chip, which is prepared by the above-mentioned preparation method of the high temperature resistant LED chip.

[0015] Correspondingly, the present invention also discloses a display screen, which includes the above-mentioned high temperature resistant LED chip.

[0016] The implementation of the present invention has the following beneficial effects: In the preparation method of the high temperature resistant LED chip in one embodiment of the present invention, a first photoresist layer and a second photoresist layer are sequentially formed on the epitaxial wafer, a photoresist opening with a specific shape is formed by exposure and development, and then a reflective layer and a protective layer are sequentially evaporated, and finally a passivation layer is formed and opened to obtain a finished high temperature resistant LED chip. Specifically, the photoresist opening includes a first opening and a second opening sequentially arranged from bottom to top, and the side wall of the cross section of the first opening includes at least a first arc segment and a first straight line segment connected thereto; the side wall of the cross section of the second opening includes at least a second arc segment and a second straight line segment connected thereto; the angle between the first straight line segment and the surface of the epitaxial wafer is α1, and the angle between the second straight line segment and the surface of the epitaxial wafer is α2, and α2-α1≥65°. Based on the photoresist opening of this specific morphology, the angles β1 and β2 between the side walls of the reflective layer and the side walls of the wire bonding layer and the surface of the epitaxial wafer formed later meet the relationship of β2-β1≥60°, and a preset distance L is provided between the side walls of the wire bonding layer and the side walls of the reflective layer, L≥2μm; such a setting greatly prolongs the service life of the LED chip in a high temperature environment and improves the reliability of the LED chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a schematic diagram of the structure of the epitaxial wafer after step S2 in one embodiment of the present invention; Figure 2 is a schematic diagram of the structure of the epitaxial wafer after step S5 in one embodiment of the present invention; Figure 3 is a schematic diagram of the structure of the epitaxial wafer after step S7 in one embodiment of the present invention; Figure 4 is a schematic structural diagram of a high temperature resistant LED chip in one embodiment of the present invention; In the figure, 1 is an epitaxial wafer, 11 is a substrate, 12 is a first semiconductor layer, 13 is an active layer, 14 is a second semiconductor layer, 15 is a conductive step, 16 is an isolation groove, 2 is a transparent conductive layer, 3 is a first photoresist layer, 4 is a second photoresist layer, 5 is a photoresist opening, 51 is a first opening, 511 is a first arc segment, 512 is a first straight line segment, 52 is a second opening, 521 is a second arc segment, 522 is a second straight line segment, 6 is a reflective layer, 61 is a reflective sublayer, 62 is a protective layer, 621 is a Ti layer, 622 is a first Pt layer, 623 is a Ni layer, 624 is a second Pt layer, 63 is a side wall of the reflective layer, 7 is a welding wire layer, 71 is a side wall of the welding wire layer, 8 is a passivation layer, and 81 is a welding wire hole. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limiting the present application. In addition, it should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0019] In the description of the present application, it should be understood that the terms "length", "width", "up", "down", "left", "right", "horizontal", "top", "bottom", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0020] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features.

[0021] The present invention discloses a method for preparing a high temperature resistant LED chip, which comprises the following steps: S1. Provide epitaxial wafers; The epitaxial wafer 1 includes a substrate 11 and an epitaxial layer. The epitaxial layer includes a first semiconductor layer 12, an active layer 13 and a second semiconductor layer 14 stacked on the substrate 11 in sequence. The substrate 11 is a sapphire substrate, a silicon substrate or a SiC substrate, but is not limited thereto. The first semiconductor layer 12 may be an N-type GaN layer, an N-type AlGaN layer, or an N-type GaAs layer, but is not limited thereto. The active layer 13 may be an InGaN-GaN type MQW layer, an InGaN-AlGaN type MQW layer or an AlGaN-AlGaN type MQW layer, but is not limited thereto. The second semiconductor layer 14 may be a P-type GaN layer, a P-type AlGaN layer, or a P-type GaAs layer, but is not limited thereto.

[0022] Preferably, in an embodiment of the present invention, the epitaxial layer may further include one or more of a buffer layer, an intrinsic semiconductor layer, a stress buffer layer, an electron blocking layer, and an ohmic contact layer commonly used in the art, but is not limited thereto.

[0023] S2, etching the epitaxial wafer to form a conductive step; Specifically, a mask (photoresist layer, SiO 2 layer, etc.), and then remove the second semiconductor layer 14, the active layer 13 and a portion of the first semiconductor layer 12 in a preset area by wet etching or dry etching to form a conductive step 15, but is not limited thereto.

[0024] Preferably, in some embodiments, a photoresist layer is first formed on the epitaxial wafer 1 obtained in step S1, and after exposing, developing and patterning it, the second semiconductor layer 14, the active layer 13 and part of the first semiconductor layer 12 are etched away using an inductively coupled plasma etching process (ICP) to obtain a conductive step 15. Further, in some embodiments, see Figure 1 , continue etching at a preset position until the substrate 11 is exposed to form an isolation groove 16 for isolating a plurality of LED chips, and finally remove the photoresist layer.

[0025] Preferably, in some embodiments, step S2 comprises: S21, etching the epitaxial wafer obtained in step S1 to form a conductive step; Specifically, in this step, only the conductive step 15 is formed by etching, but the isolation trench 16 is not formed.

[0026] S22, forming a transparent conductive layer on the epitaxial wafer obtained in step S21; The transparent conductive layer 2 may be a common ITO layer, IZO layer, AZO layer, ATO layer or FTO layer in the art, but is not limited thereto. Preferably, the transparent conductive layer 2 is an ITO layer. The thickness of the transparent conductive layer 2 is 5 to 150 nm, preferably 50 to 150 nm.

[0027] The transparent conductive layer 2 can be formed by a process such as magnetron sputtering, electron beam evaporation, etc., but is not limited thereto. Preferably, in one embodiment, after the transparent conductive layer 2 is formed, it is annealed at a temperature of 500-600° C. for a time of 3-10 minutes. Through annealing, its light transmittance can be optimized, and its ohmic contact with the second semiconductor layer 14 can be optimized.

[0028] S23, etching and removing the transparent conductive layer in the preset area, and retaining the transparent conductive layer on the second semiconductor layer; Specifically, a mask (photoresist layer, SiO 2 layer, etc.), and then remove the transparent conductive layer 2 in a preset area by wet etching or dry etching, leaving only the transparent conductive layer 2 on the second semiconductor layer 14, but not limited thereto.

[0029] Preferably, in some implementations, a photoresist layer is first formed on the epitaxial wafer 1 obtained in step S22, and after being exposed, developed and patterned, a corrosive solution is used to corrode and remove the transparent conductive layer 2 in a preset area, and then the photoresist layer is removed.

[0030] S24, etching to form an isolation groove; Specifically, a mask (photoresist layer, SiO 2 layer, etc.), and then remove the conductive step 15 in a predetermined area by wet etching or dry etching to form an isolation groove 16 exposing the substrate 11, but the present invention is not limited thereto.

[0031] Preferably, in some implementations, a photoresist layer is first formed on the epitaxial wafer 1 obtained in step S23 , and after being exposed, developed and patterned, the conductive step 15 is etched by an ICP process to form an isolation groove 16 .

[0032] It should be noted that, in some embodiments, before forming the conductive step 15 , a transparent conductive layer 2 is first formed on the epitaxial wafer 1 , and then the transparent conductive layer 2 is patterned, the conductive step 15 is formed, and the isolation groove 16 is formed by photolithography and etching processes.

[0033] S3, forming a first photoresist layer on the epitaxial wafer obtained in step S2; The first photoresist layer 3 is formed by a first photoresist, and the first photoresist is a common positive photoresist or a negative photoresist in the art, but is not limited thereto. Preferably, in one embodiment, the first photoresist is a negative photoresist, which has a high resolution and a large aspect ratio, and can lay a good foundation for forming a photoresist opening 5 of a specific shape of the present invention. The viscosity of the first photoresist is 40-80cP, exemplarily 45cP, 50cP, 60cP, 72cP or 78cP, but is not limited thereto. Preferably, it is 40-60cP.

[0034] Specifically, the first photoresist can be coated on the epitaxial wafer 1 by a spin coating process, and then baked and cured to form the first photoresist layer 3. Specifically, the thickness of the first photoresist layer 3 is 1-5 μm, exemplarily 1.5 μm, 2 μm, 3.5 μm or 4 μm, but not limited thereto, preferably 1-3 μm.

[0035] S4, forming a second photoresist layer on the first photoresist layer; The second photoresist layer 4 is formed by a second photoresist, and the second photoresist is a common positive photoresist or a negative photoresist in the art, but is not limited thereto. Preferably, in one embodiment, the second photoresist is a negative photoresist, which has a high resolution and a large aspect ratio, and lays a good foundation for forming the photoresist opening 5 of a specific shape of the present invention. The viscosity of the second photoresist is 60 to 100 cP, exemplarily 70 cP, 80 cP, 90 cP or 95 cP, but is not limited thereto. Preferably, it is 80 to 100 cP.

[0036] Specifically, the first photoresist can be coated on the epitaxial wafer 1 by a spin coating process, and then baked and cured to form the first photoresist layer 3. Specifically, the thickness of the second photoresist layer 4 is 3-15 μm, exemplarily 4.5 μm, 6 μm, 7.5 μm, 9 μm, 10.5 μm or 13 μm, but not limited thereto. Preferably, it is 5-10 μm.

[0037] Preferably, in some embodiments, in order to enhance the connection between the first photoresist layer 3 and the second photoresist layer 4 , before forming the second photoresist layer 4 , an adhesion promoter is firstly coated on the first photoresist layer 3 .

[0038] Preferably, in some embodiments, when both the first photoresist and the second photoresist are negative photoresists, the viscosity of the first photoresist is controlled to be less than the viscosity of the second photoresist. Based on this control, on the one hand, it can be ensured that when the thickness of the second photoresist layer 4 is greater than that of the first photoresist layer 3, both are relatively uniform; on the other hand, the developer in the second photoresist layer 4 diffuses more slowly, which is conducive to improving α2-α1. Accordingly, in the photoresist layer formed by the first photoresist and the second photoresist, the thickness of the first photoresist layer 3 is less than the thickness of the second photoresist layer 4. More specifically, the thickness of the first photoresist layer 3 is 1 / 3 to 1 / 2 of the thickness of the second photoresist layer 4. By controlling the thickness ratio of the two, α2-α1 can be further improved, thereby increasing the distance L between the side wall 71 of the welding wire layer and the side wall 63 of the reflective layer in the subsequent finished electrode, and further improving the high temperature resistance of the LED chip.

[0039] S5, exposing and developing the epitaxial wafer obtained in step S4, removing the first photoresist layer and the second photoresist layer in the preset area, and forming a photoresist opening; Specifically, an exposure light source is used for exposure, and then a developer is used for development to remove the conductive step 15 and a portion of the first photoresist layer 3 and the second photoresist layer 4 on the second semiconductor layer 14, thereby obtaining a photoresist opening 5. The wavelength of the exposure light source is 280-380 nm, and the light intensity is 100-200 mJ / cm 2 The exposure time is 5 to 20 seconds. The development time is 50 to 150 seconds, and post-baking is performed after development, but is not limited thereto.

[0040] Specifically, see Figure 2 After the exposure and development process, a photoresist opening 5 is formed, which includes a first opening 51 and a second opening 52 arranged in sequence from bottom to top. The side wall of the cross section of the first opening 51 includes at least a first arc segment 511 and a first straight segment 512 connected thereto; the side wall of the cross section of the second opening 52 includes at least a second arc segment 521 and a second straight segment 522 connected thereto; the angle between the first straight segment 512 and the surface of the epitaxial wafer 1 is α1, and the angle between the second straight segment 522 and the surface of the epitaxial wafer 1 is α2, and α2-α1≥65°. More specifically, α2-α1=65°~75°.

[0041] Specifically, the value range of α1 is 10° to 35°, exemplarily 12°, 18°, 24°, 30° or 33°, but not limited thereto, preferably 15° to 30°.

[0042] Specifically, the value range of α2 is 80° to 90°, exemplarily 82°, 84°, 86° or 88°, but not limited thereto, preferably 85° to 90°.

[0043] Preferably, in some embodiments, step S5 comprises: S51, using an exposure light source with a wavelength of 280-350 nm to expose the epitaxial wafer obtained in step S4 for 5-15 seconds, with a light intensity of 100-150 mJ / cm 2 ; S52: Expose the epitaxial wafer obtained in step S51 for 3-5 seconds using an exposure light source with a wavelength of 310-380 nm and a light intensity of 150-200 mJ / cm 2 ; S53, spraying the epitaxial wafer obtained in step S52 with a developer having a pressure of 0.5-0.9 bar for 30-40 seconds; wherein the temperature of the developer is 18-20° C.; S54, spraying the epitaxial wafer obtained in step S53 with a developer having a pressure of 1 to 1.3 bar for 50 to 90 seconds; wherein the temperature of the developer is 25 to 28° C.; S55, baking the epitaxial wafer obtained in step S54 at 100-110°C for 40-100s, then baking at 120-140°C for 5-10min, and finally baking at 115-125°C for 5-10min.

[0044] Based on the above specific exposure-development-post-baking process, α2-α1 can be increased to 68°~75°, further optimizing the high temperature resistance of the LED chip.

[0045] S6, vapor deposition on the epitaxial wafer obtained in step S5 to form a reflective layer on the second photoresist layer and in the photoresist opening; Specifically, when the reflective layer 6 is evaporated, the metal beam has a first angle with the surface of the epitaxial wafer 1. It should be noted that the surface of the epitaxial wafer 1 in the present invention refers to the plane where the substrate 11 is located. By controlling the first angle and matching the photoresist opening 5 with a specific shape, a reflective layer 6 with a larger width and a relatively smaller thickness can be formed at the bottom of the photoresist opening 5, thereby reducing the risk of the reflective layer 6 contacting the subsequent welding wire layer 7 due to high-temperature expansion, thereby improving the high-temperature resistance of the LED chip. Specifically, the first angle is 35°~50°, exemplarily 38°, 40°, 43°, 46° or 49°, but not limited thereto. Preferably, it is 40°~50°.

[0046] Specifically, the reflective layer 6 includes a reflective sublayer 61 and a protective layer 62 stacked in sequence, and the reflective sublayer 61 may be an Al layer, an Al-Cu alloy layer or an Ag layer, but is not limited thereto. Preferably, in some embodiments, the reflective sublayer 61 is an Al layer. The thickness of the reflective sublayer 61 is 1000-3000Å, exemplarily 1200Å, 1500Å, 1800Å, 2100Å, 2400Å or 2700Å, but is not limited thereto. Preferably, it is 1200-3000Å.

[0047] Specifically, the protective layer 62 is a metal layer that can cover the reflective sublayer 61, and can be a Pt layer, a Ti layer, a TiN layer or a Ni layer, but not limited thereto. The protective layer 62 can improve the ability of the electrode to resist moisture corrosion, and can block metal diffusion, thereby improving the reliability of the LED chip. Specifically, the thickness of the protective layer 62 is 2000-10000Å, and is exemplarily 3000Å, 4500Å, 6000Å, 7500Å or 9000Å, but not limited thereto. Preferably, in some embodiments, the protective layer 62 includes a Ti layer 621, a first Pt layer 622, a Ni layer 623 and a second Pt layer 624 stacked in sequence, wherein the thickness of the Ti layer 621 is 1000~2000Å, the thickness of the first Pt layer 622 is 500~1000Å, the thickness of the Ni layer 623 is 1000~2000Å, and the thickness of the second Pt layer 624 is 500~1000Å.

[0048] Specifically, the angle between the side wall 63 of the reflective layer and the surface of the epitaxial wafer 1 is β1, and the value range of β1 is 18° to 40°, exemplarily 22°, 26°, 32° or 36°, but not limited thereto, preferably 20° to 40°.

[0049] S7, vapor deposition is performed on the epitaxial wafer obtained in step S6 to form a bonding wire layer on the reflective layer; Specifically, see Figure 3 When evaporating the wire bonding layer 7, the metal beam has a second angle with the surface of the epitaxial wafer 1. It should be noted that the surface of the epitaxial wafer 1 in the present invention refers to the plane where the substrate 11 is located. By controlling the second angle and matching the photoresist opening 5 of a specific shape, a wire bonding layer 7 with a larger thickness and smaller width can be formed on the reflective layer 6, so that the side wall 71 of the wire bonding layer and the side wall 63 of the reflective layer have a preset distance L, and L ≥ 2μm, which effectively prevents the reflective layer 6 from contacting the wire bonding layer 7 after high-temperature expansion, greatly improving the high-temperature resistance of the LED chip. Specifically, the second angle is 25°~40°, exemplarily 28°, 31°, 34° or 37°, but not limited thereto. Preferably, it is 30°~35°.

[0050] Preferably, in some embodiments, the second angle is less than the first angle, so as to further increase L and improve the high temperature resistance. Specifically, the value range of L is 2-5 μm. If L is too large, the width of the welding wire layer 7 is too narrow, which affects the subsequent welding wire process. Exemplarily, L is 2.3 μm, 3 μm, 3.4 μm or 4.5 μm, but not limited thereto. Preferably, it is 2-4 μm.

[0051] Specifically, the wire bonding layer 7 is an Au layer or an Ag layer, but not limited thereto. Preferably, it is an Au layer. The thickness of the wire bonding layer 7 is 10000-20000Å, exemplarily 12000Å, 14000Å, 16000Å or 18000Å, but not limited thereto. Preferably, it is 15000-20000Å.

[0052] Specifically, the angle between the side wall 71 of the bonding wire layer and the surface of the epitaxial wafer 1 is β2, and the value range of β2 is 75° to 90°, exemplarily 78°, 83°, 85° or 87°, but not limited thereto, preferably 80° to 88°.

[0053] Specifically, β2-β1≥60°. More specifically, β2-β1=60°~70°.

[0054] S8, removing the first photoresist layer, the second photoresist layer, and the reflective layer and the bonding wire layer thereon; Specifically, the first photoresist layer 3, the second photoresist layer 4, and the reflective layer 6 and the wire bonding layer 7 thereon can be removed by a cleaning solution, but the invention is not limited thereto. Preferably, in some embodiments, the reflective layer 6 and the wire bonding layer 7 on the first photoresist layer 3 and the second photoresist layer 4 are removed by a blue film stripping process, and then the first photoresist layer 3 and the second photoresist layer 4 are removed by cleaning with a cleaning solution.

[0055] S9, forming a passivation layer 8 on the epitaxial wafer 1 obtained in step S8, and forming a bonding wire hole above the bonding wire layer 7, so as to obtain a finished high temperature resistant LED chip.

[0056] Specifically, step S9 includes: S91, forming a passivation layer on the epitaxial wafer 1 obtained in step S8; Among them, see Figure 4 The passivation layer 8 may be made of SiO 2 、Al 2 O 3 、SiN x 、SiO x N y Preferably, in some embodiments, the passivation layer 8 is Al 2 O 3 The thickness of the passivation layer 8 is 500-3000Å, illustratively 800Å, 1400Å, 2100Å or 2600Å, but not limited thereto. Preferably, it is 500-1200Å.

[0057] The passivation layer 8 may be formed by PECVD, ALD or MOCVD, but is not limited thereto. Preferably, the Al 2 O 3 layer, serving as a passivation layer 8.

[0058] S92, etching the passivation layer to form a bonding wire hole above the bonding wire layer; Specifically, the passivation layer 8 in the preset area can be removed by dry etching or wet etching to obtain the wire bonding hole 81, but it is not limited thereto. Preferably, in one embodiment, the wire bonding hole 81 is formed by etching by ICP etching.

[0059] In summary, in the preparation method of the high temperature resistant LED chip in this embodiment, the first photoresist layer 3 and the second photoresist layer 4 are sequentially formed on the epitaxial wafer 1, and a photoresist opening 5 with a specific shape is formed by exposure and development, and then the reflective layer 6 and the protective layer 62 are sequentially evaporated, and finally the passivation layer 8 is formed and opened to obtain a finished high temperature resistant LED chip. Specifically, the photoresist opening 5 includes a first opening 51 and a second opening 52 arranged sequentially from bottom to top, and the side wall of the cross section of the first opening 51 includes at least a first arc segment 511 and a first straight line segment 512 connected thereto; the side wall of the cross section of the second opening 52 includes at least a second arc segment 521 and a second straight line segment 522 connected thereto; the angle between the first straight line segment 512 and the surface of the epitaxial wafer 1 is α1, and the angle between the second straight line segment 522 and the surface of the epitaxial wafer 1 is α2, and α2-α1≥65°. Based on the photoresist opening 5 with a specific morphology, the angles β1 and β2 between the side wall 63 of the reflective layer, the side wall 71 of the wire bonding layer and the surface of the epitaxial wafer 1 formed later meet the relationship of β2-β1≥60°, and a preset distance L is provided between the side wall 71 of the wire bonding layer and the side wall 63 of the reflective layer, wherein L≥2μm. This arrangement greatly prolongs the service life of the LED chip in a high temperature environment and improves the reliability of the LED chip.

[0060] Specifically, based on the technical solution in this embodiment and conventional LED chips, the high temperature aging time is shown in the following table:

[0061] Specifically, the high temperature experiment process is as follows: first record the working voltage value of the LED chip before the high temperature aging begins, which is defined as the initial voltage value; after the high temperature aging begins, record the voltage value of the LED chip every 24 hours, which is defined as the current voltage value; when the difference between the current voltage value and the initial voltage value exceeds 0.1V, the LED chip fails, and the current high temperature aging time node is recorded. The high temperature aging temperature is 95℃ and the humidity is 50%RH.

[0062] It can be seen from the table that the high-temperature aging time of the LED chip in this technical solution is greatly extended.

[0063] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0064] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A method for preparing a high temperature resistant LED chip, characterized in that: The following steps are involved: S1. Providing an epitaxial wafer; wherein the epitaxial wafer comprises a substrate and a first semiconductor layer, an active layer, and a second semiconductor layer sequentially stacked on the substrate; S2, etching the epitaxial wafer to form a conductive step; S3, forming a first photoresist layer on the epitaxial wafer obtained in step S2; S4, forming a second photoresist layer on the first photoresist layer; S5, exposing and developing the epitaxial wafer obtained in step S4, removing the first photoresist layer and the second photoresist layer in the preset area, and forming a photoresist opening; the photoresist opening includes a first opening and a second opening arranged in sequence from bottom to top, the side wall of the cross section of the first opening includes at least a first arc segment and a first straight line segment connected thereto; the side wall of the cross section of the second opening includes at least a second arc segment and a second straight line segment connected thereto; the angle between the first straight line segment and the surface of the epitaxial wafer is α1, the angle between the second straight line segment and the surface of the epitaxial wafer is α2, and α2-α1≥65°; S6, vapor deposition on the epitaxial wafer obtained in step S5, forming a reflective layer on the second photoresist layer and in the photoresist opening; the reflective layer includes a reflective sublayer and a protective layer covering the reflective sublayer; the angle between the side wall of the reflective layer in the photoresist opening and the surface of the epitaxial wafer is β1; S7, vapor deposition on the epitaxial wafer obtained in step S6, forming a wire bonding layer on the reflective layer; the angle between the side wall of the wire bonding layer located in the photoresist opening and the surface of the epitaxial wafer is β2, β2-β1≥60°; and there is a preset distance L between the side wall of the wire bonding layer located in the photoresist opening and the side wall of the reflective layer located in the photoresist opening, L≥2μm; S8, removing the first photoresist layer, the second photoresist layer, and the reflective layer and the bonding wire layer thereon; S9, forming a passivation layer on the epitaxial wafer obtained in step S8, and forming a wire bonding hole above the wire bonding layer, so as to obtain a finished high temperature resistant LED chip.

2. The method for preparing a high temperature resistant LED chip according to claim 1, characterized in that: The first photoresist layer is formed of a first photoresist, and the second photoresist layer is formed of a second photoresist; the viscosity of the first photoresist is less than the viscosity of the second photoresist; The thickness of the first photoresist layer is smaller than the thickness of the second photoresist layer.

3. The method for preparing a high temperature resistant LED chip according to claim 2, characterized in that: The first photoresist is a negative photoresist having a viscosity of 40-60 cP; The second photoresist is a negative photoresist having a viscosity of 80-100 cP; The thickness of the first photoresist layer is 1 / 3 to 1 / 2 of the thickness of the second photoresist layer.

4. The method for preparing a high temperature resistant LED chip according to claim 1, characterized in that: The reflective sublayer is an Al layer, and its thickness is 1200-3000Å; The protective layer comprises a Ti layer, a first Pt layer, a Ni layer and a second Pt layer stacked sequentially on the reflective sublayer, the Ti layer has a thickness of 1000-2000Å, the first Pt layer has a thickness of 500-1000Å, the Ni layer has a thickness of 1000-2000Å, and the second Pt layer has a thickness of 500-1000Å; The bonding wire layer is an Au layer, and its thickness is 15000-20000Å; The passivation layer is an Al2O3 layer with a thickness of 600-1200Å.

5. The method for preparing a high temperature resistant LED chip according to claim 1, characterized in that: In step S6, when evaporating the reflective layer, the metal beam has a first angle with the surface of the epitaxial wafer; In step S7, when the protective layer is evaporated, the metal beam has a second angle with the surface of the epitaxial wafer; The second angle is less than the first angle.

6. The method for preparing a high temperature resistant LED chip according to claim 5, characterized in that: The first angle is 40°~50°, and the second angle is 30°~35°.

7. The method for preparing a high temperature resistant LED chip according to claim 1, characterized in that: The value range of α1 is 15°~30°, and the value range of α2 is 85°~90°; The value range of β1 is 20°~40°, and the value range of β2 is 80°~88°; The value range of L is 2~4μm; The thickness of the first photoresist layer is 1-3 μm, and the thickness of the second photoresist layer is 5-10 μm.

8. The method for preparing a high temperature resistant LED chip according to claim 1, characterized in that: Step S5 includes: S51, using an exposure light source with a wavelength of 280-350 nm to expose the epitaxial wafer obtained in step S4 for 5-15 seconds, with a light intensity of 100-150 mJ / cm 2 ; S52: Expose the epitaxial wafer obtained in step S51 for 3-5 seconds using an exposure light source with a wavelength of 310-380 nm and a light intensity of 150-200 mJ / cm 2 ; S53, spraying the epitaxial wafer obtained in step S52 with a developer having a pressure of 0.5-0.9 bar for 30-40 seconds; wherein the temperature of the developer is 18-20° C.; S54, spraying the epitaxial wafer obtained in step S53 with a developer having a pressure of 1 to 1.3 bar for 50 to 90 seconds; wherein the temperature of the developer is 25 to 28° C.; S55, baking the epitaxial wafer obtained in step S54 at 100-110°C for 40-100s, then baking at 120-140°C for 5-10min, and finally baking at 115-125°C for 5-10min.

9. A high temperature resistant LED chip, characterized in that: The LED chip is prepared by the method for preparing a high temperature resistant LED chip as described in any one of claims 1 to 8.

10. A display screen, characterized in that: It comprises the high temperature resistant LED chip as claimed in claim 9.

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