Micro-display chip, manufacturing method thereof and display panel

Abstract

The invention discloses a micro-display chip which comprises a light-emitting area and a non-light-emitting area, the non-light-emitting area is arranged around the light-emitting area and comprises a packaging layer, and the surface of the packaging layer comprises a plurality of coarse structures. The surface of the packaging layer is etched and coarsened, so that the reflectivity of the packaging layer can be reduced, light rays emitted by the light-emitting area are reflected by the outside to reach the surface of the packaging area and then diffuse reflection is generated, re-reflection of full-wave-band light rays is effectively reduced, and the image display quality is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of micro light emitting diodes, and in particular to a micro display chip and a manufacturing method thereof, and a display panel. Background Art

[0002] Micro LED (Micro Light Emitting Diode) micro display chip is a new type of LED structure obtained by thinning, miniaturizing and arraying the original LED structure. It integrates arrayed micron-level LED units on an active addressing drive panel to realize the lighting and individual control of the LED units, thereby outputting the desired display image. The Micro LED micro display panel formed by the Micro LED micro display chip can be used in many products such as AR glasses.

[0003] Figure 1 A schematic diagram showing the structure of an existing Micro LED micro display panel is shown in FIG. Figure 1 As shown, the existing MicroLED micro display panel 001 includes a micro display chip 011, an outer frame 012, a connecting wire 013 and a connector 014, wherein the outer frame 012 is arranged around the micro display chip 011, one end of the connecting wire 013 is connected to the micro display chip 011, and the other end is connected to the connector 014, and the connector 014 is used to connect with external matching equipment. As shown in the figure, the micro display chip 011 includes a light-emitting area 0111 and a non-light-emitting area 0112 surrounding the light-emitting area 0111, and the non-light-emitting area 0112 has a metal layer. Figure 2 yes Figure 1 The light propagation path diagram of the Micro LED micro display panel of the embodiment shown is applied to AR glasses. Figure 2 As shown, the light emitted by the Micro LED micro display panel 001 reaches the light guide lens 003 after passing through the optical lens 002 and can be displayed in the developing area of ​​the light guide lens 003.

[0004] However, if Figure 2 As shown, in the existing products, when the light emitted by the Micro LED micro display panel 001 reaches the optical waveguide lens 003, part of the light will be reflected back to the non-luminous area 0112 on the Micro LED micro display panel 001, and then enter the optical waveguide lens 003 again after being reflected by the metal layer on the non-luminous area 0112, thereby causing two images to be formed at different positions of the optical waveguide lens 003. The image formed after reflection from the non-luminous area 0112 is also called a "ghost image". The presence of a "ghost image" will significantly reduce the display quality. Summary of the invention

[0005] In view of some or all of the problems in the prior art, the present invention provides a micro display chip in a first aspect, comprising:

[0006] a light emitting area; and

[0007] The non-luminescent region is arranged around the luminescent region, and the non-luminescent region includes a packaging layer, wherein the surface of the packaging layer includes a plurality of coarse super structures.

[0008] Furthermore, the material of the encapsulation layer is solid plastic.

[0009] Furthermore, the material of the packaging layer includes epoxy resin.

[0010] Furthermore, the rough structure is nanoparticles, and the average diameter of the nanoparticles is no more than 1 micron.

[0011] Furthermore, the reflectivity of the surface of the encapsulation layer having the rough structure is not higher than 0.5%.

[0012] Furthermore, a shielding layer is provided at the periphery of the light emitting area, and the encapsulation layer is located on the surface of or above the shielding layer.

[0013] Furthermore, the side wall of the encapsulation layer close to the light emitting region does not exceed the side wall of the shielding layer close to the light emitting region, so that the surface of the shielding layer close to the light emitting region is exposed.

[0014] Furthermore, the exposed surface of the shielding layer close to the light emitting area has another rough structure.

[0015] Furthermore, the another rough structure is nanoparticles, and the average diameter of the nanoparticles is no more than 1 micrometer.

[0016] Furthermore, the shielding layer can shield and absorb light; and the reflectivity of the surface of the shielding layer is not higher than 0.5%.

[0017] Furthermore, the material of the shielding layer includes: photoresist, grey glue, inorganic anti-reflective material or black inorganic material.

[0018] Based on the micro display chip as described above, a second aspect of the present invention provides a display panel, which includes the micro display chip as described above.

[0019] Furthermore, the display panel further includes:

[0020] A connecting wire, comprising a first connecting end and a second connecting end opposite to each other, wherein the first connecting end of the connecting wire is electrically connected to the micro display chip; and

[0021] A connector, the second connection end of the connection line is electrically connected to the connector, and the connector is connected to a matching device in the outside world.

[0022] The third aspect of the present invention provides a method for manufacturing the aforementioned micro display chip, comprising:

[0023] forming a metal layer on the driver backplane;

[0024] forming a micro light emitting diode array and a micro lens array on the surface of the metal layer to form a light emitting area of ​​a micro display chip, wherein the edge of the micro light emitting diode array does not exceed the edge of the metal layer;

[0025] forming a shielding layer or an encapsulation layer on the surface of the metal layer not covered by the micro-LED array, wherein if an encapsulation layer is formed, the encapsulation layer completely covers the surface of the metal layer, and if a shielding layer is formed, the shielding layer at least covers a portion of the surface of the metal layer; and

[0026] An encapsulation layer is formed on the surface of the shielding layer and / or the metal layer not covered by the shielding layer, wherein the surface of the encapsulation layer includes a plurality of rough structures.

[0027] Further, forming the shielding layer includes:

[0028] Forming a light absorbing material layer on the metal layer by at least one coating and exposure and development process; and

[0029] The light absorbing material layer is exposed and developed based on a mask to remove the light absorbing material film formed on the light emitting area.

[0030] Further, forming the encapsulation layer includes:

[0031] forming a solidified material layer on the metal layer;

[0032] The surface of the solidified material layer is roughened so that the surface of the encapsulation layer has a plurality of rough structures.

[0033] Furthermore, the roughening process includes:

[0034] A plasma treatment device is used to bombard the surface of the solidified material layer, so that the surface of the encapsulation layer has a plurality of rough structures.

[0035] Furthermore, the gas used during bombardment includes one or more of O2 and Ar.

[0036] The present invention provides a micro display chip, which includes a shielding layer and an encapsulation layer, and the surface of the encapsulation layer is etched and roughened to reduce its reflectivity, so that the light emitted from the light-emitting area is reflected by the outside world and reaches the surface of the encapsulation area to generate diffuse reflection, which can effectively reduce the re-reflection of the full-band light and improve the picture display quality. In addition, the surface roughening treatment can also optimize the demoulding mark formed by the micro display chip package. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] To further illustrate the above and other advantages and features of various embodiments of the present invention, a more specific description of various embodiments of the present invention will be presented with reference to the accompanying drawings. It will be understood that these drawings only depict typical embodiments of the present invention and are therefore not to be considered as limiting the scope thereof. In the accompanying drawings, for clarity, identical or corresponding parts will be represented by identical or similar reference numerals.

[0038] Figure 1 A schematic diagram showing the structure of an existing Micro LED micro display panel;

[0039] Figure 2 Show Figure 1 A light propagation path diagram of a MicroLED micro display panel of the prior art applied to AR glasses;

[0040] Figure 3 A schematic diagram showing a top view of a metal layer of a micro light emitting diode display chip according to an embodiment of the present invention;

[0041] Figure 4 Show Figure 3 A cross-sectional schematic diagram of the embodiment along line AA;

[0042] Figure 5 A schematic diagram showing a partial structure of a light emitting area of ​​a micro light emitting diode display chip according to an embodiment of the present invention;

[0043] Figure 6 A schematic diagram showing a top view of a micro display panel according to an embodiment of the present invention;

[0044] Figure 7 Show Figure 6 A cross-sectional schematic diagram of the embodiment along line AA;

[0045] Figures 8A to 8E A schematic diagram showing a top view of a micro display panel according to different embodiments of the present invention;

[0046] Figures 9A to 9E Shown separately Figures 8A to 8E The cross-sectional schematic diagram of the embodiment shown is taken along line AA;

[0047] Fig.10A schematic flow chart showing a method for manufacturing a micro display chip according to an embodiment of the present invention;

[0048] Figures 11A to 11D A schematic diagram showing a process of a method for manufacturing a micro display chip according to an embodiment of the present invention;

[0049] Fig.12 A schematic flow chart showing a method for manufacturing a micro display chip according to another embodiment of the present invention; and

[0050] Figures 13A to 13E A schematic diagram showing a process of manufacturing a micro display chip according to yet another embodiment of the present invention. DETAILED DESCRIPTION

[0051] In the following description, the present invention is described with reference to various embodiments. However, those skilled in the art will recognize that various embodiments can be implemented without one or more specific details or with other replacement and / or additional methods, materials or components. In other cases, well-known structures, materials or operations are not shown or described in detail to avoid blurring the inventive point of the present invention. Similarly, for the purpose of explanation, specific quantities, materials and configurations are set forth to provide a comprehensive understanding of embodiments of the present invention. However, the present invention is not limited to these specific details. In addition, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn in correct proportions.

[0052] In this specification, reference to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present invention. The phrase "in one embodiment" appearing in various places in this specification does not necessarily all refer to the same embodiment.

[0053] In the description of the present invention, it should be understood that the terms "upper", "lower", "top surface", "bottom surface" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the positions or elements referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limitations of the present invention. In addition, the terms "first" and "second" are only used to distinguish an entity or operation from another entity or operation, and do not require or imply any actual relationship, order or relative importance between these entities or operations.

[0054] It should be noted that the embodiments of the present invention describe the process steps in a specific order, but this is only for the purpose of illustrating the specific embodiment, rather than limiting the order of the steps. On the contrary, in different embodiments of the present invention, the order of the steps can be adjusted according to the adjustment of the process.

[0055] like Figure 1 When the Micro LED micro-display panel shown is used in the corresponding product, when the light emitted from its light-emitting area reaches the light waveguide lens, part of the light will be reflected back to the non-light-emitting area of ​​the micro-display panel, and then reflected again into the light waveguide lens to form a ghost image. To solve this problem, a shielding layer with an uneven surface can be formed on the surface of the metal layer in the non-light-emitting area, so that the reflected light is diffusely reflected and the re-reflection of the full-band light is reduced. However, when forming the micro-display panel, the micro-display chip needs to be further surrounded by packaging, specifically, molded packaging, and the packaging layer formed may also reflect light, thereby affecting the display effect.

[0056] To solve this problem, the present invention further performs an etching and roughening treatment on the surface of the formed encapsulation layer after demolding is completed. On the one hand, it can further reduce the reflectivity of the encapsulation layer, and on the other hand, it can also repair the damage and abnormality of the shielding layer caused during the encapsulation process.

[0057] The technical solution of the present invention is further described below in conjunction with the accompanying drawings of the embodiments.

[0058] Figure 3 A schematic diagram of a metal layer structure of a micro light emitting diode display chip according to an embodiment of the present invention is shown. Figure 4 A cross-sectional schematic diagram of a micro-LED display chip along line AA according to an embodiment of the present invention is shown. As shown in the figure, a micro-LED display chip includes a light-emitting area 301 and a non-light-emitting area 302 arranged around the light-emitting area 301 .

[0059] As shown in the figure, in one embodiment of the present invention, the micro-LED display chip includes a driving backplane 401, and a light-emitting area 402 and a non-light-emitting area 403 formed on the driving backplane 401. The light-emitting area 402 includes a micro-LED array, and the micro-LED array includes a plurality of micro-LEDs 421, each of which can form at least a part of a pixel element on the micro-LED chip.

[0060] In an embodiment of the present invention, the size of each micro LED chip does not exceed 1 cm, preferably does not exceed 20 microns. The micro LED structure is formed in the micro LED chip in an array form, with a resolution of, for example, 720*480, 640*480, 1920*1080, 1280*720, 2K or 4K. The diameter of the micro LED structure is at the nanometer level, for example, 20nm to 100nm.

[0061] In some embodiments of the present invention, the micro light emitting diode array may include a single-layer micro light emitting diode structure. In some embodiments of the present invention, the micro light emitting diode array may include multiple layers of vertically stacked micro light emitting diode structures.

[0062] In some embodiments of the present invention, the micro-LED array may include blue micro-LEDs. In some embodiments of the present invention, the pitch of the micro-LED array, i.e., the minimum center-to-center distance between the micro-LEDs, may be between about 2 microns and about 50 microns. In some embodiments, the number of pixels on the micro-LED chip may be between thousands and millions.

[0063] In one embodiment of the present invention, the driving backplane may be electrically connected to each micro-LED in the micro-LED array via a separate metal interconnect. In some embodiments, each micro-LED may be electrically controlled individually by the driving backplane. In some embodiments, the driving backplane may be electrically connected to electrodes of a micro-LED chip via a metal interconnect. In some embodiments, a dielectric layer may be formed in the gaps between the micro-LEDs. In some embodiments, a dielectric layer may also be formed in the gaps between the interconnects.

[0064] Figure 5 FIG. 1 is a schematic diagram showing a partial structure of a light-emitting area of ​​a micro display panel according to an embodiment of the present invention. Figure 5 As shown, in one embodiment of the present invention, each micro-LED in the micro-LED array may include a micron-scale light-emitting mesa structure 501. In one embodiment of the present invention, the light-emitting mesa structure may include a first-type epitaxial layer 511, a light-emitting layer 512, and a second-type epitaxial layer 513 from bottom to top. That is, in the three-layer structure, the first-type epitaxial layer 511 is closest to the driving backplane 502; the light-emitting layer 512 is located above the first-type epitaxial layer 511 and is further away from the driving backplane 502; the second-type epitaxial layer 513 is located above the light-emitting layer 512 and is farthest away from the driving backplane 502. In some embodiments, the light-emitting layer 512 is formed by a plurality of stacked quantum well layers, in particular, superlattice stacked quantum well layers. Preferably, the superlattice stacked quantum well layers include a plurality of pairs of quantum well layers stacked with quantum barrier layers. In one embodiment of the present invention, the quantum well layer is an InGaN / GaN multi-quantum well layer or an InGaN / AlGaN multi-quantum well layer or an InGaAs / AlGaAs multi-quantum well layer. In one embodiment of the present invention, the light-emitting layer further comprises an electron blocking layer, and the electron blocking layer is arranged on a first side of the light-emitting layer, and the first side refers to a side along which electrons migrate out of the light-emitting layer.

[0065] In one embodiment of the present invention, the first type epitaxial layer 511 is a semiconductor material having a first conductivity type and includes a plurality of semiconductor layers. The main matrix material of the first type epitaxial layer 511 may be, but is not limited to, Ga, N, As, P, In and includes, but is not limited to, a waveguide layer, a confinement layer, a transition layer and a window layer; in addition, an ohmic contact layer may be formed below the window layer. In some embodiments, the second type epitaxial layer 513 is a semiconductor material having a second conductivity type and includes a plurality of semiconductor layers. The main matrix material of the second type epitaxial layer 513 may be, but is not limited to, composed of at least two or more elements of Ga, N, As, P, In and Al. In addition, the first type epitaxial layer 511 may include, from top to bottom, but is not limited to, a confinement layer and a waveguide layer; in addition, in some embodiments, an ohmic contact layer may be formed on the confinement layer. In one embodiment of the present invention, the first type epitaxial layer 511 is an N-type GaN layer or an N-type AlGaN layer, and the second type epitaxial layer 513 is a P-type GaN layer or a P-type AlGaN layer, that is, the material of the second type epitaxial layer 513 can be a material layer of the second conductivity type including at least two or more elements of Ga, N, As, Al, In, and P, and the first type epitaxial layer 511 can be a material layer of the first conductivity type including at least two or more elements of Ga, N, As, Al, In, and P. In another embodiment of the present invention, the first type epitaxial layer 511 can also be a P-type GaN layer or a P-type AlGaN layer, and the second type epitaxial layer 513 is an N-type GaN layer or an N-type AlGaN layer. In the embodiment of the present invention, the semiconductor light-emitting mesa 501 is stepped or trapezoidal.

[0066] In one embodiment of the present invention, a top conductive layer 503 may be formed on the top surface of the micro-LED array. In one embodiment of the present invention, the top conductive layer 503 may be shared by all micro-LEDs in the micro-LED array. In one embodiment of the present invention, the top conductive layer 503 is disposed above the micro-LED array, and contacts and covers the top of each light-emitting mesa 501, and is in electrical contact with the second type epitaxial layer 513 of the light-emitting mesa 501, so as to connect the second type epitaxial layer 513 of each semiconductor light-emitting mesa 501 in series, which is a transparent conductive layer.

[0067] In one embodiment of the present invention, the micro-LED array further includes a passivation isolation layer 504. The passivation isolation layer 504 covers the surface and side of the light-emitting mesa 501, but exposes at least part of the surface of the second type epitaxial layer 513, and the top conductive layer 503 is arranged on the surface of the passivation isolation layer 504. In one embodiment of the present invention, the passivation isolation layer 504 can be formed by CVD deposition of SiO2 or ALD deposition of Al2O3 film to effectively reduce the chip leakage rate. In some embodiments of the present invention, the passivation isolation layer 504 only covers the side of the light-emitting mesa 501, but does not cover the top surface of the light-emitting mesa 501, and the highest point of the passivation isolation layer 504 is flush with the top surface of the light-emitting mesa 501. In these embodiments, the continuous top conductive layer 503 covering the top of the light-emitting mesa 501 is in a horizontal or substantially horizontal plane. In some embodiments of the present invention, the passivation isolation layer 504 not only covers the side surfaces of the light-emitting mesa 501, but also covers the top edge portion of the light-emitting mesa 501, so that a bulge exists at the top edge of the light-emitting mesa 501, so that the continuous top conductive layer 503 covering it also forms a bulge at the top edge of the light-emitting mesa 501.

[0068] As mentioned above, there are partitions between the pixels formed by each light-emitting mesa, and a second electrode 505 is provided at the partition, and the second electrode 505 is provided on the surface of the top conductive layer 503. In one embodiment of the present invention, the second electrode 505 is a ring-shaped reflective electrode, which is provided around the light-emitting mesa 501, and is formed by magnetron sputtering or evaporation, and its material, for example, can be Al or Al alloy metal as a side wall reflective mirror, and the electrode stack metal can be Ni, Al, Ti, Ni, Pt, Au and other metal materials. In one embodiment of the present invention, each second electrode is connected to each other. In some embodiments of the present invention, a deep groove is provided at the partition between two adjacent light-emitting mesas, and the deep groove runs through the micro-light-emitting diode array, and the second electrode 505 is provided at the deep groove. In some embodiments of the present invention, a deep groove is not provided at the partition between two adjacent light-emitting mesas, but a passivation isolation layer and a top conductive layer are directly formed, so that the surface of the top conductive layer between two adjacent light-emitting mesas is a horizontal or substantially horizontal plane, and the second electrode is formed here, and its morphological interface is a trapezoid or approximates a trapezoid, which can be either a regular trapezoid or an inverted trapezoid, and the surface of the second electrode is not higher than the highest point of the continuous top conductive layer.

[0069] In one embodiment of the present invention, the micro-LED array is bonded to the driving backplane 502 through the metal bonding layer 508, and is electrically connected to the IC copper pillar on the driving backplane 502. In one embodiment of the present invention, the IC copper pillar includes a first IC copper pillar 521 and a second IC copper pillar 522, wherein the first IC copper pillar 521 is electrically connected to the first epitaxial layer 511 of the semiconductor light-emitting module in a one-to-one correspondence. The second IC copper pillar 522 is electrically connected to the first electrode 506. In one embodiment of the present invention, the polarity of the first electrode 506 is opposite to that of the second electrode 505. In one embodiment of the present invention, each semiconductor light-emitting module has a common first electrode. The first electrode 506 may be, for example, a P electrode or an anode electrode, and the second electrode 505 is an electrode with a polarity opposite to that of the first electrode 506, such as an N electrode or a cathode electrode. In one embodiment of the present invention, the first and second electrodes and their connecting parts may be made of materials such as graphene, ITO, aluminum-doped zinc oxide (AZO) or fluorine-doped tin oxide (FTO) or any combination of the above materials. In yet another embodiment of the present invention, the first and second electrodes and their connecting members may be made of non-transparent or transparent conductive materials, such as indium tin oxide (ITO).

[0070] As shown in the figure, in one embodiment of the present invention, the light-emitting area further includes a microlens array. The microlens array is arranged above the micro-LED array, wherein at least one microlens 507 is arranged on the surface of the conductive layer on the top of the micro-LED, and the horizontal profile of the microlens is greater than the maximum horizontal profile of the micro-LED. The microlens is mainly used to converge and / or collimate the optical fiber, for example, by adjusting the thickness, curvature and other parameters of the microlens so that the focus of the microlens is located in the light-emitting table of the micro-LED.

[0071] As shown in the figure, in one embodiment of the present invention, the microlenses of the microlens array correspond to the light-emitting mesas one by one. In some embodiments of the present invention, there is a gap between adjacent microlenses and their bottoms are connected to each other. The bottom of the gap may be lower than the top of the light-emitting mesas of the micro-light-emitting diode, or lower than the bottom of the light-emitting layer of the light-emitting mesas, or located above the second electrode 505, or located between the two peaks of the second electrode. In some other embodiments of the present invention, adjacent microlenses are completely connected, but there is a gap in the connecting portion, and the bottom of the connecting portion may be lower than the top of the light-emitting mesas of the micro-light-emitting diode, or lower than the bottom of the light-emitting layer of the light-emitting mesas, or located above the second electrode, or located between the two peaks of the second electrode. In addition, in one embodiment of the present invention, there is an air gap inside the microlens.

[0072] In one embodiment of the present invention, the microlens can be formed by multiple depositions. In the process of forming the microlens, a SiO2 film layer needs to be deposited first, and then ion etching is performed. The microlens is formed on the surface of the passivation isolation layer at the position corresponding to each light-emitting mesa.

[0073] like Figure 4 As shown, the non-luminous region 403 surrounds the luminous region 402, and the non-luminous region 403 includes a metal layer 431 and a shielding layer 432 stacked sequentially from bottom to top. In some embodiments of the present invention, the non-luminous region 403 further includes an encapsulation layer 433.

[0074] The metal layer 431 is formed on the surface of the driving backplane 401 and is located at the periphery of the micro LED array. At least a portion of the metal layer 431 is electrically connected to the micro LED array.

[0075] In one embodiment of the present invention, Figure 3 As shown, from the direction of the micro-LED array to the edge of the chip, the metal layer 431 includes a continuous metal area 4311 and a plurality of metal pads 4312 in sequence, wherein the continuous metal area 4311 is connected to the micro-LED array, and the plurality of metal pads 4312 form a one-dimensional or two-dimensional array in each direction of the periphery of the continuous metal area 4311. In one embodiment of the present invention, the metal pads 4312 can be used for wire bonding. In one embodiment of the present invention, Figure 3 As shown, the light emitting area, specifically, the micro-LED array is eccentrically arranged relative to the continuous metal area 4311. In one embodiment of the present invention, the continuous metal area 4311 has a first area 4313 and a second area 4314 arranged opposite to each other, wherein the width of the first area 4313 is smaller than the width of the second area 4314. As shown in the figure, in one embodiment of the present invention, the second area 4314 has a marking area 4315, wherein the metal pad 4312 is at least located outside the second area 4314.

[0076] The shielding layer 432 is formed on or above the surface of the metal layer 431, and covers at least a portion of the surface of the metal layer 431. In one embodiment of the present invention, the shielding layer 432 is located on or above the surface of the continuous metal region 4311. Specifically, the shielding layer 432 is formed on or above the surface of the first region 4313 of the metal layer 431 and on or above a portion of the second region 4314. In one embodiment of the present invention, the shielding layer 432 is also located on or above a portion of the plurality of metal pads 4312. Specifically, the shielding layer 432 exposes a plurality of metal pads 4312 near the edge of the chip, or the shielding layer 432 is located on or above the surface of the entire metal pad 4312.

[0077] In some embodiments of the present invention, the shielding layer 432 also covers part of the light emitting area, for example, covers the surface or the top of the edge of the micro LED array, thereby shielding part of the micro LEDs at the edge of the micro LED array. Figure 4 In the embodiment shown, the outer edge of the shielding layer 432 is flush with the outer edge of the metal layer 431, and the inner edge of the shielding layer 432 is located above the micro-LED array, for example, between the outermost first and second circles of micro-LEDs in the micro-LED array, that is, the shielding layer 432 completely covers the surface of the metal layer 431, and also covers part of the micro-LEDs at the edge of the micro-LED array. In some other embodiments of the present invention, the shielding layer 432 may not cover the light-emitting area, that is, the inner edge of the shielding layer 432 does not exceed the inner edge of the non-light-emitting area, such as Fig.9A , 9C At the same time, the outer edge of the shielding layer 432 may not exceed the outer edge of the metal layer 431, that is, the shielding layer 432 does not completely cover the metal layer 431. Fig. 9B , 9D shown.

[0078] In one embodiment of the present invention, the shielding layer 432 is formed by the following steps:

[0079] Forming a light absorbing material layer on the surface of the metal layer 431 by at least one coating and exposure and development process, specifically, for example, forming a light absorbing material film on the metal layer 431 and the light emitting area; and

[0080] The light-absorbing material film is exposed and developed based on the mask, and the light-absorbing material film formed on the light-emitting area is removed to form a shielding layer 432 .

[0081] In one embodiment of the present invention, the light absorbing material film at the edge of the light emitting area may also be retained. In some embodiments of the present invention, during the formation of the shielding layer, the thickness of the light absorbing layer may be increased by multiple coatings and exposure and development. For example, when the thickness of the deposited light absorbing material film is about 8000 angstroms, the light absorbing material film is exposed and developed to remove the light absorbing material film formed on the light emitting area; the aforementioned coating and exposure and development steps are repeated until the thickness of the light absorbing layer 432 is about 24000 angstroms.

[0082] In one embodiment of the present invention, the material of the light absorbing material film may be photoresist, gray resist, inorganic anti-reflective material (such as ZnO—SiO 2 ) or black inorganic material (such as carbon nanotubes, etc.).

[0083] In one embodiment of the present invention, at least a portion of the surface of the shielding layer 432 has a first rough structure 4321 , and the first rough structure 4321 is nanoparticles, and the average diameter of the nanoparticles is no more than 1 micrometer.

[0084] In one embodiment of the present invention, the reflectivity of the surface of the shielding layer 432 is not higher than 0.5%, so that the shielding layer 432 can shield and absorb light.

[0085] In one embodiment of the present invention, the shielding layer may not be provided. Fig.9E shown.

[0086] like Figure 6 , 7 As shown, in one embodiment of the present invention, a micro display chip is based on the micro light-emitting diode display chip as described above, and the non-luminous area of ​​the call number further includes an encapsulation layer 433. The encapsulation layer 433 is formed on the uncovered surface of the shielding layer 432 and / or the metal layer 431, and at least covers part of the surface of the shielding layer 432. The surface of the encapsulation layer 433 includes a plurality of rough structures 434. Figure 6 and 9A As shown, in one embodiment of the present invention, the outer edge of the encapsulation layer 433 is flush with the outer edge of the shielding layer 432, and the inner edge of the encapsulation layer 433 does not exceed the inner edge of the shielding layer, that is, part of the surface of the shielding layer 432 close to the light-emitting area is not covered. In some other embodiments of the present invention, the encapsulation layer 433 can completely cover the shielding layer 432, such as Fig. 9C When the shielding layer 432 does not completely cover the metal layer 431, the encapsulation layer 433 may be formed on the uncovered surface of the shielding layer 432 and the metal layer 431, wherein the outer edge of the encapsulation layer 433 is flush with the outer edge of the metal layer 431, as shown in FIG. Fig. 9BThe encapsulation layer 433 can also be directly formed on the uncovered surface of the metal layer 431, wherein the outer edge of the encapsulation layer 433 is flush with the outer edge of the metal layer 431, and at the same time, the encapsulation layer 433 has the same height as the shielding layer 432, as shown in FIG. Fig.9D It should be noted that the “inner side” refers to the side close to the light-emitting area, and the “outer side” refers to the side away from the light-emitting area.

[0087] In one embodiment of the present invention, the encapsulation layer 433 is formed by injection molding, so it needs to be demolded, and demolding marks may be formed during demolding, causing damage. In order to optimize this damage, in an embodiment of the present invention, the surface of the encapsulation layer 433 and the exposed shielding layer 432 is etched and roughened. In one embodiment of the present invention, the material of the encapsulation layer 433 is a solid plastic, and its basic component may be, for example, epoxy resin. The reflectivity of the encapsulation layer 433 is about 3% to 4%.

[0088] like Figure 6 As shown, in one embodiment of the present invention, the surface of the encapsulation layer 433 includes a plurality of rough structures 434. The plurality of rough structures 434 are nanoparticles, and their average diameter is not greater than 1 micron, so that a dense and rough nanostructure can be formed, so that the surface of the encapsulation layer 433 and the exposed shielding layer 432 is matte to reduce the reflectivity of the surface. In one embodiment of the present invention, the reflectivity of the molded layer after roughening can be reduced to 0.5% and below, thereby effectively reducing the optical machine reflected light. In one embodiment of the present invention, the maximum height and / or lateral size of the rough structure is in the range of 1 to 100 nanometers. In some embodiments of the present invention, the roughened portion is a conical structure; wherein the bottom width of the roughened portion is 50 to 200 nanometers, and the height of the roughened portion is 50 to 300 nanometers.

[0089] In one embodiment of the present invention, the rough structure is formed by surface roughening treatment. Specifically, it is formed by bombarding the surface of the encapsulation layer 433 and the exposed shielding layer 432 using plasma treatment equipment such as ICP / RIE / Plasma. In one embodiment of the present invention, during the bombardment process, the gas used may be O2, Ar or a mixed gas. In an embodiment of the present invention, the bombardment time is not limited and the power is not limited. The morphologies of the several rough structures formed by the roughening treatment using this process are different, that is, some of the rough structures are of irregular sizes, which can effectively enhance the effect of diffuse reflection, further reduce the re-reflection of full-band light, and improve the display quality of the picture.

[0090] In one embodiment of the present invention, before forming the encapsulation layer 433, the shielding layer 432 may be subjected to a surface roughening treatment to form a plurality of second rough structures 4321 on the surface of the shielding layer 432. The second rough structure may be formed, for example, by an ion etching process. After forming the encapsulation layer 433, the surface roughening treatment is performed again to form a first rough structure 434 on the surface of the encapsulation layer 433. The rough structure on the surface of the exposed shielding layer 432 may be understood as a superposition of the first rough structure and the second rough structure, and thus the overall morphology may be different from the rough structure on the surface of the encapsulation layer 433.

[0091] In another embodiment of the present invention, the shielding layer 432 is not subjected to surface roughening treatment before forming the encapsulation layer 433 . Instead, after forming the encapsulation layer 433 , the surfaces of the encapsulation layer 433 and the exposed shielding layer 432 are simultaneously subjected to surface roughening treatment.

[0092] Based on the micro display chip as described above, the present invention also provides a display panel, which includes the micro display chip as described above, a connecting wire and a connector. The connecting wire includes a first connecting end and a second connecting end opposite to each other, the first connecting end of the connecting wire is electrically connected to the micro display chip, the second connecting end of the connecting wire is electrically connected to the connector, and the connector is connected to a matching device in the outside world.

[0093] Fig.10 A schematic diagram showing the process of manufacturing the micro display chip as described above is shown. Figures 11A to 11D A schematic diagram showing the structure of each step. As shown in the figure, a method for manufacturing a micro display chip includes:

[0094] First, in step 1001, a metal layer is formed. A metal layer is formed on a driving backplane;

[0095] Next, in step 1002, if Fig.11AAs shown, a light-emitting area is formed. A micro-light-emitting diode array and a micro-lens array are formed on the driving backplane, and the micro-light-emitting diode array is electrically connected to the metal layer to form a light-emitting area of ​​the micro-display chip. Specifically, first, a second type of epitaxial layer, an electron blocking layer, a multi-layer quantum well and a first type of epitaxial layer are sequentially deposited on the substrate, and then the substrate is thinned to form a semiconductor light-emitting module. At the same time, an adhesion layer, a reflective layer, a blocking layer and a bonding metal can also be sequentially deposited on the surface of the first type of epitaxial layer. Then, the semiconductor light-emitting module is bonded to the driving backplane through the bonding metal, so that the IC copper column on the driving backplane is electrically interconnected with the semiconductor light-emitting module. In one embodiment of the present invention, after the chip is bonded, the substrate can also be ground and thinned to be removed, or the substrate can be removed by laser stripping to further thin the buffer layer structure, so as to facilitate the subsequent PN step structure. In an embodiment of the present invention, the bonding process can, for example, adopt a hot pressing bonding process, a eutectic bonding process, etc. Then, step etching is performed, and the semiconductor light-emitting module is ion-etched to form a positive trapezoidal structure pixel by adjusting the photolithography morphology. In one embodiment of the present invention, the horizontal angle of the positive trapezoidal structure pixel can be, for example, 65° to 85°. Then, a passivation isolation layer is formed on the side wall and surface of each pixel. In one embodiment of the present invention, the passivation isolation layer is formed by CVD deposition of SiO2 film layer and / or ALD deposition of Al2O3 film layer to reduce the chip leakage rate. After the deposition is completed, photolithography is performed above the pixel to open a hole to expose at least a part of the surface of the second type semiconductor layer. A top conductive layer is further formed on the surface of the passivation isolation layer to realize the shared series connection of the second type epitaxial layer of each pixel. An annular reflective electrode is formed at the partition of each pixel. In one embodiment of the present invention, the annular reflective electrode is realized by magnetron sputtering or evaporation process. In one embodiment of the present invention, the second electrode uses Al or Al alloy metal as the side wall reflective mirror, and the electrode stack metal uses Ni, Al, Ti, Pt, Au and other metal materials. In one embodiment of the present invention, before forming the passivation isolation layer, deep groove etching can be performed at the partition of each pixel point, for example, by using photolithography and IBE inert gas physical etching process, and the second electrode is subsequently formed at the deep groove. Subsequently, a first electrode is formed on the driving backplane, and the first electrode is connected to the IC copper column to play a protective pad height role and facilitate subsequent wiring. Finally, SiO2 is deposited, and the photolithography morphology is adjusted to form a microlens.In one embodiment of the present invention, a SiO2 film layer, i.e., a first transmission layer, is deposited by PECVD, and the thickness of the film layer is about 2.5 to 3.5 um. Subsequently, the photolithography array morphology corresponding to the pixel position is completed by adjusting the microlens photolithography morphology, such as the glue thickness, exposure energy, and hardening temperature, and the microlens passivation protection layer SiO2 material is ion-etched to form a hemispherical SiO2 microlens with a lens-like morphology, which can improve the light extraction efficiency to a certain extent. At this point, the initial structure of the micro-LED chip is formed. Since the step coverage of the SiO2 deposited by PECVD is not good, microcracks are easily formed at the deep grooves of the pixel points, causing the quantum well light source to form diffuse reflection here, reducing the light extraction efficiency of the microlens. In addition, due to the photolithography size of the microlens and ion etching, the overall microlens curvature radius, the height of the lower spacer, the ball height, and the lens ball width are all small, and the optimal conditions of the lens are not achieved. Therefore, in some embodiments of the present invention, secondary deposition can also be performed to increase the microlens curvature radius, the height of the lower spacer, the ball height, and the lens ball width. In one embodiment of the present invention, the thickness of the secondary SiO2 deposition needs to be determined according to the thickness of the SiO2 deposited by the previous microlens and the microlens etching morphology. In one embodiment of the present invention, the thickness of the secondary deposition is preferably 0.2 to 1um, and the deposition operation can be single or multiple times. In one embodiment of the present invention, the secondary deposition of SiO2 uses a mixed gas of SiH4 and N2O, and the ratio of SiH4 to N2O is 1:5. At the same time, the gas flow rate is controlled at a low level so that the deposition rate is much lower than the previous microlens deposition. The secondary deposition uses a high vacuum environment process condition and a large flow of inert gas N2 to further improve the step coverage effect of the secondary deposition SiO2, which is not easy to produce defects, and can even repair the micro defects of the previous microlens deposition, so as to obtain a better brightness improvement effect, thereby forming a luminous area;.

[0096] Next, in step 1003, if Fig. 11B As shown, a shielding layer is formed. A shielding layer is formed on the surface of the metal layer. The shielding layer may cover part of the light-emitting area and completely or partially cover the metal layer. In one embodiment of the present invention, at least one coating and exposure and development process is used to form a light-absorbing material layer on the metal layer, and then the light-absorbing material film is exposed and developed based on a mask to remove the light-absorbing material film formed on the light-emitting area;

[0097] Next, in step 1004, if Fig. 11C As shown, an encapsulation layer is formed. An encapsulation layer is formed on the surface of the shielding layer and / or the uncovered metal layer. The encapsulation layer may completely cover the shielding layer or expose part of the surface of the shielding layer, but the metal layer should be completely covered. In one embodiment of the present invention, the encapsulation layer is formed by injection molding; and

[0098] Finally, in step 1005, if Fig.11D As shown, a rough structure is formed. The surface of the encapsulation layer and the exposed shielding layer is etched and roughened. For example, a plasma treatment device, such as ICP / RIE / Plasma, is used to bombard the surface of the encapsulation layer and the exposed shielding layer. The gas used can be O2, Ar or a mixed gas. The bombardment time and power are unlimited, so that the surface of the encapsulation layer and the exposed shielding layer forms a dense and rough nanostructure, and the surface of the encapsulation layer and the exposed shielding layer is matte, thereby reducing the reflectivity of the surface of the encapsulation layer and the exposed shielding layer. The reflectivity can be reduced to 0.5%, reducing the optical machine reflected light. The demolding print formed by the encapsulation package body can be optimized simultaneously.

[0099] Fig.12 A schematic diagram showing a process flow of another method for manufacturing a micro display chip is shown. Figures 13A to 13E The schematic diagram of each step is shown in FIG. Fig.12 The manufacturing method of the embodiment shown in the figure is Fig.10 The embodiments shown are basically the same, except that, after forming the shielding layer in step 1203, step 1204 is performed first to form a second rough structure on the surface of the shielding layer by ion etching and other processes, and then steps 1205 and 1206 are performed to form an encapsulation layer, and the encapsulation layer and the exposed shielding layer surface are roughened.

[0100] Although various embodiments of the present invention are described above, it should be understood that they are presented as examples only and not as limitations. It is obvious to those skilled in the relevant art that various combinations, modifications and changes can be made thereto without departing from the spirit and scope of the present invention. Therefore, the breadth and scope of the present invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should only be defined according to the attached claims and their equivalents.

Claims

1. A micro display chip, characterized in that: include: Luminous area; as well as The non-luminescent region is arranged around the luminescent region, and the non-luminescent region comprises a packaging layer, wherein the surface of the packaging layer comprises a plurality of rough structures.

2. The micro display chip according to claim 1, characterized in that: The material of the packaging layer is solid plastic.

3. The micro display chip as claimed in claim 2, characterized in that: The reflectivity of the surface of the packaging layer having the rough structure is not greater than 0.5%.

4. The micro display chip according to claim 1, characterized in that: The rough structure is nanoparticles, and the average diameter of the nanoparticles is no more than 1 micron.

5. The micro display chip according to claim 1, characterized in that: The material of the encapsulation layer includes epoxy resin.

6. The micro display chip according to claim 1, characterized in that: A shielding layer is provided at the periphery of the light emitting area, and the encapsulation layer is located on the surface or above the shielding layer.

7. The micro display chip as claimed in claim 6, characterized in that: The side wall of the encapsulation layer close to the light emitting region does not exceed the side wall of the shielding layer close to the light emitting region, so that the surface of the shielding layer close to the light emitting region is exposed.

8. The micro display chip as claimed in claim 7, characterized in that: The exposed surface of the shielding layer close to the light emitting area has another rough structure.

9. The micro display chip as claimed in claim 8, characterized in that: The another rough structure is nanoparticles, and the average diameter of the nanoparticles is no greater than 1 micron.

10. The micro display chip according to claim 8, characterized in that: The shielding layer can shield and absorb light; the reflectivity of the surface of the shielding layer is not higher than 0.5%.

11. The micro display chip according to claim 6, characterized in that: The material of the shielding layer is one or more of the following: photoresist, gray glue, inorganic anti-reflection material or black inorganic material.

12. A display panel, characterized in that: The invention comprises the micro display chip as claimed in any one of claims 1 to 11.

13. The display panel according to claim 12, wherein: Also includes: A connecting wire, comprising a first connecting end and a second connecting end opposite to each other, wherein the first connecting end of the connecting wire is electrically connected to the micro display chip; as well as A connector, the second connection end of the connection line is electrically connected to the connector, and the connector is connected to a matching device in the outside world.

14. A method for manufacturing a micro display chip, characterized in that: Includes steps: forming a metal layer on the driver backplane; forming a micro light emitting diode array and a micro lens array on the surface of the metal layer to form a light emitting area of ​​a micro display chip, wherein the edge of the micro light emitting diode array does not exceed the edge of the metal layer; forming a shielding layer or an encapsulation layer on the surface of the metal layer not covered by the micro-LED array, wherein if an encapsulation layer is formed, the encapsulation layer completely covers the surface of the metal layer, and if a shielding layer is formed, the shielding layer at least covers a portion of the surface of the metal layer; as well as An encapsulation layer is formed on the surface of the shielding layer and / or the metal layer not covered by the shielding layer, wherein the surface of the encapsulation layer includes a plurality of rough structures.

15. The manufacturing method according to claim 14, characterized in that: Forming the shielding layer comprises the following steps: Forming a light absorbing material layer on the metal layer by at least one coating and exposure and development process; as well as The light absorbing material layer is exposed and developed based on a mask to remove the light absorbing material film formed on the light emitting area.

16. The manufacturing method according to claim 14, characterized in that: Forming the encapsulation layer comprises the steps of: forming a solidified material layer on the shielding layer; The surface of the solidified material layer is roughened so that the surface of the shielding layer has a plurality of rough structures.

17. The manufacturing method according to claim 16, characterized in that: The roughening process comprises: A plasma treatment device is used to bombard the surface of the solidified material layer so that the surface of the encapsulation layer has a plurality of first roughened portions.

18. The manufacturing method according to claim 17, characterized in that: The gases used during bombardment include one or more of O2 and Ar.

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