Display device and method of manufacturing same

Abstract

The invention discloses a display device and a method of manufacturing the same. The display device includes a first substrate, a first barrier insulating layer, a pad portion, a second substrate, a first connection line, a flexible film, and a contact portion. The first substrate includes an opening portion. The first barrier insulating layer is disposed on the first substrate and includes a first contact hole. The pad portion is disposed on the first barrier insulating layer and inserted into the first contact hole. The second substrate is disposed on the pad portion. The first connection line is disposed on the second substrate and connected to the pad portion. The flexible film is partially inserted into the opening portion of the first substrate and includes a lead electrode spaced apart from the pad portion in a plan view. The contact portion electrically connects the pad portion and the lead electrode to each other.

Description

Technical Field

[0001] The present disclosure relates to a display device and a method of manufacturing the display device. Background Art

[0002] With the development of the information society, the demand for display devices for displaying images has increased and diversified. For example, display devices have been applied to various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs. The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, or an organic light emitting display device. Among such flat panel display devices, a light emitting display device can display an image without a backlight unit that provides light to the display panel, because each of the pixels of the display panel includes a light emitting element that can emit light by itself. Summary of the invention

[0003] Aspects of the present disclosure may provide a display device capable of easily connecting a lead electrode and a pad portion to each other even when misalignment occurs in a process of aligning the lead electrode and the pad portion to each other, and a method of manufacturing the display device.

[0004] Aspects of the present disclosure may also provide a display device capable of reducing manufacturing time and manufacturing cost by minimizing the area of ​​a non-display region and simplifying a manufacturing process, and a method of manufacturing the display device.

[0005] However, the aspects of the present disclosure are not limited to those described herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below.

[0006] According to an embodiment, a display device includes: a first substrate including an opening portion; a first blocking insulating layer provided on the first substrate and including a first contact hole; a pad portion provided on the first blocking insulating layer and inserted into the first contact hole; a second substrate provided on the pad portion; a first connecting line provided on the second substrate and connected to the pad portion; a flexible film partially inserted into the opening portion of the first substrate and including a lead electrode spaced apart from the pad portion in a plan view; and a contact portion electrically connecting the pad portion and the lead electrode to each other.

[0007] The contact portion may cover a lower surface of the lead electrode and a lower surface of the pad portion.

[0008] The contact portion may cover a lower surface of the first blocking insulating layer disposed between the lead electrode and the pad portion.

[0009] The contact portion may correspond to a conductive line connecting a center of a portion of the lead electrode protruding from the flexible film and a center of a portion of the pad portion inserted into the first contact hole to each other.

[0010] The second substrate may include a second contact hole spaced apart from the first contact hole in a plan view, and the first connection line may be inserted into the second contact hole to be connected to the pad portion.

[0011] The second substrate may include a second contact hole overlapping the first contact hole, and the first connection line may be inserted into the second contact hole to be connected to the pad portion.

[0012] The display device may further include: a gate insulating layer disposed on the second substrate; a second connection line disposed on the gate insulating layer and connected to the first connection line; and an interlayer insulating layer disposed at a layer between the second connection line and the first connection line.

[0013] The display device may further include: a semiconductor region of a transistor, which is disposed on a second substrate; a gate electrode of the transistor, which is disposed on a gate insulating layer; and a connecting electrode, which is disposed on the interlayer insulating layer and is electrically connected to the transistor. The first connecting line may include the same material as the connecting electrode and may be formed by the same process as the connecting electrode. The second connecting line may include the same material as the gate electrode of the transistor and may be formed by the same process as the gate electrode.

[0014] According to an embodiment, a display device includes: a first substrate including an opening portion; a first blocking insulating layer disposed on the first substrate and including a plurality of first contact holes; a plurality of pad portions disposed on the first blocking insulating layer and respectively inserted into the plurality of first contact holes; a second substrate disposed on the plurality of pad portions; a plurality of first connecting lines disposed on the second substrate and respectively connected to the plurality of pad portions; a flexible film partially inserted into the opening portion of the first substrate and including a plurality of lead electrodes; a plurality of partition walls disposed on a lower surface of the first blocking insulating layer and between adjacent pad portions among the plurality of pad portions; and a contact portion connecting the pad portions and the lead electrodes to each other in a one-to-one manner between adjacent partition walls among the plurality of partition walls.

[0015] The lead electrode may be attached to a lower surface of the pad portion by an adhesive member, and the contact portion may cover a lower surface of the lead electrode and a lower surface of the pad portion.

[0016] The partition wall may include an organic film made of acrylic resin, epoxy resin, phenol resin, polyamide resin, or polyimide resin.

[0017] According to an embodiment, a method for manufacturing a display device includes: providing a first substrate; forming a first blocking insulating layer on the first substrate, the first blocking insulating layer including a first contact hole; forming a pad portion, the pad portion being disposed on the first blocking insulating layer and inserted into the first contact hole; forming a second substrate on the pad portion, the second substrate including a second contact hole; forming a first connecting line, the first connecting line being disposed on the second substrate and inserted into the second contact hole to be connected to the pad portion; forming an opening portion by etching a lower surface of the first substrate, the opening portion exposing a lower surface of the first blocking insulating layer and a lower surface of the pad portion; disposing a lead electrode of a flexible film on the lower surface of the first blocking insulating layer so as to be spaced apart from the pad portion in a plan view; and forming a contact portion, the contact portion electrically connecting the pad portion and the lead electrode to each other.

[0018] The forming of the contact portion may include coordinates of a center of a portion of the scan lead electrode protruding from the flexible film and coordinates of a center of the pad portion exposed by the opening portion.

[0019] The forming of the contact portion may further include printing and sintering a metal paste between a center of the lead electrode and a center of the pad portion.

[0020] The forming of the second substrate may include forming the second contact hole so as to be spaced apart from the first contact hole in a plan view.

[0021] The forming of the second substrate may include forming the second contact hole so as to overlap with the first contact hole.

[0022] According to an embodiment, a method for manufacturing a display device includes: providing a first substrate; forming a first blocking insulating layer on the first substrate, the first blocking insulating layer including a plurality of first contact holes; forming a plurality of pad portions, the plurality of pad portions being disposed on the first blocking insulating layer and being respectively inserted into the plurality of first contact holes; forming a second substrate on the plurality of pad portions, the second substrate including a plurality of second contact holes; forming a plurality of first connecting lines, the plurality of first connecting lines being disposed on the second substrate and being respectively inserted into the plurality of second contact holes to be respectively connected to the plurality of pad portions; forming an opening portion by etching a lower surface of the first substrate, the opening portion exposing a lower surface of the first blocking insulating layer and a lower surface of a plurality of pad portions; arranging a lead electrode of a flexible film on a lower surface of the pad portion; forming a plurality of partition walls, the plurality of partition walls being disposed on a lower surface of the first blocking insulating layer and between adjacent pad portions among the plurality of pad portions; and forming a contact portion connecting the pad portion and the lead electrode to each other in a one-to-one manner.

[0023] The forming of the plurality of partition walls may include covering the pad portion and the lead electrode with an organic material.

[0024] The forming of the plurality of partition walls may further include exposing the lead electrode and the pad portion by etching away a portion of the organic material overlapping the lead electrode and a portion of the organic material overlapping the pad portion.

[0025] The forming of the contact portion may include applying a conductive ink between the partition walls and then sintering the conductive ink at a low temperature.

[0026] With the display device and the method for manufacturing the display device according to the embodiment, the contact portion can be formed as a conductive line that electrically connects the lead electrode and the pad portion that are spaced apart from each other, and therefore, even when misalignment occurs between the lead electrode and the pad portion, the lead electrode and the pad portion can be easily connected to each other. In addition, with the display device and the method for manufacturing the display device, the manufacturing time and manufacturing cost can be reduced by minimizing the area of ​​the non-display region and simplifying the manufacturing process.

[0027] The effects of the present disclosure are not limited to the aforementioned effects, and various other effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other aspects and features of the present disclosure will become more apparent by describing the embodiments of the present disclosure in detail with reference to the accompanying drawings, in which:

[0029] Figure 1 is a plan view illustrating a display device according to an embodiment;

[0030] Figure 2 is a cross-sectional view illustrating a display device according to an embodiment;

[0031] Figure 3 is along Figure 1 A cross-sectional view taken along line II';

[0032] Figure 4 is a bottom view illustrating a display device according to an embodiment;

[0033] Figure 5 is a plan view illustrating a portion of a non-display area of ​​a display device according to an embodiment;

[0034] Figure 6 is a cross-sectional view illustrating a portion of a display device according to an embodiment;

[0035] Figure 7 is a cross-sectional view illustrating a connection relationship between a pad portion and a lead electrode in a display device according to an embodiment;

[0036] Figure 8is a bottom view illustrating a connection relationship between a pad portion and a lead electrode in a display device according to an embodiment;

[0037] Fig. 9 , Fig.10 and Fig.11 is a bottom view illustrating a manufacturing process of a display device according to an embodiment;

[0038] Fig.12 is a cross-sectional view illustrating a portion of a display device according to another embodiment;

[0039] Fig.13 is a cross-sectional view illustrating a connection relationship between a pad portion and a lead electrode in a display device according to another embodiment;

[0040] Fig.14 is a bottom view illustrating a connection relationship between a pad portion and a lead electrode in a display device according to another embodiment;

[0041] Fig.15 , Fig.16 and Fig.17 is a bottom view illustrating a manufacturing process of a display device according to another embodiment;

[0042] Fig.18 is a cross-sectional view illustrating a portion of a display device according to another embodiment;

[0043] Fig.19 is a cross-sectional view illustrating a connection relationship between a pad portion and a lead electrode in a display device according to another embodiment;

[0044] Fig. 20 is a bottom view illustrating a connection relationship between a pad portion and a lead electrode in a display device according to another embodiment;

[0045] Fig.21 is a cross-sectional view illustrating a partition wall in a display device according to another embodiment; and

[0046] Fig. 22 , Fig.23 , Fig.24 and Fig.25 is a cross-sectional view illustrating a manufacturing process of a display device according to another embodiment. DETAILED DESCRIPTION

[0047] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of various embodiments of the present disclosure. As used herein, "embodiment" is a non-limiting example of a device or method using one or more disclosures disclosed herein. However, it is apparent that various embodiments may be put into practice without these specific details or with one or more equivalent arrangements. In other cases, structures and devices are shown in block diagram form to avoid unnecessarily obscuring various embodiments. Further, various embodiments may be different, but need not be exclusive, nor need to limit the present disclosure. For example, the specific shapes, configurations, and features of the embodiments may be used or implemented in other embodiments without departing from the present disclosure.

[0048] Unless otherwise indicated, the illustrated embodiments will be understood as providing features of varying details of some of the ways in which the present disclosure can be implemented in practice. Therefore, unless otherwise indicated, the features, components, modules, layers, films, panels, regions or aspects, etc. (hereinafter referred to as "elements" individually or collectively) of the various embodiments may be combined, separated, interchanged or rearranged in other ways without departing from the present disclosure.

[0049] The use of cross-hatching or shading in the drawings is generally provided to make the boundaries between adjacent elements clear. As such, unless otherwise indicated, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, scale, proportion, commonality between the illustrated elements, or any other characteristic, property, characteristic, etc. of an element.

[0050] Further, in the accompanying drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity or description. When the embodiments can be implemented differently, a specific process sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed substantially simultaneously, or in an order opposite to the described sequence. Also, the same reference numerals represent the same elements.

[0051] When an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it may be directly on, directly connected to, or directly coupled to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, no intervening elements or layers exist. For this purpose, the term "connected" may refer to a physical connection, an electrical connection, or a fluid connection with or without intervening elements.

[0052] Further, the X-axis direction, the Y-axis direction, and the Z-axis direction are not limited to the directions corresponding to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the X-axis direction, the Y-axis direction, and the Z-axis direction can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0053] For the purpose of this disclosure, "at least one of A, B, and C" and "at least one selected from the group consisting of A, B, and C" may be interpreted as only A, only B, only C, or any combination of two or more of A, B, and C (e.g., ABC, AB, BC, or AC, etc.). As used herein, the word "or" refers to a logical "or", so that the expression "A, B, or C" means "A and B and C", "A and B but not C", "A and C but not B", "B and C but not A", "A but not B and not C", "B but not A and not C", and "C but not A and not B", unless the context indicates otherwise.

[0054] Although the terms "first" and "second" etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, the first element discussed below may be referred to as the second element without departing from the teachings of the present disclosure.

[0055] For descriptive purposes, spatially relative terms such as "below," "below," "under," "down," "above," "on," "above," and "side" (e.g., as in "sidewall") may be used herein and thereby describe the relationship of one element to another element(s) as illustrated in the figures. In addition to the orientations depicted in the figures, spatially relative terms are intended to encompass different orientations of the device in use, operation, or manufacture. For example, if the device in the figure is flipped, an element described as being "below" or "below" other elements or features will then be oriented to be "above" the other elements or features. Thus, the term "below" can encompass both above and below orientations. In addition, the device can be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and as such, the spatially relative descriptors used herein should be interpreted accordingly.

[0056] The term used herein is for the purpose of describing a particular embodiment, and is not intended to be limiting. Unless the context clearly indicates otherwise, as used herein, the singular "one" and "the (described)" are intended to also include plural forms. In addition, when used in this specification, the terms "include" and "comprise" and their variants indicate the existence of stated features, integral bodies, steps, operations, elements, parts or their groups, but do not exclude the existence or addition of one or more other features, integral bodies, steps, operations, elements, parts or their groups. It should also be noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms and are not used as terms of degree, and so, are used to consider the inherent deviations in measured values, calculated values ​​or provided values ​​that will be recognized by those of ordinary skill in the art.

[0057] Various embodiments are described herein with reference to cross-sectional illustrations or exploded illustrations as schematic illustrations of embodiments or intermediate structures. As such, variations in the illustrated shapes, for example due to manufacturing techniques or tolerances, are expected. Therefore, the embodiments disclosed herein should not necessarily be interpreted as limited to the shapes of the specifically illustrated zones, but will include deviations in shape due to, for example, manufacturing. In this manner, the zones illustrated in the drawings may be schematic in nature, and the shapes of these zones may not reflect the actual shapes of the zones of the device, and as such, are not necessarily intended to be limiting.

[0058] As is customary in the art, some embodiments are described and illustrated in the accompanying drawings in accordance with functional blocks, units, parts or modules. It will be appreciated by those skilled in the art that these blocks, units, parts or modules are physically implemented by electronic (or optical) circuits (such as, logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements and wiring connections, etc.), which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where these blocks, units, parts or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and they can be optionally driven by firmware or software. It is also contemplated that each block, unit, part or module can be implemented by dedicated hardware, or as a combination of dedicated hardware that performs some functions and a processor that performs other functions (e.g., one or more programmed microprocessors and associated circuits). In addition, each block, unit, part or module of some embodiments can be physically separated into two or more interacting and discrete blocks, units, parts or modules without departing from the scope of this disclosure. Furthermore, the blocks, units, parts or modules of some embodiments may be physically combined into more complex blocks, units, parts or modules without departing from the scope of the present disclosure.

[0059] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present disclosure, and unless explicitly so defined herein, these terms should not be interpreted in an ideal or overly formal sense.

[0060] Hereinafter, detailed embodiments of the present disclosure are described with reference to the accompanying drawings.

[0061] Figure 1 is a plan view illustrating a display device according to an embodiment.

[0062] refer to Figure 1 , the display device 10 can be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). As another example, the display device 10 can be applied as a display unit of a television, a laptop computer, a monitor, a billboard, or an Internet of Things (IOT) device. As yet another example, the display device 10 can be applied to wearable devices such as smart watches, watch phones, glasses-type displays, and head-mounted displays (HMDs).

[0063] The display device 10 may have a shape similar to a rectangular shape in a plan view. For example, a corner of the display device 10 where the side in the X-axis direction intersects the side in the Y-axis direction may be rounded with a predetermined curvature or be a right angle. The Z-axis direction may be perpendicular to a plane defined by the X-axis direction and the Y-axis direction. The shape of the display device 10 in a plan view is not limited to a rectangular shape, and may be a shape similar to other polygonal shapes, a circular shape, or an elliptical shape.

[0064] The display device 10 may include a display area DA and a non-display area NDA. The display area DA may include a plurality of pixels to display an image. Each of the plurality of pixels may include an organic light emitting diode (LED) including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, or a micro LED. Hereinafter, it will be mainly described that each of the plurality of pixels includes an organic light emitting diode, but the present disclosure is not limited thereto.

[0065] A plurality of pixels may be arranged along a plurality of rows and a plurality of columns in the display area DA. Each of the plurality of pixels may include an emission area EA defined by a pixel defining film or a bank, and may emit light having a predetermined peak wavelength through the emission area EA. The emission area EA may be an area in which light generated by a light emitting element of the display device 10 is emitted to the outside of the display device 10.

[0066] The display area DA of the display device 10 may include a light-blocking area BA surrounding the plurality of emission areas EA. The light-blocking area BA may prevent color mixing of light emitted from the emission areas EA.

[0067] The non-display area NDA may be arranged around the display area DA to surround the display area DA, and may not display an image. The non-display area NDA may include a scan driver SIC that supplies a scan signal to the display area DA. The scan driver SIC may be arranged on the left and right sides of the non-display area NDA. The scan driver SIC may generate a scan signal based on a scan control signal. The scan control signal may include a start signal, a clock signal, and a source voltage, but is not limited thereto. The scan driver SIC may supply a scan signal to a scan line of the display area DA according to a set order.

[0068] Figure 2 is a cross-sectional view illustrating a display device according to an embodiment.

[0069] refer to Figure 2 The display panel 100 may include a display unit DU, a touch sensing unit TSU, and an optical member POL. The display unit DU may include a first substrate SUB1, a blocking insulating layer BIL, a second substrate SUB2, a transistor layer TRL, a light emitting element layer EML, and an encapsulation layer TFEL.

[0070] The first substrate SUB1 may support the display device 10. The first substrate SUB1 may be a base substrate or a base member. The first substrate SUB1 may be a flexible substrate that may be bent, folded, or rolled. As an example, the first substrate SUB1 may include an insulating material such as a polymer resin (e.g., polyimide (PI)), but is not limited thereto. As another example, the first substrate SUB1 may be a rigid substrate including a glass material.

[0071] The blocking insulating layer BIL may be disposed on the first substrate SUB1. The blocking insulating layer BIL may include an inorganic film capable of preventing air or moisture from penetrating. For example, the blocking insulating layer BIL may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but is not limited thereto.

[0072] The second substrate SUB2 may be disposed on the blocking insulating layer BIL. The second substrate SUB2 may be a base substrate or a base member. The second substrate SUB2 may be a flexible substrate that may be bent, folded, or curled. For example, the second substrate SUB2 may include an insulating material such as a polymer resin (e.g., polyimide (PI)), but is not limited thereto.

[0073] The transistor layer TRL may be disposed on the second substrate SUB2. The transistor layer TRL may include a plurality of transistors constituting a pixel circuit of a pixel. The transistor layer TRL may include a scan line, a data line, and a power line connected to the pixel. Each of the transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when the scan driver SIC is formed on one side of the non-display area NDA of the display panel 100, the scan driver SIC may include a transistor.

[0074] The transistor layer TRL may be disposed in the display area DA and the non-display area NDA. The scan lines, data lines, power lines of the transistor layer TRL and the transistors of each pixel may be disposed in the display area DA. The transistors of the scan driver SIC may be disposed in the non-display area NDA.

[0075] The light emitting element layer EML may be disposed on the transistor layer TRL. The light emitting element layer EML may include a plurality of light emitting elements in which pixel electrodes, light emitting layers, and common electrodes are sequentially stacked to emit light, and a pixel defining film defining pixels. The plurality of light emitting elements of the light emitting element layer EML may be disposed in the display area DA.

[0076] The light emitting layer may include a hole transport layer, an organic light emitting layer, and an electron transport layer. When the pixel electrode receives a predetermined voltage through the transistor of the transistor layer TRL and the common electrode receives a cathode voltage, holes and electrons may move to the organic light emitting layer through the hole transport layer and the electron transport layer, respectively, and may be recombined with each other in the organic light emitting layer to emit light. For example, the pixel electrode may be an anode electrode, and the common electrode may be a cathode electrode, but the present disclosure is not limited thereto.

[0077] As another example, the plurality of light emitting elements may include a quantum dot light emitting diode including a quantum dot light emitting layer, an inorganic light emitting diode including an inorganic semiconductor, or a micro light emitting diode.

[0078] The encapsulation layer TFEL may cover the upper surface and the side surface of the light emitting element layer EML and may protect the light emitting element layer EML. The encapsulation layer TFEL may include at least one inorganic film and at least one organic film for encapsulating the light emitting element layer EML.

[0079] The touch sensing unit TSU may be disposed on the encapsulation layer TFEL. The touch sensing unit TSU may include a plurality of touch electrodes for sensing the touch of a user in a capacitive manner and a touch line for supplying a touch drive signal to the plurality of touch electrodes. For example, the touch sensing unit TSU may sense the touch of a user in a mutual capacitance manner or a self-capacitance manner.

[0080] A plurality of touch electrodes of the touch sensing unit TSU may be disposed in a touch sensor area overlapping the display area DA. A touch line of the touch sensing unit TSU may be disposed in a touch peripheral area overlapping the non-display area NDA.

[0081] The optical member POL may be disposed on the touch sensing unit TSU. The optical member POL may be attached to the touch sensing unit TSU by an optically clear adhesive (OCA) film or an optically clear resin (OCR). For example, the optical member POL may include a linear polarizer and a phase delay film, and the phase delay film may be a λ / 4 plate (quarter wave plate). The phase delay film and the linear polarizer may be sequentially stacked on the touch sensing unit TSU. The optical member POL may prevent color distortion due to external light reflection by reducing reflected light caused by external light.

[0082] The first substrate SUB1 may include an opening portion SOP. The opening portion SOP of the first substrate SUB1 may be etched from the lower surface of the first substrate SUB1 to extend through the first substrate SUB1. For example, the width of the lower portion of the opening portion SOP may be greater than the width of the upper portion of the opening portion SOP. In the manufacturing process of the display device 10, the pad portion provided on the blocking insulating layer BIL may be exposed through the opening portion SOP of the first substrate SUB1. The pad portion may be electrically connected to the display driver DIC through the flexible film FPCB inserted into the opening portion SOP.

[0083] The flexible film FPCB may be disposed under the first substrate SUB1. A portion of the flexible film FPCB may be inserted into the opening portion SOP of the first substrate SUB1 to be electrically connected to the pad portion. The flexible film FPCB may support the display driver DIC. The flexible film FPCB may transmit signals and voltages of the display driver DIC to the transistor layer TRL. The flexible film FPCB may supply a scan control signal to the scan driver SIC.

[0084] The display driver DIC may be mounted on the flexible film FPCB. The display driver DIC may be an integrated circuit (IC). The display driver DIC may convert digital video data into an analog data voltage based on a data control signal received from a timing controller (not shown), and may supply the analog data voltage to a data line of the display area DA through the flexible film FPCB. The display driver DIC may supply a source voltage received from a power supply unit (not shown) to a power line of the display area DA through the flexible film FPCB. The display device 10 includes a flexible film FPCB electrically connected to a pad portion at an opening portion SOP of the first substrate SUB1, and therefore, the area of ​​the non-display area NDA may be minimized.

[0085] Figure 3 is along Figure 1 A cross-sectional view taken along line II'.

[0086] refer to Figure 3 , the display area DA of the display device 10 may include a plurality of emission areas EA. Each of the emission areas EA may be a region in which light generated by the light emitting element ED is emitted to the outside of the display device 10.

[0087] The display panel 100 may include a first substrate SUB1, a first blocking insulating layer BIL1, a second blocking insulating layer BIL2, a third blocking insulating layer BIL3, a second substrate SUB2, a transistor layer TRL, a light emitting element layer EML, an encapsulation layer TFEL, a touch sensing unit TSU, a planarization layer OC, and an optical member POL.

[0088] The first substrate SUB1 may support the display panel 100. The first substrate SUB1 may be a base substrate or a base member. The first substrate SUB1 may be a flexible substrate that may be bent, folded, or rolled. As an example, the first substrate SUB1 may include an insulating material such as a polymer resin (e.g., polyimide (PI)), but is not limited thereto. As another example, the first substrate SUB1 may be a rigid substrate including a glass material.

[0089] The first blocking insulating layer BIL1 may be disposed on the first substrate SUB1. The first blocking insulating layer BIL1 may include an inorganic film capable of preventing air or moisture from penetrating. For example, the first blocking insulating layer BIL1 may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but is not limited thereto.

[0090] The second blocking insulating layer BIL2 may be disposed on the first blocking insulating layer BIL1. The second blocking insulating layer BIL2 may include an inorganic film capable of preventing air or moisture from penetrating. For example, the second blocking insulating layer BIL2 may include at least one of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, but is not limited thereto.

[0091] The third blocking insulating layer BIL3 may be disposed on the second blocking insulating layer BIL2. The third blocking insulating layer BIL3 may include an inorganic film capable of preventing air or moisture from penetrating. The third blocking insulating layer BIL3 may improve peeling defects by increasing the adhesive strength between the upper layer and the lower layer. For example, the third blocking insulating layer BIL3 may include amorphous silicon (a-Si), but is not limited thereto.

[0092] The second substrate SUB2 may be disposed on the third blocking insulating layer BIL3. The second substrate SUB2 may be a base substrate or a base member. The second substrate SUB2 may be a flexible substrate that may be bent, folded, or rolled. For example, the second substrate SUB2 may include an insulating material such as a polymer resin (e.g., polyimide (PI)), but is not limited thereto.

[0093] The transistor layer TRL may be disposed on the second substrate SUB2 and may include an active layer ACTL, a gate insulating layer GI, a gate layer GTL, an interlayer insulating layer ILD, a first source metal layer SDL1, a first via layer VIA1, a second source metal layer SDL2, and a second via layer VIA2.

[0094] The active layer ACTL may be disposed on the second substrate SUB2. The active layer ACTL may include a semiconductor region ACT, a drain electrode DE, and a source electrode SE of the transistor TR. The semiconductor region ACT may overlap with the gate electrode GE and may be insulated from the gate electrode GE by the gate insulating layer GI. The drain electrode DE and the source electrode SE may be provided by making the material of the semiconductor region ACT a conductor. The transistor TR may constitute a pixel circuit of each of the plurality of pixels.

[0095] The gate insulating layer GI may be disposed on the active layer ACTL. The gate insulating layer GI may insulate the semiconductor region ACT and the gate electrode GE of the transistor TR from each other. The gate insulating layer GI may include a contact hole through which the connection electrode CNE passes.

[0096] The gate layer GTL may be disposed on the gate insulating layer GI. The gate layer GTL may include a gate electrode GE of the transistor TR. The gate electrode GE may overlap the semiconductor region ACT, wherein the gate insulating layer GI is interposed between the gate electrode GE and the semiconductor region ACT. The gate electrode GE may receive a scan signal from a scan line. For example, the gate layer GTL may be formed as a single layer or a multilayer including at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), palladium (Pd), indium (In), neodymium (Nd), and copper (Cu).

[0097] The interlayer insulating layer ILD may be disposed on the gate layer GTL. The interlayer insulating layer ILD may insulate the gate layer GTL and the first source metal layer SDL1 from each other. The interlayer insulating layer ILD may include a contact hole through which the connection electrode CNE passes.

[0098] The first source metal layer SDL1 may be disposed on the interlayer insulating layer ILD. The first source metal layer SDL1 may include a connection electrode CNE. The connection electrode CNE may be inserted into a contact hole penetrating the interlayer insulating layer ILD and the gate insulating layer GI to be connected to the source electrode SE of the transistor TR. The connection electrode CNE may electrically connect the transistor TR and the anode connection electrode ANE to each other. The connection electrode CNE may supply the driving current received from the pixel circuit to the light emitting element ED through the anode connection electrode ANE. For example, the first source metal layer SDL1 may be formed as a single layer or multiple layers including at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), palladium (Pd), indium (In), neodymium (Nd), and copper (Cu).

[0099] The first via layer VIA1 may be disposed on the first source metal layer SDL1. The first via layer VIA1 may planarize the upper end of the pixel circuit and protect the pixel circuit. The first via layer VIA1 may include an organic insulating material such as polyimide (PI). The first via layer VIA1 may include a contact hole through which the anode connection electrode ANE passes.

[0100] The second source metal layer SDL2 may be disposed on the first via layer VIA1. The second source metal layer SDL2 may include an anode connection electrode ANE, a data line DL, and a power line VL. The second source metal layer SDL2 may include the materials exemplified in the first source metal layer SDL1.

[0101] The anode connection electrode ANE may be inserted into a contact hole penetrating the first via layer VIA1 to be connected to the connection electrode CNE. The anode connection electrode ANE may electrically connect the connection electrode CNE and the pixel electrode AE ​​of the light emitting element ED to each other. The anode connection electrode ANE may supply a driving current received from the connection electrode CNE to the light emitting element ED.

[0102] The data line DL may extend in the Y-axis direction in the display area DA. The data line DL may be electrically connected to the transistor TR. The data line DL may supply a data voltage to the pixel circuit.

[0103] The power line VL may extend in the Y-axis direction in the display area DA. The power line VL may be electrically connected to the transistor TR or the light emitting element ED. For example, the power line VL may be a high potential line, a low potential line, an initialization voltage line, a reference voltage line, or a bias voltage line, but is not limited thereto.

[0104] The second via layer VIA2 may be disposed on the second source metal layer SDL2. The second via layer VIA2 may planarize the upper end of the transistor layer TRL. The second via layer VIA2 may include an organic insulating material such as polyimide (PI). The second via layer VIA2 may include a contact hole through which the pixel electrode AE ​​passes.

[0105] The light emitting element layer EML may be disposed on the transistor layer TRL. The light emitting element layer EML may include a light emitting element ED and a pixel defining layer PDL.

[0106] The light emitting element ED may be disposed in the emission area EA and on the second through hole layer VIA2. The light emitting element ED of each of the plurality of pixels may include a pixel electrode AE, a light emitting layer EL, and a common electrode CE. The pixel electrode AE ​​may be disposed on the second through hole layer VIA2. The pixel electrode AE ​​may overlap one of the plurality of emission areas EA defined by the pixel defining film PDL. For example, the pixel electrode AE ​​may receive a driving current from the pixel circuit through the anode connection electrode ANE and the connection electrode CNE.

[0107] The light emitting layer EL may be disposed on the pixel electrode AE. For example, the light emitting layer EL may be an organic light emitting layer made of an organic material, but is not limited thereto. In the case where the light emitting layer EL is an organic light emitting layer, when a pixel circuit of a pixel applies a predetermined voltage to the pixel electrode AE ​​and the common electrode CE receives a common voltage or a cathode voltage, holes and electrons may move to the light emitting layer EL through a hole transport layer and an electron transport layer, respectively, and may be recombined with each other in the light emitting layer EL to emit light.

[0108] The common electrode CE may be disposed on the light emitting layer EL. For example, the common electrode CE is not divided for each of the plurality of pixels and may be implemented in the form of an electrode common to all pixels. The common electrode CE may be disposed on the light emitting layer EL in the plurality of emission regions EA and may be disposed on the pixel defining film PDL in a region other than the plurality of emission regions EA.

[0109] The pixel defining film PDL may be disposed in the light blocking area BA on the second via layer VIA2. The pixel defining film PDL may define a plurality of emission areas EA or a plurality of opening areas. The pixel defining film PDL may allow pixel electrodes AE of a plurality of pixels to be spaced apart and insulated from each other.

[0110] The encapsulation layer TFEL may be disposed on the common electrode CE to cover the plurality of light emitting elements ED. The encapsulation layer TFEL may include at least one inorganic film to prevent oxygen or moisture from penetrating into the plurality of light emitting elements ED. The encapsulation layer TFEL may include at least one organic film to protect the plurality of light emitting elements ED from foreign matter such as dust.

[0111] The touch sensing unit TSU may be disposed on the encapsulation layer TFEL. The touch sensing unit TSU may include a bridge electrode BRG, a first insulating layer IL1, a touch electrode TE, and a second insulating layer IL2.

[0112] The bridge electrode BRG may be disposed on the encapsulation layer TFEL. The bridge electrode BRG may be disposed at a different layer from the touch electrode TE, and may electrically connect adjacent touch electrodes TE to each other.

[0113] The first insulating layer IL1 may be disposed on the bridge electrode BRG. The first insulating layer IL1 may have an insulating function as well as an optical function. As an example, the first insulating layer IL1 may be an inorganic film including at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer. As another example, the first insulating layer IL1 may include an organic film.

[0114] The touch electrode TE may be disposed in the light blocking area BA on the first insulating layer IL1. The touch electrode TE may sense the user's touch in a capacitive manner. For example, the touch sensing unit TSU may sense the user's touch in a mutual capacitance manner in which capacitance is formed between a plurality of touch electrodes TE or in a self-capacitance manner in which capacitance is formed in each of a plurality of touch electrodes TE. The touch electrode TE may be formed as a single layer made of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or indium tin oxide (ITO), or may be formed as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a stacked structure of an APC alloy and ITO (ITO / APC / ITO). The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0115] The second insulating layer IL2 may be disposed on the touch electrode TE. The second insulating layer IL2 may have an insulating function and an optical function. The second insulating layer IL2 may be made of the material exemplified in the first insulating layer IL1.

[0116] The planarization layer OC may be disposed on the touch sensing unit TSU to planarize an upper end of the touch sensing unit TSU. For example, the planarization layer OC may include an organic insulating material.

[0117] The optical component POL may be disposed on the planarization layer OC. The optical component POL may be attached to the planarization layer OC by an optically clear adhesive (OCA) film or an optically clear resin (OCR). For example, the optical component POL may include a linear polarizer and a phase delay film, and the phase delay film may be a λ / 4 plate (quarter wave plate). The phase delay film and the linear polarizer may be sequentially stacked on the planarization layer OC. The optical component POL may prevent color distortion due to external light reflection by reducing reflected light caused by external light.

[0118] Figure 4 is a bottom view illustrating a display device according to an embodiment.

[0119] refer to Figure 4 , the flexible film FPCB may be disposed under the first substrate SUB1. The flexible film FPCB may be disposed at an edge of the lower surface of the display panel 100. The flexible film FPCB may be attached to the lower surface of the pad portion PAD by an adhesive member. The lead electrode of the flexible film FPCB may be electrically connected to the pad portion PAD through a contact portion. The pad portion PAD may be disposed in the non-display area NDA, but is not limited thereto.

[0120] The display driver DIC may be mounted on the flexible film FPCB. The display driver DIC may be an integrated circuit (IC). The display driver DIC may convert digital video data into an analog data voltage based on a data control signal received from a timing controller (not shown), and may supply the analog data voltage to the data line DL of the display area DA through the flexible film FPCB. The display driver DIC may supply a source voltage received from a power supply unit (not shown) to the power line VL of the display area DA through the flexible film FPCB. The display driver DIC may supply a scan control signal to the scan driver SIC through the flexible film FPCB. The display device 10 includes a pad portion PAD disposed on the first substrate SUB1, and a flexible film FPCB and a display driver DIC disposed under the first substrate SUB1, so that the area of ​​the non-display area NDA may be minimized.

[0121] Figure 5 is a plan view illustrating a portion of a non-display area of ​​a display device according to an embodiment.

[0122] refer to Figure 5 , the non-display area NDA may include a signal line SL, a high potential line VDL, a low potential line VSL, and a touch line TL. The signal line SL, the high potential line VDL, the low potential line VSL, and the touch line TL may extend from the pad area PDA to the display area DA. The signal line SL may be electrically connected to the data line DL to supply a data voltage, and may be electrically connected to the scan driver SIC to supply a scan control signal. The high potential line VDL may be electrically connected to the power line VL of the display area DA to supply a high potential voltage to the pixel circuit. The low potential line VSL may be electrically connected to the common electrode CE of the light emitting element ED to supply a low potential voltage. The touch line TL may be electrically connected to the touch electrode TE of the touch sensing unit TSU to supply a touch drive signal. The signal line SL, the high potential line VDL, the low potential line VSL, and the touch line TL may receive a signal or voltage from the flexible film FPCB disposed under the display panel 100 through the pad portion PAD.

[0123] The non-display area NDA may further include an antistatic circuit ESD. The antistatic circuit ESD may overlap the signal line SL and may be electrically connected to the signal line SL. Accordingly, the antistatic circuit ESD may prevent static electricity introduced from the outside from being introduced into the display area DA through the signal line SL.

[0124] Figure 5 A solid line 101 in illustrative figures indicates a boundary of the display panel 100 corresponding to any one corner of the display panel 100 . Figure 5 A solid line 102 in FIG. 1 is a virtual line indicating a boundary between the non-display area NDA and the display area DA of the display panel 100 . Figure 5The solid line 103 in FIG. 1 is a line indicating a boundary of the encapsulation layer TFEL of the display panel 100 set in any one corner of the display panel 100. The signal line SL, the high potential line VDL, and the low potential line VSL may extend to the pad portion PAD along the non-display area NDA inside the boundary where the encapsulation layer TFEL is set. The signal line SL, the high potential line VDL, and the low potential line VSL may not be set outside the boundary where the encapsulation layer TFEL is set.

[0125] Figure 6 is a cross-sectional view illustrating a portion of a display device according to an embodiment, Figure 7 is a cross-sectional view illustrating a connection relationship between a pad portion and a lead electrode in a display device according to an embodiment, and Figure 8 is a bottom view illustrating a connection relationship between a pad portion and a lead electrode in a display device according to an embodiment. Hereinafter, the same configuration as that described above will be briefly described, or a description thereof will be omitted.

[0126] refer to Figures 6 to 8 The display device 10 may include a first substrate SUB1, a first blocking insulating layer BIL1, a pad portion PAD, a second blocking insulating layer BIL2, a third blocking insulating layer BIL3, a second substrate SUB2, a transistor layer TRL ( Figure 3 )、Light Emitting Element Layer EML( Figure 3 ), an encapsulation layer TFEL, a dam DAM, an antistatic circuit ESD, a crack preventing portion CDM, a touch sensing unit TSU, a planarization layer OC, an optical member POL, a flexible film FPCB and a display driver DIC.

[0127] The pad portion PAD may be disposed on the first blocking insulating layer BIL1 and inserted into the first contact hole CNT1 provided in the first blocking insulating layer BIL1. In the manufacturing process of the display device 10, the lower surface of the pad portion PAD may be exposed through the opening portion SOP of the first substrate SUB1. The pad portion PAD may electrically connect the flexible film FPCB and the first connection line CWL1 to each other. The pad portion PAD may be spaced apart from the lead electrode LDE of the flexible film FPCB in a plan view. The pad portion PAD may be electrically connected to the lead electrode LDE of the flexible film FPCB through the contact portion CTP. The pad portion PAD may be formed as a single layer or a multilayer including at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), palladium (Pd), indium (In), neodymium (Nd), and copper (Cu).

[0128] The second blocking insulating layer BIL2 may be disposed on the pad portion PAD. The second blocking insulating layer BIL2 may include a second contact hole CNT2 into which the first connection wire CWL1 is inserted. In a manufacturing process of the display device 10, an upper surface of the pad portion PAD may be exposed through the second contact hole CNT2.

[0129] The third blocking insulating layer BIL3 may be disposed on the second blocking insulating layer BIL2. The third blocking insulating layer BIL3 may improve peeling defects by increasing the adhesive strength between the upper layer and the lower layer. For example, the third blocking insulating layer BIL3 may include amorphous silicon (a-Si), but is not limited thereto.

[0130] The second substrate SUB2 may be disposed on the third blocking insulating layer BIL3. The second substrate SUB2 may be a base substrate or a base member. The second substrate SUB2 may be a flexible substrate that may be bent, folded, or rolled. For example, the second substrate SUB2 may include an insulating material such as a polymer resin (e.g., polyimide (PI)), but is not limited thereto.

[0131] The gate insulating layer GI may be disposed on the second substrate SUB2, and the interlayer insulating layer ILD may be disposed on the gate insulating layer GI. The interlayer insulating layer ILD, the gate insulating layer GI, the second substrate SUB2, the third blocking insulating layer BIL3, and the second blocking insulating layer BIL2 may include a second contact hole CNT2. The second contact hole CNT2 may be etched from the upper surface of the interlayer insulating layer ILD to extend through the second blocking insulating layer BIL2. In the process of forming the second contact hole CNT2, the upper surface of the pad portion PAD may be exposed. The first contact hole CNT1 and the second contact hole CNT2 may be spaced apart from each other in a plan view.

[0132] The first connection line CWL1 may be disposed on the interlayer insulating layer ILD. The first connection line CWL1 may include the same material as the first source metal layer SDL1 of the display area DA, and may be formed in the same process as the first source metal layer SDL1. A portion of the first connection line CWL1 may be inserted into the second contact hole CNT2 to contact the upper surface of the pad portion PAD. Another portion of the first connection line CWL1 may penetrate the interlayer insulating layer ILD to contact the second connection line CWL2. The first connection line CWL1 may electrically connect the pad portion PAD and the second connection line CWL2 to each other. The first connection line CWL1 may supply a data voltage or a source voltage received from the pad portion PAD to the second connection line CWL2.

[0133] The second connection line CWL2 may be disposed on the gate insulating layer GI. The second connection line CWL2 may include the same material as the gate layer GTL of the display area DA and may be formed in the same process as the gate layer GTL. The second connection line CWL2 may supply the data voltage received from the first connection line CWL1 to the data line DL. The second connection line CWL2 may supply the source voltage received from the first connection line CWL1 to the power line VL. For example, the second connection line CWL2 may correspond to Figure 5 The signal line SL in the circuit may be electrically connected to the signal line SL.

[0134] The encapsulation layer TFEL may include first to third encapsulation layers TFE1 , TFE2 , and TFE3 .

[0135] The first encapsulation layer TFE1 may be disposed on the light emitting element layer EML. The first encapsulation layer TFE1 may include an inorganic material to prevent oxygen or moisture from penetrating into the light emitting element layer EML. The first encapsulation layer TFE1 may extend beyond the display area DA and the dam DAM to the crack prevention portion CDM. The first encapsulation layer TFE1 may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but is not limited thereto.

[0136] The second encapsulation layer TFE2 may be disposed on the first encapsulation layer TFE1. The second encapsulation layer TFE2 may include an organic material to protect the light emitting element layer EML from foreign matter such as dust. The second encapsulation layer TFE2 may extend beyond the display area DA to the dam DAM. The second encapsulation layer TFE2 may be filled and formed in an area surrounded by the dam DAM. The second encapsulation layer TFE2 may include an organic film made of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. The second encapsulation layer TFE2 may be formed by curing a monomer or applying a polymer.

[0137] The third encapsulation layer TFE3 may be disposed on the second encapsulation layer TFE2. The third encapsulation layer TFE3 may include an inorganic material to prevent oxygen or moisture from penetrating into the light emitting element layer EML. The third encapsulation layer TFE3 may extend beyond the display area DA and the dam DAM to the crack prevention portion CDM. The third encapsulation layer TFE3 may be disposed on the second encapsulation layer TFE2 inside the dam DAM, and may be disposed on the first encapsulation layer TFE1 from the dam DAM to the crack prevention portion CDM. The third encapsulation layer TFE3 may be made of the same material as the first encapsulation layer TFE1.

[0138] The dam DAM may surround the display area DA. The dam DAM may include the same material as the pixel defining film PDL and may be formed in the same process as the pixel defining film PDL. The dam DAM may have a predetermined height so that the second encapsulation layer TFE2 including an organic material does not exceed the dam DAM.

[0139] The antistatic circuit ESD may be disposed between the display area DA and the crack preventing portion CDM. The antistatic circuit ESD may include at least one transistor. The antistatic circuit ESD may be electrically connected to the second connection line CWL2. The antistatic circuit ESD may prevent static electricity introduced from the outside from being introduced into the display area DA through the second connection line CWL2.

[0140] The crack preventing portion CDM may surround the dam DAM. The crack preventing portion CDM may be disposed at the outermost portion of the display panel 100 and prevent cracking of the display panel 100. The first and third encapsulation layers TFE1 and TFE3 and the planarization layer OC may be formed in a region surrounded by the crack preventing portion CDM.

[0141] The crack preventing portion CDM may include first to third layers LAY1, LAY2, and LAY3. The first layer LAY1 of the crack preventing portion CDM may cover the upper surface of the first connection wire CWL1 inserted into the second contact hole CNT2. The first layer LAY1 may fill the hole formed by the first connection wire CWL1 in the second contact hole CNT2. The first layer LAY1 may include the same material as the first via layer VIA1 and may be formed in the same process as the first via layer VIA1.

[0142] The second layer LAY2 of the crack preventing portion CDM may be disposed on the first layer LAY1. The second layer LAY2 may include the same material as the second via layer VIA2, and may be formed in the same process as the second via layer VIA2.

[0143] The third layer LAY3 of the crack preventing portion CDM may be disposed on the second layer LAY2. The third layer LAY3 may include the same material as the pixel defining film PDL, and may be formed in the same process as the pixel defining film PDL.

[0144] The first substrate SUB1 may include an opening portion SOP. The opening portion SOP of the first substrate SUB1 may be etched from the lower surface of the first substrate SUB1 to extend through the first substrate SUB1. For example, the width of the lower portion of the opening portion SOP may be greater than the width of the upper portion of the opening portion SOP. In the manufacturing process of the display device 10, the lower surface of the first blocking insulating layer BIL1 and the lower surface of the pad portion PAD may be exposed through the opening portion SOP.

[0145] The flexible film FPCB may be disposed under the first substrate SUB1. A portion of the flexible film FPCB may be inserted into the opening portion SOP of the first substrate SUB1 to be electrically connected to the pad portion PAD. The flexible film FPCB may include a lead electrode LDE disposed on an upper surface of one side thereof and inserted into the opening portion SOP. The lead electrode LDE may protrude from one side of the flexible film FPCB, and the protruding portion of the lead electrode LDE may not overlap with the flexible film FPCB. The lead electrode LDE may be attached to the lower surface of the first blocking insulating layer BIL1 by an adhesive member ADM. The lead electrode LDE may be spaced apart from the pad portion PAD in a plan view. The lead electrode LDE may be electrically connected to the pad portion PAD by a contact portion CTP.

[0146] The flexible film FPCB may support a display driver DIC disposed on a lower surface of the flexible film FPCB. The lead electrode LDE may be electrically connected to the display driver DIC through a lead (not shown) provided on the flexible film FPCB. The other side of the flexible film FPCB may be connected to a source circuit board (not shown) under the first substrate SUB1. The flexible film FPCB may transmit signals and voltages of the display driver DIC to the display device 10. The flexible film FPCB may supply a scan control signal to the scan driver SIC.

[0147] The display driver DIC may be mounted on the flexible film FPCB. The display driver DIC may be an integrated circuit (IC). The display driver DIC may convert digital video data into an analog data voltage based on a data control signal received from a timing controller (not shown), and may supply the analog data voltage to the data line DL of the display area DA through the flexible film FPCB. The display driver DIC may supply a source voltage received from a power supply unit (not shown) to the power line VL of the display area DA through the flexible film FPCB. The display device 10 includes a pad portion PAD disposed on the first substrate SUB1, and a flexible film FPCB and a display driver DIC disposed under the first substrate SUB1, so that the area of ​​the non-display area NDA may be minimized.

[0148] exist Figure 8In the embodiment of the present invention, the contact portion CTP may electrically connect the lead electrode LDE and the pad portion PAD to each other. The contact portion CTP may correspond to a conductive line disposed between the lead electrode LDE and the pad portion PAD spaced apart from each other. The contact portion CTP may partially cover the lower surface of the lead electrode LDE protruding from the flexible film FPCB and the lower surface of the pad portion PAD exposed through the opening portion SOP. The contact portion CTP may partially cover the lower surface of the first blocking insulating layer BIL1 disposed between the lead electrode LDE and the pad portion PAD. The contact portion CTP may be a conductive line that connects the center CP1 of the portion of the lead electrode LDE protruding from the flexible film FPCB and the center CP2 of the portion of the pad portion PAD inserted into the first contact hole CNT1 to each other. The contact portion CTP may overlap with the first contact hole CNT1 and may not overlap with the second contact hole CNT2. Each of the plurality of contact portions CTP may connect one of the plurality of lead electrodes LDE and the pad portion PAD corresponding to the one lead electrode LDE to each other in a one-to-one manner. Even when misalignment occurs in the process of aligning the lead electrode LDE and the pad portion PAD with each other, the contact portion CTP can easily connect the lead electrode LDE and the pad portion PAD to each other by connecting the lead electrode LDE and the pad portion PAD to each other in a one-to-one manner. A plurality of contact portions CTP are formed separately without a separate laser patterning process, and therefore, damage to the display panel 100 due to laser patterning, a short-circuit defect, and an over-sintering risk of the contact portion CTP can be prevented.

[0149] As an example, the contact portion CTP may be formed by low temperature sintering of a conductive ink including nanoparticles and a polymer. The nanoparticles may include nano-scale metal particles such as silver (Ag), copper (Cu), aluminum (Al), or chromium (Cr), and the polymer may include an acrylic resin or an epoxy resin, but the present disclosure is not limited thereto. The conductive ink may include a polymer as a binder for bonding the metal particles to each other, and the nanoparticles may be closely contacted and aggregated with each other through a sintering process. The contact portion CTP may have conductivity by including the sintered nanoparticles.

[0150] As another example, the contact portion CTP may be formed by low temperature sintering of metal organic decomposition ink (MOD ink). The metal organic decomposition ink may include a liquid metal organic decomposition material smaller than nanoparticles, and the liquid metal organic decomposition material may be changed into a metal material by a sintering process. Accordingly, the contact portion CTP may have conductivity.

[0151] The contact portion CTP may be formed by printing conductive ink or metal paste on the opening portion SOP of the first substrate SUB1 using a silicon pad, and then sintering the conductive ink or metal paste using an intense pulsed light (IPL) or laser. The metal particles are in close contact with each other and aggregated due to the heat generated by the IPL or laser in the sintering process, so that the resistivity of the contact portion CTP may be reduced.

[0152] The display device 10 can reduce manufacturing time and manufacturing cost by electrically connecting the lead electrode LDE and the pad portion PAD to each other through the contact portion CTP using conductive ink or metal paste to simplify the manufacturing process without using ultrasonic bonding or thermocompression bonding.

[0153] Figures 9 to 11 is a bottom view illustrating a manufacturing process of the display device according to the embodiment.

[0154] exist Fig. 9 In the embodiment, the flexible film FPCB may be disposed under the first substrate SUB1. One side of the flexible film FPCB may be inserted into the opening portion SOP of the first substrate SUB1. The lead electrode LDE of the flexible film FPCB may be disposed to be spaced apart from the pad portion PAD in the Y-axis direction. The lead electrode LDE may protrude from one side of the flexible film FPCB, and the protruding portion of the lead electrode LDE may not overlap with the flexible film FPCB. The lead electrode LDE may be attached to the lower surface of the first blocking insulating layer BIL1 by an adhesive member ADM. For example, the lead electrode LDE and the pad portion PAD may be disposed on a virtual line extending in the Y-axis direction, but is not limited thereto.

[0155] exist Fig.10 , the camera CAM may scan the coordinates of the center CP1 of the portion of the lead electrode LDE protruding from the flexible film FPCB and the coordinates of the center CP2 of the pad portion PAD exposed by the opening portion SOP of the first substrate SUB1. The center CP1 of the lead electrode LDE and the center CP2 of the pad portion PAD corresponding to each other may be spaced apart from each other in the Y-axis direction.

[0156] exist Fig.11 In the embodiment, the contact portion CTP may be formed between the center CP1 of the lead electrode LDE and the center CP2 of the pad portion PAD. The contact portion CTP may be formed by printing a metal paste including metal particles, a monomer, and a solvent on the opening portion SOP of the first substrate SUB1 using a silicon pad, and then sintering the metal paste using a laser. Due to the heat generated by the laser in the sintering process, the metal particles are closely contacted and aggregated with each other, and the monomer is converted into a polymer, so that the resistivity of the contact portion CTP can be reduced.

[0157] The sintered metal paste may cover one lead electrode LDE among the plurality of lead electrodes LDE inserted into one opening portion SOP and a pad portion PAD corresponding to the one lead electrode LDE. The plurality of contact portions CTP may be spaced apart from each other, and one contact portion CTP may electrically connect one pad portion PAD and one lead electrode LDE to each other. The plurality of contact portions CTP are formed separately without a separate laser patterning process, and therefore, damage to the display panel 100, a short circuit defect, and an over-sintering risk of the contact portion CTP due to laser patterning may be prevented.

[0158] Accordingly, in the display device 10, by electrically connecting the lead electrode LDE and the pad portion PAD to each other via the contact portion CTP, the lead electrode LDE of the flexible film FPCB can be electrically connected to the pad portion PAD without using ultrasonic bonding or thermocompression bonding. By supplementing the alignment between the lead electrode LDE and the pad portion PAD, the contact portion CTP can easily connect the lead electrode LDE and the pad portion PAD to each other. In addition, the display device 10 can reduce manufacturing time and manufacturing cost by simplifying the manufacturing process.

[0159] Fig.12 is a cross-sectional view illustrating a portion of a display device according to another embodiment, Fig.13 is a cross-sectional view illustrating a connection relationship between a pad portion and a lead electrode in a display device according to another embodiment, and Fig.14 is a bottom view illustrating a connection relationship between a pad portion and a lead electrode in a display device according to another embodiment. Figure 12 to Figure 14 The display device has a different configuration in terms of the pad portion PAD. Figures 6 to 8 The display device is different, and the same configuration as that described above will be briefly described, or its description will be omitted.

[0160] refer to Figure 12 to Figure 14 , the pad portion PAD may be disposed on the first blocking insulating layer BIL1 and inserted into the first contact hole CNT1 provided in the first blocking insulating layer BIL1. In the manufacturing process of the display device 10, the lower surface of the pad portion PAD may be exposed through the opening portion SOP of the first substrate SUB1. The pad portion PAD may electrically connect the flexible film FPCB and the first connection line CWL1 to each other. The pad portion PAD may be spaced apart from the lead electrode LDE of the flexible film FPCB in a plan view. The pad portion PAD may be electrically connected to the lead electrode LDE of the flexible film FPCB through the contact portion CTP.

[0161] The interlayer insulating layer ILD, the gate insulating layer GI, the second substrate SUB2, the third blocking insulating layer BIL3 and the second blocking insulating layer BIL2 may include a second contact hole CNT2. The second contact hole CNT2 may be etched from the upper surface of the interlayer insulating layer ILD to extend through the second blocking insulating layer BIL2. In the process of forming the second contact hole CNT2, the upper surface of the pad portion PAD may be exposed. The second contact hole CNT2 may overlap with the first contact hole CNT1. Accordingly, a portion of the first connection wire CWL1 inserted into the second contact hole CNT2 and a portion of the lower surface of the pad portion PAD exposed through the opening portion SOP may overlap with each other.

[0162] The first connection line CWL1 may be disposed on the interlayer insulating layer ILD. The first connection line CWL1 may include the same material as the first source metal layer SDL1 of the display area DA, and may be formed in the same process as the first source metal layer SDL1. A portion of the first connection line CWL1 may be inserted into the second contact hole CNT2 to contact the upper surface of the pad portion PAD. Another portion of the first connection line CWL1 may penetrate the interlayer insulating layer ILD to contact the second connection line CWL2. The first connection line CWL1 may electrically connect the pad portion PAD and the second connection line CWL2 to each other. The first connection line CWL1 may supply a data voltage or a source voltage received from the pad portion PAD to the second connection line CWL2.

[0163] The second connection line CWL2 may be disposed on the gate insulating layer GI. The second connection line CWL2 may include the same material as the gate layer GTL of the display area DA and may be formed in the same process as the gate layer GTL. The second connection line CWL2 may supply the data voltage received from the first connection line CWL1 to the data line DL. The second connection line CWL2 may supply the source voltage received from the first connection line CWL1 to the power line VL. For example, the second connection line CWL2 may correspond to Figure 5 The signal line SL in the circuit may be electrically connected to the signal line SL.

[0164] exist Fig.14In the embodiment of the present invention, the contact portion CTP may electrically connect the lead electrode LDE and the pad portion PAD to each other. The contact portion CTP may correspond to a conductive line disposed between the lead electrode LDE and the pad portion PAD spaced apart from each other. The contact portion CTP may cover the lower surface of the lead electrode LDE protruding from the flexible film FPCB and the lower surface of the pad portion PAD exposed through the opening portion SOP. The contact portion CTP may cover the lower surface of the first blocking insulating layer BIL1 disposed between the lead electrode LDE and the pad portion PAD. The contact portion CTP may be a conductive line that connects the center CP1 of the portion of the lead electrode LDE protruding from the flexible film FPCB and the center CP2 of the portion of the pad portion PAD inserted into the first contact hole CNT1 to each other. A portion of the contact portion CTP may overlap with the first contact hole CNT1 and the second contact hole CNT2. Each of the plurality of contact portions CTP may connect one of the plurality of lead electrodes LDE and the pad portion PAD corresponding to the one lead electrode LDE to each other in a one-to-one manner. Even when misalignment occurs in the process of aligning the lead electrode LDE and the pad portion PAD with each other, the contact portion CTP can easily connect the lead electrode LDE and the pad portion PAD to each other by connecting the lead electrode LDE and the pad portion PAD to each other in a one-to-one manner. A plurality of contact portions CTP are formed separately without a separate laser patterning process, and therefore, damage to the display panel 100 due to laser patterning, a short-circuit defect, and an over-sintering risk of the contact portion CTP can be prevented.

[0165] The display device 10 may reduce manufacturing time and manufacturing cost by electrically connecting the lead electrode LDE and the pad portion PAD to each other through the contact portion CTP using a metal paste to simplify the manufacturing process without using ultrasonic bonding or thermocompression bonding.

[0166] Figures 15 to 17 is a bottom view illustrating a manufacturing process of a display device according to another embodiment.

[0167] exist Fig.15 In the embodiment, the pad portion PAD may be disposed on the first blocking insulating layer BIL1 and inserted into the first contact hole CNT1 provided in the first blocking insulating layer BIL1. The second contact hole CNT2 may overlap the first contact hole CNT1. Accordingly, a portion of the first connection wire CWL1 inserted into the second contact hole CNT2 and a portion of the lower surface of the pad portion PAD exposed through the opening portion SOP may overlap each other.

[0168] The flexible film FPCB may be disposed under the first substrate SUB1. One side of the flexible film FPCB may be inserted into the opening portion SOP of the first substrate SUB1. The lead electrode LDE of the flexible film FPCB may be disposed to be spaced apart from the pad portion PAD in the Y-axis direction. The lead electrode LDE may protrude from one side of the flexible film FPCB, and the protruding portion of the lead electrode LDE may not overlap with the flexible film FPCB. The lead electrode LDE may be attached to the lower surface of the first blocking insulating layer BIL1 by an adhesive member ADM. For example, the lead electrode LDE and the pad portion PAD may be disposed on a virtual line extending in the Y-axis direction, but is not limited thereto.

[0169] exist Fig.16 , the camera CAM may scan the coordinates of the center CP1 of the portion of the lead electrode LDE protruding from the flexible film FPCB and the coordinates of the center CP2 of the pad portion PAD exposed by the opening portion SOP of the first substrate SUB1. The center CP1 of the lead electrode LDE and the center CP2 of the pad portion PAD corresponding to each other may be spaced apart from each other in the Y-axis direction.

[0170] exist Fig.17 In the embodiment, the contact portion CTP may be formed between the center CP1 of the lead electrode LDE and the center CP2 of the pad portion PAD. The contact portion CTP may be formed by printing a metal paste including metal particles, a monomer, and a solvent on the opening portion SOP of the first substrate SUB1 using a silicon pad, and then sintering the metal paste using a laser. Due to the heat generated by the laser in the sintering process, the metal particles are closely contacted and aggregated with each other, and the monomer is converted into a polymer, so that the resistivity of the contact portion CTP can be reduced.

[0171] The sintered metal paste may cover one lead electrode LDE among the plurality of lead electrodes LDE inserted into one opening portion SOP and a pad portion PAD corresponding to the one lead electrode LDE. The plurality of contact portions CTP may be spaced apart from each other, and one contact portion CTP may electrically connect one pad portion PAD and one lead electrode LDE to each other. The plurality of contact portions CTP are formed separately without a separate laser patterning process, and therefore, damage to the display panel 100, a short circuit defect, and an over-sintering risk of the contact portion CTP due to laser patterning may be prevented.

[0172] Accordingly, in the display device 10, by electrically connecting the lead electrode LDE and the pad portion PAD to each other via the contact portion CTP, the lead electrode LDE of the flexible film FPCB can be electrically connected to the pad portion PAD without using ultrasonic bonding or thermocompression bonding. By supplementing the alignment between the lead electrode LDE and the pad portion PAD, the contact portion CTP can easily connect the lead electrode LDE and the pad portion PAD to each other. In addition, the display device 10 can reduce manufacturing time and manufacturing cost by simplifying the manufacturing process.

[0173] Fig.18 is a cross-sectional view illustrating a portion of a display device according to another embodiment, and Fig.19 is a cross-sectional view illustrating a connection relationship between a pad portion and a lead electrode in a display device according to another embodiment. Fig. 20 is a bottom view illustrating a connection relationship between a pad portion and a lead electrode in a display device according to another embodiment. Figures 18 to 20 The display device is similar to the one in the configuration of the lead electrode LDE and the contact portion CTP. Figures 6 to 8 The display device is different, and the same configuration as that described above will be briefly described, or its description will be omitted.

[0174] refer to Figures 18 to 20 , the pad portion PAD may be disposed on the first blocking insulating layer BIL1 and inserted into the first contact hole CNT1 provided in the first blocking insulating layer BIL1. In the manufacturing process of the display device 10, the lower surface of the pad portion PAD may be exposed through the opening portion SOP of the first substrate SUB1. The pad portion PAD may electrically connect the flexible film FPCB and the first connection line CWL1 to each other. The pad portion PAD may overlap a portion of the lead electrode LDE in a plan view. The pad portion PAD may be electrically connected to the lead electrode LDE of the flexible film FPCB through the contact portion CTP.

[0175] The interlayer insulating layer ILD, the gate insulating layer GI, the second substrate SUB2, the third blocking insulating layer BIL3 and the second blocking insulating layer BIL2 may include a second contact hole CNT2. The second contact hole CNT2 may be etched from the upper surface of the interlayer insulating layer ILD to extend through the second blocking insulating layer BIL2. In the process of forming the second contact hole CNT2, the upper surface of the pad portion PAD may be exposed. The first contact hole CNT1 and the second contact hole CNT2 may be spaced apart from each other in a plan view.

[0176] The first connection line CWL1 may be disposed on the interlayer insulating layer ILD. The first connection line CWL1 may include the same material as the first source metal layer SDL1 of the display area DA, and may be formed in the same process as the first source metal layer SDL1. A portion of the first connection line CWL1 may be inserted into the second contact hole CNT2 to contact the upper surface of the pad portion PAD. Another portion of the first connection line CWL1 may penetrate the interlayer insulating layer ILD to contact the second connection line CWL2. The first connection line CWL1 may electrically connect the pad portion PAD and the second connection line CWL2 to each other. The first connection line CWL1 may supply a data voltage or a source voltage received from the pad portion PAD to the second connection line CWL2.

[0177] The second connection line CWL2 may be disposed on the gate insulating layer GI. The second connection line CWL2 may include the same material as the gate layer GTL of the display area DA and may be formed in the same process as the gate layer GTL. The second connection line CWL2 may supply the data voltage received from the first connection line CWL1 to the data line DL. The second connection line CWL2 may supply the source voltage received from the first connection line CWL1 to the power line VL. For example, the second connection line CWL2 may correspond to Figure 5 The signal line SL in the circuit may be electrically connected to the signal line SL.

[0178] exist Fig. 20 In the embodiment of the present invention, the contact portion CTP may cover the lower surface of the lead electrode LDE protruding from the flexible film FPCB and the lower surface of the pad portion PAD exposed through the opening portion SOP. The contact portion CTP may electrically connect the lead electrode LDE and the pad portion PAD to each other. The contact portion CTP may overlap with the first contact hole CNT1 and may not overlap with the second contact hole CNT2. Each of the plurality of contact portions CTP may connect one of the plurality of lead electrodes LDE and the pad portion PAD corresponding to the one lead electrode LDE to each other in a one-to-one manner. The plurality of contact portions CTP are formed separately without a separate laser patterning process, and therefore, damage to the display panel 100, short circuit defects, and over-sintering risks of the contact portions CTP due to laser patterning may be prevented.

[0179] The display device 10 may reduce manufacturing time and manufacturing cost by electrically connecting the lead electrode LDE and the pad portion PAD to each other through the contact portion CTP using a metal paste to simplify the manufacturing process without using ultrasonic bonding or thermocompression bonding.

[0180] Fig.21 is a cross-sectional view illustrating a partition wall in a display device according to another embodiment.

[0181] refer to Fig.21 , the partition wall WAL may be inserted into the opening portion SOP of the first substrate SUB1 and disposed between adjacent pad portions PAD. The partition wall WAL may be disposed on the lower surface of the first blocking insulating layer BIL1 between adjacent contact portions CTP. The contact portion CTP may connect the lead electrode LDE and the pad portion PAD to each other in a one-to-one manner between adjacent partition walls WAL. The partition wall WAL may prevent adjacent contact portions CTP from being short-circuited to each other in the process of forming the contact portion CTP. The partition wall WAL may include an organic film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or the like. The thickness of the partition wall WAL may be greater than the thickness of the contact portion CTP, but is not limited thereto.

[0182] Figure 22 to Figure 25 is a cross-sectional view illustrating a manufacturing process of a display device according to another embodiment.

[0183] exist Fig. 22 In the embodiment, the opening portion SOP may be formed by etching one surface of the first substrate SUB1. At least one of a wet etching process, a dry etching process, a plasma etching process, and a laser etching process may be performed on one surface of the first substrate SUB1. The opening portion SOP may be provided in the first substrate SUB1 to expose the pad portion PAD. One opening portion SOP may expose a plurality of pad portions PAD, but is not limited thereto.

[0184] The lead electrode LDE may be inserted into the opening portion SOP of the first substrate SUB 1. The lead electrode LDE may be attached to a lower surface of the pad portion PAD by an adhesive member ADM.

[0185] exist Fig.23 In the embodiment, an organic material WALa may be inserted into the opening portion SOP of the first substrate SUB1 to cover the lower surface of the lead electrode LDE and the pad portion PAD. The organic material WALa may include at least one of acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0186] exist Fig.24 In the embodiment, a plurality of partition walls WAL may be formed by etching the organic material WALa. A portion of the organic material WALa overlapping with the lead electrode LDE and a portion of the organic material WALa overlapping with the pad portion PAD may be etched away to expose the lead electrode LDE and the pad portion PAD. For example, the organic material WALa may be etched by at least one of a wet etching process, a dry etching process, a plasma etching process, and a laser etching process.

[0187] exist Fig.25In the embodiment, the contact portion CTP may cover the lower surface of the lead electrode LDE and the lower surface of the pad portion PAD. The contact portion CTP may be formed between adjacent partition walls WAL. The lead electrode LDE may be electrically connected to the pad portion PAD through the contact portion CTP. Fig.25 As shown in the figure, the contact portion CTP and the pad portion PAD are not in direct contact with each other, but in Fig.18 and Fig.19 In cross-sectional views in other directions, the contact portion CTP and the pad portion PAD may be in direct contact with each other.

[0188] Conductive ink Ink may be applied to the lead electrode LDE and the pad portion PAD. The conductive ink Ink may include nanoparticles and polymers. The contact portion CTP may be formed by low temperature sintering of the conductive ink Ink.

[0189] The sintered conductive ink Ink may cover one lead electrode LDE among a plurality of lead electrodes LDE inserted into one opening portion SOP and a pad portion PAD corresponding to the one lead electrode LDE. A plurality of contact portions CTP may be spaced apart from one another, and one contact portion CTP may electrically connect one pad portion PAD and one lead electrode LDE to one another. A plurality of contact portions CTP are formed separately without a separate laser patterning process, and therefore, damage to the display panel 100, a short circuit defect, and an over-sintering risk of the contact portion CTP due to laser patterning may be prevented.

[0190] Accordingly, in the display device 10, by electrically connecting the lead electrode LDE and the pad portion PAD to each other via the contact portion CTP, the lead electrode LDE of the flexible film FPCB can be electrically connected to the pad portion PAD without using ultrasonic bonding or thermocompression bonding. In addition, the display device 10 can reduce manufacturing time and manufacturing cost by simplifying the manufacturing process.

[0191] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the scope and spirit of the present disclosure as set forth in the following claims.

Claims

1. A display device, comprising: A first substrate including an opening portion; a first blocking insulating layer disposed on the first substrate and comprising a first contact hole; a pad portion disposed on the first blocking insulating layer and inserted into the first contact hole; A second substrate is disposed on the pad portion; a first connection line disposed on the second substrate and connected to the pad portion; a flexible film partially inserted into the opening portion of the first substrate and including a lead electrode spaced apart from the pad portion in a plan view; as well as A contact portion electrically connects the pad portion and the lead electrode to each other.

2. The display device according to claim 1, wherein: The contact portion covers a lower surface of the lead electrode and a lower surface of the pad portion.

3. The display device according to claim 1, wherein: The contact portion covers a lower surface of the first blocking insulating layer disposed between the lead electrode and the pad portion.

4. The display device according to claim 1, wherein: The contact portion corresponds to a conductive line connecting a center of a portion of the lead electrode protruding from the flexible film and a center of a portion of the pad portion inserted into the first contact hole to each other.

5. The display device according to claim 1, wherein: The second substrate includes a second contact hole spaced apart from the first contact hole in the plan view, and the first connection line is inserted into the second contact hole to be connected to the pad portion.

6. The display device according to claim 1, wherein: The second substrate includes a second contact hole overlapping the first contact hole, and the first connection line is inserted into the second contact hole to be connected to the pad portion.

7. The display device according to any one of claims 1 to 6, further comprising: a gate insulating layer, disposed on the second substrate; a second connection line, disposed on the gate insulating layer and connected to the first connection line; as well as An interlayer insulating layer is provided at a layer between the second connection line and the first connection line.

8. The display device according to claim 7, further comprising: A semiconductor region of the transistor is disposed on the second substrate; The gate electrode of the transistor is disposed on the gate insulating layer; as well as a connection electrode disposed on the interlayer insulating layer and electrically connected to the transistor, The first connecting line and the connecting electrode are made of the same material and are formed by the same process as the connecting electrode, and The second connection line includes the same material as the gate electrode of the transistor, and is formed by the same process as the gate electrode.

9. A display device, comprising: A first substrate including an opening portion; a first blocking insulating layer disposed on the first substrate and comprising a plurality of first contact holes; a plurality of pad portions disposed on the first blocking insulating layer and respectively inserted into the plurality of first contact holes; A second substrate is disposed on the plurality of pad portions; a plurality of first connection lines, which are disposed on the second substrate and are respectively connected to the plurality of pad portions; a flexible film partially inserted into the opening portion of the first substrate and including a plurality of lead electrodes; a plurality of partition walls disposed on a lower surface of the first blocking insulating layer and between adjacent pad portions among the plurality of pad portions; as well as A contact portion connects the pad portion and the lead electrode to each other in a one-to-one manner between adjacent ones of the plurality of partition walls.

10. The display device according to claim 9, wherein: The lead electrode is attached to a lower surface of the pad portion through an adhesive member, and the contact portion covers a lower surface of the lead electrode and the lower surface of the pad portion.

11. The display device according to claim 9, wherein: The partition wall includes an organic film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin.

12. A method for manufacturing a display device, comprising: providing a first substrate; forming a first blocking insulating layer on the first substrate, wherein the first blocking insulating layer includes a first contact hole; forming a pad portion disposed on the first blocking insulating layer and inserted into the first contact hole; forming a second substrate on the pad portion, the second substrate comprising a second contact hole; forming a first connection line disposed on the second substrate and inserted into the second contact hole to be connected to the pad portion; forming an opening portion by etching a lower surface of the first substrate, the opening portion exposing a lower surface of the first blocking insulating layer and a lower surface of the pad portion; disposing a lead electrode of a flexible film on the lower surface of the first barrier insulating layer so as to be spaced apart from the pad portion in a plan view; as well as A contact portion that electrically connects the pad portion and the lead electrode to each other is formed.

13. The method for manufacturing a display device according to claim 12, wherein: The forming of the contact portion includes: The coordinates of the center of the portion of the lead electrode protruding from the flexible film and the coordinates of the center of the pad portion exposed by the opening portion are scanned.

14. The method for manufacturing a display device according to claim 13, wherein: The forming of the contact portion further comprises: A metal paste is printed and sintered between the center of the lead electrode and the center of the pad portion.

15. The method for manufacturing a display device according to claim 12, wherein: The forming of the second substrate includes: The second contact hole is formed so as to be spaced apart from the first contact hole in the plan view.

16. The method for manufacturing a display device according to claim 12, wherein: The forming of the second substrate includes: The second contact hole is formed so as to overlap with the first contact hole.

17. A method for manufacturing a display device, comprising: providing a first substrate; forming a first blocking insulating layer on the first substrate, wherein the first blocking insulating layer includes a plurality of first contact holes; forming a plurality of pad portions disposed on the first blocking insulating layer and respectively inserted into the plurality of first contact holes; forming a second substrate on the plurality of pad portions, the second substrate comprising a plurality of second contact holes; forming a plurality of first connection lines which are disposed on the second substrate and are respectively inserted into the plurality of second contact holes to be respectively connected to the plurality of pad portions; forming an opening portion by etching a lower surface of the first substrate, the opening portion exposing a lower surface of the first blocking insulating layer and lower surfaces of the plurality of pad portions; providing a lead electrode of a flexible film on the lower surface of the pad portion; forming a plurality of partition walls disposed on the lower surface of the first blocking insulating layer between adjacent pad portions among the plurality of pad portions; as well as A contact portion is formed that connects the pad portion and the lead electrode to each other in a one-to-one manner.

18. The method for manufacturing a display device according to claim 17, wherein: The forming of the plurality of partition walls comprises: The pad portion and the lead electrode are covered with an organic material.

19. The method for manufacturing a display device according to claim 18, wherein: The forming of the plurality of partition walls further comprises: The lead electrode and the pad portion are exposed by etching away a portion of the organic material overlapping the lead electrode and a portion of the organic material overlapping the pad portion.

20. The method for manufacturing a display device according to claim 17, wherein: The forming of the contact portion includes: A conductive ink is applied between the partition walls and then sintered at a low temperature.

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