Display panel, preparation method thereof and display device

Abstract

The invention provides a display panel, a preparation method thereof and a display device. The display panel comprises a substrate, at least one pixel circuit and a plurality of sub-pixels. The at least one pixel circuit is located on one side of the substrate, the pixel circuit comprises a plurality of transistors, and the sub-pixels are electrically connected with the pixel circuit. Wherein the distance between orthographic projections of grid electrodes of at least part of adjacent transistors in the same pixel circuit or different pixel circuits on the substrate is smaller than or equal to 0.6 micron. The distance between the orthographic projections of the grids of at least part of adjacent transistors on the substrate is set to be smaller than or equal to 0.6 micron, so that close arrangement of the adjacent transistors is realized, the space size occupied by the transistors in the direction perpendicular to the thickness direction of the substrate is compressed to an almost limit level, the pixel density of the display panel is effectively improved, and the display effect is improved. And the resolution of the display image is improved, so that a better display effect is obtained.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel, a method for preparing a display panel, and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) has attracted widespread attention due to its self-luminescence, low power consumption, high brightness, and fast response. With the advancement of technology and the continuous improvement of people's demand for information interaction, commercial display is being integrated into life at an unprecedented speed, such as the application of various forms of commercial display screens integrated with the environment and holographic projection.

[0003] However, the pixel density (Pixel Per Inch, PPI) of OLED displays still needs to be improved. Summary of the invention

[0004] Embodiments of the present application provide a display panel, a method for manufacturing a display panel, and a display device, which are used to improve the problem that the pixel density in OLED display needs to be improved.

[0005] In a first aspect, a display panel is provided, the display panel comprising a substrate, at least one pixel circuit and a plurality of sub-pixels. The at least one pixel circuit is located on one side of the substrate, the pixel circuit comprises a plurality of transistors, and the sub-pixels and the pixel circuit are electrically connected.

[0006] Wherein, a distance between orthographic projections of gates of at least some adjacent transistors in the same pixel circuit or in different pixel circuits on the substrate is less than or equal to 0.6 micrometers.

[0007] In combination with the first aspect, in some implementations of the first aspect, at least some of the adjacent transistors include a first transistor and a second transistor, and gates of the first transistor and the second transistor are located in different layers.

[0008] In combination with the first aspect, in some implementations of the first aspect, a distance between an orthographic projection of a gate of the first transistor and a gate of the second transistor on the substrate is less than or equal to 0.4 micrometers.

[0009] In combination with the first aspect, in some implementations of the first aspect, the first transistor and the second transistor correspond to different pixel circuits respectively.

[0010] In combination with the first aspect, in some implementations of the first aspect, the first transistor and the second transistor are both driving transistors.

[0011] In combination with the first aspect, in certain implementations of the first aspect, a plurality of transistors in the pixel circuit are arranged sequentially in a direction away from the substrate.

[0012] In combination with the first aspect, in certain implementations of the first aspect, multiple pixel circuits include a first pixel circuit and a second pixel circuit, the first transistor corresponds to the first pixel circuit, and the second transistor corresponds to the second pixel circuit; the second pixel circuit also includes at least one first other transistor other than the second transistor, and the second pixel circuit also includes at least one second other transistor other than the second transistor, and the gates of the first other transistor and the second other transistor are arranged in the same layer in a one-to-one manner.

[0013] In combination with the first aspect, in some implementations of the first aspect, the multiple transistors further include a third transistor located on a side of the second transistor away from the first transistor; a gate of the third transistor and a gate of the first transistor are on different layers.

[0014] In combination with the first aspect, in some implementations of the first aspect, the third transistor, the second transistor and the first transistor correspond to different pixel circuits respectively.

[0015] In combination with the first aspect, in certain implementations of the first aspect, the display panel also includes a first insulating layer and a second insulating layer, and in a direction away from the substrate, the gate of the first transistor, the first insulating layer, the gate of the second transistor, the second insulating layer, and the gate of the third transistor are stacked in sequence.

[0016] In combination with the first aspect, in certain implementations of the first aspect, the display panel further includes a plurality of sub-pixels, and the luminous colors of the sub-pixels connected to the first transistor, the sub-pixels connected to the second transistor, and the sub-pixels connected to the third transistor are all different.

[0017] In combination with the first aspect, in some implementations of the first aspect, the multiple transistors further include a third transistor located on a side of the second transistor away from the first transistor; a gate of the third transistor and a gate of the first transistor are located on the same layer.

[0018] In combination with the first aspect, in some implementations of the first aspect, the third transistor, the second transistor and the first transistor correspond to different pixel circuits respectively.

[0019] In combination with the first aspect, in some implementations of the first aspect, the display panel further includes a first insulating layer, and in a direction away from the substrate, the gate of the first transistor, the first insulating layer, and the gate of the second transistor are stacked in sequence.

[0020] In combination with the first aspect, in certain implementations of the first aspect, the display panel further includes a plurality of sub-pixels, and the luminous colors of the sub-pixels connected to the first transistor, the sub-pixels connected to the second transistor, and the sub-pixels connected to the third transistor are all different.

[0021] In combination with the first aspect, in some implementations of the first aspect, at least some of the adjacent transistors include a fourth transistor and a fifth transistor, and the gates of the fourth transistor and the fifth transistor are arranged in the same layer.

[0022] In combination with the first aspect, in some implementations of the first aspect, the display panel further includes a third insulating layer, the third insulating layer is located on a side of the gate of the fourth transistor away from the substrate; the third insulating layer includes an opening, and the gate of the fifth transistor is located in the opening.

[0023] In combination with the first aspect, in some implementations of the first aspect, the fourth transistor and the fifth transistor correspond to different pixel circuits respectively.

[0024] In combination with the first aspect, in some implementations of the first aspect, the fourth transistor and the fifth transistor are both driving transistors.

[0025] In combination with the first aspect, in some implementations of the first aspect, a distance between orthographic projections of the gates of the fourth transistor and the fifth transistor on the substrate is less than or equal to 0.6 micrometers and greater than or equal to 0.4 micrometers.

[0026] In combination with the first aspect, in certain implementations of the first aspect, a plurality of transistors in the pixel circuit are arranged sequentially in a direction away from the substrate.

[0027] In combination with the first aspect, in certain implementations of the first aspect, the multiple pixel circuits include a fourth pixel circuit and a fifth pixel circuit, the fourth transistor corresponds to the fourth pixel circuit, and the fifth transistor corresponds to the fifth pixel circuit; the fourth pixel circuit also includes at least one fourth other transistor other than the fourth transistor, and the fifth pixel circuit also includes at least one fifth other transistor other than the fifth transistor, and the gates of the fourth other transistors and the fifth other transistors are arranged in the same layer in a one-to-one manner.

[0028] In combination with the first aspect, in certain implementations of the first aspect, the multiple transistors further include a sixth transistor located on a side of the fifth transistor away from the fourth transistor; a gate of the sixth transistor and a gate of the fourth transistor are located on the same layer.

[0029] In combination with the first aspect, in some implementations of the first aspect, the gate of the sixth transistor and the gate of the fifth transistor are located in the same layer.

[0030] In combination with the first aspect, in certain implementations of the first aspect, the pixel circuit includes a driving transistor; and the gates of the driving transistors in the pixel circuits connected to sub-pixels of the same color are arranged in the same layer.

[0031] In a second aspect, a method for preparing a display panel is provided, comprising:

[0032] An active layer is prepared on a substrate, wherein the active layer includes a first active portion and a second active portion;

[0033] Prepare a first insulating layer on the side of the active layer facing away from the substrate;

[0034] A first gate is formed on a side of the first insulating layer facing away from the substrate, wherein an orthographic projection of the first gate on the substrate partially overlaps an orthographic projection of the first active portion on the substrate;

[0035] Prepare a second insulating layer on the side of the first gate facing away from the substrate;

[0036] Opening a hole in the second insulating layer, wherein the orthographic projection of the hole on the substrate covers the orthographic projection of the second active portion on the substrate;

[0037] preparing a second grid in the hole;

[0038] A sub-pixel is prepared on the side of the second gate facing away from the substrate.

[0039] In a third aspect, a method for preparing a display panel is provided, comprising:

[0040] An active layer is prepared on a substrate, wherein the active layer includes a first active portion and a second active portion;

[0041] Prepare a first insulating layer on the side of the active layer facing away from the substrate;

[0042] A first gate is formed on a side of the first insulating layer facing away from the substrate, wherein an orthographic projection of the first gate on the substrate partially overlaps an orthographic projection of the first active portion on the substrate;

[0043] Prepare a second insulating layer on the side of the first gate facing away from the substrate;

[0044] A second gate is formed on a side of the second insulating layer facing away from the substrate, wherein an orthographic projection of the second gate on the substrate partially overlaps an orthographic projection of the second active portion on the substrate;

[0045] A sub-pixel is prepared on the side of the second gate facing away from the substrate.

[0046] In a fourth aspect, a display device is provided, comprising any one of the display panels described above.

[0047] The present application provides a display panel, a method for preparing a display panel, and a display device. The display panel of the present application includes a substrate, at least one pixel circuit, and a plurality of sub-pixels. At least one pixel circuit is located on one side of the substrate, the pixel circuit includes a plurality of transistors, and the sub-pixels and the pixel circuit are electrically connected. Among them, the distance between the gates of at least some adjacent transistors in the same pixel circuit or different pixel circuits on the substrate is less than or equal to 0.6 microns.

[0048] The present application achieves close arrangement of adjacent transistors by setting the distance between the gates of at least some adjacent transistors on the substrate to be less than or equal to 0.6 microns, compressing the space occupied by the transistors in the direction perpendicular to the thickness of the substrate to an almost limit level, effectively improving the pixel density of the display panel and the resolution of the displayed image, thereby obtaining a better display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0050] Figure 1 It is a schematic diagram of the cross-sectional structure of a display panel in the prior art.

[0051] Figure 2 FIG. 1 is a schematic diagram of a cross-sectional structure of a display panel in an embodiment of the present application.

[0052] Figure 3 FIG. 4 is a schematic diagram of a cross-sectional structure of a display panel in another embodiment of the present application.

[0053] Figure 4 FIG. 1 is a schematic diagram of pixel arrangement of a display panel in an embodiment of the present application.

[0054] Figure 5 FIG. 4 is a schematic diagram of a cross-sectional structure of a display panel in another embodiment of the present application.

[0055] Figure 6 FIG. 4 is a schematic diagram of a cross-sectional structure of a display panel in another embodiment of the present application.

[0056] Figure 7 FIG. 4 is a schematic diagram of a cross-sectional structure of a display panel in another embodiment of the present application.

[0057] Figure 8 FIG. 1 is a schematic diagram of pixel arrangement of a display panel in another embodiment of the present application.

[0058] Fig. 9 Detailed description of the invention The figure is a flow chart of a method for preparing a display panel in one embodiment of the present application.

[0059] Fig.10 This is a flow chart of a method for preparing a display panel in yet another embodiment of the present application. DETAILED DESCRIPTION

[0060] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. In the detailed description below, many specific details are proposed to provide a comprehensive understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating examples of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application. The features and exemplary embodiments of various aspects of the present application will be described in detail below.

[0061] As described in the background art, the pixel density of OLED displays in the prior art still needs to be improved. Figure 1 As shown, Figure 1 Schematic diagram of the cross-sectional structure of a display panel in the prior art. The display panel includes a substrate 10, at least one pixel circuit and a plurality of sub-pixels 20. At least one pixel circuit is located on one side of the substrate 10, the pixel circuit includes a plurality of transistors, and the sub-pixels 20 and the pixel circuit are electrically connected. The transistor includes a first transistor 31 and a second transistor 32 arranged adjacent to each other, wherein a gate 310 of the first transistor 31 and a gate 320 of the second transistor 32 are arranged in the same layer and are obtained by the same process.

[0062] Due to the influence of factors such as equipment accuracy in the existing gate manufacturing process, the distance D between adjacent gates of the same layer prepared by the same process is large and difficult to compress. Generally speaking, the distance D is not less than 1.5 microns. Therefore, in the direction perpendicular to the thickness of the substrate 10, the space occupied by the transistor is large, which in turn limits the further improvement of the pixel density of the display panel and hinders the effective improvement of the display effect of the display panel.

[0063] In view of this, the present application provides a display panel, a method for preparing a display panel, and a display device. The present application achieves close arrangement of adjacent transistors by setting the distance between the orthographic projections of at least some of the gates of adjacent transistors on the substrate to be less than or equal to 0.6 microns, compressing the space occupied by the transistors in the direction perpendicular to the thickness of the substrate to an almost limit level, effectively improving the pixel density of the display panel, and improving the resolution of the displayed image, thereby obtaining a better display effect.

[0064] Figure 2 FIG. 1 is a schematic diagram of a cross-sectional structure of a display panel in an embodiment of the present application. Figure 2As shown, the display panel includes a substrate 10, at least one pixel circuit and a plurality of sub-pixels 20. At least one pixel circuit is located on one side of the substrate 10, the pixel circuit includes a plurality of transistors, and the sub-pixels 20 are electrically connected to the pixel circuit. The distance D between the gates of at least some adjacent transistors in the same pixel circuit or different pixel circuits on the substrate 10 is less than or equal to 0.6 microns.

[0065] In the present application, the distance D refers to the minimum distance between the orthographic projections of the gates of adjacent transistors on the substrate 10 .

[0066] This embodiment achieves close arrangement of adjacent transistors by setting the distance between the gates of at least some adjacent transistors on the substrate to be less than or equal to 0.6 microns, compressing the space occupied by the transistors in the direction perpendicular to the thickness of the substrate to an almost limit level, effectively improving the pixel density of the display panel and the resolution of the displayed image, thereby obtaining a better display effect.

[0067] In one embodiment, at least some of the adjacent transistors include a first transistor 31 and a second transistor 32, wherein a gate 310 of the first transistor 31 and a gate 320 of the second transistor 32 are located at different layers, as shown in FIG. Figure 2 As shown. Since the gate 310 of the first transistor 31 and the gate 320 of the second transistor 32 are formed by different processes and are located in different layers, the distance between adjacent gates is not limited by the accuracy of the equipment in the manufacturing process, and there is no risk of short circuit. Therefore, compared with the prior art, in this embodiment, the distance between adjacent gates can be compressed to an almost extreme level.

[0068] In one embodiment, a distance D between the gate 310 of the first transistor 31 and the gate 320 of the second transistor 32 on the substrate 10 is less than or equal to 0.4 micrometers. In this embodiment, the distance D refers to the minimum distance between the gate 310 of the first transistor 31 and the gate 320 of the second transistor 32, specifically, the distance between the side wall of the gate 310 of the first transistor 31 close to the gate 320 of the second transistor 32 and the side wall of the gate 320 of the second transistor 32 close to the gate 310 of the first transistor 31.

[0069] In one embodiment, the first transistor 31 and the second transistor 32 correspond to different pixel circuits respectively.

[0070] In one embodiment, the first transistor 31 and the second transistor 32 are both driving transistors. In this embodiment, the first transistor 31 and the second transistor 32 are transistors for driving different sub-pixels. By arranging the first transistor 31 and the second transistor 32 in different layers, the distance between the positive projection of the gate 310 of the first transistor 31 and the gate 320 of the second transistor 32 on the substrate 10 can be less than or equal to 0.4 microns, thereby achieving a significant release of space, which is conducive to improving the pixel density of the display panel and the resolution of the displayed image, thereby obtaining a better display effect.

[0071] In one embodiment, multiple transistors in the pixel circuit are arranged in sequence in a direction away from the substrate 10. In this embodiment, multiple transistors are arranged in a stacked manner in a direction away from the substrate 10, which can further reduce the space occupied by the transistors, thereby further improving the pixel density of the display panel and the resolution of the displayed image to obtain a better display effect.

[0072] In one embodiment, the plurality of pixel circuits include a first pixel circuit and a second pixel circuit, the first transistor 31 corresponds to the first pixel circuit, and the second transistor 32 corresponds to the second pixel circuit; the second pixel circuit also includes at least one first other transistor in addition to the second transistor 32, and the second pixel circuit also includes at least one second other transistor in addition to the second transistor 32, and the gates of the first other transistor and the second other transistor are arranged in the same layer in a one-to-one correspondence. In this embodiment, by arranging multiple transistors of the same pixel circuit in the same layer, the space occupied by the transistors can be further reduced, thereby further improving the pixel density of the display panel and the resolution of the displayed image to obtain a better display effect.

[0073] In one embodiment, the transistor further includes a source and a drain 40 . The source and the drain 40 are located on a side of the gate 320 of the second transistor 32 away from the substrate 10 .

[0074] In one embodiment, the display panel further includes an anode 21 and a cathode 22. The anode 21 is located on a side of the sub-pixel 20 close to the substrate 10, and the cathode 22 is located on a side of the sub-pixel 20 away from the substrate 10.

[0075] In one embodiment, the display panel further includes an encapsulation layer 50. The encapsulation layer 50 is located on the side of the sub-pixel away from the substrate 10, and is used to encapsulate the sub-pixel 20 to prevent water and oxygen in the external environment from corroding the luminescent material, thereby increasing the service life of the luminescent structure formed by the sub-pixel 20, the anode 21 and the cathode 22.

[0076] In one embodiment, the encapsulation layer 50 includes a thin film encapsulation layer. The thin film encapsulation layer may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer stacked sequentially on a side away from the sub-pixel 20. The first inorganic encapsulation layer and the second inorganic encapsulation layer block external water and ions, and the organic encapsulation layer can be made by coating or inkjet printing process to play a flattening role.

[0077] Figure 3 FIG. 1 is a schematic diagram of a cross-sectional structure of a display panel in another embodiment of the present application. Figure 2 , Figure 3 The plurality of transistors in the display panel further include a third transistor 33, which is located on a side of the second transistor 32 away from the first transistor 31. The gate 330 of the third transistor 33 and the gate 310 of the first transistor 31 are in different layers.

[0078] In this embodiment, the gate 310 of the first transistor 31, the gate 320 of the second transistor 32 and the gate 330 of the third transistor 33 are prepared by different processes, and the above three are respectively located in different layers. The distance between adjacent gates is not limited by the accuracy of equipment in the preparation process, and there is no risk of short circuit. Therefore, compared with the distance between adjacent gates in the prior art, the distance can be compressed to an almost extreme level.

[0079] In one embodiment, the gate 320 of the second transistor 32 is located on a side of the gate 310 of the first transistor 31 away from the substrate 10 , and the gate 330 of the third transistor 33 is located on a side of the gate 320 of the second transistor 32 away from the substrate 10 .

[0080] In one embodiment, the third transistor 33 , the second transistor 32 and the first transistor 31 correspond to different pixel circuits respectively, that is, the three transistors are used to control three different sub-pixels respectively.

[0081] In one embodiment, the display panel also includes a first insulating layer 510 and a second insulating layer 520. In a direction away from the substrate 10, the gate 310 of the first transistor 31, the first insulating layer 510, the gate 320 of the second transistor 32, the second insulating layer 520, and the gate 330 of the third transistor 33 are stacked in sequence.

[0082] In one embodiment, the display panel further includes an active layer 60 , and the active layer 60 is located between the substrate 10 and the gate 310 of the first transistor 31 .

[0083] In one embodiment, the display panel further includes a gate insulating layer 530 , and the gate insulating layer 530 is located between the active layer 60 and the gate 310 of the first transistor.

[0084] In one embodiment, the display panel further includes an interlayer insulating layer 540 , and the interlayer insulating layer 540 is located between the gate 330 and the source and drain 40 of the third transistor 33 .

[0085] In one embodiment, the display panel further includes a plurality of sub-pixels 20 , and the sub-pixel 20 - 1 connected to the first transistor 31 , the sub-pixel 20 - 2 connected to the second transistor 32 , and the sub-pixel 20 - 3 connected to the third transistor 33 all emit different colors.

[0086] In one embodiment, the pixel arrangement of the display panel includes an RGB type arrangement, and the luminous colors of the sub-pixels 20-1, 20-2 and 20-3 of the display panel are red, green and blue, respectively. Figure 4 As shown, Figure 4 FIG. 1 is a schematic diagram of pixel arrangement of a display panel in an embodiment of the present application.

[0087] Figure 5 FIG. 2 is a schematic diagram of a cross-sectional structure of a display panel in another embodiment of the present application. The plurality of transistors further includes a third transistor 33, and the third transistor 33 is located on a side of the second transistor 32 away from the first transistor 31. Figure 3 , Figure 5 In the display panel shown, the gate 330 of the third transistor 33 and the gate 310 of the first transistor 31 are located in the same layer. With such an arrangement, on the one hand, the distance D between adjacent transistors can be compressed to a near limit, thereby realizing a close arrangement of transistors; on the other hand, the structures of the first transistor 31 and the third transistor 33 can be made similar to each other to the greatest extent, thereby making the pixel driving currents in the sub-pixel 20-1 controlled by the first transistor 31 and the sub-pixel 20-3 controlled by the third transistor 33 consistent.

[0088] In one embodiment, the third transistor 33 , the second transistor 32 and the first transistor 31 correspond to different pixel circuits respectively.

[0089] In one embodiment, the display panel further includes a first insulating layer 510 , and in a direction away from the substrate, the gate 310 of the first transistor 31 , the first insulating layer 510 , and the gate 320 of the second transistor 32 are stacked in sequence.

[0090] In one embodiment, the display panel further includes a plurality of sub-pixels 20 , and the sub-pixel 20 - 1 connected to the first transistor 31 , the sub-pixel 20 - 2 connected to the second transistor 32 , and the sub-pixel 20 - 3 connected to the third transistor 33 all emit different colors.

[0091] Figure 6 FIG. 4 is a schematic diagram of a cross-sectional structure of a display panel in another embodiment of the present application. Figure 6In the display panel shown, at least some of the adjacent transistors include a fourth transistor 34 and a fifth transistor 35, and the gate 340 of the fourth transistor 34 and the gate 350 of the fifth transistor 35 are arranged in the same layer. Specifically, the display panel further includes a third insulating layer 550, and the third insulating layer 550 is located on the side of the gate 340 of the fourth transistor 34 away from the substrate 10, wherein the third insulating layer 550 includes an opening, and the gate 350 of the fifth transistor 35 is located in the opening. In this embodiment, the gate 340 of the fourth transistor 34 and the gate 350 of the fifth transistor 35 are prepared and formed by different processes.

[0092] Since the gate 310 of the first transistor 31 and the gate 320 of the second transistor 32 are formed through different processes, the distance between adjacent gates is not limited by the accuracy of equipment in the preparation process. Compared with the prior art, in this embodiment, the distance between adjacent gates can be compressed to a greater extent.

[0093] In one embodiment, a distance D between the orthographic projections of the gate 340 of the fourth transistor 34 and the gate 350 of the fifth transistor 35 on the substrate 10 is less than or equal to 0.6 micrometers and greater than or equal to 0.4 micrometers. Since the gate 340 of the fourth transistor 34 and the gate 350 of the fifth transistor 35 are located in the same layer, the distance D between the orthographic projections of the gate 340 of the fourth transistor 34 and the gate 350 of the fifth transistor 35 on the substrate 10 is set to be greater than or equal to 0.4 micrometers, which can reduce the risk of short circuit.

[0094] In one embodiment, the fourth transistor 34 and the fifth transistor 35 correspond to different pixel circuits respectively.

[0095] In one embodiment, the fourth transistor 34 and the fifth transistor 35 are both driving transistors.

[0096] In one embodiment, multiple transistors in the pixel circuit are arranged in sequence in a direction away from the substrate 10. In this embodiment, multiple transistors are arranged in a stacked manner in a direction away from the substrate 10, which can further reduce the space occupied by the transistors, thereby further improving the pixel density of the display panel and the resolution of the displayed image to obtain a better display effect.

[0097] In one embodiment, the plurality of pixel circuits include a fourth pixel circuit and a fifth pixel circuit, the fourth transistor 34 corresponds to the fourth pixel circuit, and the fifth transistor 35 corresponds to the fifth pixel circuit. The fourth pixel circuit also includes at least one fourth other transistor in addition to the fourth transistor 34, and the fifth pixel circuit also includes at least one fifth other transistor in addition to the fifth transistor 35, and the gates of the fourth other transistor and the fifth other transistor are arranged in the same layer in a one-to-one correspondence.

[0098] In one embodiment, the plurality of transistors further include a sixth transistor, which is located on a side of the fifth transistor 35 away from the fourth transistor 34 , and a gate of the sixth transistor and a gate 340 of the fourth transistor 34 are located in the same layer.

[0099] In one embodiment, the gate of the sixth transistor and the gate 350 of the fifth transistor 35 are located at the same layer.

[0100] In one embodiment, the pixel circuit includes a driving transistor, and the gates of the driving transistors in the pixel circuit connected to the sub-pixels of the same color are arranged in the same layer. The structures of the driving transistors arranged in the same layer are similar to the greatest extent, so that the pixel driving currents of the sub-pixels controlled by the driving transistors are consistent, thereby reducing the risk of different display effects of the sub-pixels of the same color.

[0101] Figure 7 FIG. 4 is a schematic diagram of a cross-sectional structure of a display panel in another embodiment of the present application. Figure 7 In the display panel shown, Figure 5 Compared with the display panel shown, the multiple transistors also include a seventh transistor 37, which is located on the side of the third transistor 33 away from the second transistor 32, and the gate 370 of the seventh transistor 37 is arranged on a different layer from the gate 330 of the third transistor 33, and the gate 370 of the seventh transistor 37 is arranged on the same layer as the gate 320 of the second transistor 32, and the gate 370 of the seventh transistor 37 is connected to the sub-pixel 20-7.

[0102] In one embodiment, the pixel arrangement of the display panel includes an RGBG type arrangement. Figure 8 As shown, Figure 8 Schematic diagram of pixel arrangement of a display panel in another embodiment of the present application. Specifically, in a direction perpendicular to the thickness of the substrate 10, the sub-pixel 20-1 connected to the first transistor 31, the sub-pixel 20-2 connected to the second transistor 32, the sub-pixel 20-3 connected to the third transistor 33, and the sub-pixel 20-7 connected to the seventh transistor are arranged in sequence. The luminous colors of the sub-pixels 20-1, 20-2, 20-3, and 20-7 of the display panel are red, green, blue, and green, respectively.

[0103] In this embodiment, the gate 320 of the second transistor 32 and the gate 370 of the seventh transistor 37 are arranged on the same layer, so that the structures of the second transistor 32 and the seventh transistor 37 are similar to the greatest extent, so that the pixel driving current in the sub-pixel 20-2 connected to the second transistor 32 and the sub-pixel 20-7 connected to the seventh transistor are consistent, thereby reducing the risk of differences in display effects of sub-pixels of the same color under this pixel arrangement.

[0104] The present application also provides a method for preparing a display panel, the specific steps of which are as follows: Fig. 9 As shown, Fig. 9 FIG. 1 is a flow chart of a method for preparing a display panel in an embodiment of the present application. Fig. 9 As shown, the specific steps of the method for preparing the display panel in this embodiment are as follows:

[0105] S910: preparing an active layer on a substrate, wherein the active layer includes a first active portion and a second active portion.

[0106] S920: preparing a first insulating layer on a side of the active layer facing away from the substrate.

[0107] S930: preparing a first gate on a side of the first insulating layer facing away from the substrate, wherein an orthographic projection of the first gate on the substrate partially overlaps an orthographic projection of the first active portion on the substrate.

[0108] S940: preparing a second insulating layer on a side of the first gate facing away from the substrate.

[0109] S950: preparing a second gate on a side of the second insulating layer facing away from the substrate, wherein an orthographic projection of the second gate on the substrate partially overlaps an orthographic projection of the second active portion on the substrate.

[0110] S960: preparing a sub-pixel on a side of the second gate facing away from the substrate.

[0111] Through this embodiment, the following can be prepared: Figure 2 In the display panel shown, since the first gate and the second gate are prepared by different processes and are located in different layers, the distance between adjacent gates is not limited by the equipment accuracy in the preparation process, and there is no risk of short circuit. Therefore, the distance between adjacent gates can be compressed to an almost extreme level compared to the prior art.

[0112] In one embodiment, a distance between orthographic projections of the first gate and the second gate on the substrate is less than or equal to 0.4 micrometers.

[0113] The present application also provides a method for preparing a display panel, the specific steps of which are as follows: Fig.10 As shown, Fig.10 This is a flow chart of a method for preparing a display panel in another embodiment of the present application. Fig.10 As shown, the specific steps of the method for preparing the display panel in this embodiment are as follows:

[0114] S1010: preparing an active layer on a substrate, wherein the active layer includes a first active portion and a second active portion.

[0115] S1020: preparing a first insulating layer on the side of the active layer facing away from the substrate.

[0116] S1030: preparing a first gate on a side of the first insulating layer facing away from the substrate, wherein an orthographic projection of the first gate on the substrate partially overlaps an orthographic projection of the first active portion on the substrate.

[0117] S1040: Prepare a second insulating layer on the side of the first gate facing away from the substrate.

[0118] S1050: drilling a hole in the second insulating layer, wherein the orthographic projection of the hole on the substrate covers the orthographic projection of the second active portion on the substrate.

[0119] S1060: Prepare a second gate in the hole.

[0120] S1070: Prepare a sub-pixel on the side of the second gate facing away from the substrate.

[0121] Through this embodiment, the following can be prepared: Figure 6 In the display panel shown, since the first gate and the second gate are prepared by different processes, the distance between adjacent gates is not limited by the equipment accuracy in the preparation process. Therefore, compared with the prior art, in this embodiment, the distance between adjacent gates can be compressed to a greater extent.

[0122] In one embodiment, a distance between orthographic projections of the first gate and the second gate on the substrate is less than or equal to 0.6 micrometers and greater than or equal to 0.4 micrometers.

[0123] The present application also provides a display device, comprising any one of the display panels described above.

[0124] The display device may be any device with a display function, for example, a mobile phone, a tablet computer, a laptop computer, a PDA, an in-vehicle electronic device, a wearable device, an ultra-mobile personal computer (UMPC), a netbook, or a personal digital assistant (PDA), etc. It may also be a non-mobile device such as a personal computer (PC), a television (TV), a teller machine, or an automated machine.

[0125] It should be noted that in the drawings of the present application document, the sizes of layers and regions may be exaggerated for clarity of illustration. It is also understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it is understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it may be the only layer between the two layers or two elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0126] In addition, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0127] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0128] The above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A display panel, characterized in that: include: substrate; at least one pixel circuit, the pixel circuit being located on one side of the substrate, and the pixel circuit comprising a plurality of transistors; as well as A plurality of sub-pixels, wherein the sub-pixels are electrically connected to the pixel circuit; Wherein, a distance between gate electrodes of at least some adjacent transistors in the same pixel circuit or in different pixel circuits and their orthographic projections on the substrate is less than or equal to 0.6 micrometers.

2. The display panel according to claim 1, characterized in that: At least some of the adjacent transistors include a first transistor and a second transistor, and gates of the first transistor and the second transistor are located at different layers; Preferably, a distance between the orthographic projections of the gate of the first transistor and the gate of the second transistor on the substrate is less than or equal to 0.4 micrometers; Preferably, the first transistor and the second transistor correspond to different pixel circuits respectively; Preferably, both the first transistor and the second transistor are driving transistors; Preferably, in a direction away from the substrate, the plurality of transistors in the pixel circuit are arranged in sequence; Preferably, the plurality of pixel circuits include a first pixel circuit and a second pixel circuit, the first transistor corresponds to the first pixel circuit, and the second transistor corresponds to the second pixel circuit; The second pixel circuit also includes at least one first other transistor except the second transistor, and the second pixel circuit also includes at least one second other transistor except the second transistor, and the gates of the first other transistor and the second other transistor are arranged in the same layer in a one-to-one correspondence.

3. The display panel according to claim 2, characterized in that: The plurality of transistors further include a third transistor located at a side of the second transistor away from the first transistor; a gate of the third transistor and a gate of the first transistor are at different layers; Preferably, the third transistor, the second transistor and the first transistor correspond to different pixel circuits respectively; Preferably, the display panel further comprises a first insulating layer and a second insulating layer, and in a direction away from the substrate, the gate of the first transistor, the first insulating layer, the gate of the second transistor, the second insulating layer, and the gate of the third transistor are stacked in sequence; Preferably, the display panel further comprises a plurality of sub-pixels, and the sub-pixels connected to the first transistor, the sub-pixels connected to the second transistor and the sub-pixels connected to the third transistor all emit different colors of light.

4. The display panel according to claim 2, characterized in that: The plurality of transistors further include a third transistor located on a side of the second transistor away from the first transistor; a gate of the third transistor and a gate of the first transistor are located on the same layer; Preferably, the third transistor, the second transistor and the first transistor correspond to different pixel circuits respectively; Preferably, the display panel further comprises a first insulating layer, and in a direction away from the substrate, the gate of the first transistor, the first insulating layer, and the gate of the second transistor are stacked in sequence; Preferably, the display panel further comprises a plurality of sub-pixels, and the sub-pixels connected to the first transistor, the sub-pixels connected to the second transistor and the sub-pixels connected to the third transistor all emit different colors of light.

5. The display panel according to any one of claims 1 to 4, characterized in that: At least part of the adjacent transistors include a fourth transistor and a fifth transistor, and the gates of the fourth transistor and the fifth transistor are arranged in the same layer; Preferably, the display panel further comprises a third insulating layer, wherein the third insulating layer is located on a side of the gate of the fourth transistor away from the substrate; the third insulating layer comprises an opening, and the gate of the fifth transistor is located in the opening; Preferably, the fourth transistor and the fifth transistor correspond to different pixel circuits respectively; Preferably, the fourth transistor and the fifth transistor are both driving transistors; Preferably, a distance between the gate electrodes of the fourth transistor and the fifth transistor and the orthographic projection of the substrate is less than or equal to 0.6 micrometers and greater than or equal to 0.4 micrometers; Preferably, in a direction away from the substrate, the plurality of transistors in the pixel circuit are arranged in sequence; Preferably, the plurality of pixel circuits include a fourth pixel circuit and a fifth pixel circuit, the fourth transistor corresponds to the fourth pixel circuit, and the fifth transistor corresponds to the fifth pixel circuit; the fourth pixel circuit also includes at least one fourth other transistor besides the fourth transistor, and the fifth pixel circuit also includes at least one fifth other transistor besides the fifth transistor, and the gates of the fourth other transistor and the fifth other transistor are arranged in the same layer in a one-to-one manner.

6. The display panel according to claim 5, characterized in that: The plurality of transistors further include a sixth transistor located on a side of the fifth transistor away from the fourth transistor; a gate of the sixth transistor and a gate of the fourth transistor are located on the same layer; Preferably, the gate of the sixth transistor and the gate of the fifth transistor are located in the same layer.

7. The display panel according to claim 1, characterized in that: The pixel circuit includes a driving transistor; the gates of the driving transistors in the pixel circuits connected to the sub-pixels of the same color are arranged in the same layer.

8. A method for preparing a display panel, characterized in that: include: preparing an active layer on a substrate, wherein the active layer includes a first active portion and a second active portion; Prepare a first insulating layer on the side of the active layer facing away from the substrate; A first gate is formed on a side of the first insulating layer facing away from the substrate, wherein an orthographic projection of the first gate on the substrate partially overlaps with an orthographic projection of the first active portion on the substrate; forming a second insulating layer on a side of the first gate away from the substrate; Opening a hole in the second insulating layer, wherein the orthographic projection of the hole on the substrate covers the orthographic projection of the second active portion on the substrate; preparing a second grid in the hole; A sub-pixel is prepared on a side of the second gate facing away from the substrate.

9. A method for preparing a display panel, characterized in that: include: preparing an active layer on a substrate, wherein the active layer includes a first active portion and a second active portion; Prepare a first insulating layer on the side of the active layer facing away from the substrate; A first gate is formed on a side of the first insulating layer facing away from the substrate, wherein an orthographic projection of the first gate on the substrate partially overlaps with an orthographic projection of the first active portion on the substrate; forming a second insulating layer on a side of the first gate away from the substrate; A second gate is formed on a side of the second insulating layer facing away from the substrate, wherein an orthographic projection of the second gate on the substrate partially overlaps with an orthographic projection of the second active portion on the substrate; A sub-pixel is prepared on a side of the second gate facing away from the substrate.

10. A display device, characterized in that: A display panel comprising any one of claims 1-7.

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