Display device

Abstract

A display device includes: a substrate including an emission area and a sensing area; a light emitting device corresponding to the emission region on the substrate; and a light receiving device corresponding to the sensing area on the substrate. The light emitting device includes a pixel electrode, a lower emission layer on the pixel electrode, an upper emission layer on the lower emission layer, and a portion of a counter electrode on the upper emission layer. The light receiving device includes a sensing electrode, an active layer and a sub-charge generation layer on the sensing electrode, and another portion of the counter electrode on the active layer and the sub-charge generation layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0151937 filed in the Korean Intellectual Property Office on November 6, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments of the present disclosure described herein relate to the structure of a display device. Background Art

[0004] Generally, a display apparatus has a light emitting device (eg, an organic light emitting diode) and a thin film transistor formed on a substrate, and operates by causing the light emitting device to emit light (eg, display an image).

[0005] For example, each pixel of the display device has a light-emitting device (e.g., an organic light-emitting diode) having an intermediate layer, the intermediate layer including an emission layer between a pixel electrode and a counter electrode. The display device usually controls the light emission of each pixel and / or controls the degree of light emission by a thin film transistor electrically connected to the pixel electrode. Some layers included in the intermediate layer region (e.g., the intermediate layer) of the light-emitting device can be provided in a plurality of light-emitting devices. Summary of the invention

[0006] Aspects according to one or more embodiments of the present disclosure are directed to a display device with improved detection performance while achieving an image with good or suitable quality. However, this is merely an example, and the scope of the present disclosure is not limited.

[0007] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0008] According to one or more embodiments, a display device includes: a substrate including an emission area and a sensing area; a light-emitting device arranged on the substrate to correspond to the emission area; and a light-receiving device arranged on the substrate to correspond to the sensing area, wherein the light-emitting device includes a pixel electrode, a lower emission layer arranged on the pixel electrode, an upper emission layer arranged on the lower emission layer, and a portion of a counter electrode arranged on the upper emission layer, and the light-receiving device includes a sensing electrode, an active layer and a sub-charge generating layer arranged on the sensing electrode, and another portion of the counter electrode arranged on the active layer and the sub-charge generating layer.

[0009] According to one or more embodiments, the sub-charge generation layer may be disposed on the active layer.

[0010] According to one or more embodiments, the lower emission layer may be arranged on substantially the same layer as the active layer (for example, may be a part of the same layer forming the active layer), and the upper emission layer may be arranged on substantially the same layer as the sub-charge generation layer (for example, may be a part of the same layer forming the sub-charge generation layer).

[0011] According to one or more embodiments, the active layer may be disposed on the sub-charge generation layer.

[0012] According to one or more embodiments, the lower emission layer may be arranged on substantially the same layer as the sub-charge generation layer (for example, may be a part of the same layer that forms the sub-charge generation layer), and the upper emission layer may be arranged on substantially the same layer as the active layer (for example, may be a part of the same layer that forms the active layer).

[0013] According to one or more embodiments, the sub-charge generation layer may include a p-type or species sub-charge generation layer and an n-type or species sub-charge (e.g., n-sub-charge) generation layer arranged on the p-type or species sub-charge (e.g., p-sub-charge) generation layer.

[0014] According to one or more embodiments, the lower emission layer and the upper emission layer may be patterned for each light emitting device, and the active layer and the sub-charge generation layer may be patterned for each light receiving device.

[0015] According to one or more embodiments, the display device may further include a main charge generation layer between the lower emission layer and the upper emission layer and between the active layer and the sub charge generation layer.

[0016] According to one or more embodiments, the main charge generation layer may include an n-type or species main charge (e.g., n main charge) generation layer and a p-type or species (e.g., p charge) main charge generation layer arranged on the n-type or species main charge generation layer.

[0017] According to one or more embodiments, the n-type or p-type main charge generation layer may be integrally formed as a single body on the entire surface of the substrate, and the p-type or p-type main charge generation layer may be patterned for each of the light emitting device and the light receiving device.

[0018] According to one or more embodiments, the display device may further include a first hole transport layer between the pixel electrode and the lower emission layer and between the sensing electrode and the active layer, wherein the first hole transport layer may be integrally formed as a monomer on the entire surface of the substrate.

[0019] According to one or more embodiments, the display device may further include a lower auxiliary layer between the first hole transport layer and the lower emission layer and between the first hole transport layer and the active layer, wherein the lower auxiliary layer may be patterned for each of the light emitting device and the light receiving device.

[0020] According to one or more embodiments, the display device may further include a second hole transport layer between the main charge generation layer and the upper emission layer and between the main charge generation layer and the sub-charge generation layer, wherein the second hole transport layer may be patterned for each of the light-emitting device and the light-receiving device.

[0021] According to one or more embodiments, the display device may further include an upper auxiliary layer between the second hole transport layer and the upper emission layer and between the second hole transport layer and the sub-charge generation layer, wherein the upper auxiliary layer may be patterned for each of the light emitting device and the light receiving device.

[0022] According to one or more embodiments, the display device may further include a buffer layer and an electron transport layer between the upper emission layer and the counter electrode and between the sub-charge generation layer and the counter electrode, wherein the buffer layer and the electron transport layer may be integrally formed as a monomer on the entire surface of the substrate.

[0023] According to one or more embodiments, the active layer may include a p-type or kind of semiconductor compound (eg, p-semiconductor compound) and an n-type or kind of semiconductor compound (eg, n-semiconductor compound).

[0024] According to one or more embodiments, the p-type or p-type semiconductor compound may include or be a compound represented by Formula 1:

[0025] Formula 1

[0026]

[0027] In formula 1,

[0028] Ar 111 and Ar 112 may be independently unsubstituted or substituted with at least one R 10a Substituted C 6 -C 30 Arylene is either unsubstituted or substituted with at least one R 10a Substituted C 3 -C 30 Heteroarylene,

[0029] X111 It may be (for example, selected from) -Se-, -Te-, -S(=O)-, -S(=O)- 2 -、-N(Q 111 )-、-B(Q 111 )-、-C(Q 111 )(Q 112 )-、-Si(Q 111 )(Q 112 )-and / or-Ge(Q 111 )(Q 112 )-,

[0030] X 112 and L 111 Each may be (for example, selected from) -O-, -S-, -Se-, -Te-, -S(=O)-, -S(=O)- 2 -、-N(Q 111 )-、-B(Q 111 )-、-C(Q 111 )(Q 112 )-、-Si(Q 111 )(Q 112 )-、-Ge(Q 111 )(Q 112 )-、-(C(Q 111 )=C(Q 112 ))-and / or-(C(Q 111 )=N)-,

[0031] When L 111 is (for example, selected from) -N(Q 111 )-、-B(Q 111 )-、-C(Q 111 )(Q 112 )-、-Si(Q 111 )(Q 112 )-、-Ge(Q 111 )(Q 112 )-、-(C(Q 111 )=C(Q 112 ))-and / or-(C(Q 111 )=N)-, then L 111 Optionally with Ar 111 or Ar 112 connected to form (or provide) a fused ring,

[0032] Z 111 It may be a molecule having at least one functional group selected from C═O, C═S, C═Se and C═Te and being unsubstituted or substituted by at least one R 10a Substituted C 6 -C30 A carbocyclic group, or a group having at least one functional group selected from C=O, C=S, C=Se and C=Te and being unsubstituted or substituted by at least one R 10a Substituted C 1 -C 30 Heterocyclic group,

[0033] R 111 and R 112 can be independently hydrogen, deuterium, halogen, cyano, nitro, hydroxyl, unsubstituted or substituted with at least one R 10a Substituted C 1 -C 30 Alkyl, unsubstituted or substituted with at least one R 10a Substituted C 1 -C 30 Alkoxy, unsubstituted or substituted with at least one R 10a Substituted C 6 -C 30 Aryl, unsubstituted or substituted with at least one R 10a Substituted C 3 -C 30 Heteroaryl, unsubstituted or substituted with at least one R 10a Substituted C 2 -C 30 acyl or a combination thereof (eg, any suitable combination thereof), R 10a Can be (e.g., selected from):

[0034] deuterium (-D), -F, -Cl, -Br, -I, hydroxyl, cyano, nitro, or a combination thereof (e.g., any suitable combination thereof);

[0035] C 1 -C 60 Alkyl, C 2 -C 60 Alkenyl, C 2 -C 60 Alkynyl and / or C 1 -C 60 Alkoxy, unsubstituted or deuterated, -F, -Cl, -Br, -I, hydroxy, cyano, nitro, C 3 -C 60 Carbocyclic group, C 1 -C 60 Heterocyclic group, C 6 -C 60 Aryloxy, C 6 -C 60 Arylthio, C 1 -C 60 Heteroaryloxy, C 1 -C 60Heteroarylthio, -Si(Q 11 )(Q 12 )(Q 13 )、-N(Q 11 )(Q 12 )、-B(Q 11 )(Q 12 )、-C(=O)(Q 11 )、-S(=O) 2 (Q 11 )、-P(=O)(Q 11 )(Q 12 ) or a combination thereof (e.g., any suitable combination thereof);

[0036] C 3 -C 60 Carbocyclic group, C 1 -C 60 Heterocyclic group, C 6 -C 60 Aryloxy, C 6 -C 60 Arylthio, C 1 -C 60 Heteroaryloxy and / or C 1 -C 60 Heteroarylthio, unsubstituted or deuterated, -F, -Cl, -Br, -I, hydroxy, cyano, nitro, C 1 -C 60 Alkyl, C 2 -C 60 Alkenyl, C 2 -C 60 Alkynyl, C 1 -C 60 Alkoxy, C 3 -C 60 Carbocyclic group, C 1 -C 60 Heterocyclic group, C 6 -C 60 Aryloxy, C 6 -C 60 Arylthio, C 1 -C 60 Heteroaryloxy, C 1 -C 60 Heteroarylthio, -Si(Q 21 )(Q 22 )(Q 23 )、-N(Q 21 )(Q 22 )、-B(Q 21 )(Q 22 )、-C(=O)(Q 21 )、-S(=O) 2(Q 21 )、-P(=O)(Q 21 )(Q 22 ) or any combination thereof (e.g., any suitable combination thereof); or

[0037] -Si(Q 31 )(Q 32 )(Q 33 )、-N(Q 31 )(Q 32 )、-B(Q 31 )(Q 32 )、-C(=O)(Q 31 )、-S(=O) 2 (Q 31 )、-P(=O)(Q 31 )(Q 32 ) or a combination thereof (e.g., any suitable combination thereof),

[0038] Among them, Q 11 To Q 13 , Q 21 To Q 23 , Q 31 To Q 33 , Q 111 , and Q 112 can be each independently (e.g., selected from): hydrogen; deuterium; -F; -Cl; -Br; -I; hydroxyl; cyano; nitro; C 1 -C 60 Alkyl; C 2 -C 60 Alkenyl; C 2 -C 60 Alkynyl; C 1 -C 60 Alkoxy; and C 3 -C 60 Carboxyl, C 1 -C 60 Heterocyclic group, C 7 -C 60 Arylalkyl or C 2 -C 60 Heteroaralkyl, unsubstituted or deuterated, -F, cyano, C 1 -C 60 Alkyl, C 1 -C 60 The present invention is substituted with an alkoxy group, a phenyl group, a biphenyl group, or a combination thereof (eg, any suitable combination thereof).

[0039] According to one or more embodiments, Z of Formula 1 111It can be represented by one of Formulas 111A to 111F (for example, selected from Formulas 111A to 111F):

[0040]

[0041] In Formulas 111A to 111F,

[0042] Z 112 To Z 114 can be O, S, Se or Te,

[0043] X 113 Can be N or C (Q 113 ),

[0044] X 114 and X 115 can be independently O, S, Se, Te, Si (Q 111 )(Q 112 ) or Ge(Q 111 )(Q 112 ),

[0045] n111a to n111c can each be an integer from 0 to 3,

[0046] R 113 To R 117 can be independently hydrogen, deuterium, halogen, cyano, nitro, hydroxyl, unsubstituted or substituted with at least one R 10a Substituted C1-C30 alkyl, unsubstituted or replaced by at least one R 10a Substituted C 6 -C 30 Aryl, unsubstituted or substituted with at least one R 10a Substituted C 3 -C 30 heteroaryl or a combination thereof (e.g., any suitable combination thereof), and

[0047] Q 111 To Q 113 The definition of Q can be compared with the previously described 111 The same limitations apply.

[0048] According to one or more embodiments, the n-type or n-type semiconductor compound may include or be represented by (eg, selected from) Formula 2 or Formula 3:

[0049] Formula 2

[0050]

[0051] Formula 3

[0052]

[0053] Among them, in formula 2,

[0054] X 111 and X 112 can be independently O or N(R 119 ),and

[0055] R 111 To R 119 can be independently hydrogen, deuterium, halogen, cyano, nitro, hydroxyl, unsubstituted or substituted with at least one R 10a Substituted C 1 -C 30 Alkyl, unsubstituted or substituted with at least one R 10a Substituted C 6 -C 30 Aryl, unsubstituted or substituted with at least one R 10a Substituted C 3 -C 30 heteroaryl or a combination thereof (eg, any suitable combination thereof),

[0056] Among them, in formula 3,

[0057] X 121 and X 122 can be independently O or N(R 125 ),and

[0058] R 121 To R 125 can be independently hydrogen, deuterium, halogen, cyano, nitro, hydroxyl, unsubstituted or substituted with at least one R 10a Substituted C 1 -C 30 Alkyl, unsubstituted or substituted with at least one R 10a Substituted C 6 -C 30 Aryl, unsubstituted or substituted with at least one R 10a Substituted C 3 -C 30 heteroaryl or a combination thereof (eg, any suitable combination thereof),

[0059] Among them, in formula 2 and formula 3,

[0060] R 10a Can be (e.g., selected from):

[0061] deuterium (-D), -F, -Cl, -Br, -I, hydroxyl, cyano, nitro, or a combination thereof (e.g., any suitable combination thereof);

[0062] C 1-C 60 Alkyl, C 2 -C 60 Alkenyl, C 2 -C 60 Alkynyl and / or C 1 -C 60 Alkoxy, unsubstituted or deuterated, -F, -Cl, -Br, -I, hydroxy, cyano, nitro, C 3 -C 60 Carbocyclic group, C 1 -C 60 Heterocyclic group, C 6 -C 60 Aryloxy, C 6 -C 60 Arylthio, C 1 -C 60 Heteroaryloxy, C 1 -C 60 Heteroarylthio, -Si(Q 11 )(Q 12 )(Q 13 )、-N(Q 11 )(Q 12 )、-B(Q 11 )(Q 12 )、-C(=O)(Q 11 )、-S(=O) 2 (Q 11 )、-P(=O)(Q 11 )(Q 12 ) or a combination thereof (e.g., any suitable combination thereof);

[0063] C 3 -C 60 Carbocyclic group, C 1 -C 60 Heterocyclic group, C 6 -C 60 Aryloxy, C 6 -C 60 Arylthio, C 1 -C 60 Heteroaryloxy and / or C 1 -C 60 Heteroarylthio, unsubstituted or deuterated, -F, -Cl, -Br, -I, hydroxy, cyano, nitro, C 1 -C 60 Alkyl, C 2 -C 60 Alkenyl, C 2 -C 60 Alkynyl, C 1 -C 60 Alkoxy, C 3 -C60 Carbocyclic group, C 1 -C 60 Heterocyclic group, C 6 -C 60 Aryloxy, C 6 -C 60 Arylthio, C 1 -C 60 Heteroaryloxy, C 1 -C 60 Heteroarylthio, -Si(Q 21 )(Q 22 )(Q 23 )、-N(Q 21 )(Q 22 )、-B(Q 21 )(Q 22 )、-C(=O)(Q 21 )、-S(=O) 2 (Q 21 )、-P(=O)(Q 21 )(Q 22 ) or any combination thereof (e.g., any suitable combination thereof); or

[0064] -Si(Q 31 )(Q 32 )(Q 33 )、-N(Q 31 )(Q 32 )、-B(Q 31 )(Q 32 )、-C(=O)(Q 31 )、-S(=O) 2 (Q 31 )、-P(=O)(Q 31 )(Q 32 ) or a combination thereof (e.g., any suitable combination thereof),

[0065] Where Q 11 To Q 13 , Q 21 To Q 23 , Q 31 To Q 33 can each independently be (e.g., selected from): hydrogen; deuterium; -F; -Cl; -Br; -I; hydroxyl; cyano; nitro; C 1 -C 60 Alkyl; C 2 -C 60 Alkenyl; C 2 -C 60 Alkynyl; C 1 -C 60 Alkoxy; and C 3-C 60 Carboxylic acid group, C 1 -C 60 Heterocyclic group, C 7 -C 60 Arylalkyl and / or C 2 -C 60 Heteroaralkyl, unsubstituted or deuterated, -F, cyano, C 1 -C 60 Alkyl, C 1 -C 60 The present invention is substituted with an alkoxy group, a phenyl group, a biphenyl group, or a combination thereof (eg, any suitable combination thereof).

[0066] According to one or more embodiments, the n-type or n-type semiconductor compound may include or be one of (eg, selected from) the following compounds:

[0067]

[0068]

[0069] BRIEF DESCRIPTION OF THE DRAWINGS

[0070] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0071] Figure 1 is a plan view schematically showing a portion of a display device according to one or more embodiments;

[0072] Figure 2 is a schematic cross-sectional view of a display device according to one or more embodiments;

[0073] Figure 3 is an equivalent circuit diagram of a pixel circuit electrically connected to a light emitting device and a sensor circuit electrically connected to a light receiving device in a display device according to one or more embodiments;

[0074] Figure 4 is a plan view schematically showing a portion of a display device according to one or more embodiments;

[0075] Figure 5 is a cross-sectional view schematically showing a portion of a display device according to one or more embodiments;

[0076] Figure 6 is a conceptual diagram schematically illustrating a portion of a display device according to one or more embodiments;

[0077] Figure 7is a graph showing comparison of external quantum efficiency (EQE) according to wavelength between a display device according to a comparative example and a display device according to an example;

[0078] Figure 8 is a cross-sectional view schematically showing a portion of a display device according to one or more embodiments; and

[0079] Fig. 9 is a conceptual diagram schematically illustrating a portion of a display device according to one or more embodiments. DETAILED DESCRIPTION

[0080] Now will refer to embodiment in more detail, the example of embodiment is shown in the accompanying drawings, wherein the same reference numerals always refer to the same elements, and repeated description may not be provided. In this regard, the present embodiment may have different forms, and should not be construed as being limited to the description set forth herein. Therefore, the embodiments are described herein only by reference to the accompanying drawings to explain aspects of this specification. As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. Throughout the disclosure, expression "at least one of a, b and c" means only a, only b, only c, a and b both (e.g., a and b simultaneously), a and c both (e.g., a and c simultaneously), b and c both (e.g., b and c simultaneously), a, b and c all or its variant.

[0081] In this specification, “including A or B”, “A and / or B”, etc. means A or B, or A and B.

[0082] As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation rather than terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​recognized by those of ordinary skill in the art. Taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), as used herein, "substantially" includes the stated value and means within an acceptable deviation range for a particular value determined by those of ordinary skill in the art. For example, "substantially" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0083] In addition, any numerical range described herein is intended to include all sub-ranges of the same numerical precision included in the range. For example, the range of "1.0 to 10.0" is intended to include all sub-ranges between the minimum value 1.0 and the maximum value 10.0 (and including the minimum value 1.0 and the maximum value 10.0), that is, having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limit described herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit described in this specification is intended to include all higher numerical limits contained therein. Therefore, the applicant reserves the right to modify this specification (including claims) to explicitly describe any sub-ranges included in the range explicitly listed herein.

[0084] Furthermore, the use of “may” when describing embodiments of the present disclosure refers to “one or more embodiments of the present disclosure”.

[0085] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0086] In the present disclosure, "not including one or any 'component (ingredient)'", "excluding one or any 'component (ingredient)'", and / or "no 'component (ingredient)'" etc. means that the "component (ingredient)" is not added, selected or utilized as a component (ingredient) in the composition / structure, but due to other impurities and / or external factors, the "component (ingredient)" may still be contained in less than an appropriate amount.

[0087] In the present disclosure, when a point, a plurality of points or a point particle is spherical, "diameter" means the particle diameter or the average particle diameter, and when the particle is non-spherical, "diameter" means the major axis length or the average major axis length. The diameter of the particle can be measured using a scanning electron microscope or a particle size analyzer. As a particle size analyzer, for example, a HORIBA, LA-950 laser particle size analyzer can be used. When the size of the particle is measured using a particle size analyzer, the average particle diameter is referred to as D50. D50 refers to the average diameter of the particles corresponding to 50 vol% of the cumulative volume in a particle size distribution (e.g., cumulative distribution), and refers to the value of the particle size corresponding to 50% starting from the smallest particle when the total number of particles is 100% in a distribution curve accumulated in the order of the smallest particle size to the largest particle size.

[0088] Since the present specification allows one or more suitable variations and many embodiments, specific embodiments will be shown in the drawings and described in more detail in the written specification. The effects and features of the present disclosure and methods for achieving them will be explained with reference to the embodiments described in more detail with reference to the drawings. However, the present disclosure is not limited to the following embodiments and may be embodied in one or more suitable forms.

[0089] Hereinafter, the embodiments will be described in more detail with reference to the accompanying drawings. When describing the embodiments with reference to the accompanying drawings, the same or corresponding elements are denoted by the same reference numerals.

[0090] It will be understood that although the terms "first" and / or "second", etc. may be used herein to describe one or more suitable elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0091] Unless the context clearly indicates otherwise, the singular forms used herein are intended to include the plural forms as well.

[0092] It will also be understood that the terms “comprises” and / or “comprising” used herein specify the presence of stated features or elements, but do not exclude the presence or addition of one or more other features or elements.

[0093] It will also be understood that when a layer, region or element is referred to as being "on" another layer, region or element, the layer, region or element may be directly or indirectly on the other layer, region or element. For example, intervening layers, regions or elements may exist between the layer, region or element and the other layer, region or element.

[0094] In addition, the size of the elements in the drawings may be exaggerated or reduced for convenience of explanation. For example, since the size and thickness of the elements in the drawings are arbitrarily shown for convenience of explanation, the present disclosure is not limited thereto.

[0095] When a specific embodiment can be implemented differently, a specific process order can be performed differently from the order described. For example, two processes described in succession can be performed substantially simultaneously or in the reverse order of the order described.

[0096] It will also be understood that when layers, regions, or components are referred to as being connected to each other, they may be directly connected to each other, or indirectly connected to each other with intervening layers, regions, or components therebetween. For example, when layers, regions, or elements are referred to as being electrically connected to each other, they may be directly electrically connected to each other, or indirectly electrically connected to each other through intervening layers, regions, or elements therebetween.

[0097] Figure 1 is a plan view schematically showing a part of the display device 1 according to one or more embodiments.

[0098] Reference Figure 1 , the display device 1 may include a display area DA in which a plurality of pixels PX are arranged and a peripheral area PA outside the display area DA. For example, the peripheral area PA may completely surround the display area DA. It is understood that the substrate (see FIG. 1 ) included in the display device 1 Figure 5 The substrate 100 has a display area DA and a peripheral area PA.

[0099] Each of the pixels PX of the display device 1 refers to the smallest unit for displaying an image, and the display device 1 can display a desired or suitable image by a combination of pixels PX. For example, the pixel PX can be configured to emit a beam of light (e.g., light) of a specific color, and the display device 1 can display a desired or suitable image by a beam emitted from the pixel PX. For example, each of the pixels PX can be configured to emit red light, green light, or blue light. Each of the pixels PX can include a light emitting device, such as an organic light emitting diode. The pixel PX can be connected to a pixel circuit including a thin film transistor (TFT) and a storage capacitor.

[0100] like Figure 1 As shown in , the display area DA may have a polygonal shape such as a rectangular shape. For example, the display area DA may have a rectangular shape in which the horizontal length is greater than the vertical length, a rectangular shape in which the horizontal length (e.g., length) is shorter than the vertical length (e.g., width), or a square shape. In one or more embodiments, the display area DA may have other shapes, such as an elliptical shape or a circular shape.

[0101] The peripheral area PA may be a non-display area in which the pixels PX are not arranged. A driver configured to provide an electrical signal and / or power to the pixels PX, etc. may be arranged in the peripheral area PA. A plurality of pads may be arranged in the peripheral area PA, and one or more suitable electronic devices or printed circuit boards may be electrically connected to the plurality of pads. The plurality of pads may be separated from each other in the peripheral area PA and may be electrically connected to a printed circuit board or an integrated circuit device.

[0102] Figure 2 is a schematic cross-sectional view of a display device 1 according to one or more embodiments.

[0103] Reference Figure 2 The display device 1 according to one or more embodiments may further include an optical sensor and a plurality of pixels (see Figure 1 Each of the pixels (see Figure 1The pixel PX) may include at least one of a first light emitting device ED1, a second light emitting device ED2, and a third light emitting device ED3, and the optical sensor may include a first light receiving device PD1. The first light emitting device ED1, the second light emitting device ED2, and the third light emitting device ED3 may be configured to emit different light beams (e.g., light) outwardly. For example, the first light emitting device ED1 may be configured to emit green light outwardly, the second light emitting device ED2 may be configured to emit red light outwardly, and the third light emitting device ED3 may be configured to emit blue light outwardly.

[0104] like Figure 2 As shown in , the display device 1 may have a function of sensing an object (e.g., a fingerprint of a finger F) in contact with the cover window CW. Among the light beams emitted from at least one of the first light emitting device ED1, the second light emitting device ED2, and the third light emitting device ED3, at least a portion of the reflected light reflected from the fingerprint of the user may be re-incident on the first light receiving device PD1, and thus, the first light receiving device PD1 may be configured to detect the reflected light. For example, the green light emitted by the first light emitting device ED1 may be reflected from the object in contact with the cover window CW and may be re-incident on the first light receiving device PD1, and thus, the first light receiving device PD1 may be configured to detect the re-incident green light.

[0105] Figure 3 is an equivalent circuit diagram of a pixel circuit electrically connected to a light emitting device and a sensor circuit electrically connected to a light receiving device in a display device according to one or more embodiments.

[0106] Reference Figure 3 , pixels (see Figure 1 The pixel PX) may include a light emitting device ED and a pixel circuit PC, the pixel circuit PC is configured to control the amount of light emitted from the light emitting device ED. The optical sensor may include a light receiving device PD and a sensor circuit PC', the sensor circuit PC' is configured to control the amount of light received by the light receiving device PD.

[0107] The pixel circuit PC may be connected to a scan enable line GIL, a scan control line GCL, a first scan write line GWL1, a second scan write line GWL2, an emission line EML, and a data line DL. In one or more embodiments, the pixel circuit PC may be connected to a first drive voltage line VDDL to which a first drive voltage is applied, a second drive voltage line VSSL to which a second drive voltage is applied, a first initialization voltage line to which a first initialization voltage Vint1 is applied, and a second initialization voltage line to which a second initialization voltage Vint2 is applied.

[0108] The sensor circuit PC' may be connected to the first scan write line GWL1, the reset line RSTL, and the fingerprint detection line FRL. In one or more embodiments, the sensor circuit PC' may be connected to the second driving voltage line VSSL to which the second driving voltage is applied, the reset voltage line to which the reset voltage Vrst is applied, and the first initialization voltage line to which the first initialization voltage Vint1 is applied.

[0109] The pixel circuit PC may include a plurality of transistors and at least one capacitor, and may be connected to the light emitting device ED. The plurality of transistors may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. Among the plurality of transistors, the first transistor T1 may be a driving transistor, and the second transistor T2 to the seventh transistor T7 may be a switching transistor, and the second transistor T2 to the seventh transistor T7 are configured to be turned on or off in response to a scan signal applied to the gate electrode thereof.

[0110] The first transistor T1 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the first transistor T1 may be connected to the first electrode of the third transistor T3 and the storage capacitor C ST The first electrode of the first transistor T1 may be connected to the second electrode of the second transistor T2 and the second electrode of the fifth transistor T5. The second electrode of the first transistor may be connected to the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6.

[0111] The light emitting device ED may be configured to emit light according to a driving current. The amount of light emitted from the light emitting device ED may be proportional to the driving current. The light emitting device ED may be an organic light emitting diode including a pixel electrode, a counter electrode, and an organic emission layer between the pixel electrode and the counter electrode. In one or more embodiments, the light emitting device ED may be an inorganic light emitting diode including an inorganic emission layer between the pixel electrode and the counter electrode, or may be a quantum dot light emitting diode including a quantum dot emission layer between the pixel electrode and the counter electrode. In addition, the light emitting device ED may be a micro light emitting diode. The pixel electrode of the light emitting device ED may be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the counter electrode may be connected to the second driving voltage line VSSL.

[0112] The second transistor T2 may be configured to be turned on in response to a scan signal of the first scan write line GWL1 and connect the first electrode of the first transistor T1 to the data line DL. The gate electrode of the second transistor T2 may be connected to the first scan write line GWL1, the first electrode of the second transistor T2 may be connected to the data line DL, and the second electrode of the second transistor T2 may be connected to the first electrode of the first transistor T1.

[0113] The third transistor T3 may be configured to be turned on in response to a scan signal of the scan control line GCL, and to connect the gate electrode of the first transistor T1 to the second electrode of the first transistor T1. For example, when the third transistor T3 is turned on, the gate electrode of the first transistor T1 is connected to the second electrode of the first transistor T1, and thus, the first transistor T1 may function as a diode. The gate electrode of the third transistor T3 may be connected to the scan control line GCL, the second electrode of the third transistor T3 may be connected to the second electrode of the first transistor T1, and the first electrode of the third transistor T3 may be connected to the gate electrode of the first transistor T1.

[0114] The fourth transistor T4 may be configured to be turned on in response to a scan signal of the scan enable line GIL and to connect the gate electrode of the first transistor T1 to the second initialization voltage line. In this case, the gate electrode of the first transistor T1 may be discharged to the second initialization voltage Vint2 of the second initialization voltage line. The gate electrode of the fourth transistor T4 may be connected to the scan enable line GIL, the first electrode of the fourth transistor T4 may be connected to the second initialization voltage line, and the second electrode of the fourth transistor T4 may be connected to the gate electrode of the first transistor T1.

[0115] The fifth transistor T5 may be configured to be turned on in response to an emission signal of the emission line EML and connect the first electrode of the first transistor T1 to the first driving voltage line VDDL. A gate electrode of the fifth transistor T5 may be connected to the emission line EML, a first electrode of the fifth transistor T5 may be connected to the first driving voltage line VDDL, and a second electrode of the fifth transistor T5 may be connected to the first electrode of the first transistor T1.

[0116] The sixth transistor T6 may be configured to be turned on in response to an emission signal of the emission line EML, and to connect the second electrode of the first transistor T1 to the pixel electrode of the light emitting device ED. The gate electrode of the sixth transistor T6 may be connected to the emission line EML, the first electrode of the sixth transistor T6 may be connected to the second electrode of the first transistor T1, and the second electrode of the sixth transistor T6 may be connected to the pixel electrode of the light emitting device ED. When both the fifth transistor T5 and the sixth transistor T6 (e.g., the fifth transistor T5 and the sixth transistor T6 are turned on at the same time), a driving current may be supplied to the light emitting device ED.

[0117] The seventh transistor T7 may be configured to be turned on in response to the scan signal of the second scan write line GWL2, and to connect the first initialization voltage line to the pixel electrode of the light emitting device ED. In this case, the pixel electrode of the light emitting device ED may be discharged to the first initialization voltage Vint1. The gate electrode of the seventh transistor T7 may be connected to the second scan write line GWL2, the first electrode of the seventh transistor T7 may be connected to the first initialization voltage line, and the second electrode of the seventh transistor T7 may be connected to the pixel electrode of the light emitting device ED.

[0118] Storage capacitor C ST The storage capacitor C may be between the gate electrode of the first transistor T1 and the first driving voltage line VDDL. ST One electrode of the capacitor C can be connected to the gate electrode of the first transistor T1, and the storage capacitor C ST The other electrode of the storage capacitor C may be connected to the first driving voltage line VDDL. ST A potential difference between the gate electrode of the first transistor T1 and the first driving voltage line VDDL may be maintained.

[0119] Boost capacitor C BOOST The boost capacitor C may be between the gate electrode of the second transistor T2 and the gate electrode of the first transistor T1. BOOST One electrode of the capacitor C may be connected to the first scan write line GWL1 connected to the gate electrode of the second transistor T2, and the boost capacitor C BOOST The other electrode of the first transistor T1 can be connected to the gate electrode of the first transistor T1 and the storage capacitor C ST One electrode of the boost capacitor C BOOST It can be a boost capacitor. When the signal of the first scan write line GWL1 is a voltage that turns off the second transistor T2, the boost capacitor C BOOST The voltage of the node may be increased and the voltage for displaying black (black voltage) may be decreased.

[0120] The sensor circuit PC' may include a plurality of transistors and may be connected to the light receiving device PD. The transistor may include an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10. Among the plurality of transistors, the eighth transistor T8 may be a driving transistor, and the ninth transistor T9 and the tenth transistor T10 may be switching transistors, which are configured to be turned on or off in response to a reset signal and a scan signal applied to their gate electrodes.

[0121] When a plurality of light emitting devices ED and a plurality of light receiving devices PD are arranged in a single display device (see Figure 1When the light receiving device PD is driven, the voltage line or signal line configured to drive the light emitting device ED can be commonly used. For example, by minimizing or reducing the voltage line or signal line configured to drive the display device (see Figure 1 The additional arrangement of the voltage line or signal line of the light receiving device PD in the display device 1) can ensure that the display device (see Figure 1 The resolution of the display device 1) and the peripheral area can be minimized or reduced (see Figure 1 For example, with pixels (see Figure 1 The signal line connected to the gate electrode of the second transistor T2 in the pixel PX of the optical sensor can be commonly used with the signal line connected to the gate electrode of the tenth transistor T10 in the optical sensor. For example, the gate electrode of the second transistor T2 and the gate electrode of the tenth transistor T10 can be connected to the first scan write line GWL1. As another example, the second drive voltage line VSSL can be a common voltage line connected to the counter electrode of the light emitting device ED and the counter electrode of the light receiving device PD. As another example, the first initialization voltage line configured to apply the first initialization voltage Vint1 can be a common voltage line connected to the second electrode of the eighth transistor T8 and the second electrode of the seventh transistor T7 in the optical sensor.

[0122] The light receiving device PD may be a light receiving diode including a sensing electrode, a counter electrode, and a photoelectric conversion layer between the sensing electrode and the counter electrode. The light receiving device PD may convert light incident from the outside into an electrical signal. The light receiving device PD may be a light receiving diode or a phototransistor including a PN type or type or a PIN type or type inorganic material. In one or more embodiments, the light receiving device PD may be an organic light receiving diode including an electron donor material that generates donor ions and an electron acceptor material that generates acceptor ions.

[0123] When the light receiving device PD is exposed to external light, photocharges may be generated, and the generated photocharges may be accumulated on the sensing electrode of the light receiving device PD. In this case, the voltage of the node electrically connected to the sensing electrode may increase. When the light receiving device PD and the fingerprint detection line FRL are connected to each other according to the conduction of the eighth transistor T8 and the tenth transistor T10, a current may flow through the fingerprint detection line FRL in proportion to the voltage of the node where the charge is accumulated.

[0124] The eighth transistor T8 may be turned on in response to a voltage applied to the gate electrode, and the first electrode of the tenth transistor T10 is connected to the first initialization voltage line to which the first initialization voltage Vint1 is applied. In this case, the second electrode of the tenth transistor T10 may be discharged to the first initialization voltage Vint1. The gate electrode of the eighth transistor T8 may be connected to a node between the ninth transistor T9 and the light receiving device PD, the first electrode of the eighth transistor T8 may be connected to the first initialization voltage line, and the second electrode of the eighth transistor T8 may be connected to the first electrode of the tenth transistor T10. The eighth transistor T8 may be a source follower amplifier configured to generate a source-drain current proportional to the amount of charge input to the node of its gate electrode. In another embodiment, the first electrode of the eighth transistor T8 may be connected to the first drive voltage line VDDL or the second initialization voltage line.

[0125] The tenth transistor T10 may be turned on in response to a scan signal of the first scan write line GWL1, and connect the second electrode of the eighth transistor T8 to the fingerprint detection line FRL. The fingerprint detection line FRL may be configured to transmit a fingerprint detection signal to a readout circuit. The gate electrode of the tenth transistor T10 may be connected to the first scan write line GWL1, the first electrode of the tenth transistor T10 may be connected to the second electrode of the eighth transistor T8, and the second electrode of the tenth transistor T10 may be connected to the fingerprint detection line FRL.

[0126] The ninth transistor T9 may be turned on in response to a reset signal of the reset line RSTL, and reset a node connected to the gate electrode of the eighth transistor T8 to a reset voltage Vrst. The gate electrode of the ninth transistor T9 may be connected to the reset line RSTL, the first electrode of the ninth transistor T9 may be connected to the reset voltage line, and the second electrode of the ninth transistor T9 may be connected to a node connecting the light receiving device PD to the eighth transistor T8. When a reset driver configured to output a reset signal of the reset line RSTL is not provided, the ninth transistor T9 may be turned on in response to a scan signal.

[0127] When the first electrode of each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 is a source electrode, the second electrode thereof may be a drain electrode. In one or more embodiments, when the first electrode of each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 is a drain electrode, the second electrode thereof may be a source electrode.

[0128] The active layer of each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 may include one of polysilicon, amorphous silicon and an oxide semiconductor. For example, each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the tenth transistor T10 may be a p-type or kind transistor (e.g., a p-transistor). In this case, the active layer of each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the tenth transistor T10 may include polysilicon. In one or more embodiments, each of the third transistor T3, the fourth transistor T4 and the ninth transistor T9 may be an n-type or kind transistor (e.g., an n-transistor) forming an oxide semiconductor active layer.

[0129] However, the embodiment is not limited thereto, and each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 may be a p-type or type transistor. As another example, each of the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 may be formed as a p-type or type transistor.

[0130] Figure 4 is a plan view schematically showing a portion of a display device according to an embodiment. For example, Figure 4 It is schematically shown Figure 1 An enlarged plan view of area A. For convenience, Figure 4 A plan view on the bank layer 215 is shown.

[0131] Reference Figure 4, the display device 1 may include a plurality of light emitting devices and a plurality of light receiving devices. The light emitting devices may include a first light emitting device ED1, a second light emitting device ED2, and a third light emitting device ED3, and the light receiving device may include a first light receiving device PD1. The first light emitting device ED1, the second light emitting device ED2, and the third light emitting device ED3 may be configured to emit light beams of different colors outwardly. For example, the first light emitting device ED1 may be configured to emit green light outwardly, the second light emitting device ED2 may be configured to emit red light outwardly, and the third light emitting device ED3 may be configured to emit blue light outwardly. The red light may be light within a wavelength band of about 580 nanometers (nm) to about 780 nm, the blue light may be light within a wavelength band of about 380 nm to about 495 nm, and the green light may be light within a wavelength band of about 495 nm to about 580 nm. The first light receiving device PD1 may sense an object by detecting light emitted from the first light emitting device ED1, the second light emitting device ED2, and / or the third light emitting device ED3 and then reflected from the object.

[0132] Each of the light-emitting devices may include a pixel electrode, a counter electrode, and an intermediate layer between the pixel electrode and the counter electrode, and each of the light-receiving devices may include a sensing electrode, a counter electrode, and an intermediate layer between the sensing electrode and the counter electrode. Therefore, the first light-emitting device ED1 may include a first pixel electrode 210-1, the second light-emitting device ED2 may include a second pixel electrode 210-2, the third light-emitting device ED3 may include a third pixel electrode 210-3, and the first light-receiving device PD1 may include a first sensing electrode 210-4. The first pixel electrode 210-1, the second pixel electrode 210-2, the third pixel electrode 210-3, and the first sensing electrode 210-4 may be formed on a substrate (see Figure 5 In the present specification, the expression "in a plan view" refers to a plane observed from a direction orthogonal (e.g., vertical) to the substrate 100. For example, the expression "A and B separated from each other in a plan view" means "A and B separated from each other when observed from a direction orthogonal (e.g., vertical) to the substrate 100".

[0133] The bank layer 215 may be disposed on the first pixel electrode 210-1, the second pixel electrode 210-2, the third pixel electrode 210-3, and the first sensing electrode 210-4, and may cover the edge of each of the first pixel electrode 210-1, the second pixel electrode 210-2, the third pixel electrode 210-3, and the first sensing electrode 210-4. For example, the bank layer 215 may have a first opening OP1 exposing a central portion of the first pixel electrode 210-1, a second opening OP2 exposing a central portion of the second pixel electrode 210-2, a third opening OP3 exposing a central portion of the third pixel electrode 210-3, and a fourth opening OP4 exposing a central portion of the first sensing electrode 210-4.

[0134] In some embodiments, a plurality of emission layers configured to emit light may be respectively located in a first opening OP1, a second opening OP2, and a third opening OP3 of the embankment layer 215. Each of a plurality of active layers configured to detect light may be located in a fourth opening OP4 of the embankment layer 215. The counter electrode may be arranged on the emission layer and the active layer. As described above, the stacked structure of the pixel electrode, the emission layer, and the counter electrode may constitute a light-emitting device. In one or more embodiments, as described above, the stacked structure of the sensing electrode, the active layer, and the counter electrode may constitute a light-receiving device. An opening of the embankment layer 215 may correspond to a light-emitting device and may define an emission area. In one or more embodiments, an opening of the embankment layer 215 may correspond to a light-emitting device and may define an emission area.

[0135] For example, an emission layer configured to emit green light may be arranged in the first opening OP1, and therefore, the first opening OP1 may define a first emission area EA1. Similarly, an emission layer configured to emit red light may be arranged in the second opening OP2, and therefore, the second opening OP2 may define a second emission area EA2. An emission layer configured to emit blue light may be arranged in the third opening OP3, and therefore, the third opening OP3 may define a third emission area EA3. In contrast, an active layer configured to detect light may be arranged in the fourth opening OP4, and therefore, the fourth opening OP4 may define a first sensing area SA1.

[0136] Therefore, the area of ​​the first opening OP1 may be equal to the area of ​​the first emission area EA1. Of course, the area of ​​the second opening OP2 may be equal to the area of ​​the second emission area EA2, and the area of ​​the third opening OP3 may be equal to the area of ​​the third emission area EA3. The area of ​​the fourth opening OP4 may be equal to the area of ​​the first sensing area SA1.

[0137] When from the base (see Figure 5When viewed from a direction (z-axis direction) orthogonal (e.g., vertical) to the substrate 100, each of the first opening OP1, the second opening OP2, the third opening OP3, and the fourth opening OP4 may have a polygonal shape. In other words, when viewed from a direction (z-axis direction) orthogonal (e.g., vertical) to the substrate 100, each of the first emission area EA1, the second emission area EA2, the third emission area EA3, and the first sensing area SA1 may have a polygonal shape. Figure 4 It is shown that each of the first emission area EA1, the second emission area EA2, the third emission area EA3, and the first sensing area SA1 has a rectangular shape, specifically, a rectangular shape with rounded corners when viewed from a direction (z-axis direction) orthogonal (e.g., vertical) to the substrate 100. However, the present disclosure is not limited to this. In other words, when viewed from a direction (z-axis direction) orthogonal (e.g., vertical) to the substrate 100, each of the first emission area EA1, the second emission area EA2, the third emission area EA3, and the first sensing area SA1 may have a circular shape or an elliptical shape.

[0138] Figure 5 is a cross-sectional view schematically showing a portion of a display device according to one or more embodiments. Figure 5 It is along Figure 4 The line I-I' intercepts Figure 4 Schematic cross-sectional view of a display device. Figure 6 is a conceptual diagram schematically showing a portion of a display device according to one or more embodiments. For example, Figure 6 is a cross-sectional view schematically illustrating a stacked structure of a light emitting device and a light receiving device of a display apparatus according to one or more embodiments.

[0139] like Figure 5 As shown in, the display device 1 according to the present embodiment may include a substrate 100. The substrate 100 may include one or more suitable flexible (e.g., bendable) materials. For example, the substrate 100 may include glass, metal, or polymer resin. In one or more embodiments, the substrate 100 may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, and / or cellulose acetate propionate. Of course, other modifications are possible. For example, the substrate 100 may have a multilayer structure including two layers and a barrier layer between the two layers. The two layers may include a polymer resin, and the barrier layer may include an inorganic material (e.g., silicon oxide, silicon nitride, and / or silicon oxynitride, etc.).

[0140] First, second and third light emitting devices ED1, ED2 and ED3, a light receiving device PD, a pixel circuit PC and a sensor circuit PC' may be arranged on a substrate 100. The pixel circuit PC may be electrically connected to the light emitting device ED, and the sensor circuit PC' may be electrically connected to the light receiving device PD.

[0141] By electrically connecting the first light emitting device ED1, the second light emitting device ED2 and the third light emitting device ED3 to the pixel circuit PC, the light emission of the first light emitting device ED1, the second light emitting device ED2 and the third light emitting device ED3 can be controlled or selected. In one or more embodiments, by electrically connecting the first light receiving device PD1 to the sensor circuit PC', light detection can be controlled or selected. The pixel circuit PC may include a plurality of thin film transistors TFT and a storage capacitor C ST , and can be compared with the reference Figure 3 The structure of the pixel circuit PC described is basically the same. For ease of explanation, Figure 5 A thin film transistor TFT is shown in FIG. 1 , and the thin film transistor TFT may correspond to the first transistor (see FIG. 1 ). Figure 3 Similarly, the sensor circuit PC' may include a plurality of thin film transistors TFT' and may be connected to the reference Figure 3 The structure of the sensor circuit PC' described is basically the same. For ease of explanation, Figure 5 A thin film transistor TFT' is shown in FIG. 1 , and the thin film transistor TFT' may correspond to the eighth transistor (see Figure 3 For the convenience of explanation, the following description will focus on one pixel circuit PC.

[0142] A buffer layer 201 including an inorganic material such as silicon oxide, silicon nitride and / or silicon oxynitride may be between the thin film transistor TFT and the substrate 100, and the buffer layer 201 may increase the smoothness of the upper surface of the substrate 100, or may prevent or reduce or minimize impurities from penetrating from the substrate 100, etc. into the semiconductor layer Act of the thin film transistor TFT.

[0143] like Figure 5 As shown in , the thin film transistor TFT may include a semiconductor layer Act, and the semiconductor layer Act includes amorphous silicon, polycrystalline silicon, an organic semiconductor material or an oxide semiconductor material. The thin film transistor TFT may include a gate electrode GE, a source electrode SE and / or a drain electrode DE. The gate electrode GE may include one or more suitable conductive materials (e.g., a conductor) and have one or more suitable layered structures. For example, the gate electrode GE may include a Mo layer and an Al layer. In one or more embodiments, the gate electrode GE may include a TiN xThe source electrode SE and the drain electrode DE may also include one or more suitable conductive materials and have one or more suitable layered structures. For example, each of the source electrode SE and the drain electrode DE may include a Ti layer, an Al layer and / or a Cu layer.

[0144] In order to ensure electrical insulation characteristics between the semiconductor layer Act and the gate electrode GE, a gate insulating layer 203 including an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride may be between the semiconductor layer Act and the gate electrode GE. Figure 5 The gate insulating layer 203 is shown to have a shape corresponding to the entire surface of the substrate 100 and has a structure in which a contact hole is formed in a preset portion, but the present disclosure is not limited thereto. For example, the gate insulating layer 203 may be patterned to have the same shape as the gate electrode GE.

[0145] In one or more embodiments, a first interlayer insulating layer 205 including an inorganic material such as silicon oxide, silicon nitride and / or silicon oxynitride may be arranged on the gate electrode GE. The first interlayer insulating layer 205 may have a single-layer structure or a multi-layer structure including the above-mentioned material. The insulating layer including the above-mentioned inorganic material, such as the gate insulating layer 203 and / or the first interlayer insulating layer 205, may be formed by chemical vapor deposition (CVD) and / or atomic layer deposition (ALD).

[0146] Storage capacitor C ST The storage capacitor C may include a first electrode CE1 and a second electrode CE2 that overlap each other in the z-axis direction with the first interlayer insulating layer 205 located between the first electrode CE1 and the second electrode CE2. ST It can overlap with the thin film transistor TFT in the z-axis direction. In this regard, Figure 5 The gate electrode GE of the thin film transistor TFT is a storage capacitor C ST The first electrode CE1 of the storage capacitor C is provided, but the present disclosure is not limited thereto. ST The storage capacitor C may not overlap with the thin film transistor TFT. ST The second electrode CE2 may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), etc., and may include a single layer or a plurality of layers including the above conductive materials.

[0147] The second interlayer insulating layer 207 including an inorganic material such as silicon oxide, silicon nitride and / or silicon oxynitride may be disposed between the storage capacitor C ST The second interlayer insulating layer 207 may have a single layer structure or a multilayer structure including the above-mentioned inorganic material.

[0148] The source electrode SE and the drain electrode DE may be arranged on the second interlayer insulating layer 207. The data line DL may be arranged on the same layer as the source electrode SE and the drain electrode DE and may include the same material as the source electrode SE and the drain electrode DE. The source electrode SE, the drain electrode DE and the data line DL may each include a material having excellent or suitable electrical conductivity. The source electrode SE and the drain electrode DE may each include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu) and / or titanium (Ti), etc., and may include a single-layer structure or a multilayer structure including the above conductive materials. For example, the source electrode SE, the drain electrode DE and the data line DL may each have a multilayer structure of Ti / Al / Ti. The present disclosure is not limited thereto. For example, the thin film transistor TFT may have only (selected from) one of the source electrode SE and the drain electrode DE, or may not have both the source electrode SE and the drain electrode DE (for example, not having the source electrode SE and the drain electrode DE at the same time).

[0149] The planarization layer 208 may be arranged to cover the thin film transistor TFT and the storage capacitor C ST . The planarization layer 208 may include an organic insulating material. For example, the planarization layer 208 may include a photoresist, benzocyclobutene (BCB), hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA), polystyrene, a polymer derivative having a phenolic group, an acrylic polymer, an imide-based polymer such as polyimide, an aromatic ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or any suitable mixture thereof. In some embodiments, a third interlayer insulating layer may be further arranged below the planarization layer 208. The third interlayer insulating layer may include an inorganic insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0150] The first light emitting device ED1, the second light emitting device ED2, the third light emitting device ED3, and the first light receiving device PD1 may be spaced apart from each other on the planarization layer 208. The first light emitting device ED1, the second light emitting device ED2, and the third light emitting device ED3 may be configured to emit light beams of different colors outwardly. For example, the first light emitting device ED1 may be configured to emit green light outwardly, the second light emitting device ED2 may be configured to emit red light outwardly, and the third light emitting device ED3 may be configured to emit blue light outwardly. The first light receiving device PD1 may be configured to detect light emitted from the first light emitting device ED1, the second light emitting device ED2, and the third light emitting device ED3 and light reflected from an object.

[0151] The first light emitting device ED1 may include a first pixel electrode 210-1, a first intermediate layer 220-1, and an opposing electrode 230. The second light emitting device ED2 may include a second pixel electrode 210-2, a second intermediate layer 220-2, and an opposing electrode 230. The third light emitting device ED3 may include a third pixel electrode 210-3, a third intermediate layer 220-3, and an opposing electrode 230. The first light receiving device PD1 may include a first sensing electrode 210-4, a fourth intermediate layer 220-4, and an opposing electrode 230. For example, the first pixel electrode 210-1, the second pixel electrode 210-2, the third pixel electrode 210-3, and the first sensing electrode 210-4 respectively provided in the first light emitting device ED1, the second light emitting device ED2, the third light emitting device ED3, and the first light receiving device PD1 may be patterned for each pixel. The counter electrode 230 of the first light emitting device ED1, the second light emitting device ED2, the third light emitting device ED3, and the first light receiving device PD1 may be integrally formed as a single body throughout the first light emitting device ED1, the second light emitting device ED2, the third light emitting device ED3, and the first light receiving device PD1. The first intermediate layer 220-1, the second intermediate layer 220-2, the third intermediate layer 220-3, and the fourth intermediate layer 220-4 may be respectively between the counter electrode 230 and the first pixel electrode 210-1, the second pixel electrode 210-2, the third pixel electrode 210-3, and the first sensing electrode 210-4.

[0152] The first pixel electrode 210-1, the second pixel electrode 210-2, the third pixel electrode 210-3, and the first sensing electrode 210-4 may be separated from each other and arranged on the substrate 100. The first pixel electrode 210-1, the second pixel electrode 210-2, the third pixel electrode 210-3, and the first sensing electrode 210-4 may include a transmissive conductive layer and a reflective layer, wherein the transmissive conductive layer includes a conductive layer such as indium tin oxide (ITO), In 2 O 3 The reflective layer may include a transmissive conductive oxide such as indium zinc oxide (IZO), and the reflective layer may include a metal such as Al or Ag. For example, the first pixel electrode 210-1, the second pixel electrode 210-2, the third pixel electrode 210-3, and the first sensing electrode 210-4 may each have a triple-layer structure of ITO / Ag / ITO.

[0153] like Figure 5As shown in , the first pixel electrode 210-1, the second pixel electrode 210-2, and the third pixel electrode 210-3 may each be in contact with one of the source electrode SE and the drain electrode DE, and thus be electrically connected to the thin film transistor TFT. For example, each of the first pixel electrode 210-1, the second pixel electrode 210-2, and the third pixel electrode 210-3 may be in contact with one of the source electrode SE and the drain electrode DE through a contact hole formed in the planarization layer 208. Similarly, the first sensing electrode 210-4 may be electrically connected to the thin film transistor TFT' through a contact hole formed in the planarization layer 208.

[0154] The bank layer 215 may be disposed on the planarization layer 208. Since the bank layer 215 has openings corresponding to the first light emitting device ED1, the second light emitting device ED2, and the third light emitting device ED3 and the first light receiving device PD1, that is, an opening exposing at least the central portion of the pixel electrode (or sensing electrode), the bank layer 215 may be used to define an emission area and a sensing area. For example, the bank layer 215 may have a plurality of openings, for example, first to fourth openings (see FIG. 1 ) that expose the central portions of the first pixel electrode 210-1, the second pixel electrode 210-2, the third pixel electrode 210-3, and the first sensing electrode 210-4, respectively. Figure 4 In one or more embodiments, the bank layer 215 may increase the distance between the pixel electrode and the counter electrode 230 or the distance between the sensing electrode and the counter electrode 230. Thus, arcing or the like may be prevented or reduced at the edge of the first pixel electrode 210-1, the second pixel electrode 210-2, and the third pixel electrode 210-3 and / or at the edge of the first sensing electrode 210-4. The bank layer 215 may include, for example, an organic material such as polyimide and / or hexamethyldisiloxane (HMDSO).

[0155] The counter electrode 230 may be disposed on the first pixel electrode 210-1. The counter electrode 230 may be formed as a single body throughout the first light emitting device ED1, the second light emitting device ED2, the third light emitting device ED3, and the first light receiving device PD1. Therefore, the counter electrode 230 may also be disposed on the second pixel electrode 210-2, the third pixel electrode 210-3, and the first sensing electrode 210-4. The counter electrode 230 may include a substrate including ITO, In 2 O 3 The counter electrode 230 may include a transmissive conductive layer of Mg or IZO, and may further include a semi-transmissive layer including a metal such as Al or Ag. For example, the counter electrode 230 may be a semi-transmissive layer including Mg or Ag.

[0156] The first intermediate layer 220-1 may be between the first pixel electrode 210-1 and the counter electrode 230. The second intermediate layer 220-2 may be between the second pixel electrode 210-2 and the counter electrode 230, and the third intermediate layer 220-3 may be between the third pixel electrode 210-3 and the counter electrode 230. The fourth intermediate layer 220-4 may be between the first sensing electrode 210-4 and the counter electrode 230. For example, the first intermediate layer 220-1 may be disposed on the first pixel electrode 210-1, and the second intermediate layer 220-2 may be disposed on the second pixel electrode 210-2. The third intermediate layer 220-3 may be disposed on the third pixel electrode 210-3, and the fourth intermediate layer 220-4 may be disposed on the first sensing electrode 210-4.

[0157] like Figure 6 As shown in , each of the first light emitting device ED1, the second light emitting device ED2, and the third light emitting device ED3 may be provided in a series structure including a plurality of emission layers. Since each of the first light emitting device ED1, the second light emitting device ED2, and the third light emitting device ED3 has a structure in which a plurality of emission layers are stacked, color purity and light emitting efficiency may be improved. In one or more embodiments, similar to the series structure of each of the first light emitting device ED1, the second light emitting device ED2, and the third light emitting device ED3, the first light receiving device PD1 may have a double stack structure in which an active layer, etc. are stacked.

[0158] like Figure 5 and Figure 6 As shown in, in one or more embodiments, each of the first intermediate layer 220-1, the second intermediate layer 220-2, and the third intermediate layer 220-3 respectively included in the first light-emitting device ED1, the second light-emitting device ED2, and the third light-emitting device ED3 may include a plurality of emission layers. For example, the first intermediate layer 220-1 may include a first lower emission layer 223b-1 and a first upper emission layer 227b-1. The first lower emission layer 223b-1 may be arranged on the first pixel electrode 210-1, and the first upper emission layer 227b-1 may be arranged on the first lower emission layer 223b-1 so as to overlap with the first lower emission layer 223b-1. Likewise, the second intermediate layer 220-2 may include a second lower emission layer 223b-2 and a second upper emission layer 227b-2 disposed thereon, and the third intermediate layer 220-3 may include a third lower emission layer 223b-3 and a third upper emission layer 227b-3 disposed thereon.

[0159] In one or more embodiments, the fourth intermediate layer 220-4 included in the first light receiving device PD1 may have a double stack structure including an active layer, etc. In one or more embodiments, the fourth intermediate layer 220-4 may include an active layer 223b-4 and a sub-charge generation layer SCGL. Figure 5 and Figure 6 As shown in , the sub-charge generation layer SCGL may overlap with the active layer 223b-4 and may be arranged on the active layer 223b-4. The active layer 223b-4 may be arranged on substantially the same layer as the first lower emission layer 223b-1, the second lower emission layer 223b-2, and the third lower emission layer 223b-3, and the sub-charge generation layer SCGL may be arranged on substantially the same layer as the first upper emission layer 227b-1, the second upper emission layer 227b-2, and the third upper emission layer 227b-3.

[0160] The first lower emission layer 223b-1, the second lower emission layer 223b-2, the third lower emission layer 223b-3 and the active layer 223b-4 may be provided separately for the first light emitting device ED1, the second light emitting device ED2, the third light emitting device ED3 and the first light receiving device PD1 by patterning. In one or more embodiments, the first upper emission layer 227b-1, the second upper emission layer 227b-2, the third upper emission layer 227b-3 and the sub-charge generation layer SCGL may be provided separately for the first light emitting device ED1, the second light emitting device ED2, the third light emitting device ED3 and the first light receiving device PD1 by patterning.

[0161] The first light emitting device ED1 may be configured to emit green light outward, the second light emitting device ED2 may be configured to emit red light outward, and the third light emitting device ED3 may be configured to emit blue light outward. In order to achieve such light emission, the first lower emission layer 223b-1 and the first upper emission layer 227b-1 may be configured to emit green light outward, the second lower emission layer 223b-2 and the second upper emission layer 227b-2 may be configured to emit red light outward, and the third lower emission layer 223b-3 and the third upper emission layer 227b-3 may be configured to emit blue light outward. The first lower emission layer 223b-1, the second lower emission layer 223b-2, and the third lower emission layer 223b-3 may be included in the first unit UN1, and the first upper emission layer 227b-1, the second upper emission layer 227b-2, and the third upper emission layer 227b-3 may be included in the second unit UN2.

[0162] The first lower emission layer 223b-1, the second lower emission layer 223b-2 and the third lower emission layer 223b-3 and the first upper emission layer 227b-1, the second upper emission layer 227b-2 and the third upper emission layer 227b-3 may each include an organic material including a fluorescent material or a phosphorescent material configured to emit red light, green light or blue light. The first lower emission layer 223b-1, the second lower emission layer 223b-2 and the third lower emission layer 223b-3 and the first upper emission layer 227b-1, the second upper emission layer 227b-2 and the third upper emission layer 227b-3 may each be an organic emission layer containing a relatively low molecular weight organic material or a relatively high molecular weight organic material. The first lower emission layer 223b-1, the second lower emission layer 223b-2 and the third lower emission layer 223b-3 and the first upper emission layer 227b-1, the second upper emission layer 227b-2 and the third upper emission layer 227b-3 can each be an organic emission layer containing copper phthalocyanine, tri-8-hydroxyquinoline aluminum, polyphenylene vinylene (PPV)-based materials and / or polyfluorene-based materials.

[0163] In one or more embodiments, the first lower emission layer 223b-1, the second lower emission layer 223b-2, and the third lower emission layer 223b-3, and the first upper emission layer 227b-1, the second upper emission layer 227b-2, and the third upper emission layer 227b-3 may each include a host material and a dopant material. The dopant material is a material configured to emit light of a specific color, and may include a luminescent material. The luminescent material may include at least one of a phosphorescent dopant, a fluorescent dopant, and a quantum dot. The host material is the main material of the emission layer, and is a material that helps the dopant material emit light.

[0164] The first light receiving device PD1 may be configured to detect light emitted from the first light emitting device ED1, the second light emitting device ED2, and the third light emitting device ED3, and light reflected from an object. The first light receiving device PD1 may be configured to detect light reflected from an object when the active layer 223b-4 absorbs light and converts the absorbed light into an electrical signal. For example, the active layer 223b-4 is a layer configured to receive light from the outside, generate excitons, and then separate the generated excitons into holes and electrons.

[0165] In one or more embodiments, the active layer 223b-4 may be arranged in the lower stack in the double stack structure of the first light receiving device PD1. For example, the active layer 223b-4 may be arranged on substantially the same layer as the above-mentioned first lower emission layer 223b-1, the second lower emission layer 223b-2, and the third lower emission layer 223b-3 to be included in the first unit UN1. In one or more embodiments, the active layer 223b-4 may be configured to detect green light emitted from the first light emitting device ED1 and light reflected from an object. For example, the active layer 223b-4 may be configured to absorb light in a band of about 495nm to about 570nm corresponding to green light. However, the present disclosure is not limited thereto, and the active layer 223b-4 may be configured to detect light emitted from the second light emitting device ED2 and the third light emitting device ED3 according to the materials contained therein. In some cases, the active layer 223b-4 may be configured to detect light in a near-infrared band.

[0166] The active layer 223b-4 may include a p-type or kind semiconductor compound (e.g., a p-semiconductor compound) and an n-type or kind semiconductor compound (e.g., an n-semiconductor compound). For example, the active layer 223b-4 may be a mixed layer including a p-type or kind semiconductor compound and an n-type or kind semiconductor compound. In one or more embodiments, the active layer 223b-4 may have a structure in which a layer including a p-type or kind semiconductor compound and a layer including an n-type or kind semiconductor compound are stacked. The layer including the p-type or kind semiconductor compound and the layer including the n-type or kind semiconductor compound may form (or provide) a PN junction. Excitons may be effectively separated into holes and electrons by light-induced charge separation occurring at the interface of these layers.

[0167] The p-type or kind of semiconductor compound included in the active layer 223b-4 may be a compound that acts as an electron donor to provide electrons. For example, the p-type or kind of semiconductor compound may be an organic compound that can provide electrons. For example, the p-type or kind of semiconductor compound may include or be a triarylamine compound, a benzidine compound, a pyrazoline compound, a styrylamine compound, a hydrazone compound, a triphenylmethane compound, a carbazole compound, a polysilane compound, a thiophene compound, a phthalocyanine compound, a naphthalocyanine compound, a cyanine compound, a methycyanine compound, an oxocyanine compound, a polyamine compound, an indole compound, a pyrrole compound, a pyrazole compound, a polyaromatic compound, a condensed aromatic carbocyclic compound (naphthalene derivatives, anthracene derivatives, phenanthrene derivatives, tetracene derivatives, pyrene derivatives, perylene derivatives and / or fluoranthene derivatives, etc.) and / or a metal complex having a nitrogen-containing heterocyclic compound as a ligand, but the present disclosure is not limited thereto.

[0168] In one or more embodiments, the p-type or p-type semiconductor compound may include or be a compound represented by Formula 1:

[0169] Formula 1

[0170]

[0171] In formula 1, Ar 111 and Ar 112 may be independently unsubstituted or substituted with at least one R 10a Substituted C 6 -C 30 Arylene is either unsubstituted or substituted with at least one R 10a Substituted C 3 -C 30 Heteroarylene. X 111 It can be (for example, selected from): -Se-, -Te-, -S(=O)-, -S(=O) 2 -、-N(Q 111 )-、-B(Q 111 )-、-C(Q 111 )(Q 112 )-、-Si(Q 111 )(Q 112 )- and / or -Ge(Q 111 )(Q 112 )-, and X 112 and L 111 Each may be (for example, selected from): -O-, -S-, -Se-, -Te, -S(=O)-, -S(=O) 2 -、-N(Q 111 )-、-B(Q 111 )-、-C(Q 111 )(Q 112 )-、-Si(Q 111 )(Q 112 )-、-Ge(Q 111 )(Q 112 )-、-(C(Q 111 )=C(Q 112 ))-and / or-(C(Q 111 )=N)-. When L 111 is (for example, selected from) -N(Q 111 )-、-B(Q 111 )-、-C(Q 111 )(Q 112 )-、-Si(Q 111 )(Q 112 )-、-Ge(Q 111 )(Q 112 )-、-(C(Q 111 )=C(Q 112 ))-and / or-(C(Q 111)=N)-, L 111 Can optionally be combined with Ar 111 or Ar 112 connected to form (or provide) a fused ring, and Z 111 It may be a group having at least one functional group selected from (for example) C═O, C═S, C═Se and C═Te and unsubstituted or substituted by at least one R 10a Substituted C 6 -C 30 A carbocyclic group, or a group having at least one functional group selected from (for example) C═O, C═S, C═Se and C═Te and being unsubstituted or substituted by at least one R 10a Substituted C 1 -C 30 Heterocyclic group.

[0172] R 111 and R 112 can be independently hydrogen, deuterium, halogen, cyano, nitro, hydroxyl, unsubstituted or substituted with at least one R 10a Substituted C 1 -C 30 Alkyl, unsubstituted or substituted with at least one R 10a Substituted C 1 -C 30 Alkoxy, unsubstituted or substituted with at least one R 10a Substituted C 6 -C 30 Aryl, unsubstituted or substituted with at least one R 10a Substituted C 3 -C 30 Heteroaryl, unsubstituted or substituted with at least one R 10a Substituted C 2 -C 30 acyl group, or a combination thereof (eg, any suitable combination thereof).

[0173] R 10a can be (e.g., selected from): deuterium (-D), -F, -Cl, -Br, -I, hydroxyl, cyano, nitro, or a combination thereof (e.g., any suitable combination thereof); and C 1 -C 60 Alkyl, C 2 -C 60 Alkenyl, C 2 -C 60 Alkynyl and / or C 1 -C 60 Alkoxy, unsubstituted or deuterated, -F, -Cl, -Br, -I, hydroxy, cyano, nitro, C 3 -C 60 Carbocyclic group, C 1 -C60 Heterocyclic group, C 6 -C 60 Aryloxy, C 6 -C 60 Arylthio, C 1 -C 60 Heteroaryloxy, C 1 -C 60 Heteroarylthio, -Si(Q 11 )(Q 12 )(Q 13 )、-N(Q 11 )(Q 12 )、-B(Q 11 )(Q 12 )、-C(=O)(Q 11 )、-S(=O) 2 (Q 11 )、-P(=O)(Q 11 )(Q 12 ) or a combination thereof (e.g., any suitable combination thereof). In one or more embodiments, R 10a Can be C 3 -C 60 Carbocyclic group, C 1 -C 60 Heterocyclic group, C 6 -C 60 Aryloxy, C 6 -C 60 Arylthio, C 1 -C 60 Heteroaryloxy and / or C 1 -C 60 Heteroarylthio, unsubstituted or substituted with deuterium, -F, -Cl, -Br, -I, hydroxy, cyano, nitro, C 1 -C 60 Alkyl, C 2 -C 60 Alkenyl, C 2 -C 60 Alkynyl, C 1 -C 60 Alkoxy, C 3 -C 60 Carbocyclic group, C 1 -C 60 Heterocyclic group, C 6 -C 60 Aryloxy, C 6 -C 60 Arylthio, C 1 -C 60 Heteroaryloxy, C 1 -C 60 Heteroarylthio, -Si(Q 21)(Q 22 )(Q 23 )、-N(Q 21 )(Q 22 )、-B(Q 21 )(Q 22 )、-C(=O)(Q 21 )、-S(=O) 2 (Q 21 )、-P(=O)(Q 21 )(Q 22 ) or a combination thereof (e.g., any suitable combination thereof), or may be -Si(Q 31 )(Q 32 )(Q 33 )、-N(Q 31 )(Q 32 )、-B(Q 31 )(Q 32 )、-C(=O)(Q 31 )、-S(=O) 2 (Q 31 )、-P(=O)(Q 31 )(Q 32 ) or a combination thereof (e.g., any suitable combination thereof).

[0174] Q 11 To Q 13 , Q 21 To Q 23 , Q 31 To Q 33 , Q 111 and Q 112 can be each independently (e.g., selected from): hydrogen; deuterium; -F; -Cl; -Br; -I; hydroxyl; cyano; nitro; C 1 -C 60 Alkyl; C 2 -C 60 Alkenyl; C 2 -C 60 Alkynyl; C 1 -C 60 Alkoxy; and C 3 -C 60 Carboxyl, C 1 -C 60 Heterocyclic group, C 7 -C 60 Arylalkyl or C 2 -C 60 Heteroarylalkyl, unsubstituted or substituted with deuterium, -F, cyano, C 1 -C 60 Alkyl, C 1 -C 60The present invention is substituted with an alkoxy group, a phenyl group, a biphenyl group, or a combination thereof (eg, any suitable combination thereof).

[0175] In one or more embodiments, Z of Formula 1 111 It can be represented by (for example, selected from) one of Formula 111A to Formula 111F:

[0176]

[0177] In Formulas 111A to 111F, Z 112 To Z 114 Each of them can be O, S, Se or Te, X 113 Can be N or C (Q 113 ), X 114 and X 115 can be independently O, S, Se, Te, Si (Q 111 )(Q 112 ) or Ge(Q 111 )(Q 112 ). n111a to n111c may each be an integer from 0 to 3. 113 To R 117 can be independently hydrogen, deuterium, halogen, cyano, nitro, hydroxyl, unsubstituted or substituted with at least one R 10a Substituted C 1 -C 30 Alkyl, unsubstituted or substituted with at least one R 10a Substituted C 6 -C 30 Aryl, unsubstituted or substituted with at least one R 10a Substituted C 3 -C 30 heteroaryl or a combination thereof (eg, any suitable combination thereof). 111 To Q 113 The limitation can be compared with the above Q 111 The same limitations apply.

[0178] The n-type or kind semiconductor compound included in the active layer 223b-4 may be a compound that acts as an electron acceptor to accept electrons. For example, the n-type or kind semiconductor compound may be an organic compound that can accept electrons. For example, the n-type or kind semiconductor compound may be a fullerene, a fullerene derivative, a fused aromatic carbocyclic compound (naphthalene derivatives, anthracene derivatives, phenanthrene derivatives, tetracene derivatives, pyrene derivatives, perylene derivatives and / or fluoranthene derivatives, etc.), a 5- to 7-membered heterocyclic compound containing nitrogen atoms, oxygen atoms and sulfur atoms (for example, pyridine, pyrazine, pyrimidine, pyridazine, triazine, quinoline, quinoxaline, quinazoline, phthalazine, cinnoline, isoquinoline, pteridine, acridine, phenazine, phenanthroline, tetrazole, pyrazole, imidazole, thiol The present invention may be directed to a metal complex having a nitrogen-containing heterocyclic compound as a ligand, such as oxazole, oxazole, indazole, benzimidazole, benzotriazole, benzoxazole, benzothiazole, carbazole, purine, triazole, pyridazine, triazolopyrimidine, tetrazine (tetrazynedene), oxadiazole, imidazopyridine, pyrrolidine, pyrrolopyridine, thiadiazolopyridine, dibenzoazepine and / or tribenzoazepine, etc.), a polyaromatic compound, a fluorene compound, a cyclopentadiene compound, a silyl compound or a metal complex having a nitrogen-containing heterocyclic compound as a ligand, but the present disclosure is not limited thereto.

[0179] In one or more embodiments, the n-type or n-type semiconductor compound may include or be a compound represented by (eg, selected from) Formula 2 or 3:

[0180] Formula 2

[0181]

[0182] Formula 3

[0183]

[0184] In formula 2, X 111 and X 112 can be independently O or N(R 119 ), and R 111 To R 119 can be independently hydrogen, deuterium, halogen, cyano, nitro, hydroxyl, unsubstituted or substituted with at least one R 10a Substituted C 1 -C 30 Alkyl, unsubstituted or substituted with at least one R 10a Substituted C 6 -C 30 Aryl, unsubstituted or substituted with at least one R 10a Substituted C 3 -C 30 or combinations thereof (eg, any suitable combinations thereof).

[0185] In formula 3, X 121and X 122 can be independently O or N(R 125 ), and R 121 To R 125 can be independently hydrogen, deuterium, halogen, cyano, nitro, hydroxyl, unsubstituted or substituted with at least one R 10a Substituted C 1 -C 30 Alkyl, unsubstituted or substituted with at least one R 10a Substituted C 6 -C 30 Aryl, unsubstituted or substituted with at least one R 10a Substituted C 3 -C 30 or combinations thereof (eg, any suitable combinations thereof).

[0186] In equations 2 and 3, R 10a can be (e.g., selected from): deuterium (-D), -F, -Cl, -Br, -I, hydroxyl, cyano or nitro; and C 1 -C 60 Alkyl, C 2 -C 60 Alkenyl, C 2 -C 60 Alkynyl and / or C 1 -C 60 Alkoxy, unsubstituted or deuterated, -F, -Cl, -Br, -I, hydroxy, cyano, nitro, C 3 -C 60 Carbocyclic group, C 1 -C 60 Heterocyclic group, C 6 -C 60 Aryloxy, C 6 -C 60 Arylthio, C 1 -C 60 Heteroaryloxy, C 1 -C 60 Heteroarylthio, -Si(Q 11 )(Q 12 )(Q 13 )、-N(Q 11 )(Q 12 )、-B(Q 11 )(Q 12 )、-C(=O)(Q 11 )、-S(=O) 2 (Q 11 )、-P(=O)(Q 11 )(Q 12 ) or a combination thereof (e.g., any suitable combination thereof).

[0187] In one or more embodiments, R 10a Can be C 3 -C 60 Carbocyclic group, C 1 -C 60 Heterocyclic group, C 6 -C 60 Aryloxy, C 6 -C 60 Arylthio, C 1 -C 60 Heteroaryloxy and / or C 1 -C 60 Heteroarylthio, unsubstituted or substituted with deuterium, -F, -Cl, -Br, -I, hydroxy, cyano, nitro, C 1 -C 60 Alkyl, C 2 -C 60 Alkenyl, C 2 -C 60 Alkynyl, C 1 -C 60 Alkoxy, C 3 -C 60 Carbocyclic group, C 1 -C 60 Heterocyclic group, C 6 -C 60 Aryloxy, C 6 -C 60 Arylthio, C 1 -C 60 Heteroaryloxy, C 1 -C 60 Heteroarylthio, -Si(Q 21 )(Q 22 )(Q 23 )、-N(Q 21 )(Q 22 )、-B(Q 21 )(Q 22 )、-C(=O)(Q 21 )、-S(=O) 2 (Q 21 )、-P(=O)(Q 21 )(Q 22 ) or a combination thereof (e.g., any suitable combination thereof), or may be -Si(Q 31 )(Q 32 )(Q 33 )、-N(Q 31 )(Q 32 )、-B(Q 31 )(Q 32 )、-C(=O)(Q31 )、-S(=O) 2 (Q 31 )、-P(=O)(Q 31 )(Q 32 ) or a combination thereof (e.g., any suitable combination thereof).

[0188] Q 11 To Q 13 , Q 21 To Q 23 , and Q 31 To Q 33 can each independently be (e.g., selected from): hydrogen; deuterium; -F; -Cl; -Br; -I; hydroxyl; cyano; nitro; C 1 -C 60 Alkyl; C 2 -C 60 Alkenyl; C 2 -C 60 Alkynyl; C 1 -C 60 Alkoxy; and C 3 -C 60 Carboxyl, C 1 -C 60 Heterocyclic group, C 7 -C 60 Arylalkyl or C 2 -C 60 Heteroarylalkyl, unsubstituted or substituted with deuterium, -F, cyano, C 1 -C 60 Alkyl, C 1 -C 60 The present invention is substituted with alkoxy, phenyl, biphenyl and / or combinations thereof (eg, any suitable combination thereof).

[0189] In one or more embodiments, the n-type or n-type semiconductor compound may include or be (eg, selected from) one of the following compounds.

[0190]

[0191]

[0192]

[0193] In contrast, the first light receiving device PD1 may further include a sub-charge generation layer SCGL arranged in the upper stack of the double stack structure. For example, the sub-charge generation layer SCGL may be arranged on substantially the same layer as the above-mentioned first upper emission layer 227b-1, second upper emission layer 227b-2, and third upper emission layer 227b-3 to be included in the second unit UN2. The sub-charge generation layer SCGL may be used to supply charges to the double stack structure of the first light receiving device PD1 including the first unit UN1 and the second unit UN2.

[0194] In other words, the first light receiving device PD1 may have a double stack structure of the active layer 223 b - 4 disposed in the lower stack and the sub-charge generation layer SCGL disposed in the upper stack. Figure 5 and Figure 6 As shown in , when the first light receiving device PD1 has a structure in which the active layer 223b-4 and the sub-charge generating layer SCGL are stacked, the device efficiency can be superior compared to the case in which the first light receiving device PD1 has a structure in which two active layers are stacked. For example, when the active layer is arranged in the lower stack and the active layer is also arranged in the upper stack, the active layer arranged in the upper stack can be configured to absorb most of the light reflected from the object, and therefore, a small amount of light may reach the active layer arranged in the lower stack. In this case, since the active layer arranged in the lower stack may not work properly, the overall current flow of the first light receiving device PD1 may not be smooth. In contrast, when the first light receiving device PD1 includes a structure in which the active layer 223b-4 and the sub-charge generating layer SCGL are stacked, the sub-charge generating layer SCGL can be used to supply charges, and a sufficient amount of light can reach the active layer 223b-4 arranged in the lower stack. Therefore, the device efficiency can be improved.

[0195] For example, the sub-charge generation layer SCGL may include a p-type or species sub-charge generation layer 227p and an n-type or species (e.g., n-type) sub-charge generation layer 227n disposed on the p-type or species (e.g., p-type) sub-charge generation layer 227p. The p-type or species sub-charge generation layer 227p may supply holes to the lower portion of the sub-charge generation layer SCGL, and the n-type or species sub-charge generation layer 227n may supply electrons to the upper portion of the sub-charge generation layer SCGL. The n-type or species sub-charge generation layer 227n may be disposed on the p-type or species sub-charge generation layer 227p and may be in contact with the p-type or species sub-charge generation layer 227p. Since the first light receiving device PD1 includes the sub-charge generation layer SCGL as described above, the current flow in the first light receiving device PD1 may become smooth, and the light receiving efficiency may be improved.

[0196] The n-type or species sub-charge generation layer 227n may include an n-type or species doping material and an n-type or species host material. The n-type or species doping material may be a metal of Group 1 and Group 2 of the periodic table, an organic material capable of injecting electrons, or any suitable mixture thereof. For example, the n-type or species doping material may be one of an alkali metal and an alkaline earth metal. In other words, the n-type or species sub-charge generation layer 227n may include an inorganic layer doped with an alkali metal (such as lithium (Li), sodium (Na), potassium (K), or cesium (Cs)) or an alkaline earth metal (e.g., magnesium (Mg), strontium (Sr), barium (Ba), or radium (Ra)), but the present disclosure is not limited thereto. The n-type or species host material may include a material capable of transferring electrons (e.g., tris(8-hydroxyquinoline)aluminum (Alq 3 ), 8-hydroxyquinoline-lithium (Liq), 2-(4-biphenyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole (PBD), 3-(4-biphenyl)-4-phenyl-5-tert-butylphenyl-1,2,4-triazole (TAZ), spiro-PBD, bis(2-methyl-8-hydroxyquinoline)-4-(phenylphenoxy)aluminum (BAlq), SAlq, 2,2',2"-(1,3,5-benzotriyl)-tris(1-phenyl-1-H-benzimidazole (TPBi), oxadiazole, triazole, phenanthroline, benzoxazole and benzothiazole), and the present disclosure is not limited thereto.

[0197] The p-type or species sub-charge generation layer 227p may include a p-type or species doping material and a p-type or species host material. The p-type or species doping material may include a metal oxide, an organic material such as tetrafluoro-tetracyanoquinodimethane (F4-TCNQ), hexaazatriphenylene-hexanitrile (HAT-CN) or hexaazatriphenylene, or an organic material such as V 2 O 5 、MoO x or WO 3 The p-type or p-type host material may include at least one of a material capable of transporting holes (e.g., N,N'-dinaphthyl-N,N'-diphenylbenzidine (NPD), N,N'-bis(naphthalene-1-yl)-N,N'-bis(phenyl)-2,2'-dimethylbenzidine, N,N'-bis-(3-methylphenyl)-N,N'-bis-(phenyl)-benzidine (TPD), and 4,4',4"-tris(N-3-methylphenyl-N-phenyl-amino)-triphenylamine (MTDATA)), but the present disclosure is not limited thereto.

[0198] Refer again Figure 5 and Figure 6, the main charge generation layer MCGL may be between the first unit UN1 and the second unit UN2. For example, the main charge generation layer MCGL may be between the first lower emission layer 223b-1 and the first upper emission layer 227b-1, between the second lower emission layer 223b-2 and the second upper emission layer 227b-2, between the third lower emission layer 223b-3 and the third upper emission layer 227b-3, and between the active layer 223b-4 and the sub-charge generation layer SCGL.

[0199] The main charge generation layer MCGL may include an n-type or species main charge generation layer 224 and a p-type or species main charge generation layer 225 disposed on the n-type or species main charge generation layer 224. The p-type or species main charge generation layer 225 may be disposed on the n-type or species main charge generation layer 224 and may be in contact with the n-type or species main charge generation layer 224. The n-type or species main charge generation layer 224 may include the same material as the n-type or species sub-charge generation layer 227n, and the p-type or species main charge generation layer 225 may include the same material as the p-type or species sub-charge generation layer 227p. However, the present disclosure is not limited thereto, and the main charge generation layer MCGL and the sub-charge generation layer SCGL may include different materials.

[0200] The n-type or kind main charge generation layer 224 may be integrally formed as a monomer throughout the first light emitting device ED1, the second light emitting device ED2, and the third light emitting device ED3 and the first light receiving device PD1. In contrast, the p-type or kind main charge generation layer 225 may be patterned for each light emitting device and each light receiving device. For example, the p-type or kind main charge generation layer 225 may include a first p-type or kind main charge generation layer 225-1 arranged on the first light emitting device ED1, a second p-type or kind main charge generation layer 225-2 arranged on the second light emitting device ED2, a third p-type or kind main charge generation layer 225-3 arranged on the third light emitting device ED3, and a fourth p-type or kind main charge generation layer 225-4 arranged on the first light receiving device PD1. The first p-type or kind main charge generation layer 225-1, the second p-type or kind main charge generation layer 225-2, the third p-type or kind main charge generation layer 225-3, and the fourth p-type or kind main charge generation layer 225-4 may have different thicknesses in order to compensate for the resonance distance of the light emitting device or the light receiving device formed and arranged separately. However, the present disclosure is not limited thereto, and the p-type or kind main charge generation layer 225 may be integrally formed as a monomer like the n-type or kind main charge generation layer 224.

[0201] The main charge generation layer MCGL having the above structure can be used to generate charges in the first light emitting device ED1, the second light emitting device ED2, and the third light emitting device ED3. For example, the n-type or kind main charge generation layer 224 can be configured to supply electrons to the first unit UN1, and the p-type or kind main charge generation layer 225 can be configured to supply holes to the second unit UN2. For example, the main charge generation layer MCGL arranged in the first light emitting device ED1, the second light emitting device ED2, and the third light emitting device ED3 can be used to supply charges to the series structure like the sub-charge generation layer SCGL. Since the main charge generation layer MCGL is between the first lower emission layer 223b-1, the second lower emission layer 223b-2, and the third lower emission layer 223b-3 and the first upper emission layer 227b-1, the second upper emission layer 227b-2, and the third upper emission layer 227b-3, the current flow in each unit of the first light emitting device ED1, the second light emitting device ED2, and the third light emitting device ED3 becomes smooth, and thus each unit can be driven normally.

[0202] On the contrary, the main charge generation layer MCGL arranged in the first light receiving device PD1 may be used to promote the recombination of holes and electrons. As described above, since the sub-charge generation layer SCGL included in the upper stack of the first light receiving device PD1 has been used to generate charges, the main charge generation layer MCGL arranged in the first light receiving device PD1 may not generate charges like the main charge generation layer MCGL arranged in the first light emitting device ED1, the second light emitting device ED2, and the third light emitting device ED3. On the contrary, the main charge generation layer MCGL arranged in the first light receiving device PD1 may be a point where the electrons generated in the active layer 223b-4 meet the holes generated in the sub-charge generation layer SCGL. Therefore, the electrons of the active layer 223b-4 and the holes of the sub-charge generation layer SCGL recombine in the main charge generation layer MCGL, and thus material degradation can be prevented or reduced, and the current flow in the first light receiving device PD1 becomes smooth. Therefore, since the first light receiving device PD1 included in the display apparatus 1 according to one or more embodiments includes a double charge generation layer structure of the main charge generation layer MCGL and the sub charge generation layer SCGL, sensing sensitivity and device efficiency of the first light receiving device PD1 may be improved.

[0203] On the contrary, the first unit UN1 may further include a first common layer 221 and a second common layer 222. The first common layer 221 and the second common layer 222 may be between the first pixel electrode 210-1 and the first lower emission layer 223b-1, between the second pixel electrode 210-2 and the second lower emission layer 223b-2, between the third pixel electrode 210-3 and the third lower emission layer 223b-3, and between the first sensing electrode 210-4 and the active layer 223b-4. The first common layer 221 and the second common layer 222 may be integrally formed as a monomer throughout the first light emitting device ED1, the second light emitting device ED2, and the third light emitting device ED3 and the first light receiving device PD1.

[0204] The first common layer 221 and the second common layer 222 may constitute a hole transport region. The hole transport region may have a single layer structure or a multilayer structure, for example, the first common layer 221 of the hole transport region may be a hole injection layer (HIL), and the second common layer 222 of the hole transport region may be a hole transport layer (HTL). In one or more embodiments, the hole transport region may further include an electron blocking layer (EBL).

[0205] The first common layer 221 and the second common layer 222 may each include (e.g., selected from) at least one of m-MTDATA, TDATA, 2-TNATA, NPB (NPD), β-NPB, TPD, spiro-TPD, spiro-NPB, methylated-NPB, TAPC, HMTPD, 4,4',4"-tri(N-carbazolyl)triphenylamine (TCTA), polyaniline / dodecylbenzenesulfonic acid (PANI / DBSA), polyaniline / camphorsulfonic acid (PANI / CSA), poly(3,4-ethylenedioxythiophene) / poly(4-styrenesulfonate) (PEDOT / PSS) and polyaniline / poly(4-styrenesulfonate) (PANI / PSS).

[0206] In one or more embodiments, the first unit UN1 may further include an electron transport layer (ETL). The electron transport layer included in the first unit UN1 may be arranged below the n-type or species main charge generation layer 224, and may include the same material as the n-type or species main charge generation layer 224. However, the n-type or species main charge generation layer 224 may be a layer doped with an n-type or species dopant in the ETL.

[0207] In contrast, the second unit UN2 may further include a third common layer 226. The third common layer 226 may be an HTL and may transfer holes generated in the main charge generation layer MCGL to the second unit UN2. The third common layer 226 may include PEDOT or PANI.

[0208] The third common layer 226 may be between the main charge generation layer MCGL and the first upper emission layer 227b-1, the second upper emission layer 227b-2, and the third upper emission layer 227b-3, and between the main charge generation layer MCGL and the sub-charge generation layer SCGL. The third common layer 226 may be patterned for each light emitting device and each light receiving device. For example, the third common layer 226 may include a 3rd-1 common layer 226-1 arranged in the first light emitting device ED1, a 3rd-2 common layer 226-2 arranged in the second light emitting device ED2, a 3rd-3 common layer 226-3 arranged in the third light emitting device ED3, and a 3rd-4 common layer 226-4 arranged in the first light receiving device PD1. The 3rd-1 common layer 226-1, the 3rd-2 common layer 226-2, the 3rd-3 common layer 226-3, and the 3rd-4 common layer 226-4 may be formed to have different thicknesses so as to compensate for the resonance distance of the light emitting device or light receiving device formed and arranged separately. However, the present disclosure is not limited thereto, and the third common layer 226 may be integrally formed throughout the first, second, and third light emitting devices ED1 , ED2 , and ED3 and the first light receiving device PD1 as a single body.

[0209] In one or more embodiments, the second unit UN2 may further include a buffer layer 228 and a fourth common layer 229. The buffer layer 228 and the fourth common layer 229 may be between the first upper emission layer 227b-1, the second upper emission layer 227b-2, and the third upper emission layer 227b-3 and the counter electrode 230, and between the sub-charge generation layer SCGL and the counter electrode 230. The buffer layer 228 may include an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride. The fourth common layer 229 may include an ETL and / or an electron injection layer (EIL). The fourth common layer 229 may include (for example, selected from): 2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline (BCP), 4,7-diphenyl-1,10-phenanthroline (Bphen), Alq 3 , BAlq, TAZ and NTAZ.

[0210] The display device 1 may further include an auxiliary layer disposed below the emission layer and / or the active layer. The auxiliary layer may be used to increase device efficiency by compensating for the optical resonance distance according to the wavelength of light emitted from the emission layer and / or light incident to the active layer. For example, the thickness of the auxiliary layer may be about 100 angstroms. To about Since the auxiliary layer is a layer added to adjust the resonance distance, the auxiliary layer may include a resonance auxiliary material. For example, the auxiliary layer may include the same material as the HTL.

[0211] The auxiliary layer may include a lower auxiliary layer 223a included in the first unit UN1 and an upper auxiliary layer 227a included in the second unit UN2. For example, the lower auxiliary layer 223a may be arranged below the first lower emission layer 223b-1, the second lower emission layer 223b-2, and the third lower emission layer 223b-3 and the active layer 223b-4, and the upper auxiliary layer 227a may be arranged below the first upper emission layer 227b-1, the second upper emission layer 227b-2, and the third upper emission layer 227b-3.

[0212] The lower auxiliary layer 223a and the upper auxiliary layer 227a may be patterned for each light emitting device and each light receiving device. For example, the lower auxiliary layer 223a may include a first lower auxiliary layer 223a-1 disposed below the first lower emission layer 223b-1, a second lower auxiliary layer 223a-2 disposed below the second lower emission layer 223b-2, a third lower auxiliary layer 223a-3 disposed below the third lower emission layer 223b-3, and a fourth lower auxiliary layer 223a-4 disposed below the active layer 223b-4. The first lower auxiliary layer 223a-1, the second lower auxiliary layer 223a-2, the third lower auxiliary layer 223a-3, and the fourth lower auxiliary layer 223a-4 may be formed separately and may be formed to have different thicknesses so as to compensate for the resonance distance of the light emitting device or the light receiving device. Similarly, the upper auxiliary layer 227a may include a first upper auxiliary layer 227a-1 disposed below the first upper emission layer 227b-1, a second upper auxiliary layer 227a-2 disposed below the second upper emission layer 227b-2, and a third upper auxiliary layer 227a-3 disposed below the third upper emission layer 227b-3. The first upper auxiliary layer 227a-1, the second upper auxiliary layer 227a-2, and the third upper auxiliary layer 227a-3 may be formed separately and may be formed to have different thicknesses in order to compensate for the resonance distance of the light emitting device.

[0213] The cover layer 240 may be disposed on the first light emitting device ED1, the second light emitting device ED2, and the third light emitting device ED3 and the first light receiving device PD1 having the above-described structure. For example, the cover layer 240 may be disposed on the counter electrode 230 and may be integrally formed as a single body on the entire surface of the substrate 100. The cover layer 240 may increase the reliability of the display device 1 by preventing or reducing impurities such as water or oxygen from penetrating into the display device 1.

[0214] The covering layer 240 may be an organic covering layer including an organic material, an inorganic covering layer including an inorganic material, or an organic-inorganic composite covering layer including an organic material and an inorganic material. The covering layer 240 may include a carbocyclic compound, a heterocyclic compound, an amine-containing compound, a porphine derivative, a phthalocyanine derivative, a naphthalocyanine derivative, an alkali metal complex, an alkaline earth metal complex, or a combination thereof (e.g., any suitable combination thereof). The carbocyclic compound, the heterocyclic compound, and the amine-containing compound may be optionally substituted with a substituent including O, N, S, Se, Si, F, Cl, Br, I, or a combination thereof (e.g., any suitable combination thereof). According to one or more embodiments, the first covering layer and / or the second covering layer may each independently include an amine-containing compound.

[0215] In one or more embodiments, the encapsulation portion may be arranged on the cover layer 240. The encapsulation portion may be arranged on the first light emitting device ED1, the second light emitting device ED2, the third light emitting device ED3, and the first light receiving device PD1, and may be used to protect the first light emitting device ED1, the second light emitting device ED2, the third light emitting device ED3, and the first light receiving device PD1 from moisture or oxygen. The encapsulation portion may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. For example, the encapsulation portion may include: an inorganic layer including silicon nitride (SiN x ), silicon oxide (SiO x ), indium tin oxide, indium zinc oxide or a combination thereof (e.g., any suitable combination thereof); an organic layer including polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, an acrylic resin (e.g., polymethyl methacrylate and / or polyacrylic acid, etc.), an epoxy resin (e.g., aliphatic glycidyl ether (AGE), etc.) or a combination thereof (e.g., any suitable combination thereof); or a combination of (multiple) inorganic layers and (multiple) organic layers.

[0216] Figure 7 is a graph showing comparison of external quantum efficiency (EQE) changes according to wavelength between a display device according to a comparative example and a display device according to an example.

[0217] Figure 7 : is a graph showing a comparison of EQE measured according to wavelength absorbed by a light receiving device of a display device between a comparative example and an example. Figure 7 , the horizontal axis represents the wavelength (nm) absorbed by the light receiving device, and the vertical axis represents the EQE (%) of the light receiving device. Figure 7 (a) is the evaluation result of the comparative example, and Figure 7(b) is an evaluation result of the example. In the comparative example, the light receiving device has a single stack structure and corresponds to a structure in which only the active layer is between the sensing electrode and the counter electrode. In the example, the light receiving device has a double stack structure and includes an active layer 223b-4 and a sub-charge generation layer SCGL between the first sensing electrode 210-4 and the counter electrode 230.

[0218] Reference Figure 7 , both the optical receiving device according to the example and the optical receiving device according to the comparative example (for example, the optical receiving device according to the example and the optical receiving device according to the comparative example at the same time) (each) have an absorption center wavelength of about 530±50nm. For example, the optical receiving device according to the example and the optical receiving device according to the comparative example can be configured to absorb and detect green light in substantially the same manner.

[0219] However, referring to Figure 7 Combined with Figure 6 , compared with the light receiving device according to the comparative example, the spectrum half-maximum full width of the light receiving device according to the example is significantly increased. In one or more embodiments, although the external quantum efficiency (EQE) of the light receiving device according to the comparative example is about 36% at the absorption center wavelength, the EQE of the light receiving device according to the example is about 50% at the absorption center wavelength. For example, compared with the light receiving device according to the comparative example, the EQE of the light receiving device according to the example is improved by about 40%.

[0220] Therefore, when the first light receiving device PD1 has a double stack structure of the active layer 223 b - 4 and the sub-charge generation layer SCGL as in the display device according to the example, the device efficiency is more excellent than the case of having only the active layer 223 b - 4 .

[0221] Figure 8 is a cross-sectional view schematically showing a portion of a display device according to another embodiment. Fig. 9 2 is a conceptual diagram schematically showing a portion of a display device according to another embodiment. Figure 8 and Fig. 9 , except for the first light receiving device PD1, the characteristics can be independently compared with the reference Figure 5 and Figure 6 The characteristics described are the same. Figure 8 and Fig. 9 In the drawings, the same reference numerals denote Figure 5 and Figure 6 The same elements are described herein, and mainly the differences will be described in more detail.

[0222] Reference Figure 8 and Fig. 9, the first light emitting device ED1 may include a first pixel electrode 210-1, a first intermediate layer 220-1, and an opposing electrode 230. The second light emitting device ED2 may include a second pixel electrode 210-2, a second intermediate layer 220-2, and an opposing electrode 230. The third light emitting device ED3 may include a third pixel electrode 210-3, a third intermediate layer 220-3, and an opposing electrode 230. The first light receiving device PD1 may include a first sensing electrode 210-4, a fourth intermediate layer 220-4′, and an opposing electrode 230.

[0223] In this case, the first intermediate layer 220-1 may be between the first pixel electrode 210-1 and the opposing electrode 230. The second intermediate layer 220-2 may be between the second pixel electrode 210-2 and the opposing electrode 230, and the third intermediate layer 220-3 may be between the third pixel electrode 210-3 and the opposing electrode 230. The fourth intermediate layer 220-4′ may be between the first sensing electrode 210-4 and the opposing electrode 230.

[0224] Each of the first light emitting device ED1, the second light emitting device ED2, and the third light emitting device ED3 may be provided in a series structure including a plurality of emission layers. Similarly, the fourth intermediate layer 220-4' included in the first light receiving device PD1 may also have a double stacked structure. In one or more embodiments, the fourth intermediate layer 220-4' may include an active layer 227b-4 and a sub-charge generation layer SCGL. In this case, the sub-charge generation layer SCGL may overlap with the active layer 227b-4 and may be arranged below the active layer 227b-4. For example, the sub-charge generation layer SCGL may be arranged on substantially the same layer (e.g., layer 222) as the first lower emission layer 223b-1, the second lower emission layer 223b-2, and the third lower emission layer 223b-3, and the active layer 227b-4 may be arranged on substantially the same layer as the first upper emission layer 227b-1, the second upper emission layer 227b-2, and the third upper emission layer 227b-3.

[0225] The active layer 227b-4 may be Figure 5 The active layer 223b-4 includes the same material, and the sub-charge generation layer SCGL may be Figure 5 The sub-charge generation layer SCGL has substantially the same structure as Figure 5 The sub-charge generation layer SCGL includes the same material. For example, the sub-charge generation layer SCGL may include a p-type or species sub-charge generation layer 223p and an n-type or species sub-charge generation layer 223n disposed on the p-type or species sub-charge generation layer 223p. In one or more embodiments, the fourth upper auxiliary layer 227a-4 disposed under the active layer 227b-4 may also be Figure 5 The fourth lower auxiliary layer 223a-4 includes the same material.

[0226] In other words, the first light receiving device PD1 may have a double stack structure of the sub-charge generation layer SCGL arranged in the lower stack and the active layer 227b-4 arranged in the upper stack. Figure 8 When the structure of the stacked sub-charge generation layer SCGL and the active layer 227b-4 shown in , the device efficiency may be more superior than the case where the first light receiving device PD1 has a structure in which two active layers are stacked. For example, when the first light receiving device PD1 includes a structure in which the sub-charge generation layer SCGL and the active layer 227b-4 are stacked, the sub-charge generation layer SCGL can be used to supply charges, and a sufficient amount of light can reach the active layer 227b-4 arranged in the upper stack. Therefore, the device efficiency can be improved.

[0227] The display device according to one or more embodiments can improve display quality, and can also improve EQE and sensing sensitivity of a light receiving device.These effects are only examples, and the scope of the present disclosure is not limited by these effects.

[0228] According to the light-emitting device, display device, electronic device, electronic equipment or any other related device or component of the embodiment of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., a dedicated integrated circuit), software or a combination of software, firmware and hardware. For example, the various components of the device can be formed on an integrated circuit (IC) chip or on a separate IC chip. In addition, the various components of the device can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate. In addition, the various components of the device can be processes or threads running on one or more processors in one or more computing devices, executing computer program instructions and interacting with other system components to perform the various functions described herein. Computer program instructions are stored in a memory, which can be implemented in a computing device using a standard memory device (such as, for example, a random access memory (RAM)). Computer program instructions can also be stored in other non-temporary computer-readable media, such as, for example, a CD-ROM, or a flash drive, etc. In addition, those skilled in the art should recognize that, without departing from the scope of the embodiments of the present disclosure, the functions of various computing devices may be combined or integrated into a single computing device, or the functions of a particular computing device may be distributed on one or more other computing devices.

[0229] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered as other similar features or aspects that can be used in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it should be understood by those of ordinary skill in the art that one or more appropriate changes may be made (or provided) in form and detail without departing from the spirit and scope defined by the appended claims and their equivalents.

Claims

1. A display device, wherein: The display device comprises: a substrate including an emitting region and a sensing region; a light emitting device, on the substrate corresponding to the emission area; and a light receiving device, on the substrate corresponding to the sensing area, The light emitting device comprises a pixel electrode, a lower emission layer on the pixel electrode, an upper emission layer on the lower emission layer, and a portion of the counter electrode on the upper emission layer, and The light receiving device includes a sensing electrode, an active layer and a sub-charge generating layer on the sensing electrode, and another portion of the counter electrode on the active layer and the sub-charge generating layer.

2. The display device according to claim 1, wherein: The sub-charge generating layer is on the active layer.

3. The display device according to claim 2, wherein: The lower emission layer is arranged on the same layer as the active layer, and The upper emission layer is disposed on the same layer as the sub-charge generation layer.

4. The display device according to claim 1, wherein: The active layer is on the sub-charge generating layer.

5. The display device according to claim 4, wherein: The lower emission layer is arranged on the same layer as the sub-charge generation layer, and The upper emission layer is arranged on the same layer as the active layer.

6. The display device according to claim 1, wherein: The sub-charge generation layer comprises: p-type sub-charge generation layer; and An n-type sub-charge generation layer is on the p-type sub-charge generation layer.

7. The display device according to claim 1, wherein: The lower emission layer and the upper emission layer are patterned for each light emitting device, and The active layer and the sub-charge generating layer are patterned for each light receiving device.

8. The display device according to claim 1, wherein: The display device further includes a main charge generation layer between the lower emission layer and the upper emission layer and between the active layer and the sub-charge generation layer.

9. The display device according to claim 8, wherein: The main charge generating layer comprises: n-type main charge generation layer; and A p-type main charge generation layer is on the n-type main charge generation layer.

10. The display device according to claim 9, wherein: The n-type main charge generation layer is integrally formed as a single body on the entire surface of the substrate, and The p-type main charge generation layer is patterned for each of the light emitting device and the light receiving device.

11. The display device according to claim 8, wherein: The display device further includes a first hole transport layer between the pixel electrode and the lower emission layer and between the sensing electrode and the active layer. The first hole transport layer is formed integrally on the entire surface of the substrate as a single body.

12. The display device according to claim 11, wherein: The display device further includes a lower auxiliary layer between the first hole transport layer and the lower emission layer and between the first hole transport layer and the active layer, Wherein, the lower auxiliary layer is patterned for each of the light emitting device and the light receiving device.

13. The display device according to claim 8, wherein: The display device further includes a second hole transport layer between the main charge generation layer and the upper emission layer and between the main charge generation layer and the sub-charge generation layer, The second hole transport layer is patterned for each of the light emitting device and the light receiving device.

14. The display device according to claim 13, wherein: The display device further includes an upper auxiliary layer between the second hole transport layer and the upper emission layer and between the second hole transport layer and the sub-charge generation layer, Wherein, the upper auxiliary layer is patterned for each of the light emitting device and the light receiving device.

15. The display device according to claim 8, wherein: The display device further includes a buffer layer and an electron transport layer between the upper emission layer and the counter electrode and between the sub-charge generation layer and the counter electrode, The buffer layer and the electron transport layer are integrally formed as a single body on the entire surface of the substrate.

16. The display device according to claim 1, wherein: The active layer includes a p-type semiconductor compound and an n-type semiconductor compound.

17. The display device according to claim 16, wherein: The p-type semiconductor compound includes a compound represented by Formula 1: Formula 1 In formula 1, Ar 111 and Ar 112 are each independently unsubstituted or substituted with at least one R 10a Substituted C6-C 30 Arylene is either unsubstituted or substituted with at least one R 10a Substituted C3-C 30 Heteroarylene, X 111 Selected from -Se-, -Te-, -S(=O)-, -S(=O)2-, -N(Q 111 )-、-B(Q 111 )-、 -C(Q 111 )(Q 112 )-、-Si(Q 111 )(Q 112 )-and-Ge(Q 111 )(Q 112 )-among them, X 112 and L 111 Each is selected from -O-, -S-, -Se-, -Te-, -S(=O)-, -S(=O)2-, -N(Q 111 )-、-B(Q 111 )-、-C(Q 111 )(Q 112 )-、-Si(Q 111 )(Q 112 )-、-Ge(Q 111 )(Q 112 )-、-(C(Q 111 )=C(Q 112 ))-and-(C(Q 111 )=N)-, When L 111 Selected from -N(Q 111 )-、-B(Q 111 )-、-C(Q 111 )(Q 112 )-、-Si(Q 111 )(Q 112 )-、-Ge(Q 111 )(Q 112 )-、-(C(Q 111 )=C(Q 112 ))-and-(C(Q 111 )=N)-, then L 111 Optionally with Ar 111 or Ar 112 connected to provide a fused ring, Z 111 has at least one functional group selected from C=O, C=S, C=Se and C=Te and is unsubstituted or substituted with at least one R 10a Substituted C6-C 30 A carbocyclic group, or a group having at least one functional group selected from C=O, C=S, C=Se and C=Te and being unsubstituted or substituted by at least one R 10a Substituted C1-C 30 Heterocyclic group, R 111 and R 112 are each independently hydrogen, deuterium, halogen, cyano, nitro, hydroxyl, unsubstituted or substituted with at least one R 10a Substituted C1-C 30 Alkyl, unsubstituted or substituted with at least one R 10a Substituted C1-C 30 Alkoxy, unsubstituted or substituted with at least one R 10a Substituted C6-C 30 Aryl, unsubstituted or substituted with at least one R 10a Substituted C3-C 30 Heteroaryl, unsubstituted or substituted with at least one R 10a Substituted C2-C 30 acyl or a combination thereof, R 10a Selected from: deuterium, -F, -Cl, -Br, -I, hydroxyl, cyano, nitro or a combination thereof; C1-C 60 Alkyl, C2-C 60 Alkenyl, C2-C 60 Alkynyl and / or C1-C 60 Alkoxy, unsubstituted or deuterated, -F, -Cl, -Br, -I, hydroxy, cyano, nitro, C3-C 60 Carbocyclic group, C1-C 60 Heterocyclic group, C6-C 60 Aryloxy, C6-C 60 Arylthio, C1-C 60 Heteroaryloxy, C1-C 60 Heteroarylthio, -Si(Q 11 )(Q 12 )(Q 13 )、-N(Q 11 )(Q 12 )、-B(Q 11 )(Q 12 )、-C(=O)(Q 11 )、-S(=O)2(Q 11 )、-P(=O)(Q 11 )(Q 12 ) or a combination thereof; C3-C 60 Carbocyclic group, C1-C 60 Heterocyclic group, C6-C 60 Aryloxy, C6-C 60 Arylthio, C1-C 60 Heteroaryloxy and / or C1-C 60 Heteroarylthio, unsubstituted or deuterated, -F, -Cl, -Br, -I, hydroxy, cyano, nitro, C1-C 60 Alkyl, C2-C 60 Alkenyl, C2-C 60 Alkynyl, C1-C 60 Alkoxy, C3-C 60 Carbocyclic group, C1-C 60 Heterocyclic group, C6-C 60 Aryloxy, C6-C 60 Arylthio, C1-C 60 Heteroaryloxy, C1-C 60 Heteroarylthio, -Si(Q 21 )(Q 22 )(Q 23 )、-N(Q 21 )(Q 22 )、-B(Q 21 )(Q 22 )、-C(=O)(Q 21 )、-S(=O)2(Q 21 )、-P(=O)(Q 21 )(Q 22 ) or a combination thereof; or -Si(Q 31 )(Q 32 )(Q 33 )、-N(Q 31 )(Q 32 )、-B(Q 31 )(Q 32 )、-C(=O)(Q 31 )、-S(=O)2(Q 31 )、-P(=O)(Q 31 )(Q 32 ) or a combination thereof, and Q 11 To Q 13 , Q 21 To Q 23 , Q 31 To Q 33 , Q 111 , and Q 112 Each is independently selected from: hydrogen; deuterium; -F; -Cl; -Br; -I; hydroxyl; cyano; nitro; C1-C 60 Alkyl; C2-C 60 Alkenyl; C2-C 60 Alkynyl; C1-C 60 Alkoxy; and C3-C 60 Carboxyl, C1-C 60 Heterocyclic group, C7-C 60 Arylalkyl or C2-C 60 Heteroaralkyl, unsubstituted or deuterated, -F, cyano, C1-C 60 Alkyl, C1-C 60 The present invention is substituted with alkoxy, phenyl, biphenyl or a combination thereof.

18. The display device according to claim 17, wherein: Z in Formula 1 111 It is represented by one selected from Formula 111A to Formula 111F: In Formulas 111A to 111F, Z 112 To Z 114 each is O, S, Se or Te, X 113 N or C (Q 113 ), X 114 and X 115 Each independently is O, S, Se, Te, Si (Q 111 )(Q 112 ) or Ge(Q 111 )(Q 112 ), n111a to n111c are each an integer from 0 to 3, R 113 To R 117 are each independently hydrogen, deuterium, halogen, cyano, nitro, hydroxyl, unsubstituted or substituted with at least one R 10a Substituted C1-C 30 Alkyl, unsubstituted or substituted with at least one R 10a Substituted C6-C 30 Aryl, unsubstituted or substituted with at least one R 10a Substituted C3-C 30 heteroaryl or a combination thereof, and Q 113 Limitation and Q 111 The same restrictions apply.

19. The display device according to claim 16, wherein: The n-type semiconductor compound includes a compound represented by Formula 2 or Formula 3: Formula 2 Formula 3 In formula 2, X 111 and X 112 Each independently is O or N(R 119 ),and R 111 To R 119 are each independently hydrogen, deuterium, halogen, cyano, nitro, hydroxyl, unsubstituted or substituted with at least one R 10a Substituted C1-C 30 Alkyl, unsubstituted or substituted with at least one R 10a Substituted C6-C 30 Aryl, unsubstituted or substituted with at least one R 10a Substituted C3-C 30 heteroaryl or a combination thereof, In formula 3, X 121 and X 122 Each independently is O or N(R 125 ),and R 121 To R 125 are each independently hydrogen, deuterium, halogen, cyano, nitro, hydroxyl, unsubstituted or substituted with at least one R 10a Substituted C1-C 30 Alkyl, unsubstituted or substituted with at least one R 10a Substituted C6-C 30 Aryl, unsubstituted or substituted with at least one R 10a Substituted C3-C 30 heteroaryl or a combination thereof, and In equation 2 and equation 3, R 10a Selected from: deuterium, -F, -Cl, -Br, -I, hydroxyl, cyano, nitro or a combination thereof; C1-C 60 Alkyl, C2-C 60 Alkenyl, C2-C 60 Alkynyl and / or C1-C 60 Alkoxy, unsubstituted or deuterated, -F, -Cl, -Br, -I, hydroxy, cyano, nitro, C3-C 60 Carbocyclic group, C1-C 60 Heterocyclic group, C6-C 60 Aryloxy, C6-C 60 Arylthio, C1-C 60 Heteroaryloxy, C1-C 60 Heteroarylthio, -Si(Q 11 )(Q 12 )(Q 13 )、-N(Q 11 )(Q 12 )、-B(Q 11 )(Q 12 )、-C(=O)(Q 11 )、-S(=O)2(Q 11 )、-P(=O)(Q 11 )(Q 12 ) or a combination thereof; C3-C 60 Carbocyclic group, C1-C 60 Heterocyclic group, C6-C 60 Aryloxy, C6-C 60 Arylthio, C1-C 60 Heteroaryloxy and / or C1-C 60 Heteroarylthio, unsubstituted or deuterated, -F, -Cl, -Br, -I, hydroxy, cyano, nitro, C1-C 60 Alkyl, C2-C 60 Alkenyl, C2-C 60 Alkynyl, C1-C 60 Alkoxy, C3-C 60 Carbocyclic group, C1-C 60 Heterocyclic group, C6-C 60 Aryloxy, C6-C 60 Arylthio, C1-C 60 Heteroaryloxy, C1-C 60 Heteroarylthio, -Si(Q 21 )(Q 22 )(Q 23 )、-N(Q 21 )(Q 22 )、-B(Q 21 )(Q 22 )、-C(=O)(Q 21 )、-S(=O)2(Q 21 )、-P(=O)(Q 21 )(Q 22 ) or a combination thereof; or -Si(Q 31 )(Q 32 )(Q 33 )、-N(Q 31 )(Q 32 )、-B(Q 31 )(Q 32 )、-C(=O)(Q 31 )、-S(=O)2(Q 31 )、-P(=O)(Q 31 )(Q 32 ) or a combination thereof, and Q 11 To Q 13 , Q 21 To Q 23 , and Q 31 To Q 33 Each is independently selected from: hydrogen; deuterium; -F; -Cl; -Br; -I; hydroxyl; cyano; nitro; C1-C 60 Alkyl; C2-C 60 Alkenyl; C2-C 60 Alkynyl; C1-C 60 Alkoxy; and C3-C 60 Carboxylic acid group, C1-C 60 Heterocyclic group, C7-C 60 Arylalkyl or C2-C 60 Heteroaralkyl, unsubstituted or deuterated, -F, cyano, C1-C 60 Alkyl, C1-C 60 The present invention is substituted with alkoxy, phenyl, biphenyl or a combination thereof.

20. The display device according to claim 19, wherein The n-type semiconductor compound is one selected from the following compounds:

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