Display substrate and display device

Abstract

The invention discloses a display substrate and a display device. The display substrate comprises a plurality of sub-pixel groups; each sub-pixel group comprises a first sub-pixel, a second sub-pixel and a third sub-pixel pair, and the third sub-pixel pair comprises two third sub-pixels; the display substrate further comprises a first flat layer, the first sub-pixel comprises a first via hole located in the first flat layer, the second sub-pixel comprises a second via hole located in the first flat layer, the third sub-pixel comprises a third via hole located in the first flat layer, the first via hole is used for connecting the first anode with a first pixel driving circuit, and the second via hole is used for connecting the second anode with a second pixel driving circuit. The second via holes are used for connecting the second anodes with the second pixel driving circuit, the third via holes are used for connecting the third anodes with the third pixel driving circuit, and the first via holes, the second via holes and part of the third via holes in one row of sub-pixel groups are approximately located on the first straight line. Therefore, the display substrate is convenient to manage and control the process deviation.

Description

[0001] This application is a divisional application of the Chinese invention patent application (application number: 201980001218.X, application date: July 31, 2019, invention name: display substrate and display device). Technical Field

[0002] Embodiments of the present disclosure relate to a display substrate and a display device. Background Art

[0003] With the continuous development of display technology, organic light emitting diode (OLED) display panels have been increasingly used in various electronic devices due to their advantages such as self-luminescence, wide viewing angle, high contrast, low power consumption, and high response speed. Summary of the invention

[0004] At least one embodiment of the present disclosure provides a display substrate, which includes: a base substrate; a plurality of sub-pixel groups, which are arranged on the base substrate in row and column directions; and a first spacer, a second spacer and a third spacer, each of the sub-pixel groups includes a first sub-pixel, a second sub-pixel and a third sub-pixel, and in a row of the sub-pixel groups, the first spacer is located between adjacent first sub-pixels and second sub-pixels, the second spacer is located between adjacent second sub-pixels and third sub-pixels, and the third spacer is located between adjacent third sub-pixels and the first sub-pixel, and the number of the first spacers, the number of the second spacers and the number of the third spacers are approximately equal.

[0005] For example, in a display substrate provided in an embodiment of the present disclosure, in a row of the sub-pixel groups, the first spacer, the second spacer and the third spacer are cyclically arranged in sequence.

[0006] For example, in the display substrate provided in an embodiment of the present disclosure, each of the sub-pixel groups includes at most one of the first spacers, one of the second spacers, or one of the third spacers.

[0007] For example, in a display substrate provided in an embodiment of the present disclosure, each of the sub-pixel groups includes one first sub-pixel, one second sub-pixel and one third sub-pixel pair, the third sub-pixel pair includes two third sub-pixels, and in a row of the sub-pixel groups, the first spacer is located between adjacent first sub-pixels and second sub-pixels, the second spacer is located between adjacent second sub-pixels and the third sub-pixel pair, and the third spacer is located between adjacent third sub-pixel pairs and the first sub-pixel.

[0008] For example, in the display substrate provided in one embodiment of the present disclosure, in each of the sub-pixel groups, the first sub-pixel, the second sub-pixel and the third sub-pixel pairs are arranged along the row direction and form three sub-pixel columns, and the two third sub-pixels in the third sub-pixel pair are arranged along the column direction.

[0009] For example, in a display substrate provided in an embodiment of the present disclosure, in a row of the sub-pixel groups, 1+3n sub-pixel columns are spaced between the first spacer and the second spacer, 1+3n sub-pixel columns are spaced between the second spacer and the third spacer, and 1+3n sub-pixel columns are spaced between the third spacer and the first spacer, where n is a positive integer greater than or equal to 1.

[0010] For example, in a display substrate provided in an embodiment of the present disclosure, two adjacent rows of sub-pixel groups are staggered by 1 / 2 pitch, where the pitch is the distance between the centers of two first sub-pixels in two adjacent sub-pixel groups along the row direction.

[0011] For example, in a display substrate provided in an embodiment of the present disclosure, the first sub-pixel is configured to emit light of a first color, the second sub-pixel is configured to emit light of a second color, and the third sub-pixel is configured to emit light of a third color.

[0012] For example, in a display substrate provided in an embodiment of the present disclosure, the first color is blue, the second color is red, and the third color is green.

[0013] For example, in a display substrate provided in one embodiment of the present disclosure, the shape of the first spacer is roughly a strip, and the extension direction of the first spacer is roughly parallel to the column direction, the shape of the second spacer is roughly a strip, and the extension direction of the second spacer is roughly parallel to the column direction, and the shape of the third spacer is roughly a strip, and the extension direction of the third spacer is roughly parallel to the column direction.

[0014] For example, in a display substrate provided in an embodiment of the present disclosure, the size of the first spacer in the column direction is smaller than the size of the first sub-pixel in the column direction, the sizes of the second spacer and the third spacer in the column direction are smaller than the size of the third sub-pixel pair in the column direction, and the center of the first spacer, the center of the second spacer, the center of the third spacer, the center of the first sub-pixel, the center of the second sub-pixel and the center of the third sub-pixel pair are roughly located on a straight line roughly parallel to the row direction.

[0015] For example, in the display substrate provided in one embodiment of the present disclosure, the first spacer, the second spacer and the third spacer have the same size, the width of the first spacer along the row direction is in the range of 6-15 microns, the length of the first spacer along the column direction is in the range of 35-45 microns, and the height of the first spacer in the direction simultaneously perpendicular to the base substrate is in the range of 1.5-2.5 microns.

[0016] For example, in a display substrate provided in an embodiment of the present disclosure, the first sub-pixel includes a first anode and a first light-emitting functional layer, the second sub-pixel includes a second anode and a second light-emitting functional layer, the third sub-pixel includes a third anode and a third light-emitting functional layer, and the display substrate further includes: a pixel defining layer, which is located on a side of the first anode, the second anode and the third anode away from the base substrate, and includes a first opening, a second opening and a third opening, the first opening exposes the first anode, the second opening exposes the second anode, and the third opening exposes the third anode, at least a portion of the first light-emitting functional layer is located in the first opening and covers the exposed portion of the first anode, at least a portion of the second light-emitting functional layer is located in the second opening and covers the exposed portion of the second anode, at least a portion of the third light-emitting functional layer is located in the third opening and covers the exposed portion of the third anode, and the first spacer, the second spacer and the third spacer are located on the surface of the pixel defining layer away from the base substrate.

[0017] For example, in a display substrate provided in an embodiment of the present disclosure, the orthographic projections of the first spacer, the second spacer and the third spacer on the base substrate do not overlap with the orthographic projections of the first opening, the second opening and the third opening on the base substrate.

[0018] For example, in a display substrate provided in an embodiment of the present disclosure, the first spacer, the second spacer, and the third spacer are formed by a single mask process.

[0019] At least one embodiment of the present disclosure further provides a display device, comprising any of the display substrates described above.

[0020] At least one embodiment of the present disclosure further provides a display substrate, comprising: a base substrate; a plurality of sub-pixel groups arranged on the base substrate in row and column directions; each of the sub-pixel groups comprises a first sub-pixel, a second sub-pixel and a third sub-pixel pair, each of the third sub-pixel pairs comprises two third sub-pixels, the first sub-pixel comprises a first anode and a first pixel driving circuit, the second sub-pixel comprises a second anode and a second pixel driving circuit, the third sub-pixel comprises a third anode and a third pixel driving circuit, the display substrate further comprises a first planar layer located between the first anode and the first pixel driving circuit, between the second anode and the second pixel driving circuit, and between the third anode and the third pixel driving circuit, the first sub-pixel comprises a first via hole located in the first planar layer, the second sub-pixel comprises a second via hole located in the first planar layer, the third sub-pixel comprises a third via hole located in the first planar layer, the first via hole is used for connecting the first anode with the first pixel driving circuit, the second via hole is used for connecting the second anode with the second pixel driving circuit, and the third via hole is used for connecting the third anode with the third pixel driving circuit, and the first via hole, the second via hole and part of the third via hole in a row of the sub-pixel groups are approximately located on a first straight line.

[0021] For example, in a display substrate provided by an embodiment of the present disclosure, the first straight line is substantially parallel to the row direction.

[0022] For example, in the display substrate provided in an embodiment of the present disclosure, in each of the sub-pixel groups, the first sub-pixel, the second sub-pixel and the third sub-pixel pair are arranged along the row direction, the two third sub-pixels in the third sub-pixel pair are arranged along the column direction, and the two third via holes of the two third sub-pixels in the third sub-pixel pair are respectively located on two adjacent first straight lines.

[0023] For example, in a display substrate provided in an embodiment of the present disclosure, the display substrate also includes: a second flat layer, located between the first flat layer and the first pixel driving circuit, the second pixel driving circuit and the third pixel driving circuit; a first connecting electrode, a second connecting electrode and a third connecting electrode, located between the second flat layer and the first flat layer, the first pixel driving circuit includes a first electrode, the second pixel driving circuit includes a second electrode, the third pixel driving circuit includes a third electrode, the first sub-pixel includes a fourth via located in the second flat layer, the second sub-pixel includes a fifth via located in the second flat layer, the third sub-pixel includes a sixth via located in the second flat layer, the fourth via is used for connecting the first electrode and the first connecting electrode, the fifth via is used for connecting the second electrode and the second connecting electrode, the sixth via is used for connecting the third electrode and the third connecting electrode, and the fourth via, the fifth via and part of the sixth via in a row of the sub-pixel groups are approximately located on a second straight line.

[0024] For example, in the display substrate provided by an embodiment of the present disclosure, the two sixth via holes of the two third sub-pixels in the third sub-pixel pair are respectively located on two adjacent second straight lines.

[0025] For example, in a display substrate provided by an embodiment of the present disclosure, in a row of the sub-pixel groups, the first straight line and the second straight line substantially coincide with each other.

[0026] For example, in a display substrate provided in an embodiment of the present disclosure, the fourth via hole, the first via hole, the sixth via hole, the third via hole, the fifth via hole, the second via hole, the sixth via hole, and the third via hole in a row of sub-pixel groups are arranged in sequence in a cycle.

[0027] For example, in the display substrate provided in an embodiment of the present disclosure, the first via hole, the second via hole, the third via hole, the fourth via hole, the fifth via hole and the sixth via hole are arranged at intervals from each other.

[0028] For example, in a display substrate provided in an embodiment of the present disclosure, the first via hole, the second via hole, and the third via hole are arranged at equal intervals.

[0029] For example, in the display substrate provided in an embodiment of the present disclosure, the fourth via hole, the fifth via hole and the sixth via hole are arranged at equal intervals.

[0030] For example, in a display substrate provided in an embodiment of the present disclosure, the distance between the first via hole and the fourth via hole is smaller than the distance between the first via hole and the second via hole, the distance between the second via hole and the fifth via hole is smaller than the distance between the second via hole and the third via hole, and the distance between the third via hole and the sixth via hole is smaller than the distance between the second via hole and the third via hole.

[0031] For example, in a display substrate provided by an embodiment of the present disclosure, the first straight line is located between two adjacent rows of sub-pixel groups.

[0032] At least one embodiment of the present disclosure further provides a display device, comprising any of the display substrates described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0034] Figure 1 It is a structural schematic diagram of an OLED display substrate;

[0035] Figure 2A A schematic diagram showing the light emission of a sub-pixel in a display substrate;

[0036] Figure 2B is a schematic diagram of another sub-pixel light-emitting condition in a display substrate;

[0037] Figure 3 A schematic plan view of a display substrate provided according to an embodiment of the present disclosure;

[0038] Figure 4 A schematic plan view of another display substrate provided according to an embodiment of the present disclosure;

[0039] Figure 5 A schematic plan view of another display substrate provided according to an embodiment of the present disclosure;

[0040] Figure 6 A schematic structural diagram of a sub-pixel in a display substrate provided according to an embodiment of the present disclosure;

[0041] Figure 7 A schematic plan view of a display substrate provided according to an embodiment of the present disclosure;

[0042] Figure 8 A schematic diagram of the structure of a sub-pixel in a display substrate provided according to an embodiment of the present disclosure; and

[0043] Fig. 9A schematic diagram of the structure of a sub-pixel in another display substrate provided according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0045] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0046] Figure 1 Schematic diagram of the structure of an OLED display substrate. Figure 1 As shown, the OLED display substrate includes: a base substrate 10, a pixel driving circuit 20, a flat layer 30, an anode 40, a pixel defining layer 50 and a spacer (PS) 60. The pixel driving circuit 20 is arranged on the base substrate 10; the flat layer 30 is arranged on the side of the pixel driving circuit 20 away from the base substrate 10; the anode 40 is arranged on the side of the flat layer 30 away from the base substrate 10, and can be electrically connected to the pixel driving circuit 20 through a via 35 in the flat layer 30; the pixel defining layer 50 is arranged on the side of the anode 40 away from the base substrate 10 and is formed with an opening 52, and the opening 52 can expose the anode 40; the spacer 60 is arranged on the side of the pixel defining layer 50 away from the base substrate 10. The orthographic projection of the spacer 60 on the base substrate 10 does not overlap with the orthographic projection of the opening 52 on the base substrate 10.

[0047] like Figure 1As shown, the opening 52 can be provided with a light-emitting layer (not shown in the figure), and the light-emitting layer is provided in contact with the anode 50. A cathode (not shown in the figure) can also be provided on the side of the light-emitting layer away from the anode 50. The light-emitting layer can emit light under the action of the current between the anode and the cathode. Usually, the area of ​​the anode 50 is slightly larger than the area of ​​the opening 52, so the opening 52 can define the effective light-emitting area of ​​a sub-pixel. The spacer 60 is usually provided around the sub-pixel and can play a role in supporting the fine metal mask (FMM) when the light-emitting layer is evaporated. However, the conventional arrangement of spacers has the following problems: when the arrangement density of the spacers is high, the FMM placed on the spacers may scratch the spacers, causing the scratched parts to fall off from the spacers to form particles, which will directly bring particle risks and reduce product yield; on the other hand, when a sub-pixel is provided with a spacer on the first lateral side, the spacer will limit the light-emitting angle of the sub-pixel on the first lateral side, while the second lateral side of the sub-pixel without a spacer (the second lateral side is opposite to the first lateral side) will not limit the light-emitting angle of the sub-pixel on the second lateral side. The light-emitting angle of the side results in that when the sub-pixel is observed from the first lateral side and the second lateral side at the same angle as the normal of the display substrate, the brightness of the sub-pixel observed from the first lateral side is different from the brightness of the sub-pixel observed from the second lateral side, resulting in color deviation at different viewing angles, that is, the color observed from the first lateral side is different from the color observed from the second lateral side; and, since the spacers around the sub-pixels of different colors are distributed differently, the sub-pixels of different colors are affected by the spacers to different degrees, which will further cause the display substrate to produce color deviation when the picture is viewed at different viewing angles.

[0048] Figure 2A A schematic diagram showing the light emission of sub-pixels in a display substrate. Figure 2B Another schematic diagram showing the light emission of a sub-pixel in a display substrate. Figure 2A and 2B The blue sub-pixel 71, the red sub-pixel 72, the pixel defining layer 50, and the spacer 60 between the blue sub-pixel 71 and the red sub-pixel 72 are shown. Figure 2A and 2B As shown, due to the shielding effect of the spacer 60, the blue sub-pixel 71 is moved toward the first lateral side (eg Figure 2A The light emitted by the blue sub-pixel 71 toward the second lateral side (such as the left side in the figure) will be blocked by the pixel defining layer 50, while the light emitted by the blue sub-pixel 71 toward the second lateral side (such as the left side in the figure) will be blocked by the pixel defining layer 50. Figure 2A) will be blocked by the pixel defining layer 50 and the spacer 60; the spacer 60 is arranged on the pixel defining layer 50, so that the light emitted by the blue sub-pixel 71 to the second lateral side is blocked to a more serious extent. On the one hand, the brightness of the light emitted by the blue sub-pixel 71 to the second lateral side is less than the brightness of the light emitted by the blue sub-pixel 71 to the first lateral side, and on the other hand, the viewing angle of the blue sub-pixel 71 on the second lateral side is less than the viewing angle of the blue sub-pixel 71 on the first lateral side; on the contrary, due to the blocking effect of the spacer 60, the light emitted by the red sub-pixel 72 to the first lateral side is blocked to a more serious extent. On the one hand, the brightness of the light emitted by the red sub-pixel 72 to the first lateral side is less than the brightness of the light emitted by the red sub-pixel 72 to the second lateral side, and on the other hand, the viewing angle of the red sub-pixel 72 on the first lateral side is less than the viewing angle of the red sub-pixel 72 on the second lateral side. Therefore, when observing from the first lateral side and the second lateral side at the same angle as the normal of the display substrate, the brightness of the blue sub-pixel or the red sub-pixel observed from the first lateral side is different from the brightness of the sub-pixel observed from the second lateral side, which leads to color deviation when the picture is viewed at different viewing angles, that is, the color observed from the first lateral side is different from the color observed from the second lateral side; in addition, due to the different distribution of spacers around the blue sub-pixel and the red sub-pixel, the brightness of the light emitted by the blue sub-pixel to the second lateral side is lower than the brightness of the light emitted by the blue sub-pixel to the first lateral side, and the brightness of the light emitted by the red sub-pixel to the first lateral side is lower than the brightness of the light emitted by the red sub-pixel to the second lateral side, which will further cause the display substrate to produce color deviation when the picture is viewed at different viewing angles.

[0049] In this regard, the embodiments of the present disclosure provide a display substrate and a display device. The display substrate includes a base substrate, a plurality of sub-pixel groups, a first spacer, a second spacer, and a third spacer. The plurality of sub-pixel groups are arranged along the row direction and the column direction on the base substrate, and each sub-pixel group includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. In a row of sub-pixel groups, the first spacer is located between adjacent first sub-pixels and second sub-pixels, the second spacer is located between adjacent second sub-pixels and third sub-pixels, and the third spacer is located between adjacent third sub-pixels and the first sub-pixel, and the number of the first spacers, the number of the second spacers, and the number of the third spacers are approximately equal. Therefore, for a type of sub-pixel in a row of sub-pixel groups (for example, the first sub-pixel, the second sub-pixel or the third sub-pixel), since the number of first spacers, the number of second spacers and the number of third spacers are approximately equal, the number of spacers on the first lateral side and the number of spacers on the second lateral side of each sub-pixel are also approximately the same, thereby improving the symmetry of the spacers in a row of sub-pixel groups, so that when observed from the first lateral side and the second lateral side at the same angle as the normal of the display substrate, the brightness of a type of sub-pixel in a row of sub-pixel groups observed from the first lateral side and the second lateral side is approximately the same, thereby improving or even eliminating color deviation when viewing the picture at different viewing angles; and, since the number of first spacers, the number of second spacers and the number of third spacers are approximately equal, the number of spacers around different sub-pixels in a row of sub-pixel groups is also approximately the same, so that the situations in which different sub-pixels in a row of sub-pixel groups are blocked by spacers are also approximately the same, thereby further improving or even eliminating color deviation when viewing the picture at different viewing angles. Therefore, the display substrate can effectively improve or even avoid the color shift phenomenon caused by uneven distribution of spacers.

[0050] Hereinafter, the display substrate and the display device provided by the embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0051] Figure 3 FIG. 1 is a schematic plan view of a display substrate provided according to an embodiment of the present disclosure. Figure 3As shown, the display substrate 100 includes a base substrate 110, a plurality of sub-pixel groups 120, a first spacer 131, a second spacer 132, and a third spacer 133. The plurality of sub-pixel groups 120 are disposed on the base substrate 110 and arranged along the row direction and the column direction, and each sub-pixel group 120 includes a first sub-pixel 121, a second sub-pixel 122, and a third sub-pixel 123. In a row of sub-pixel groups 120, the first spacer 131 is located between the adjacent first sub-pixel 121 and the second sub-pixel 122, that is, the first spacer 131 is located in the spacing area between the adjacent first sub-pixel 121 and the second sub-pixel 122; the second spacer 132 is located between the adjacent second sub-pixel 122 and the third sub-pixel 123, that is, the second spacer 132 is located in the spacing area between the adjacent second sub-pixel 122 and the third sub-pixel 123; the third spacer 133 is located between the adjacent third sub-pixel 123 and the first sub-pixel 121, that is, the third spacer 133 is located in the spacing area between the adjacent third sub-pixel 123 and the first sub-pixel 121; and the number of first spacers 131, the number of second spacers 132 and the number of third spacers 133 are approximately equal. It should be noted that, Figure 3 The first sub-pixel 121 shown may be an effective light emitting area of ​​the first sub-pixel 121. Figure 3 The second sub-pixel 122 shown may be an effective light emitting area of ​​the second sub-pixel 122. Figure 3 The third sub-pixel 123 shown may be an effective light-emitting area of ​​the third sub-pixel 123. In addition, in the display field, a pixel generally includes a plurality of sub-pixels that can respectively display a single color (such as red, green or blue), and different colors can be displayed by controlling the ratio of sub-pixels of different colors. Therefore, the first sub-pixel mentioned above may be a single-color sub-pixel.

[0052] In the display substrate provided in the embodiment of the present disclosure, for a type of sub-pixel in a row of sub-pixel groups 120 (for example, the first sub-pixel 121, the second sub-pixel 122 or the third sub-pixel 123), since the number of first spacers 131, the number of second spacers 132 and the number of third spacers 133 are approximately equal, the number of spacers on the first lateral side and the number of spacers on the second lateral side of each sub-pixel is also approximately the same, thereby improving the symmetry of the influence of the spacers in a row of sub-pixel groups on the luminescence of the sub-pixels, so that when observed from the first lateral side and the second lateral side at the same angle as the normal of the display substrate, the brightness of a type of sub-pixel in a row of sub-pixel groups observed from the first lateral side and the second lateral side is approximately the same, thereby improving or even eliminating the color deviation when viewing the picture at different viewing angles. For example, assuming that in a row of sub-pixel groups 120, 100 first sub-pixels 121 are provided with the third spacer 133 on the first lateral side, and 100 second sub-pixels 122 are provided with the first spacer 131 on the second lateral side, at this time, due to the shielding effect of the third spacer 133, the light emitted to the first lateral side by the 100 first sub-pixels 121 with the third spacer 133 on the first lateral side will be blocked by the third spacer 133, thereby causing the light emitted to the first lateral side by the 100 first sub-pixels 121 with the third spacer 133 on the first lateral side to be blocked. The brightness of the line is less than the brightness of the light emitted to the second lateral side; on the contrary, the brightness of the light emitted to the second lateral side by the 100 first sub-pixels 121 provided with the first spacer 131 on the second lateral side is less than the brightness of the light emitted to the first lateral side; taking the first sub-pixels 121 in the row of sub-pixels 120 as a whole, the brightness of the light emitted to the second lateral side by these first sub-pixels 121 is roughly equal to the brightness of the light emitted to the first lateral side by these first sub-pixels 121, thereby improving or even eliminating the color deviation when viewing the picture at different viewing angles. For example, in some examples, in a row of sub-pixel groups 120, the number of first spacers 131, the number of second spacers 132, and the number of third spacers 133 are equal, thereby better improving or even eliminating the color deviation when viewing the picture at different viewing angles.

[0053] Figure 4 FIG. 1 is a schematic plan view of a display substrate provided according to an embodiment of the present disclosure. Figure 4As shown, the display substrate 100 includes a base substrate 110, a plurality of sub-pixel groups 120, a first spacer 131, a second spacer 132, and a third spacer 133. The plurality of sub-pixel groups 120 are disposed on the base substrate 110 and arranged along the row direction and the column direction, each sub-pixel group 120 includes a first sub-pixel 121, a second sub-pixel 122, and a third sub-pixel pair 126, and the third sub-pixel pair 126 includes two third sub-pixels 123. In a row of sub-pixel groups 120, the first spacer 131 is located between the adjacent first sub-pixel 121 and the second sub-pixel 122, that is, the first spacer 131 is located in the spacing area between the adjacent first sub-pixel 121 and the second sub-pixel 122; the second spacer 132 is located between the adjacent second sub-pixel 122 and the third sub-pixel pair 126, that is, the second spacer 132 is located in the spacing area between the adjacent second sub-pixel 122 and the third sub-pixel pair 126; the third spacer 133 is located between the adjacent third sub-pixel pair 126 and the first sub-pixel 121, that is, the third spacer 133 is located in the spacing area between the adjacent third sub-pixel pair 126 and the first sub-pixel 121; and the number of first spacers 131, the number of second spacers 132 and the number of third spacers 133 are approximately equal. It should be noted that Figure 4 The first sub-pixel 121 shown may be an effective light emitting area of ​​the first sub-pixel 121. Figure 4 The second sub-pixel 122 shown may be an effective light emitting area of ​​the second sub-pixel 122. Figure 4 The third sub-pixel 123 shown may be an effective light-emitting area of ​​the third sub-pixel 123. In addition, in the display field, a pixel generally includes a plurality of sub-pixels that can respectively display a single color (such as red, green or blue), and different colors can be displayed by controlling the ratio of sub-pixels of different colors. Therefore, the first sub-pixel mentioned above may be a single-color sub-pixel.

[0054] In the display substrate provided in the embodiment of the present disclosure, for a type of sub-pixel in a row of sub-pixel groups 120 (for example, the first sub-pixel 121, the second sub-pixel 122 or the third sub-pixel 123), since the number of first spacers 131, the number of second spacers 132 and the number of third spacers 133 are approximately equal, the number of spacers on the first lateral side and the number of spacers on the second lateral side of each sub-pixel is also approximately the same, thereby improving the symmetry of the influence of the spacers in a row of sub-pixel groups on the luminescence of the sub-pixels, so that when observed from the first lateral side and the second lateral side at the same angle as the normal of the display substrate, the brightness of a type of sub-pixel in a row of sub-pixel groups observed from the first lateral side and the second lateral side is approximately the same, thereby improving or even eliminating the color deviation when viewing the picture at different viewing angles. For example, assuming that in a row of sub-pixel groups 120, 100 first sub-pixels 121 are provided with the third spacer 133 on the first lateral side, and 100 second sub-pixels 122 are provided with the first spacer 131 on the second lateral side, at this time, due to the shielding effect of the third spacer 133, the light emitted to the first lateral side by the 100 first sub-pixels 121 with the third spacer 133 on the first lateral side will be blocked by the third spacer 133, thereby causing the light emitted to the first lateral side by the 100 first sub-pixels 121 with the third spacer 133 on the first lateral side to be blocked. The brightness of the line is less than the brightness of the light emitted to the second lateral side; on the contrary, the brightness of the light emitted to the second lateral side by the 100 first sub-pixels 121 provided with the first spacer 131 on the second lateral side is less than the brightness of the light emitted to the first lateral side; taking the first sub-pixels 121 in the row of sub-pixels 120 as a whole, the brightness of the light emitted to the second lateral side by these first sub-pixels 121 is roughly equal to the brightness of the light emitted to the first lateral side by these first sub-pixels 121, thereby improving or even eliminating the color deviation when viewing the picture at different viewing angles.

[0055] In addition, in the display substrate provided by the embodiment of the present disclosure, for a sub-pixel (e.g., the first sub-pixel 121, the second sub-pixel 122, or the third sub-pixel 123) in a row of sub-pixel groups 120, since the number of the first spacers 131, the number of the second spacers 132, and the number of the third spacers 133 are substantially equal, the number of spacers around different sub-pixels in a row of sub-pixel groups 120 is also substantially the same, so that different sub-pixels in a row of sub-pixel groups 120 are blocked by spacers (e.g., the first spacer 131, the second spacer 132, and the third spacer 133) in substantially the same situation, that is, the first sub-pixel 121, the second sub-pixel 122, and the third sub-pixel 123 in a row of sub-pixel groups 120 are blocked by spacers in substantially the same situation, thereby further improving or even eliminating the color deviation when viewing the picture at different viewing angles. Therefore, the display substrate can effectively improve or even avoid the color deviation phenomenon caused by uneven distribution of spacers.

[0056] For example, the number of the first spacers, the number of the second spacers and the number of the third spacers being approximately equal may mean that the ratio of the number of the first spacers, the number of the second spacers and the number of the third spacers to the average value of the number of the first spacers, the number of the second spacers and the third spacers respectively is in the range of 0.9-1.1.

[0057] For example, the first spacer, the second spacer and the third spacer can be made of polyimide. Of course, the embodiments of the present disclosure include but are not limited to this, and the first spacer, the second spacer and the third spacer can also be made of other materials such as silicone.

[0058] For example, the first spacer, the second spacer and the third spacer may also be made of a material with a relatively high light transmittance, thereby reducing the light shielding effect of the first spacer, the second spacer and the third spacer.

[0059] For example, in some examples, such as Figure 4 As shown, in a row of sub-pixel groups 120, the first spacer 131, the second spacer 132 and the third spacer 133 are arranged in a cycle in sequence. That is, in a row of sub-pixel groups 120, the first spacer 131, the second spacer 132 and the third spacer 133 are continuously repeated as a group. Thus, in a row of sub-pixel groups 120, within a certain area, it can be ensured that the number of the first spacer 131, the number of the second spacer 132 and the number of the third spacer 133 are approximately equal, so that the color deviation when viewing the picture at different viewing angles can be further improved or even eliminated.

[0060] For example, a row of sub-pixel groups 120 is divided into N (N is a positive integer greater than or equal to 1) regions arranged in sequence, and each region includes M (M is a positive integer greater than or equal to 1) groups of the above-mentioned first spacers 131, second spacers 132 and third spacers 133; at this time, for each region, the number of spacers on the first lateral side and the number of spacers on the second lateral side of each sub-pixel is also roughly the same, thereby improving the symmetry of the effect of the spacers in the region on the luminescence of the sub-pixel, so that when the first lateral side and the second lateral side are observed at the same angle as the normal of the display substrate, the brightness of a sub-pixel in the region observed from the first lateral side and the second lateral side is roughly the same, thereby further improving or even avoiding the color shift phenomenon caused by uneven distribution of spacers. Similarly, for each region, for a sub-pixel in each region, the number of spacers around different sub-pixels in each region is also roughly the same, so that the situation where different sub-pixels in each region are blocked by spacers is also roughly the same, thereby further improving or even eliminating the color shift when viewing the picture at different viewing angles.

[0061] For example, in some examples, such as Figure 4 As shown, each sub-pixel group 120 includes at most one first spacer 131, one second spacer 132 or one third spacer 133, thereby reducing the density of the spacers and further controlling the particle risk.

[0062] For example, in some examples, such as Figure 4 As shown, in each sub-pixel group 120, the first sub-pixel 121, the second sub-pixel 122 and the third sub-pixel pair 126 are arranged along the row direction to form three sub-pixel columns 128, and the two third sub-pixels 123 in a third sub-pixel pair 126 are arranged along the column direction. In other words, each sub-pixel group 120 may include three sub-pixel columns 128. Thus, the pixel arrangement structure of the display substrate may apply the pixel borrowing technology, thereby improving the resolution of the display substrate.

[0063] For example, in some examples, such as Figure 4As shown, in a row of sub-pixel groups 120, there are 1+3n sub-pixel columns 128 between the first spacer 131 and the second spacer 132, 1+3n sub-pixel columns 128 between the second spacer 132 and the third spacer 133, and 1+3n sub-pixel columns 128 between the third spacer 133 and the first spacer 131, where n is a positive integer greater than or equal to 1. For an OLED display substrate, the spacers have two functions: one is to support the FMM for evaporation, and the other is to support the cover plate during packaging. Therefore, on the one hand, the display substrate provided by this example can ensure that in a row of sub-pixel groups 120, the number of the first spacers 131, the number of the second spacers 132, and the number of the third spacers 133 are approximately equal; on the other hand, when the value of n is large, for example, when n is greater than or equal to 2, the display substrate provided by this example can further reduce the density of the spacers, thereby reducing the particle risk when supporting the FMM for evaporation and improving the product yield. Of course, the value of n can be set according to the need to support FMM and reduce the risk of Particles.

[0064] For example, in some examples, such as Figure 4 As shown, two adjacent rows of sub-pixel groups 120 are staggered by 1 / 2 pitch, and the pitch is the distance between the centers of two first sub-pixels 121 in two adjacent sub-pixel groups 120 along the row direction. It should be noted that the pitch can also be the distance between the centers of two second sub-pixels 122 or third sub-pixel pairs 126 in two adjacent sub-pixel groups 120 along the row direction; the above-mentioned center can be the geometric center of the sub-pixel. In addition, two adjacent rows of sub-pixel groups 120 are staggered by 1 / 2 pitch along the row direction. Of course, the embodiments of the present disclosure include but are not limited to this, and two adjacent rows of sub-pixel groups 120 are staggered by other distances.

[0065] For example, in some examples, such as Figure 4 As shown, the first sub-pixel 121 is configured to emit light of a first color, the second sub-pixel 122 is configured to emit light of a second color, and the third sub-pixel 123 is configured to emit light of a third color. It should be noted that the embodiments of the present disclosure include but are not limited to this, and one third sub-pixel in the third sub-pixel pair may be configured to emit light of a third color, and the other third sub-pixel in the third sub-pixel pair may be configured to emit light of a fourth color.

[0066] For example, the first color is blue, the second color is red, and the third color is green. Thus, the display substrate adopts a red, green, and blue color scheme; of course, the present disclosure includes but is not limited to this, and the display substrate may also adopt other color schemes.

[0067] For example, in some examples, such as Figure 4As shown, the shape of the effective light-emitting area of ​​the first sub-pixel 121 is substantially hexagonal or elliptical, and the major symmetry axis of the hexagon or the major axis of the ellipse is substantially parallel to the column direction.

[0068] For example, in some examples, such as Figure 4 As shown, the shape of the effective light-emitting area of ​​the second sub-pixel 122 is also substantially hexagonal or elliptical, and the major symmetry axis of the hexagon or the major axis of the ellipse is substantially parallel to the column direction.

[0069] For example, in some examples, such as Figure 4 As shown, the shape of the effective light-emitting area of ​​the third sub-pixel 123 is substantially a pentagon, and the right-angled sides of the pentagon are substantially parallel to the row direction.

[0070] It should be noted that the above-mentioned effective light-emitting area is generally designed to be a regular shape, such as the above-mentioned hexagon, pentagon, or ellipse. However, in the actual manufacturing process, the shape of the effective light-emitting area formed generally has a certain deviation from the regular shape designed above. For example, the corners of the above-mentioned regular shape may become rounded, so the shape of the effective light-emitting area (for example, the first effective light-emitting area, the second effective light-emitting area or the third effective light-emitting area) can be a rounded shape. In addition, the shape of the effective light-emitting area actually manufactured may also have other changes from the designed shape. For example, the shape of the effective light-emitting area designed as a hexagon may become an approximate ellipse in actual manufacturing.

[0071] For example, in some examples, such as Figure 4 As shown, the shape of the first spacer 131 is roughly strip-shaped, and the extension direction of the first spacer 131 is roughly parallel to the column direction, the shape of the second spacer 132 is roughly strip-shaped, and the extension direction of the second spacer 132 is roughly parallel to the column direction, and the shape of the third spacer 133 is roughly strip-shaped, and the extension direction of the third spacer 133 is roughly parallel to the column direction. Therefore, since the sub-pixels are usually also strip-shaped (hexagonal or elliptical), the display substrate can make full use of the intervals or gaps between the sub-pixels. For example, the shape of the above-mentioned spacers (for example, the first spacer, the second spacer or the third spacer) is the shape of the positive projection of the spacer on the base substrate. Similarly, the shape of the effective light-emitting area of ​​the above-mentioned sub-pixels (for example, the first sub-pixel, the second sub-pixel or the third sub-pixel) is the shape of the positive projection of the sub-pixel on the base substrate.

[0072] For example, in the embodiments of the present disclosure, the long strip shape means that the length in one direction is greater than the length in another direction, or the size in one direction is greater than the size in other directions. The strip shape is not limited to a rectangle, and can be other shapes, for example, a long hexagon, an oblong, a trapezoid or other shapes.

[0073] For example, in some examples, such as Figure 4 As shown, the size of the first spacer 131 in the column direction is smaller than the size of the first sub-pixel 121 in the column direction, the sizes of the second spacer 132 and the third spacer 133 in the column direction are smaller than the size of the third sub-pixel pair 126 in the column direction, and the center of the first spacer 131, the center of the second spacer 132, the center of the third spacer 133, the center of the first sub-pixel 121, the center of the second sub-pixel 122 and the center of the third sub-pixel pair 126 are roughly located on a straight line roughly parallel to the row direction.

[0074] For example, in some examples, such as Figure 4 As shown, the first spacer 131, the second spacer 132 and the third spacer 133 have the same size, the width of the first spacer 131 along the row direction is in the range of 6-15 microns, the length of the first spacer 131 along the column direction is in the range of 35-45 microns, and the height of the first spacer 131 along the direction perpendicular to both the row direction and the column direction is in the range of 1.5-2.5 microns. For example, the height of the first spacer 131 along the direction perpendicular to both the row direction and the column direction is 2 microns.

[0075] For example, in some examples, the effective light-emitting area of ​​the first sub-pixel 121 has a size range of 15-23 microns in the row direction and a size range of 35-45 microns in the column direction; the effective light-emitting area of ​​the second sub-pixel 122 has a size range of 11-21 microns in the row direction and a size range of 35-45 microns in the column direction; the effective light-emitting area of ​​the third sub-pixel 123 has a size range of 9-13 microns in the row direction and a size range of 9-13 microns in the column direction; in a third sub-pixel pair 116, the shortest distance between two third sub-pixels 113 is in the range of 13-15 microns.

[0076] Figure 5 The diagram is a plan view of another display substrate provided according to an embodiment of the present disclosure. Figure 6 FIG. 1 is a schematic diagram of a sub-pixel structure in a display substrate provided according to an embodiment of the present disclosure. In order to clearly illustrate the structure of the sub-pixel group in the display substrate, Figure 5 Only one sub-pixel group is shown. Figure 6 As shown, in the sub-pixel group 120, the first sub-pixel 121 includes a first anode 1212 and a first light-emitting functional layer 1214, the second sub-pixel 122 includes a second anode 1222 and a second light-emitting functional layer 1224, and the third sub-pixel 123 includes a third anode 1232 and a third light-emitting functional layer 1234. Figure 5 and 6As shown, the display substrate further includes: a pixel defining layer 160, which is located on the side of the first anode 1212, the second anode 1222 and the third anode 1232 away from the base substrate 110, and the pixel defining layer 160 includes a first opening 171, a second opening 172 and a third opening 173, wherein the first opening 171 exposes the first anode 1212, the second opening 172 exposes the second anode 1222, and the third opening 173 exposes the third anode 1232. At least a portion of the first light-emitting functional layer 1214 is located in the first opening 171 and covers the exposed portion of the first anode 1212, at least a portion of the second light-emitting functional layer 1224 is located in the second opening 172 and covers the exposed portion of the second anode 1222, at least a portion of the third light-emitting functional layer 1234 is located in the third opening 173 and covers the exposed portion of the third anode 1232, and the first spacer 131, the second spacer 132 and the third spacer 133 are located on the surface of the pixel defining layer 160 away from the base substrate 110. It should be noted that the area of ​​the first anode 1212 may be slightly larger than the area of ​​the first light-emitting functional layer 1214. In addition, the first light-emitting functional layer 1214 may include the electroluminescent layer itself and other functional layers located on both sides of the electroluminescent layer, such as a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer. The area of ​​the second anode 1222 may be slightly larger than the area of ​​the second light-emitting functional layer 1224. In addition, the second light-emitting functional layer 1224 may include the electroluminescent layer itself and other functional layers located on both sides of the electroluminescent layer, such as a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer. The area of ​​the third anode 1232 may be slightly larger than the area of ​​the third light-emitting functional layer 1234. In addition, the third light-emitting functional layer 1234 may include the electroluminescent layer itself and other functional layers located on both sides of the electroluminescent layer, such as a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer. For example, in some examples, the orthographic projections of the first spacer 131 , the second spacer 132 , and the third spacer 133 on the base substrate 101 do not overlap with the orthographic projections of the first opening 171 , the second opening 172 , and the third opening 173 on the base substrate 101 .

[0077] For example, in some examples, the orthographic projection of the first opening 171 on the substrate substrate 101 is completely located within the orthographic projection of the first anode 1212 on the substrate substrate 101; the orthographic projection of the second opening 172 on the substrate substrate 101 is completely located within the orthographic projection of the second anode 1222 on the substrate substrate 101; and the orthographic projection of the third opening 173 on the substrate substrate 101 is completely located within the orthographic projection of the third anode 1232 on the substrate substrate 101.

[0078] For example, in some examples, the orthographic projection of the first opening 171 on the base substrate 101 is completely located within the orthographic projection of the first light-emitting functional layer 1214 on the base substrate 101; the orthographic projection of the second opening 172 on the base substrate 101 is completely located within the orthographic projection of the second light-emitting functional layer 1224 on the base substrate 101; and the orthographic projection of the third opening 173 on the base substrate 101 is completely located within the orthographic projection of the third light-emitting functional layer 1234 on the base substrate 101.

[0079] For example, in some examples, an edge of the orthographic projection of the first anode 1212 on the substrate 101 , an edge of the orthographic projection of the second anode 1222 on the substrate 101 , and an edge of the orthographic projection of the third anode 1232 on the substrate 101 are covered by the orthographic projection of the pixel defining layer 160 on the substrate 101 .

[0080] For example, in some examples, the first light-emitting functional layer 1214 may also partially cover the pixel defining layer 160 , the second light-emitting functional layer 1224 may also partially cover the pixel defining layer 160 , and the third light-emitting functional layer 1234 may also partially cover the pixel defining layer 160 .

[0081] For example, in some examples, the first spacer 131, the second spacer 132, and the third spacer 133 are formed by a single mask process. For example, a spacer layer may be first formed on the surface of the pixel defining layer 160 away from the base substrate 110, and then the spacer layer may be patterned by a patterning process to form the first spacer 131, the second spacer 132, and the third spacer 133.

[0082] For example, in some examples, the first spacer 131, the second spacer 132, the third spacer 133 and the pixel defining layer 160 are also formed by a single mask process. For example, the first spacer 131, the second spacer 132, the third spacer 133 and the pixel defining layer 160 can be made of the same material. At least one embodiment of the present disclosure also provides a display device, including the above-mentioned display substrate. Therefore, the display device can take into account the density of the spacer and the problem of improving the color deviation. On the one hand, it can improve or even eliminate the color deviation when viewing the picture at different viewing angles. On the other hand, it can also reduce the density of the spacer, thereby controlling the particle risk and improving the product yield. When the display device adopts the display panel of the pixel arrangement structure provided in the embodiment of the present disclosure, the resolution of the display device can be further improved, and then a display device with real high resolution can be provided. In addition, since the pixel arrangement structure provided in the embodiment of the present disclosure can have good symmetry, the uniformity of the pixel distribution can be improved, and the display effect of the display device can be improved.

[0083] For example, in some examples, the display device may be any product or component with a display function, such as a smart phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like.

[0084] An embodiment of the present disclosure provides a display substrate. Figure 7 The present invention is a schematic plan view of a display substrate provided according to an embodiment of the present disclosure. Figure 8 FIG. 1 is a schematic diagram of a sub-pixel structure in a display substrate according to an embodiment of the present disclosure. Figure 7 As shown, the display substrate includes a base substrate 110 and a plurality of sub-pixel groups 120. The plurality of sub-pixel groups 120 are disposed on the base substrate 110 and arranged along the row direction and the column direction, and each sub-pixel group 120 includes a first sub-pixel 121, a second sub-pixel 122 and a third sub-pixel pair 126, and the third sub-pixel pair 126 includes two third sub-pixels 123. Figure 8 shows a sub-pixel along Figure 7 Schematic diagram of the cross section along the AA direction. Figure 8 As shown, the first sub-pixel 121 includes a first anode 1212 and a first pixel driving circuit 1216, the second sub-pixel 122 includes a second anode 1222 and a second pixel driving circuit 1226, and the third sub-pixel 123 includes a third anode 1232 and a third pixel driving circuit 1236. The display substrate further includes a first planar layer 140, which is located between the first anode 1212 and the first pixel driving circuit 1216, between the second anode 1222 and the second pixel driving circuit 1226, and between the third anode 1232 and the third pixel driving circuit 1236. The first sub-pixel 121 includes a first via hole 141 located in the first flat layer 140, the second sub-pixel 122 includes a second via hole 142 located in the first flat layer 140, and the third sub-pixel 123 includes a third via hole 143 located in the first flat layer 140; the first via hole 141 is used for connecting the first anode 1212 and the first pixel driving circuit 1216, the second via hole 142 is used for connecting the second anode 1222 and the second pixel driving circuit 1226, and the third via hole 143 is used for connecting the third anode 1232 and the third pixel driving circuit 1236; the first via hole 141, the second via hole 142 and part of the third via hole 143 in a row of sub-pixel groups 120 are approximately located on the same straight line. It should be noted that the portion of the first anode used for connection can cover and fill the corresponding first via hole, thereby connecting to the corresponding first pixel driving circuit; the portion of the second anode used for connection can cover and fill the corresponding second via hole, thereby connecting to the corresponding second pixel driving circuit; the portion of the third anode used for connection can cover and fill the corresponding third via hole, thereby connecting to the corresponding third pixel driving circuit.

[0085] In the display substrate provided by the embodiment of the present disclosure, since the first via hole 141, the second via hole 142 and part of the third via hole 143 in a row of sub-pixel groups 120 are approximately located on the first straight line, that is, the first via hole 141, the second via hole 142 and part of the third via hole 143 are arranged in a row, and the spacing is one sub-pixel distance. Therefore, when the process margin changes, the first via hole 141, the second via hole 142 and part of the third via hole 143 can move up and down at the same time, so as to facilitate the control of process deviation. For example, when the process margin changes greatly, the first via hole 141, the second via hole 142 and part of the third via hole 143 move up and down at the same time, either all of them are defective or none of them are defective, so as to facilitate the control of process deviation. It should be noted that when the first via hole 141, the second via hole 142 and part of the third via hole 143 are all defective, these defects are easily detected, so that the process can be adjusted in time.

[0086] For example, in some examples, such as Figure 7 As shown, the first via hole 141 of the first sub-pixel 121, the second via hole 142 of the second sub-pixel 122, and the third via hole 143 of a third sub-pixel 123 in the third pixel pair 126 in any two adjacent sub-pixel groups 120 in a row of sub-pixel groups 120 are approximately located on the same straight line. Therefore, when the process margin changes, these first via holes 141, second via holes 142, and third via holes 143 can move up and down at the same time, so as to facilitate the control of process deviation.

[0087] For example, in some examples, such as Figure 7 As shown, the first straight line does not overlap with the effective light-emitting area of ​​each sub-pixel (eg, the first sub-pixel, the second sub-pixel and the third sub-pixel), that is, the first straight line is not located in the overlapping area of ​​the organic layer and the anode of each sub-pixel.

[0088] For example, in some examples, such as Figure 7 As shown, the first straight line is located between adjacent pixel group rows.

[0089] For example, in some examples, such as Figure 7 As shown, the first straight line where the first via hole 141, the second via hole 142 and part of the third via hole 143 in a row of sub-pixel groups 120 are located is substantially parallel to the row direction. Figure 7As shown, in each sub-pixel group 120, the first sub-pixel 121, the second sub-pixel 122 and the third sub-pixel pair 126 are arranged along the row direction, the two third sub-pixels 123 in the third sub-pixel pair 126 are arranged along the column direction, and the two third via holes of the two third sub-pixels in the third sub-pixel pair are respectively located on two adjacent first straight lines. In other words, one of the two third via holes 143 of the two third sub-pixels 123 arranged along the column direction in the third sub-pixel pair 126 is located on the same straight line as the first via hole 141 and the second via hole 142 in the sub-pixel group row (which can be recorded as the Nth sub-pixel group row) to which the third sub-pixel pair 126 belongs, and the first via hole 141 and the second via hole 142 in the other sub-pixel group row adjacent to the sub-pixel group row to which the third sub-pixel pair 126 belongs (which can be recorded as the N-1th sub-pixel group row) are located on the same straight line.

[0090] For example, in some examples, such as Figure 8 As shown, the first pixel driving circuit 1216 may include a first active layer 12161, a first gate insulating layer 12162, a first gate 12163, a first interlayer insulating layer 12164 and a first source-drain electrode layer 12165; the second pixel driving circuit 1226 may include a second active layer 12261, a second gate insulating layer 12262, a second gate 12263, a second interlayer insulating layer 12264 and a second source-drain electrode layer 12265; the third pixel driving circuit 1236 may include a third active layer 12361, a third gate insulating layer 12362, a third gate 12363, a third interlayer insulating layer 12364 and a third source-drain electrode layer 12365.

[0091] For example, the source and drain in the first source-drain electrode layer 12165 are respectively connected to the source region and drain region of the first active layer 12161 through via holes in the first gate insulating layer 12162 and the first interlayer insulating layer 12164; the orthographic projection of the first gate 12163 on the substrate 101 overlaps with the orthographic projection of the channel region of the first active layer 12161 on the substrate 101. The source and drain in the second source-drain electrode layer 12265 are respectively connected to the source region and drain region of the second active layer 12261 through via holes in the second gate insulating layer 12262 and the second interlayer insulating layer 12264; the orthographic projection of the second gate 12263 on the substrate 101 overlaps with the orthographic projection of the channel region of the second active layer 12261 on the substrate 101. The source and drain in the third source-drain electrode layer 12365 are respectively connected to the source region and the drain region of the third active layer 12361 through the via holes in the third gate insulating layer 12362 and the third interlayer insulating layer 12364; the orthographic projection of the third gate 12363 on the substrate 101 overlaps with the orthographic projection of the channel region of the third active layer 12361 on the substrate 101. For example, in some examples, the first active layer 12161, the second active layer 12261 and the third active layer 12361 can be made of the same semiconductor layer; for example, the first active layer 12161, the second active layer 12261 and the third active layer 12361 can be made of polycrystalline silicon, single crystal silicon, oxide semiconductor and the like.

[0092] For example, in some examples, the first gate insulating layer 12162, the second gate insulating layer 12262, and the third gate insulating layer 12362 are the same gate insulating layer; for example, the first gate insulating layer 12162, the second gate insulating layer 12262, and the third gate insulating layer 12362 can be made of insulating materials such as silicon nitride, silicon oxide, and silicon oxynitride.

[0093] For example, in some examples, the first gate 12163, the second gate 12263, and the third gate 12363 can be made of the same conductive layer; for example, the first gate 12163, the second gate 12263, and the third gate 12363 can be made of conductive materials such as molybdenum, titanium, aluminum, and copper.

[0094] For example, in some examples, the first interlayer insulating layer 12164, the second interlayer insulating layer 12264, and the third interlayer insulating layer 12364 are the same interlayer insulating layer; the first interlayer insulating layer 12164, the second interlayer insulating layer 12264, and the third interlayer insulating layer 12364 can be made of insulating materials such as silicon nitride, silicon oxide, and silicon oxynitride.

[0095] For example, in some examples, the first source-drain electrode layer 12165, the second source-drain electrode layer 12265 and the third source-drain electrode layer 12365 can be made of the same conductive layer; for example, the first source-drain electrode layer 12165, the second source-drain electrode layer 12265 and the third source-drain electrode layer 12365 can be made of aluminum, titanium, copper, molybdenum and other materials. Fig. 9 FIG. 1 is a schematic diagram of a sub-pixel structure in another display substrate provided according to an embodiment of the present disclosure. Fig. 9 As shown, the display substrate further includes: a second flat layer 150, located between the first flat layer 140 and the first pixel driving circuit 1216, the second pixel driving electrode 1226 and the third pixel driving circuit 1236, the first pixel driving circuit 1216 includes a first electrode 181, the second pixel driving circuit 1226 includes a second electrode 182, and the third pixel driving circuit 1236 includes a third electrode 183; the display substrate further includes a first connecting electrode 191, a second connecting electrode 192 and a third connecting electrode 193, located between the second flat layer 150 and the first flat layer 140, and the first sub-pixel 121 also includes a second ... sub-pixel 121 The fourth via hole 151 in the planar layer 150, the second sub-pixel 122 further includes a fifth via hole 152 in the second planar layer 150, the third sub-pixel 123 further includes a sixth via hole 153 in the second planar layer 150, the fourth via hole 151 is used for connecting the first electrode 181 and the first connection electrode 191, the fifth via hole 152 is used for connecting the second electrode 182 and the second connection electrode 192, and the sixth via hole 153 is used for connecting the third electrode 183 and the third connection electrode 193. The fourth via hole 151, the fifth via hole 152 and part of the sixth via hole 153 in a row of sub-pixel groups 120 are approximately located on the second straight line. It should be noted that the first electrode, the second electrode and the third electrode can be the drain electrode in the source-drain electrode layer in the corresponding pixel driving circuit.

[0096] In the display substrate provided by the embodiment of the present disclosure, since the fourth via 151, the fifth via 152 and part of the sixth via 153 in a row of sub-pixel groups 120 are approximately located on the second straight line, that is, the fourth via 151, the fifth via 152 and part of the sixth via 153 are arranged in a row, and the spacing is one sub-pixel distance. Therefore, when the process margin changes, the fourth via 151, the fifth via 152 and part of the sixth via 153 can move up and down at the same time, so as to facilitate the control of process deviation. For example, when the process margin changes greatly, the fourth via 151, the fifth via 152 and the sixth via 153 move up and down at the same time, either all of them are defective or none of them are defective, so as to facilitate the control of process deviation. It should be noted that when the fourth via 151, the fifth via 152 and the sixth via 153 are all defective, these defects are easily detected, so that the process can be adjusted in time.

[0097] For example, in some examples, such as Figure 7 As shown, the fourth via hole 151 of the first sub-pixel 121, the fifth via hole 152 of the second sub-pixel 122, and the sixth via hole 153 of a third sub-pixel 123 in the third sub-pixel pair 126 in any two adjacent sub-pixel groups 120 in a row of sub-pixel groups 120 are approximately located on the second straight line. Therefore, when the process margin changes, these fourth via holes 151, fifth via holes 152, and sixth via holes 153 can move up and down at the same time, so as to facilitate the control of process deviation.

[0098] For example, in some examples, such as Figure 7 As shown, the two sixth via holes 153 of the two third sub-pixels 123 in the third sub-pixel pair 126 are respectively located on two adjacent second straight lines. That is, one of the two sixth via holes 153 of the two third sub-pixels 123 arranged along the column direction in the third sub-pixel pair 126 is located on the same straight line as the fourth via hole 151 and the fifth via hole 152 in the sub-pixel group row (which can be recorded as the Nth sub-pixel group row) to which the third sub-pixel pair 126 belongs, and the fourth via hole 151 and the fifth via hole 152 in the other sub-pixel group row adjacent to the sub-pixel group row to which the third sub-pixel pair 126 belongs (which can be recorded as the N-1th sub-pixel group row) are located on the same straight line.

[0099] For example, in some examples, such as Figure 7 As shown, the first straight line and the second straight line in a row of sub-pixel groups 120 are roughly coincident, for example, they are the same straight line; that is, the first via hole 141, the second via hole 142, part of the third via hole 143, the fourth via hole 151, the fifth via hole 152 and part of the sixth via hole 153 in a row of sub-pixel groups 120 are roughly located on the same straight line. Thus, when the process margin changes, the first via hole 141, the second via hole 142, part of the third via hole 143, the fourth via hole 151, the fifth via hole 152 and part of the sixth via hole 153 can move up and down at the same time, so as to facilitate the control of process deviation. For example, when the process margin changes greatly, the first via hole 141, the second via hole 142, part of the third via hole 143, the fourth via hole 151, the fifth via hole 152 and part of the sixth via hole 153 move up and down at the same time, and either all of them are defective or none of them are defective, so as to facilitate the control of process deviation. It should be noted that when the first via 141 , the second via 142 , part of the third via 143 , the fourth via 151 , the fifth via 152 , and part of the sixth via 153 are defective, these defects can be easily detected so that the process can be adjusted in time.

[0100] For example, in some examples, such as Figure 7As shown, the first via hole 141 and the fourth via hole 151 of the first sub-pixel 121, the second via hole 142 and the fifth via hole 152 of the second sub-pixel 122, and the third via hole 143 and the sixth via hole 153 of a third sub-pixel 123 in any two adjacent sub-pixel groups 120 in a row of sub-pixel groups 120 are substantially located on the same straight line. Therefore, when the process margin changes, these first via holes 141, second via holes 142, third via holes 143, fourth via holes 151, fifth via holes 152 and sixth via holes 153 can move up and down at the same time, so as to facilitate the control of process deviation.

[0101] For example, in some examples, such as Figure 7 As shown, the orthographic projections of the first via hole 141 , the second via hole 142 , the third via hole 143 , the fourth via hole 151 , the fifth via hole 152 and the sixth via hole 153 in a row of sub-pixel groups 120 on the base substrate 110 do not overlap with each other.

[0102] For example, in some examples, such as Figure 7 As shown, the first via holes 141 , the second via holes 142 , and the third via holes 143 in a row of sub-pixel groups 120 are arranged at equal intervals.

[0103] For example, in some examples, such as Figure 7 As shown, the fourth via holes 151 , the fifth via holes 152 and the sixth via holes 153 in a row of sub-pixel groups 120 are arranged at equal intervals.

[0104] For example, in some examples, the distance between the fourth via 151 and the first via 141, the distance between the fifth via 152 and the second via 142, and the distance between the sixth via 153 and the third via 143 are substantially equal. It should be noted that the distance between the fourth via 151 and the first via 141 mentioned above refers to the shortest distance between the fourth via 151 and the first via 141 in the same first sub-pixel, and similarly, the distance between the fifth via 152 and the second via 142 mentioned above refers to the shortest distance between the fifth via 152 and the second via 142 in the same second sub-pixel, and the distance between the sixth via 153 and the third via 143 mentioned above refers to the shortest distance between the sixth via 153 and the third via 143 in the same third sub-pixel. For example, in some examples, the distance between the first via 141 and the fourth via 151 is smaller than the distance between the first via 141 and the second via 142, the distance between the second via 142 and the fifth via 152 is smaller than the distance between the second via 142 and the third via 143, and the distance between the third via 143 and the sixth via 153 is smaller than the distance between the second via 142 and the third via 143.

[0105] For example, in some examples, such as Figure 7 As shown, the arrangement of the first sub-pixel 121, the second sub-pixel 122 and the third sub-pixel 123 in each sub-pixel group 120 can be seen in Figure 3 The pixel arrangement structure in the display substrate shown, that is, the first sub-pixel 121, the second sub-pixel 122 and the third sub-pixel pair 126 are arranged along the row direction, and the two third sub-pixels 123 are arranged along the column direction.

[0106] For example, in some examples, such as Figure 7 As shown, the first via hole 141 , the second via hole 142 and the third via hole 143 in a row of sub-pixel groups 120 are located between two adjacent rows of sub-pixel groups 120 .

[0107] For example, in some examples, such as Figure 7 As shown, in each sub-pixel group 120, the first sub-pixel 121, the second sub-pixel 122 and the third sub-pixel pair including two third sub-pixels 123 are arranged in the row direction, and the two third sub-pixels 123 in the third sub-pixel pair are arranged in the column direction. Under this pixel arrangement, the third via 143 and the sixth via 153 located on the same straight line need to provide electrical connection for the anode and the pixel driving circuit in the third sub-pixel in the two adjacent rows of pixel groups in the straight line. At this time, the fourth via 151, the first via 141, the sixth via 153, the third via 143, the fifth via 152, the second via 142, the sixth via 153, and the third via 143 are arranged in a cycle.

[0108] For example, in some examples, when the first sub-pixel 121 is a blue sub-pixel, the second sub-pixel 122 is a red sub-pixel, and the third sub-pixel 123 is a green sub-pixel, the fourth via 151, the first via 141, the sixth via 153, the third via 143, the fifth via 152, the second via 142, the sixth via 153, and the third via 143 are arranged in a cycle; at this time, the fourth via 151 and the first via 141 provide electrical connections for the pixel driving circuit and the anode of the blue sub-pixel in the first row, the fifth via 152 and the second via 142 provide electrical connections for the pixel driving circuit and the anode of the red sub-pixel in the first row, the first group of the sixth via 153 and the third via 143 provide electrical connections for the pixel driving circuit and the anode of the green sub-pixel in the second row, and the second group of the sixth via 153 and the third via 143 provide electrical connections for the pixel driving circuit and the anode of the green sub-pixel in the first row.

[0109] For example, in some examples, such as Figure 7As shown, the distance between the fourth via 151 and the first via 141 is smaller than the distance between the first via 141 and the second via 142; the distance between the fifth via 152 and the second via 142 is smaller than the distance between the first via 141 and the second via 142; the distance between the sixth via 153 and the third via 142 is smaller than the distance between the first via 141 and the second via 142. For example, in some examples, the first anode 1212 also includes a first connecting electrode block 12125. In the row direction, the first connecting electrode block 12125 is located on the side of the first anode 1212 away from the second sub-pixel 122, and the first connecting electrode block 12125 is electrically connected to the first pixel driving electrode 1216 through the first via 141; the second anode 1222 also includes a second connecting electrode block 12225, and the second connecting electrode block 12225 is electrically connected to the second pixel driving electrode 1226 through the second via 142, and the third anode 1232 also includes a second connecting electrode block 12325, and the second connecting electrode block 12325 is electrically connected to the third pixel driving electrode 1236 through the third via 143.

[0110] For example, in some examples, such as Figure 7 As shown, the first via hole 141 and the fourth via hole 151 are located on a side of the main portion of the first anode 1212 (the portion overlapping with the first effective light-emitting area) away from the main portion of the adjacent second anode 1222 (the portion overlapping with the second effective light-emitting area), and the fourth via hole 151 is located on a side of the first via hole 141 away from the main portion of the adjacent first anode 1212.

[0111] For example, in some examples, such as Figure 7 As shown, the second via hole 142 is located directly below the main body of the second anode 1222, that is, the orthographic projection of the second via hole 132 in the row direction overlaps with the orthographic projection of the main body of the second anode 1222 in the row direction. The fifth via hole 152 is located on the side of the second via hole 142 away from the adjacent third sub-pixel pair 126.

[0112] For example, in some examples, such as Figure 7 As shown, the two third via holes 143 of the third sub-pixel pair 126 are respectively located on two adjacent first straight lines, and the two third via holes 143 are respectively located on the upper and lower sides of the third sub-pixel pair 126, that is, the orthographic projections of the two third via holes 143 in the row direction overlap with the orthographic projections of the third sub-pixel pair 126 in the row direction. The sixth via hole 153 is located on the side of the corresponding third via hole 143 away from the adjacent first sub-pixel 121.

[0113] An embodiment of the present disclosure also provides a display device. The display device includes the above-mentioned display substrate. Since the first via hole 141, the second via hole 142 and the third via hole 143 in a row of sub-pixel groups 120 are approximately located on the same straight line, that is, the first via hole 141, the second via hole 142 and the third via hole 143 are arranged in a row, and the spacing is one sub-pixel distance. Therefore, when the process margin changes, it is convenient to control the process deviation. When the display device adopts a display panel with a pixel arrangement structure provided in an embodiment of the present disclosure, the resolution of the display device can be further improved, and thus a display device with a real high resolution can be provided. In addition, since the pixel arrangement structure provided in an embodiment of the present disclosure can have good symmetry, the uniformity of pixel distribution can be improved, and the display effect of the display device can be improved. For example, in some examples, the display device can be any product or component with a display function, such as a smart phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.

[0114] There are a few points to note:

[0115] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0116] (2) In the absence of conflict, features in the same embodiment or in different embodiments of the present disclosure may be combined with each other.

[0117] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display substrate, comprising: substrate substrate; A plurality of sub-pixel groups are arranged on the substrate in row and column directions; Wherein, each of the sub-pixel groups includes a first sub-pixel, a second sub-pixel and a third sub-pixel pair, each of the third sub-pixel pairs includes two third sub-pixels, the first sub-pixel includes a first anode and a first pixel driving circuit, the second sub-pixel includes a second anode and a second pixel driving circuit, the third sub-pixel includes a third anode and a third pixel driving circuit, the display substrate also includes a first planar layer located between the first anode and the first pixel driving circuit, between the second anode and the second pixel driving circuit, and between the third anode and the third pixel driving circuit, the first sub-pixel includes a first via hole located in the first planar layer, the second sub-pixel includes a second via hole located in the first planar layer, and the third sub-pixel includes a third via hole located in the first planar layer, The first via hole is used to connect the first anode to the first pixel driving circuit, the second via hole is used to connect the second anode to the second pixel driving circuit, and the third via hole is used to connect the third anode to the third pixel driving circuit. The first via holes, the second via holes and part of the third via holes in a row of the sub-pixel groups are substantially located on a first straight line.

2. The display substrate according to claim 1, wherein: The first straight line is substantially parallel to the row direction.

3. The display substrate according to claim 1, wherein: In each of the sub-pixel groups, the first sub-pixel, the second sub-pixel and the third sub-pixel pair are arranged along the row direction, and the two third sub-pixels in the third sub-pixel pair are arranged along the column direction. The two third via holes of two third sub-pixels in the third sub-pixel pair are respectively located on two adjacent first straight lines.

4. The display substrate according to any one of claims 1 to 3, further comprising: a second planar layer, located between the first planar layer and the first pixel driving circuit, the second pixel driving circuit and the third pixel driving circuit; A first connecting electrode, a second connecting electrode and a third connecting electrode are located between the second planar layer and the first planar layer. The first pixel driving circuit includes a first electrode, the second pixel driving circuit includes a second electrode, the third pixel driving circuit includes a third electrode, the first sub-pixel includes a fourth via hole located in the second flat layer, the second sub-pixel includes a fifth via hole located in the second flat layer, the third sub-pixel includes a sixth via hole located in the second flat layer, the fourth via hole is used for connecting the first electrode and the first connecting electrode, the fifth via hole is used for connecting the second electrode and the second connecting electrode, and the sixth via hole is used for connecting the third electrode and the third connecting electrode. The fourth via hole, the fifth via hole and part of the sixth via hole in a row of the sub-pixel groups are substantially located on a second straight line.

5. The display substrate according to claim 4, wherein: The two sixth via holes of two third sub-pixels in the third sub-pixel pair are respectively located on two adjacent second straight lines.

6. The display substrate according to claim 4, wherein: In a row of the sub-pixel groups, the first straight line and the second straight line substantially coincide with each other.

7. The display substrate according to claim 4, wherein: The fourth via hole, the first via hole, the sixth via hole, the third via hole, the fifth via hole, the second via hole, the sixth via hole, and the third via hole in a row of the sub-pixel groups are arranged in sequence in a cycle.

8. The display substrate according to claim 4, wherein: The first via hole, the second via hole, the third via hole, the fourth via hole, the fifth via hole and the sixth via hole are arranged at intervals from each other.

9. The display substrate according to any one of claims 1 to 3, wherein: The first via hole, the second via hole and the third via hole are arranged at equal intervals.

10. The display substrate according to claim 4, wherein: The fourth via hole, the fifth via hole and the sixth via hole are arranged at equal intervals.

11. The display substrate according to claim 4, wherein: The distance between the first via and the fourth via is smaller than the distance between the first via and the second via, the distance between the second via and the fifth via is smaller than the distance between the second via and the third via, and the distance between the third via and the sixth via is smaller than the distance between the second via and the third via.

12. The display substrate according to any one of claims 1 to 3, wherein: The first straight line is located between two adjacent rows of sub-pixel groups.

13. The display substrate according to any one of claims 1 to 3, wherein: The first sub-pixel is configured to emit light of a first color, the second sub-pixel is configured to emit light of a second color, and the third sub-pixel is configured to emit light of a third color.

14. The display substrate according to claim 13, wherein: The first color is blue, the second color is red, and the third color is green.

15. A display device comprising the display substrate according to any one of claims 1 to 14.

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