Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a substrate; the light-emitting functional layer is positioned on one side of the substrate; the light-emitting functional layer is provided with a plurality of sub-pixels; the first conductive layer is located between the substrate and the light-emitting functional layer; the first conductive layer comprises a first power supply wire and a second power supply wire which extend along a first direction; in the second direction, the first power supply wires and the second power supply wires are alternately arranged, and the first direction intersects with the second direction; the orthographic projection of the sub-pixel on the substrate and the orthographic projection of the first power supply wire on the substrate are overlapped; the orthographic projection of at least part of the sub-pixels on the substrate is overlapped with the orthographic projection of the second power supply wire on the substrate; in the first direction, the first power source wires between the adjacent sub-pixels are of an integrated structure, color cast under different viewing angles is reduced, and the display uniformity of the display panel is improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the rapid development of display technology, the application of display products using organic light emitting devices (OLED) is becoming more and more widespread.

[0003] However, the display uniformity of current OLED display panels needs to be improved. Summary of the invention

[0004] The present invention provides a display panel and a display device, which reduce color deviation under different viewing angles and improve display uniformity of the display panel.

[0005] In a first aspect, an embodiment of the present invention provides a display panel, including:

[0006] substrate;

[0007] A light-emitting functional layer is located on one side of the substrate; the light-emitting functional layer has a plurality of sub-pixels;

[0008] A first conductive layer is located between the substrate and the light-emitting functional layer; the first conductive layer includes a first power supply line extending along a first direction;

[0009] The orthographic projection of the sub-pixel on the substrate at least overlaps with the orthographic projection of the first power line on the substrate; and in the first direction, the first power line between adjacent sub-pixels is an integrated structure.

[0010] Optionally, the first conductive layer further includes a second power supply line extending along the first direction, and in the second direction, the first power supply line and the second power supply line are alternately arranged, and the first direction intersects with the second direction;

[0011] An orthographic projection of at least one of the sub-pixels on the substrate does not overlap with an orthographic projection of the second power supply line on the substrate;

[0012] Optionally, within the sub-pixel, the first power supply line is symmetrical about a center line of the sub-pixel in the second direction;

[0013] Optionally, in the sub-pixel, if an orthographic projection of the sub-pixel on the substrate overlaps with an orthographic projection of the second power line on the substrate, the second power line is symmetrical about a center line of the sub-pixel in the second direction;

[0014] Optionally, in the second direction, the spacing between the first power wiring and the second power wiring is alternately arranged as a first spacing and a second spacing, and the first spacing is greater than the second spacing.

[0015] Optionally, the first power supply line is configured to provide a first power supply voltage, the second power supply line is configured to provide a second power supply voltage, and the first power supply voltage is greater than the second power supply voltage;

[0016] Optionally, the first power supply line includes a first line segment and a second line segment;

[0017] In the first direction, the first routing segment and the second routing segment are alternately arranged, and the first routing segment and the second routing segment are connected to each other; in the second direction, the first routing segment and the second routing segment are staggered;

[0018] In the same sub-pixel, an orthographic projection of the sub-pixel on the substrate overlaps with an orthographic projection of the first routing segment on the substrate; or an orthographic projection of the sub-pixel on the substrate overlaps with an orthographic projection of the second routing segment on the substrate;

[0019] Optionally, the first power routing line further includes: a third routing line segment;

[0020] The third routing segment is arranged between the first power routing segment and the second power routing segment at the first interval, wherein one end of the third routing segment is connected to the first routing segment; the other end of the third routing segment is extended along the second direction, and the orthographic projection of the third routing segment on the substrate does not overlap with the orthographic projection of the second power routing segment on the substrate;

[0021] Optionally, an orthographic projection of the third routing segment on the substrate coincides with an orthographic projection of a center line of the sub-pixel in the second direction on the substrate;

[0022] Optionally, in the second direction, extension lines of adjacent third routing segments are located on the same straight line.

[0023] Optionally, the display panel further comprises: a connecting portion and a second conductive layer; the second conductive layer is located on a side of the first conductive layer away from the substrate;

[0024] The second conductive layer includes a third power line extending along the second direction, wherein the third power line is connected to the first power line through the connecting portion;

[0025] Optionally, the connecting portion is arranged in an overlapping area of ​​an orthographic projection of the third power line on the substrate and an orthographic projection of the first power line on the substrate;

[0026] Optionally, the connecting portion includes a via hole, and the via hole passes through the insulating layer between the third power line and the first power line.

[0027] Optionally, the second conductive layer further includes a data signal line extending along the second direction; the data signal line is arranged between the third power supply lines adjacent to each other in the first direction;

[0028] Optionally, an orthographic projection of the data signal line on the substrate coincides with an orthographic projection of a center line of the sub-pixel in the second direction on the substrate.

[0029] Optionally, the second conductive layer further includes at least two signal traces extending along the second direction;

[0030] The signal wiring is symmetrically arranged with respect to the third power wiring and between the third power wirings adjacent to each other in the first direction.

[0031] Optionally, hollow portions are arranged at intervals on the third power line along the second direction, and the orthographic projections of the solid portions between adjacent hollow portions on the substrate at least partially cover the orthographic projections of the first power line and the second power line on the substrate;

[0032] Optionally, an orthographic projection of the entity portion on the substrate at least partially covers an orthographic projection of the second routing segment on the substrate and an orthographic projection of the second power routing line adjacent to the second spacing on the substrate.

[0033] Optionally, the plurality of sub-pixels include a first color sub-pixel, a second color sub-pixel and a third color sub-pixel;

[0034] The first color sub-pixels and the second color sub-pixels are alternately arranged in a row along the first direction; the first color sub-pixels and the second color sub-pixels are alternately arranged in a column along the second direction;

[0035] In the second direction, the third color sub-pixel is located between the first color sub-pixel and the second color sub-pixel, and in the first direction, the third color sub-pixel is staggered with the adjacent first color sub-pixel or the second color sub-pixel;

[0036] Optionally, the first color sub-pixel is a red sub-pixel, the second color sub-pixel is a blue sub-pixel, and the third color sub-pixel is a green sub-pixel;

[0037] Optionally, the orthographic projection area of ​​the first color sub-pixel on the substrate is smaller than the orthographic projection area of ​​the second color sub-pixel on the substrate, and the orthographic projection area of ​​the third color sub-pixel on the substrate is smaller than the orthographic projection area of ​​the first color sub-pixel on the substrate.

[0038] Optionally, the orthographic projection of the first color sub-pixel on the substrate covers the orthographic projection of the third routing segment and the first routing segment on the substrate; the orthographic projection of the first color sub-pixel on the substrate does not overlap with the orthographic projection of the second power routing segment on the substrate;

[0039] Optionally, the orthographic projection of the second color sub-pixel on the substrate covers the orthographic projections of the third routing segment and the first routing segment on the substrate, and at least partially covers the orthographic projection of the second power routing segment on the substrate;

[0040] Optionally, the orthographic projection of the third color sub-pixel on the substrate covers the orthographic projection of the second routing segment and the second power routing adjacent to the substrate at the second interval.

[0041] In a second aspect, an embodiment of the present invention provides a display device, comprising the display panel described in any embodiment of the present invention.

[0042] The display panel provided by the embodiment of the present invention is provided with a first power supply line extending along a first direction on a first conductive layer adjacent to the light-emitting functional layer. In the first direction, the first power supply lines between adjacent sub-pixels on the light-emitting functional layer are an integrated structure, so that each row of sub-pixels has a first power supply line passing through it, and lines running or extending along the first direction can be provided in the sub-pixels, thereby improving the consistency of the substrate structure under the sub-pixels, reducing color deviation under different viewing angles, and improving the display uniformity of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A schematic diagram of a partial structure of a display panel in the related art;

[0044] Figure 2 A schematic diagram of the structure of a display panel is provided for an embodiment of the present invention;

[0045] Figure 3 for Figure 2 A schematic cross-sectional view of AA' of a sub-pixel D;

[0046] Figure 4 A schematic structural diagram of a sub-pixel D is provided for an embodiment of the present invention;

[0047] Figure 5A structural schematic diagram of another display panel is provided for an embodiment of the present invention;

[0048] Figure 6 A schematic diagram of the structure of another display panel provided in an embodiment of the present invention;

[0049] Figure 7 A schematic diagram of the structure of a third power supply line provided in an embodiment of the present invention;

[0050] Figure 8 A schematic structural diagram of a display device is provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0052] Figure 1 The schematic diagram of a partial structure of a display panel in the related art, wherein a flat layer 120, a first electrode layer 130, a pixel definition layer 140, a light-emitting layer 150 and a second electrode layer are sequentially stacked on one side of a substrate 100. The first electrode layer includes a plurality of first electrodes, and a plurality of pixel openings are provided on the pixel definition layer 140, wherein the pixel openings can expose a portion of the first electrode, and the light-emitting layer 150 is located at the pixel openings and connected to the first electrodes. Each pixel opening constitutes a sub-pixel D, and the adjacent conductive layers 110 under the sub-pixel D have signal wires 111 arranged and connected differently, so that related signal wires 111 exist in some sub-pixels D, while related signal wires 111 do not exist in other sub-pixels D, resulting in different substrates under different sub-pixels D in the display panel, thereby causing large color changes of different sub-pixels D under different viewing angles, resulting in uneven display.

[0053] In view of this, Figure 2 A schematic diagram of the structure of a display panel is provided in accordance with an embodiment of the present invention. Figure 3 for Figure 2 A schematic cross-sectional view of AA' of a sub-pixel D in FIG. Figure 2 and Figure 3 ,include:

[0054] Substrate 100;

[0055] The light-emitting functional layer is located on one side of the substrate 100; the light-emitting functional layer has a plurality of sub-pixels D;

[0056] The first conductive layer 210 is located between the substrate 100 and the light-emitting functional layer; the first conductive layer 210 includes a first power supply line 220 extending along a first direction X;

[0057] The orthographic projection of the sub-pixel D on the substrate 100 at least overlaps with the orthographic projection of the first power line 220 on the substrate 100; the orthographic projection of at least part of the sub-pixel D on the substrate 100 overlaps with the orthographic projection of the second power line 230 on the substrate 100; and in the first direction X, the first power line 220 between adjacent sub-pixels D is an integrated structure.

[0058] Specifically, the substrate 100 can provide buffering, protection or support for the display panel. The substrate 100 can be a flexible substrate, and the material of the flexible substrate can be polyimide (PI), polyethylene naphthalate (PEN) or polyethylene terephthalate (PET), etc., or a mixture of the above materials. The substrate 100 can also be a hard substrate formed of materials such as glass.

[0059] A plurality of conductive layers are arranged on one side of the substrate 100, and only the first conductive layer 210 is shown in the figure as an example. The plurality of conductive layers are isolated from each other by insulating layers. A pixel circuit is formed in the plurality of conductive layers, and the pixel circuit can provide a driving signal to the light-emitting device in the light-emitting functional layer to drive the light-emitting device to emit light. Figure 1 , the light-emitting functional layer may include a first electrode layer 130, a light-emitting layer 150, and a second electrode layer. The first electrode layer 130, the light-emitting layer 150, and the second electrode layer may form a plurality of light-emitting devices, each of which includes an anode, a light-emitting layer, and a cathode. Each light-emitting device may be electrically connected to a pixel circuit through an anode, so that the pixel circuit provides a driving signal to the light-emitting device to drive the light-emitting device to emit light. Among them, each pixel opening constitutes a sub-pixel D. In the multi-layer conductive layer, the conductive layer closest to the display functional layer in the thickness direction of the display panel is usually used to set the power supply line of the pixel circuit. The conductive layer here may be recorded as a first conductive layer 210. The first conductive layer 210 includes a first power supply line 220. The first power supply line 220 is configured to provide a first power supply voltage. Exemplarily, the first power supply line 220 may be configured to provide a first power supply voltage ELVDD.

[0060] The first power supply line 220 extends along the first direction X. In the first direction X, the first power supply line 220 passes through the entire display panel. The first power supply line 220 may pass through the sub-pixels D arranged along the first direction X. The first power supply lines 220 between adjacent sub-pixels D are an integrated structure, that is, each row of sub-pixels D has a first power supply line 220 passing through it. A line running or extending along the first direction X may be provided in each sub-pixel D.

[0061] The display panel provided by the embodiment of the present invention is provided with a first power line 220 extending along the first direction X on the first conductive layer 210 adjacent to the light-emitting functional layer. In the first direction X, the first power lines 220 between adjacent sub-pixels D on the light-emitting functional layer are an integrated structure, so that each row of sub-pixels D has a first power line 220 passing through it, and a line running or extending along the first direction X can be provided in the sub-pixel D, thereby improving the consistency of the structure of the substrate 100 under the sub-pixel D, reducing the color deviation under different viewing angles, and improving the display uniformity of the display panel.

[0062] Optionally, the first conductive layer 210 further includes a second power supply line 230 extending along the first direction X; in the second direction Y, the first power supply line 220 and the second power supply line 230 are alternately arranged, and the first direction X intersects with the second direction Y; the orthographic projection of at least one sub-pixel D on the substrate 100 does not overlap with the orthographic projection of the second power supply line 230 on the substrate 100.

[0063] Specifically, the first conductive layer 210 includes a first power supply line 220 and a second power supply line 230. The first power supply line 220 can be configured to provide a first power supply voltage, and the second power supply line 230 can be configured to provide a second power supply voltage. The power supply voltages configured for the first power supply line 220 and the second power supply line 230 are different. Exemplarily, the first power supply voltage is greater than the second power supply voltage, the first power supply line 220 is configured to provide a first power supply voltage ELVDD, and the second power supply line 230 is configured to provide a second power supply voltage ELVSS.

[0064] The first power trace 220 and the second power trace 230 are disposed in the same layer and extend along the first direction X. In the second direction Y, the first power trace 220 and the second power trace 230 are alternately arranged. Exemplarily, the first direction X and the second direction Y are perpendicular. According to the size distribution of different sub-pixels D, the orthographic projection of the sub-pixel D on the substrate 100 can be overlapped with the orthographic projection of the second power line 230 on the bottom 100; or the orthographic projection of the sub-pixel D on the substrate 100 can be non-overlapped with the orthographic projection of the second power line 230 on the bottom 100; or the orthographic projection of a part of the sub-pixel D on the substrate 100 can be overlapped with the orthographic projection of the second power line 230 on the bottom 100, and the orthographic projection of a part of the sub-pixel D on the substrate 100 can be non-overlapped with the orthographic projection of the second power line 230 on the bottom 100. Since the first power line 220 running or extending along the first direction X can be provided in the sub-pixel D, whether the second power line 230 exists in the sub-pixel D will not affect the routing trend running or extending along the first direction X, thereby reducing the influence of the second power line 230 on the consistency of the substrate 100 structure under the sub-pixel D.

[0065] Furthermore, the undulation of the first power supply line 220 and the second power supply line 230 under the sub-pixel D will also affect the flatness of the planarization layer, thereby causing the anode to tilt, causing the problem of uneven display of the light-emitting device. Therefore, in some embodiments, in the sub-pixel D, the first power supply line 220 is symmetrical about the center line of the sub-pixel D in the second direction Y. If the orthographic projection of the sub-pixel D on the substrate 100 overlaps with the orthographic projection of the second power supply line 230 on the substrate 100, the second power supply line 230 is symmetrical about the center line of the sub-pixel D in the second direction Y.

[0066] Specifically, according to the arrangement of sub-pixels D, Figure 4 A schematic diagram of the structure of a sub-pixel D is provided in an embodiment of the present invention. Figure 4 , the first power line 220 and the second power line 230 both pass through the sub-pixel D. The first power line 220 in the sub-pixel D is symmetrical about the center line L1 of the sub-pixel D in the second direction Y, and the second power line 230 is symmetrical about the center line L1 of the sub-pixel D in the second direction Y. This can balance the fluctuation of the first electrode on both sides of the center line L1 of the sub-pixel D, thereby making the viewing angles of the sub-pixel D on both sides of the center line L1 approximately consistent, which helps to balance the display differences of the display panel at different viewing angles, so as to improve the color deviation problem of the display panel and thus improve the display uniformity. Combined with Figure 2 If only the first power line 220 passes through the sub-pixel D, the first power line 220 in the sub-pixel D is symmetrical about the center line L1 of the sub-pixel D in the second direction Y, which can also improve the display uniformity.

[0067] It should be noted that, in the second direction Y, the spacing between the first power line 220 and the second power line 230 can be selected as a uniform spacing according to the arrangement of the sub-pixels D and the circuit layout, that is, the spacing between the first power line 220 and the second power line 230 is the same. It can also be selected as an unequal spacing. In the embodiment of the present invention, the spacing between the first power line 220 and the second power line 230 is alternately arranged with a first spacing and a second spacing, wherein the first spacing is greater than the second spacing. By using different spacings, sub-pixels D of different sizes can be arranged in the space of the first spacing or the second spacing.

[0068] Continue to see Figure 2 , Optionally, the first power supply line 220 includes a first line segment 221 and a second line segment 222;

[0069] In the first direction X, the first routing segment 221 and the second routing segment 222 are alternately arranged, and the first routing segment 221 and the second routing segment 222 are connected to each other; in the second direction Y, the first routing segment 221 and the second routing segment 222 are staggered;

[0070] In the same sub-pixel D, the orthographic projection of the sub-pixel D on the substrate 100 overlaps with the orthographic projection of the first wiring segment 221 on the substrate 100; or, the orthographic projection of the sub-pixel D on the substrate 100 overlaps with the orthographic projection of the second wiring segment 222 on the substrate 100;

[0071] Specifically, in the first direction X, the first routing segments 221 and the second routing segments 222 are alternately arranged, and the first routing segments 221 and the second routing segments 222 adjacent in the first direction X are staggered in the second direction Y. The staggered distance between the first routing segments 221 and the second routing segments 222 in the second direction Y can be selected and set according to the arrangement of the sub-pixels D of the display panel. By adjusting the staggered distance between the first routing segments 221 and the second routing segments 222 in the second direction Y, a more flexible arrangement space for sub-pixels D of different sizes in the second direction Y can be provided.

[0072] In the first direction X, the adjacent first routing segments 221 and second routing segments 222 are connected to each other, that is, the first routing segments 221 and the second routing segments 222 form a continuous signal routing in the first direction X to achieve signal transmission in the first direction X. In combination with the arrangement of the sub-pixels D, in the first direction X, the first routing segment 221 can be used to pass through one sub-pixel D, and then the adjacent second routing segment 222 can be used to pass through another adjacent sub-pixel D, so that each row of sub-pixels D has a first power routing line 220 passing through it, thereby improving the consistency of the material of the substrate 100 under the sub-pixels D, reducing the color deviation under different viewing angles, and improving the display uniformity.

[0073] Furthermore, the first routing segment 221 and the second routing segment 222 can be symmetrical about the center line L1 of their respective sub-pixels D in the second direction Y, thereby balancing the fluctuation of the first electrode on both sides of the center line L1 of the sub-pixel D to improve the color deviation problem of the display panel, thereby improving display uniformity.

[0074] Optionally, Figure 5 A structural diagram of another display panel is provided for an embodiment of the present invention, see Figure 5 ; The first power supply line 220 also includes a third line segment 223;

[0075] The third routing segment 223 is arranged between the first power routing segment 220 and the second power routing segment 230 of the first spacing, wherein one end of the third routing segment 223 is connected to the first routing segment 221; the other end of the third routing segment 223 is extended along the second direction Y, and the orthographic projection of the third routing segment 223 on the substrate 100 does not overlap with the orthographic projection of the second power routing segment 230 on the substrate 100;

[0076] Specifically, one end of the third routing segment 223 is connected to the first routing segment 221, so the third routing segment 223 and the first power routing line 220 are configured to provide the same power supply voltage. The other end of the third routing segment 223 extends along the second direction Y, and the third routing segment 223 does not intersect with the second power routing line 230, so as to avoid the third routing segment 223 from contacting with the second power routing line 230 and causing a signal short circuit. By setting the third routing segment 223 in the second direction Y, it is equivalent to increasing the effective area in the display panel that can provide the first power supply voltage, which is conducive to reducing the routing length of the transistor that needs to be connected to the first power supply voltage in the pixel circuit.

[0077] Optionally, the third routing segment 223 is arranged at intervals with the first routing segment 221 in the first direction X, and according to the size of the sub-pixel D, the orthographic projection of the third routing segment 223 on the substrate 100 is located within the orthographic projection of the sub-pixel D on the substrate 100. Optionally, the orthographic projection of the third routing segment 223 on the substrate 100 coincides with the orthographic projection of the center line L1 of the sub-pixel D in the second direction Y on the substrate 100, that is, the third routing segment 223 is located on the center line L1 of the sub-pixel D. Therefore, when the size of the sub-pixel D is relatively large, the first routing segment 221, the third routing segment 223, and the portion of the second power routing 230 adjacent to each other at the first spacing may exist in the sub-pixel D, and the first routing segment 221, the third routing segment 223, and the portion of the second power routing 230 are in a symmetrical form similar to an "I" shape, thereby improving the undulation on both sides of the center line L1 of the sub-pixel D, and thereby making the viewing angles of the sub-pixel D on both sides of the center line L1 approximately consistent, which helps to balance the display differences of the display panel at different viewing angles, thereby improving display uniformity. When the size of the sub-pixel D is relatively small, the first routing segment 221 and the third routing segment 223 exist in the sub-pixel D, and the first routing segment 221 and the third routing segment 223 are in a symmetrical form similar to a "T" shape, which also helps to balance the display differences of the display panel at different viewing angles, thereby improving display uniformity.

[0078] Optionally, to facilitate the array design of the first routing segment 221, the second routing segment 222, the second power routing line 230, and the third routing segment 223 in the display panel, the first routing segment 221 can be arranged in the same column, and the second routing segment 222 can be arranged in the same column in the second direction Y. In addition, in the second direction Y, the extension lines of adjacent third routing segments 223 can be located in the same straight line.

[0079] Figure 6 FIG. 1 is a schematic diagram of a structure of another display panel provided in an embodiment of the present invention. Figure 6 , the display panel further includes: a connecting portion 310 and a second conductive layer; the second conductive layer is located on a side of the first conductive layer 210 away from the substrate 100;

[0080] The second conductive layer includes a third power line 320 extending along the second direction Y, wherein the third power line 320 is connected to the first power line 220 through the connecting portion 310;

[0081] Specifically, when the first power supply line 220 is configured to provide the first power supply voltage ELVDD, the first power supply line 220 is used to transmit a power supply signal to the pixel circuit in the display panel. In order to reduce the resistance of the first power supply line 220, a second conductive layer can be provided on the side of the first conductive layer 210 away from the substrate 100, and a third power supply line 320 extending along the second direction Y can be provided on the second conductive layer. The third power supply line 320 is electrically connected to the first power supply line 220 through the connecting portion 310, thereby forming a mesh power transmission.

[0082] Optionally, the connection portion 310 is disposed in an overlapping region of an orthographic projection of the third power line 320 on the substrate 100 and an orthographic projection of the first power line 220 on the substrate 100 .

[0083] Specifically, the orthographic projections of the third power supply line 320 and the first power supply line 220 on the substrate 100 have at least a partial overlapping area, so they can be electrically connected to each other through the connecting portion 310 in the overlapping area. Each third power supply line 320 can form a parallel structure with the corresponding first power supply line 220, thereby reducing the resistance of the power supply line, so as to reduce the power supply voltage difference between the display area near the bottom of the display panel and the display area near the top of the display panel, thereby improving the display uniformity of the display panel. Exemplarily, the connecting portion 310 can be a via, and the via can penetrate the insulating layer of the overlapping area to expose part of the third power supply line 320 and the first power supply line 220, so that the third power supply line 320 is in contact with the first power supply line 220, thereby avoiding bridging the lines and saving the layout space of the display panel.

[0084] Optionally, the second conductive layer further includes a data signal line 330 extending along the second direction Y; the data signal line 330 is arranged between adjacent third power lines 320 in the first direction X.

[0085] Specifically, the data signal line 330 is configured to provide a data voltage data, and the data signal line 330 is used to transmit a data signal to a pixel circuit in the display panel. The data signal line 330 is arranged between adjacent third power lines 320, and in order to make the upper structure flat, the line widths of the third power line 320 and the data signal line 330 can be different. In order to further improve the flatness of the upper structure, optionally, the orthographic projection of the data signal line 330 on the substrate 100 coincides with the orthographic projection of the center line L1 of the sub-pixel D in the second direction Y on the substrate 100, that is, the data signal line 330 can be arranged in parallel with the third line segment 223 in the thickness of the display panel, and the data signal line 330 is located parallel to and above the third line segment 223. The data signal line 330 is also located on the center line L1 of the sub-pixel D, thereby reducing the impact of the data signal line 330 on the edge flatness of the sub-pixel D, reducing the degree of warping of the edge of the sub-pixel D, and making the viewing angles of the sub-pixel D on both sides of the center line L1 approximately consistent, which helps to improve display uniformity.

[0086] Optionally, the second conductive layer further includes at least two signal traces 340 extending along the second direction Y; the signal traces are symmetrically arranged between adjacent third power traces 320 in the first direction X with respect to the third power traces 320 .

[0087] Specifically, the data signal line 330 is located at the center line L1 of the sub-pixel D, and the signal lines 340 are respectively arranged on both sides of the data signal line 330. The first signal line 340 and the second signal line 340 are symmetrically distributed about the data signal line 330. The first signal line 340 and the second signal line 340 can provide an approximate undulation to the upper flat layer, so that the viewing angles on both sides of the center line L1 in the sub-pixel D are approximately consistent, which helps to balance the display differences of the display panel under different viewing angles, so as to improve the color deviation problem of the display panel, thereby improving the display uniformity. It should be noted that the signal line 340 can be configured to provide a signal according to the line requirements. For example, the signal line 340 can be configured as a second power supply voltage or a data signal. The signal line 340 can also be used as a connecting line connecting the driver chip and the data signal line 330. The signal line 340 can also be a dummy line without a configured signal.

[0088] Figure 7This is a schematic diagram of the structure of the third power supply line provided in an embodiment of the present invention. The third power supply line 320 is provided with hollow portions 321 at intervals along the second direction Y. The hollow portions 321 can improve the light transmittance of the display panel, avoid blocking the light and reduce the impact on the photosensitive device under the screen. And the position of the hollow portion 321 can provide an escape space for the connection structure such as the lower layer via. The positive projection of the solid portion 322 between the adjacent hollow portions 321 on the substrate 100 at least partially covers the positive projection of the first power supply line 220 and the second power supply line 230 on the substrate 100. In other words, part of the first power supply line 220 and the second power supply line 230 in the first direction X are arranged in the lower layer of the solid portion 322, and the first power supply line 220 and the second power supply line 230 use the already blocked area to complete the routing, thereby reducing the occupation of the first power supply line 220 and the second power supply line 230 on other unblocked wiring space, and further improving the light transmittance of the display panel. Optionally, the orthographic projection of the entity portion 322 on the substrate 100 at least partially covers the orthographic projection of the second routing segment 222 on the substrate 100 and the orthographic projection of the second power routing line 230 adjacent to the second spacing on the substrate 100. In other words, by using the entity portion 322 to shield the second routing segment 222 and part of the second power routing line 230 at the second spacing, it is possible to avoid the entity portion 322 being too long in the second direction Y, while enabling the second routing segment 222 and part of the second power routing line 230 to complete routing by using the already shielded area.

[0089] Continue to see Figure 6 , the plurality of sub-pixels D include a first color sub-pixel D1, a second color sub-pixel D2, and a third color sub-pixel D3;

[0090] In the first direction X, the first color sub-pixels D1 and the second color sub-pixels D2 are alternately arranged in a row; in the first direction X, the first color sub-pixels D1 and the second color sub-pixels D2 are alternately arranged in a column;

[0091] In the second direction Y, the third color sub-pixel D3 is located between the first color sub-pixel D1 and the second color sub-pixel D2 , and in the first direction X, the third color sub-pixel D3 is alternately arranged with the adjacent first color sub-pixel D1 or second color sub-pixel D2 .

[0092] Specifically, the luminous color corresponding to each sub-pixel D is determined according to the material characteristics of the organic layer. For example, the first color sub-pixel D1 is a red sub-pixel D, the second color sub-pixel D2 is a blue sub-pixel D, and the third color sub-pixel D3 is a green sub-pixel D. That is, the luminous color of the organic layer of the first color sub-pixel D1 is red, the luminous color of the organic layer of the second color sub-pixel D2 is blue, and the luminous color of the organic layer of the third color sub-pixel D3 is green. The sizes of the sub-pixels D may also be different. In the embodiment of the present invention, the orthographic projection area of ​​the red sub-pixel D on the substrate 100 is smaller than the orthographic projection area of ​​the blue sub-pixel D on the substrate 100, and the orthographic projection area of ​​the green sub-pixel D on the substrate 100 is smaller than the orthographic projection area of ​​the red sub-pixel D on the substrate 100.

[0093] In the first direction X and the second direction Y, the red sub-pixels D and the blue sub-pixels D are alternately arranged to form a matrix arrangement. The green sub-pixels D are arranged between the red sub-pixels D and the blue sub-pixels D and are staggered in the first direction X and the second direction Y. For example, the green sub-pixels D are located on the extension line perpendicular to the middle line between the red sub-pixels D and the blue sub-pixels D in adjacent rows, and the green sub-pixels D are located on the extension line perpendicular to the middle line between the red sub-pixels D and the blue sub-pixels D in adjacent columns, forming a pentile arrangement. This arrangement can reduce the number of sub-pixels while improving display brightness.

[0094] Based on the above embodiment, optionally, the orthographic projection of the first color sub-pixel D1 on the substrate 100 covers the orthographic projections of the first routing segment 221 and the third routing segment 223 on the substrate 100, and the orthographic projection of the first color sub-pixel D1 on the substrate 100 does not overlap with the orthographic projection of the second power routing line 230 on the substrate 100.

[0095] Specifically, the orthographic projection of the third routing segment 223 on the substrate 100 is located within the orthographic projection on the substrate 100, the third routing segment 223 coincides with the center line L1 of the first color sub-pixel D1 in the second direction Y, the second power routing line 230 does not pass through the first color sub-pixel D1, and the first routing segment 221 and the third routing segment 223 are approximately "T"-shaped symmetrical in the first color sub-pixel D1. When the second conductive layer is provided, the data signal routing line 330 is also located on the center line L1 of the sub-pixel D. Furthermore, the signal routing lines 340 symmetrical on both sides of the data signal routing line 330 can provide an approximate undulation to the upper flat layer, so that the viewing angles on both sides of the center line L1 in the sub-pixel D are approximately consistent, which helps to balance the display differences of the first color sub-pixel D1 under different viewing angles, so as to improve the color deviation problem of the display panel, thereby improving the display uniformity.

[0096] Optionally, the orthographic projection of the second color sub-pixel D2 on the substrate 100 covers the orthographic projections of the third routing segment 223 and the first routing segment 221 on the substrate 100, and at least partially covers the orthographic projection of the second power routing line 230 on the substrate 100;

[0097] Specifically, the second color sub-pixel D2 contains the first routing segment 221, the third routing segment 223 and part of the second power routing 230, and the first routing segment 221, the third routing segment 223 and part of the second power routing 230 are in a symmetrical form similar to an "I" shape. Similarly, when a second conductive layer is provided, the data signal routing 330 is also located on the center line L1 of the sub-pixel D. Furthermore, the signal routings 340 symmetrical on both sides of the data signal routing 330 can provide similar undulations to the upper flat layer, so that the viewing angles on both sides of the center line L1 in the sub-pixel D are approximately consistent, which helps to balance the display differences of the first color sub-pixel D1 under different viewing angles, so as to improve the color deviation problem of the display panel, thereby improving the display uniformity.

[0098] Optionally, the orthographic projection of the third color sub-pixel D3 on the substrate 100 covers the orthographic projection of the second routing segment 222 and the second power routing line 230 adjacent to the substrate 100 at the second interval.

[0099] Specifically, the second routing segment 222 and part of the second power routing line 230 are present in the third color sub-pixel D3, and the second routing segment 222 and part of the second power routing line 230 are in a symmetrical form that is approximately "two". When the second conductive layer is provided, the positive projection of the solid portion 322 in the third power routing line 320 at least partially covers the second routing segment 222, that is, the second routing segment 222 and part of the second power routing line 230 are located below the solid portion 322, and the second routing segment 222 and part of the second power routing line 230 in the third color sub-pixel D3 complete the routing by using the already blocked area, thereby reducing the occupation of other wiring space by the second routing segment 222 and part of the second power routing line 230, and improving the light transmittance of the display panel.

[0100] The embodiment of the present invention further provides a display device. Figure 8 As shown, the display device 20 includes a display panel 21 provided by any embodiment of the present invention.

[0101] Specifically, the display panel 21 is a display panel provided by any embodiment of the present invention. When the display device 20 includes the display panel provided by any embodiment of the present invention, it has the same beneficial effects as the display panel 21 provided by any embodiment of the present invention, which will not be described in detail here. The display device 20 can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, etc., which is not limited here.

[0102] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: include: substrate; A light-emitting functional layer is located on one side of the substrate; The light-emitting functional layer has a plurality of sub-pixels; A first conductive layer is located between the substrate and the light-emitting functional layer; the first conductive layer includes a first power supply line extending along a first direction; The orthographic projection of the sub-pixel on the substrate at least overlaps with the orthographic projection of the first power line on the substrate; and in the first direction, the first power line between adjacent sub-pixels is an integrated structure.

2. The display panel according to claim 1, characterized in that: The first conductive layer further includes a second power supply line extending along the first direction, wherein the first power supply line and the second power supply line are alternately arranged in the second direction, and the first direction intersects with the second direction; An orthographic projection of at least one of the sub-pixels on the substrate does not overlap with an orthographic projection of the second power supply line on the substrate; Preferably, in the sub-pixel, the first power supply line is symmetrical about a center line of the sub-pixel in the second direction; Preferably, in the sub-pixel, if the orthographic projection of the sub-pixel on the substrate overlaps with the orthographic projection of the second power line on the substrate, the second power line is symmetrical about the center line of the sub-pixel in the second direction; Preferably, in the second direction, the spacing between the first power wiring and the second power wiring is alternately arranged as a first spacing and a second spacing, and the first spacing is greater than the second spacing.

3. The display panel according to claim 2, characterized in that: The first power supply line is configured to provide a first power supply voltage, the second power supply line is configured to provide a second power supply voltage, and the first power supply voltage is greater than the second power supply voltage; Preferably, the first power supply line includes a first line segment and a second line segment; In the first direction, the first routing segment and the second routing segment are alternately arranged, and the first routing segment and the second routing segment are connected to each other; in the second direction, the first routing segment and the second routing segment are staggered; In the same sub-pixel, an orthographic projection of the sub-pixel on the substrate overlaps with an orthographic projection of the first routing segment on the substrate; or an orthographic projection of the sub-pixel on the substrate overlaps with an orthographic projection of the second routing segment on the substrate; Preferably, the first power supply routing line further includes: a third routing line segment; The third routing segment is arranged between the first power routing segment and the second power routing segment at the first interval, wherein one end of the third routing segment is connected to the first routing segment; the other end of the third routing segment is extended along the second direction, and the orthographic projection of the third routing segment on the substrate does not overlap with the orthographic projection of the second power routing segment on the substrate; Preferably, an orthographic projection of the third wiring segment on the substrate coincides with an orthographic projection of a center line of the sub-pixel in the second direction on the substrate; Preferably, in the second direction, extension lines of adjacent third routing segments are located on the same straight line.

4. The display panel according to claim 3, characterized in that: The display panel further comprises: a connecting portion and a second conductive layer; the second conductive layer is located on a side of the first conductive layer away from the substrate; The second conductive layer includes a third power line extending along the second direction, wherein the third power line is connected to the first power line through the connecting portion; Preferably, the connecting portion is arranged in an overlapping area of ​​an orthographic projection of the third power line on the substrate and an orthographic projection of the first power line on the substrate; Preferably, the connecting portion comprises a via hole, and the via hole penetrates the insulating layer between the third power line and the first power line.

5. The display panel according to claim 4, characterized in that: The second conductive layer further comprises a data signal line extending along the second direction; the data signal line is arranged between the third power supply lines adjacent to each other in the first direction; Preferably, an orthographic projection of the data signal wiring on the substrate coincides with an orthographic projection of a center line of the sub-pixel in the second direction on the substrate.

6. The display panel according to claim 5, characterized in that: The second conductive layer further includes at least two signal traces extending along the second direction; The signal wiring is symmetrically arranged with respect to the third power wiring and between the third power wirings adjacent to each other in the first direction.

7. The display panel according to any one of claims 4 to 6, characterized in that: Hollow portions are arranged at intervals on the third power supply line along the second direction, and the orthographic projection of the solid portion between adjacent hollow portions on the substrate at least partially covers the orthographic projection of the first power supply line and the second power supply line on the substrate; Preferably, the orthographic projection of the entity portion on the substrate at least partially covers the orthographic projection of the second routing segment on the substrate and the orthographic projection of the second power routing line adjacent to the second spacing on the substrate.

8. The display panel according to claim 7, characterized in that: The plurality of sub-pixels include a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel; The first color sub-pixels and the second color sub-pixels are alternately arranged in a row along the first direction; the first color sub-pixels and the second color sub-pixels are alternately arranged in a column along the second direction; In the second direction, the third color sub-pixel is located between the first color sub-pixel and the second color sub-pixel, and in the first direction, the third color sub-pixel is staggered with the adjacent first color sub-pixel or the second color sub-pixel; Preferably, the first color sub-pixel is a red sub-pixel, the second color sub-pixel is a blue sub-pixel, and the third color sub-pixel is a green sub-pixel; Preferably, the orthographic projection area of ​​the first color sub-pixel on the substrate is smaller than the orthographic projection area of ​​the second color sub-pixel on the substrate, and the orthographic projection area of ​​the third color sub-pixel on the substrate is smaller than the orthographic projection area of ​​the first color sub-pixel on the substrate.

9. The display panel according to claim 8, characterized in that: The orthographic projection of the first color sub-pixel on the substrate covers the orthographic projection of the third routing segment and the first routing segment on the substrate; the orthographic projection of the first color sub-pixel on the substrate does not overlap with the orthographic projection of the second power routing segment on the substrate; Preferably, the orthographic projection of the second color sub-pixel on the substrate covers the orthographic projections of the third routing segment and the first routing segment on the substrate, and at least partially covers the orthographic projection of the second power routing line on the substrate; Preferably, the orthographic projection of the third color sub-pixel on the substrate covers the orthographic projection of the second routing segment and the second power routing adjacent to the substrate at the second interval.

10. A display device, characterized in that: A display panel comprising any one of claims 1 to 9.

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