Method for manufacturing a memory device including a capacitor

Abstract

A method for manufacturing a memory device including capacitors is disclosed. In one aspect, a method for manufacturing a memory device including capacitors is described, wherein each capacitor includes a first electrode and a second electrode separated by an isolation layer. The method includes: providing a first wafer including a sacrificial material and a first electrode disposed in a first via and in contact with the sacrificial material; co-bonding the first wafer with a second wafer including a complementary metal-oxide-semiconductor (CMOS) device; removing the sacrificial material to expose the first electrode; depositing an isolation layer on the first electrode; and forming a second electrode on the isolation layer.

Description

Technical Field

[0001] This specification relates to the field of semiconductor technology, and more specifically, to methods of manufacturing memory devices including capacitors. Background Technology

[0002] As memory devices shrink to smaller die sizes to reduce manufacturing costs and increase memory density, scaling planar memory cells faces challenges due to process technology limitations and reliability issues. Three-dimensional (3D) memory architectures can address the density and performance limitations of planar memory cells by vertically stacking memory cells or by using memory cells with vertical transistors.

[0003] 3D memory architectures typically include multiple arrays of memory cells and peripheral devices for managing data fed to and from the memory cells. Such memory cells (e.g., DRAM cells) typically include capacitors for storing data bits, such as metal-oxide-silicon (MOS) capacitors, metal-oxide-metal (MOM) capacitors, or polysilicon-oxide-polysilicon (POP) capacitors. The trend in 3D memory is towards higher density memory cells to increase data storage capacity. However, to reduce manufacturing costs, the dedicated silicon area of ​​memory chips remains largely unchanged. Summary of the Invention

[0004] This specification describes a method for manufacturing a memory device including a capacitor. According to some embodiments, the method may employ one or more high-temperature processes using a sacrificial material to replace a high-k material. After the high-temperature process, the sacrificial material can be removed, and subsequently, a high-k material can be deposited.

[0005] In a first aspect, a method for manufacturing a memory device including capacitors is described, wherein each capacitor includes a first electrode and a second electrode separated by an isolation layer. The method includes: providing a first wafer including a sacrificial material and a first electrode disposed in a first via and in contact with the sacrificial material; co-bonding the first wafer with a second wafer including a complementary metal-oxide-semiconductor (CMOS) device; removing the sacrificial material to expose the first electrode; depositing an isolation layer on the first electrode; and forming a second electrode on the isolation layer.

[0006] In a second aspect, a method for manufacturing a memory device including capacitors is described, wherein each capacitor includes a first electrode and a second electrode separated by an isolation layer. The method includes: providing a first wafer including a sacrificial material and a first electrode disposed in a first aperture and in contact with the sacrificial material; heat-treating the first wafer; removing the sacrificial material to expose the first electrode; depositing an isolation layer on the first electrode; and forming a second electrode on the isolation layer.

[0007] In a third aspect, a memory device includes a first wafer and a second wafer, the first wafer including a capacitor and the second wafer including a CMOS device, wherein the second wafer is co-bonded to the first wafer. Each capacitor includes a first electrode and a second electrode separated by an isolation layer, wherein the isolation layer includes a dielectric material having a dielectric constant of 5 or greater.

[0008] In a fourth aspect, a system includes a memory device and a memory controller electrically connected to the memory device, wherein the memory controller is configured to control the memory device. The memory device includes a storage plane comprising a first wafer and a second wafer, the first wafer including a capacitor and the second wafer including a CMOS device, wherein the second wafer is co-bonded to the first wafer. Each capacitor includes a first electrode and a second electrode separated by an isolation layer, wherein the isolation layer comprises a dielectric material having a dielectric constant of 5 or greater.

[0009] Details of one or more embodiments of the subject matter of this specification are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. Attached Figure Description

[0010] Figure 1A This is a cross-sectional view depicting an example of a memory device.

[0011] Figure 1B This is a cross-sectional view depicting another example of a memory device.

[0012] Figure 2A This is a schematic diagram illustrating an example of a memory device comprising an array of peripheral circuitry and memory cells, each memory cell having a vertical transistor.

[0013] Figure 2B This is a schematic circuit diagram illustrating an example of a memory device including peripheral circuitry and an array of dynamic random access memory (DRAM) cells.

[0014] Figures 3A-3D This is a cross-sectional view depicting different stages of an exemplary manufacturing method for a memory device, including a capacitor.

[0015] Figures 4A-4C This is a flowchart of an exemplary process for manufacturing a memory device with capacitors.

[0016] Figure 5A and Figure 5B These are, respectively, a top view and a cross-sectional view depicting an example of a semiconductor wafer fabricated for use in manufacturing memory devices.

[0017] Figures 6A-6L These are various views depicting different stages of an exemplary manufacturing method for a memory device, including cylindrical capacitors.

[0018] Figures 7A-7E These are various views depicting different stages of an exemplary manufacturing method for a memory device, including a cup-shaped capacitor.

[0019] Figure 8 It is a block diagram depicting an example of a system including one or more memory devices and a memory controller. Detailed Implementation

[0020] Specific embodiments of the subject matter described in this specification may be implemented to achieve one or more of the following advantages.

[0021] This disclosure describes a method for manufacturing a memory device, in some embodiments of which can be adapted to one or more high-temperature processes while preventing the failure of the high-k dielectric of the memory device's capacitors. Specifically, during the high-temperature process, this disclosure employs a sacrificial material to replace the high-k material. By introducing the high-k material after the high-temperature process has been completed, the dielectric constant of the high-k material does not deteriorate compared to other manufacturing methods, and capacitors with higher quality characteristics (e.g., increased capacitance) can be formed. In some instances, the capacitors (e.g., vertical capacitors) can provide improved performance for the entire memory device and / or facilitate smaller feature sizes for the memory device. Therefore, higher-density components (e.g., DRAM cells) can be incorporated on a wafer (e.g., a silicon wafer) to increase the storage capacity of the memory device and improve functionality (e.g., reduced latency and memory cell programming errors).

[0022] Reference will now be made in detail to the exemplary embodiments illustrated in the accompanying drawings in order to understand and implement this disclosure and achieve the technical effects. It is understood that the following description has been made by way of example only and not by way of limitation. Various embodiments of this disclosure, and various non-conflicting features within those embodiments, can be combined and rearranged in various ways. Modifications, equivalents, or improvements to this disclosure will be understood by those skilled in the art without departing from the spirit and scope of this disclosure, and they are intended to be covered within the scope of this disclosure.

[0023] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0024] Generally, terms can be understood at least in part from their usage in context. For example, depending at least in part from the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part from the context, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage.

[0025] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on” but also includes “on” with an intermediate feature or layer between them, and that “above” or “on top of” means not only “above” or “on top of” but also includes “above” or “on top of” without an intermediate feature or layer between them (i.e., directly on).

[0026] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or feature and another (or more) elements or features as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and similarly, the spatial relative descriptive terms used herein may be interpreted accordingly. The term “vertical” refers to a direction perpendicular to the surface of the semiconductor substrate, and the term “horizontal” refers to any direction parallel to the surface of the semiconductor substrate.

[0027] As used herein, the term "substrate" generally refers to a material on which subsequent layers of material are added. The substrate itself may include multiple layers of material and / or may be patterned, for example, an array with first holes. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material (e.g., various dielectric materials, glass, plastics, oxides, or sapphire wafers). Memory devices may include multiple substrates.

[0028] As used herein, the term "layer" generally refers to a portion of material comprising a region of thickness. A layer may extend over the entire underlying or overlying structure, or may have a range smaller than that of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or non-homogeneous continuous structure having a thickness smaller than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where interconnects and / or vertical contacts are formed) and one or more dielectric layers.

[0029] According to some embodiments of this disclosure, structures and methods of manufacturing vertical capacitors for achieving higher density and lower silicon area consumption on a wafer are provided. For example, vertical capacitors can be used as memory cells for vertical transistors in DRAM memory arrays. Generally, capacitance is proportional to the area of ​​the capacitor; therefore, planar capacitors involve a larger silicon area to provide sufficient capacitance for the integrated circuits of the memory device. By using vertical capacitors instead of planar capacitors in the memory device, sufficient capacitance can be provided while increasing overall storage density and reducing manufacturing costs.

[0030] The manufacturing methods described in this specification can be used to form high-quality vertical capacitors in semiconductor devices, even when one or more high-temperature processes are involved in the manufacturing process. High-temperature processes can include rapid thermal processing (RTP), rapid thermal annealing (RTA), various thermal processes, hybrid wafer bonding (e.g., die-to-wafer (D2W) or wafer-to-wafer (W2W) hybrid bonding), other types of wafer bonding (e.g., direct bonding, eutectic bonding, glass frit bonding, thermocompression bonding, etc.), and other high-temperature processes that may be involved in the manufacturing of prior art semiconductor devices. The manufacturing methods disclosed herein can also be used for planar capacitors when a planar capacitor structure is desired (e.g., in a planar memory device).

[0031] High-temperature processes can involve temperatures of approximately 500°C or higher (e.g., approximately 600°C or higher, approximately 700°C or higher, approximately 800°C or higher, approximately 900°C or higher, approximately 1000°C or higher) and can be implemented at various points along the overall manufacturing flow line of a semiconductor device. Generally, one or more components of a semiconductor device may involve high-temperature processes that facilitate the formation of those components. For example, in memory devices, high-temperature processes such as RTAs can be used to form bit lines, as these components typically involve the formation of metal silicides. As another example, hybrid bonding generally involves high-temperature processes for producing direct bonded interconnects (DBIs), i.e., bonding dielectrics (e.g., silicon oxide (SiO2)). x Hybrid bonding is a permanent bonding process involving an embedded metal (e.g., copper (Cu)). In semiconductor manufacturing, hybrid bonding has become an industry-standard practice for forming metal interconnects between two semiconductor wafers (e.g., two silicon wafers). For memory devices, hybrid bonding can allow one or more peripheral devices (e.g., complementary metal-oxide-semiconductor (CMOS) devices) to interact with various components of the memory device (e.g., memory cell transistors). Hybrid bonding can offer advanced 3D device stacking, higher memory density, greater bandwidth, improved efficiency, improved speed and performance, higher power consumption, and several other advantages.

[0032] However, capacitors in memory devices can be sensitive to high-temperature processes. Specifically, high-k materials, which are typically used as the insulating layer between the electrodes of capacitors, can degrade during high-temperature processes. High-k dielectric materials generally refer to dielectric materials with a dielectric constant greater than that of silicon oxide (SiO2), for example, a dielectric constant of about 3.7 or greater (e.g., about 4 or greater, about 4.5 or greater, about 5 or greater, about 5.5 or greater, about 6 or greater, about 6.5 or greater, about 7 or greater). Such high-k materials can include, for example, alumina (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), or combinations thereof. During high-temperature processes (e.g., involving temperatures of about 500°C or higher), high-k materials are prone to failure due to changes in their crystal structure and / or crystal phase caused by the high temperatures. For example, high-temperature processes may cause crystal growth in high-k materials, increasing the percentage of large crystals in the high-k material. In such cases, the dielectric constant of high-k materials generally decreases, and high-k materials provide reduced capacitance. In some cases, after one or more high-temperature processes, high-k materials may have a dielectric constant of about 6 or less (e.g., about 5.5 or less, about 5 or less, about 4.5 or less, about 4 or less, about 3.7 or less, about 3.5 or less).

[0033] To address one or more of the aforementioned problems, this disclosure provides a method for manufacturing a memory device, in some embodiments of which can be adapted to one or more high-temperature processes while preventing the failure of the high-k dielectric of the memory device's capacitors. Specifically, during the high-temperature process, this disclosure employs a sacrificial material to replace the high-k material. By introducing the high-k material after the high-temperature process has been completed, the dielectric constant of the high-k material does not deteriorate, and a capacitor with higher quality characteristics (e.g., increased capacitance) can be formed.

[0034] Figure 1A A schematic cross-sectional view of an exemplary memory device 100 is shown. Memory device 100 represents an example of a bonded chip that can be formed using the manufacturing methods disclosed herein. In some embodiments, at least some memory cell arrays and peripheral circuitry in memory device 100 are formed in parallel on different wafers and then bonded together to form a bonded chip (this process is referred to herein as a "parallel process"). It should be noted that in Figure 1A The x-axis and y-axis have been added to further illustrate the spatial relationships of the components of a semiconductor device.

[0035] Memory device 100 may include a first wafer 102 comprising an array of memory cells (also referred to herein as a "memory cell array"). In some embodiments, the memory cell array comprises an array of DRAM cells. For ease of description, a DRAM cell array may be used as an example to describe a memory cell array in this disclosure. In some embodiments, each DRAM cell includes a capacitor for storing data bits and one or more transistors (also referred to as transfer transistors) for controlling (e.g., switching and selecting) access to it. In some embodiments, each DRAM memory cell is a transistor-capacitor (1T1C) cell. Because transistors often leak small amounts of charge, capacitors can discharge slowly, causing the information stored in them to deplete. Thus, DRAM cells can be refreshed, for example, by peripheral circuitry to retain data.

[0036] like Figure 1AAs shown, the first wafer 102 may include at least some of the peripheral circuitry of the memory device 100. The second wafer 104 may include the remaining peripheral circuitry of the memory device 100. That is, the peripheral circuitry of the memory device 100 may be distributed across at least two wafers 102 and 104, with some peripheral circuitry and the memory cell array integrated into the first wafer 102. The peripheral circuitry (also referred to as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of the memory cell array. For example, the peripheral circuitry may include one or more of the following: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), data input / output buffers, charge pumps, voltage sources or voltage generators, current or voltage references, any portion (e.g., sub-circuits) of the aforementioned functional circuitry, or any active or passive component of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuits in the first wafer 102 and the second wafer 104 can use CMOS technology, for example, they can be implemented using logic processes of any appropriate technology node (e.g., 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

[0037] The first wafer 102 and the second wafer 104 are stacked in different planes. Therefore, compared to a memory device where all peripheral circuits are disposed in the same plane, the memory cell array and peripheral circuits in the first wafer 102 and the peripheral circuits in the second wafer 104 can be stacked in different planes, thereby reducing the planar size of the memory device 100. Figure 1A As shown, the memory device 100 also includes a bonding interface 106 located between the first wafer 102 and the second wafer 104. The bonding interface 106 can be an interface formed between the two semiconductor wafers using any suitable bonding technique (e.g., hybrid bonding) described in detail below. In some embodiments, the bonding interface 106 is where bonding layers meet and bond. In practice, the bonding interface 106 can be a layer of a certain thickness, including the bottom surface of the bonding layer of the first wafer 102 and the top surface of the bonding layer of the second wafer 104.

[0038] The first wafer 102 and the second wafer 104 can be manufactured separately (and in some embodiments, in parallel) using parallel processes, such that the thermal budget for manufacturing one of the first wafer 102 and the second wafer 104 does not limit the process for manufacturing the other of the first wafer 102 and the second wafer 104. Furthermore, in contrast to long-distance (e.g., millimeter or centimeter-scale) chip-to-chip data buses on circuit boards such as printed circuit boards (PCBs), a large number of interconnects (e.g., bonding contacts) can be formed across the bonding interface 106 to form direct, short-distance (e.g., micrometer-scale) electrical connections between wafers 102 and 104, thereby eliminating chip interface latency and achieving high-speed I / O throughput with reduced power consumption. Data transfer between memory cell arrays and different peripheral circuits in the first wafer 102 and the second wafer 104 can be performed via interconnects (e.g., bonding contacts) across the bonding interface 106. By vertically integrating the first wafer 102 and the second wafer 104, chip size can be reduced and memory cell density can be increased.

[0039] In addition, such as Figure 1A As shown, the first wafer 102 of the memory device 100 may further include a pad output interconnect layer 103 for pad output purposes (i.e., interconnection with external devices using contact pads on which bonding leads can be soldered). In some examples, the pad output interconnect layer 103 may be included in a second wafer 104 that does not include the memory cell array. For example, as Figure 1B As shown, the second wafer 104 of the memory device 100' may include a bonding interface 106. That is, the pad output interconnect layer 103 may be disposed on either side of the memory device 100 or 100'.

[0040] Figure 2A A schematic diagram of a memory device 200 (which may be operatively and / or structurally similar to memory device 100) including an array of peripheral circuitry 108 and memory cells 208 is shown, each memory cell 208 having a vertical transistor 210. The memory device 200 may include a memory cell array 201 and peripheral circuitry 108 coupled to the memory cell array 201. The memory cell array 201 may be any suitable memory cell array in which each memory cell 208 includes a vertical transistor 210 and a vertical capacitor 10. The vertical capacitor 10 is coupled to the vertical transistor 210 for storing charge as binary information of the memory cell 208.

[0041] like Figure 2AAs shown, the memory cells 208 in the memory cell array 201 can be arranged as a two-dimensional (2D) array with rows and columns. The memory device 200 may include: word lines 204 that couple peripheral circuitry 108 to the memory cell array 201 for controlling the switching of vertical transistors 210 in a row of memory cells 208; and bit lines 206 that couple peripheral circuitry 108 to the memory cell array 201 for sending data to and / or receiving data from a column of memory cells 208. That is, each word line 204 is coupled to a memory cell 208 in a corresponding row, and each bit line 206 is coupled to a memory cell 208 in a corresponding column.

[0042] A vertical transistor 210 (e.g., a vertical metal-oxide-semiconductor field-effect transistor (MOSFET)) includes a semiconductor body 124 extending vertically above a substrate (not shown). That is, the semiconductor body 124 may extend above the top surface of the substrate, thereby exposing not only the top surface of the semiconductor body 124 but also one or more of its side surfaces. Figure 2A As shown, for example, the semiconductor body 124 may have a cuboid shape to expose its four sides. It should be understood that the semiconductor body 124 may have any suitable 3D shape, such as a polyhedral shape or a cylindrical shape. That is, the cross-section of the semiconductor body 124 in a planar view (e.g., in the xy plane) may have a square shape, a rectangular shape (or a trapezoidal shape), a circular shape (or an elliptical shape), or any other suitable shape.

[0043] like Figure 2A As shown, the vertical transistor 210 also includes a gate structure 216 that contacts one or more sides of the semiconductor body 124, i.e., located in one or more planes on the side surfaces(s) of the active region. In other words, the active region (i.e., the semiconductor body 124) of the vertical transistor 210 may be at least partially surrounded by the gate structure 216. The gate structure 216 may include a gate dielectric 126 located over one or more sides of the semiconductor body 124, for example, as... Figure 2AAs shown, it contacts the four side surfaces of the semiconductor body 124. The gate structure 216 may also include a gate electrode 114 located on and in contact with the gate dielectric 126. The gate dielectric 126 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the gate dielectric 126 may include silicon oxide, i.e., a gate oxide. The gate electrode 114 may include any suitable conductive material, such as polysilicon, a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), a metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or a silicide. For example, the gate electrode 114 may include doped polysilicon, i.e., gate polysilicon. In some embodiments, the gate electrode 114 includes multiple conductive layers, such as a W layer over a TiN layer. It should be understood that in some examples, the gate electrode 114 and the word line 204 may be a continuous conductive structure. In other words, the gate electrode 114 can be considered as part of the word line 204 forming the gate structure 216, or the word line 204 can be considered as an extension of the gate electrode 114 that will be coupled to the peripheral circuitry 108.

[0044] like Figure 2A As shown, the vertical transistor 210 may further include a pair of source and drain electrodes (S / D doped regions, also referred to as source and drain electrodes) formed respectively at both ends of the semiconductor body 124 in the vertical direction (y-direction). The source and drain electrodes may be doped with any suitable P-type dopant (e.g., boron (B) or gallium (Ga)) or any suitable N-type dopant (e.g., phosphorus (P) or arsenic (As)). The source and drain electrodes may be separated in the vertical direction (y-direction) by a gate structure 216. In other words, the gate structure 216 is formed vertically between the source and drain electrodes. Therefore, when the gate voltage applied to the gate electrode 114 is higher than the threshold voltage of the vertical transistor 210, one or more channels (not shown) of the vertical transistor 210 may be formed vertically in the semiconductor body 124 between the source and drain electrodes. That is, each channel of the vertical transistor 210 is also formed in the vertical direction along which the semiconductor body 124 extends.

[0045] In some embodiments, the vertical transistor 210 is a multi-gate transistor. That is, the gate structure 216 may be connected to more than one side of the semiconductor body 124 (e.g., Figure 2A The four sides of the transistor are contacted to form more than one gate, allowing more than one channel to be formed between the source and drain during operation. Although the vertical transistor 210 is in Figure 2A The vertical transistor 210 is shown as a multi-gate transistor, but it may also include a single-gate transistor. That is, for example, for the purpose of increasing transistor and memory cell density, the gate structure 216 may be in contact with only one side of the semiconductor body 124.

[0046] Peripheral circuitry 108 can be coupled to memory cell array 201 via bit lines 206, word lines 204, and any other suitable metal interconnects. As described above, peripheral circuitry 108 may include any suitable circuitry for facilitating operation of memory cell array 201 by applying voltage and / or current signals to each memory cell 208 via word lines 204 and bit lines 206, and by sensing voltage and / or current signals from each memory cell 208. Peripheral circuitry 108 may include various types of peripheral circuitry (e.g., CMOS devices) formed using CMOS technology.

[0047] like Figure 2A As shown, the vertical capacitor 10 can be coupled to the source or drain of the vertical transistor 210 and is capable of storing binary data (e.g., 0 and 1). In some embodiments, the vertical transistor 210 controls the selection and / or state switching of the corresponding capacitor 10. Figure 2B As shown, in some embodiments, each memory cell 208 includes a transistor 304 (e.g., using...). Figure 2A (implemented by transistor 210 in the middle) and capacitor 306 (e.g., Figure 2A The DRAM cell 302 (example of capacitor 10 in the example). The gate of transistor 304 (e.g., corresponding to gate electrode 114) can be coupled to word line 204, one of the source and drain of transistor 304 can be coupled to bit line 206, the other of the source and drain of transistor 304 can be coupled to the first electrode of capacitor 306, and the second electrode of capacitor 306 can be coupled to ground.

[0048] Figures 3A-3D These are cross-sectional views depicting different stages during a manufacturing process involving high-temperature techniques for memory devices. Specifically, Figures 3A-3D A memory device 300 having vertical capacitors 10 is shown (which may be operatively and / or structurally similar to memory device 100 and / or memory device 200), each vertical capacitor 10 including an isolation layer (e.g., a high-k dielectric material) between two electrodes (e.g., a first electrode 13 and a second electrode 14). Generally, a sacrificial material 12 is used to replace one or more components of the capacitor 10 to support the structure of the capacitor 10 throughout the manufacturing steps involving high-temperature processes. The sacrificial material 12 is then removed after the high-temperature processes have been completed, and a high-k material is deposited as the isolation layer between the first electrode 13 and the second electrode 14 of each capacitor 10 (e.g., see [reference needed]). Figure 3C ).

[0049] Figure 3AA first stage of forming a memory device 300 is illustrated, which includes providing a first wafer 102. In this example, the first wafer 102 is formed by bonding a carrier wafer 52 to the top of an array wafer 50. Any suitable wafer bonding technique (e.g., direct bonding, adhesive bonding, thermocompression bonding, reactive bonding, etc.) that may include one or more high-temperature processes can be used to form the array wafer 50 and the carrier wafer 52. Generally, the carrier wafer 52 is used to support (e.g., carry) the array wafer 50 during various steps throughout the manufacturing process and does not include any functional components of the memory device 300. In some embodiments, the first wafer 102 and the array wafer 50 are the same wafer, such that the carrier wafer 52 is not involved in the manufacturing process.

[0050] The array wafer 50 provides a memory cell array 201 including multiple memory cells. Each memory cell includes a structure of a vertical transistor 210 and a vertical capacitor 10. For example, the vertical transistor 210 can perform selection and / or state switching on data bits stored in the vertical capacitor 10 of the resulting memory device 300. In some embodiments, the resulting memory device 300 is a DRAM device with memory cells provided in the form of an array of DRAM cells. Figure 2A As described, each memory cell may include a semiconductor body 124 surrounded by a gate structure including a gate dielectric 126 and a gate electrode. The gate electrode is located in... Figures 3A-3D The middle part is depicted as a continuous section of line 204. For example... Figure 3A As shown, each semiconductor body 124 can extend vertically through word line 204. Vertical transistors 210 can be separated by dielectric material 130 (in some cases, air gap) to electrically isolate two adjacent vertical transistors 210.

[0051] A structure for a vertical capacitor 10 is provided in the form of an array of first holes 11 penetrating a semiconductor structure 140, which is located above a transistor array region 150, including vertical transistors 210 and word lines 204. The semiconductor structure 140 may comprise any suitable semiconductor or insulating material, such as silicon, gallium arsenide, silicon dioxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiO2). x N yOr a combination thereof. The first hole 11 is filled with a sacrificial material 12. Depending on the implementation, the sacrificial material 12 may include a variety of different materials, such as insulating materials (e.g., SiO2, Si3N4, carbon), semiconductor materials (e.g., silicon, gallium arsenide), or others. Since the sacrificial material 12 is generally an intermediate step, i.e., removed at some point in the manufacturing process, the sacrificial material 12 can be selected based on a convenient material removal process (e.g., wet etching, ashing, etc.). In some implementations, the sacrificial material 12 is included in the semiconductor structure 140, and the first hole 11 is filled with a filler material. The semiconductor structure 140 may be patterned and / or include multiple layers of sacrificial material 12. Generally, the sacrificial material 12 (e.g., by filling the first hole 11 and / or being included in the semiconductor structure 140) supports the capacitor 10 throughout the manufacturing steps involving high-temperature processes. The first hole 11 has a cylindrical (e.g., pillar) shape, but various geometries are possible, such as conical, tapered, cuboid, etc. The first electrode 13 is lined within the first hole 11 and is in contact with the sacrificial material 12. The first electrode 13 can be made of any suitable conductive material (e.g., titanium nitride (TiN)). In this case, for example, the first electrode 13 is in interface with the semiconductor body 124, enabling the vertical transistor 210 to communicate with the capacitor 10 of the resulting memory device 300 to store data bits.

[0052] Figure 3B A second stage of forming a memory device 300 is illustrated, which includes hybrid bonding a first wafer 102 to the top of a second wafer 104. The second wafer 104 includes, for example, peripheral circuitry 108 (e.g., a CMOS device) capable of being fabricated in the parallel process described above. As mentioned earlier, hybrid bonding generally involves at least one high-temperature process for forming interconnects between the first wafer 102 and the second wafer 104. Figure 3B As seen in some embodiments, the bottom surface of the first wafer 102 (i.e., the bottom surface of the array wafer 50 portion of the first wafer 102) may be thinned prior to co-bonding with the second wafer 104. For example, excess material may be removed and / or the bottom surface may be polished by chemical mechanical polishing (CMP) or other suitable methods to provide a clean interface for co-bonding.

[0053] like Figure 3BAs seen, the memory device 300 is a bonded chip formed from a first wafer 102 and a second wafer 104, which are bonded together at a bonding interface 106 located therebetween. The second wafer 104 includes a substrate 101, which may be made of silicon (e.g., crystalline silicon (c-Si) such as polycrystalline silicon (polycrystalline Si) or monocrystalline silicon (monocrystalline Si)), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), or silicon-on-insulator (SOI). The substrate 101 includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in the x and / or z directions (i.e., the lateral direction).

[0054] The second wafer 104 of the memory device 300 may include peripheral circuitry 108 located on the substrate 101. In some embodiments, the peripheral circuitry 108 is configured to control and sense the memory device 300. The peripheral circuitry 108 may be any suitable digital, analog, and / or mixed-signal control and sensing circuitry for facilitating the operation of the memory device 300, including but not limited to: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuitry 108 may include transistors formed on the substrate 101, wherein all or part of the transistors are formed in the substrate 101 (e.g., below the top surface of the substrate 101) and / or directly on the substrate 101. Isolation regions (e.g., shallow trench isolation (STI)) and doped regions (e.g., source and drain regions of the transistors) may also be formed in the substrate 101. Transistors can be high-speed and have advanced logic processes (e.g., technology nodes such as 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.). In some embodiments, peripheral circuitry 108 may also include any other circuitry compatible with advanced logic processes, including logic circuitry (e.g., processors and programmable logic devices (PLDs)) or memory circuitry (e.g., static random access memory (SRAM) and dynamic RAM (DRAM)).

[0055] The second wafer 104 of the memory device 300 may further include an interconnect layer 110 located near the bonding interface 106 and above the peripheral circuitry 108. The interconnect layer 110 may include a plurality of interconnects 111 and a dielectric material electrically isolating the interconnects 111. The interconnects 111 may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The remaining regions of the interconnect layer 110 may be formed using a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0056] Similarly, such as Figure 3B As shown, the first wafer 102 of the memory device 300 may further include an interconnect layer 112 located near the bonding interface 106. The interconnect layer 112 may include a plurality of bit line contacts 113 connected to bit lines 206 and a dielectric material electrically isolating the bit line contacts 113. The bit line contacts 113 and bit lines 206 may include conductive materials, including but not limited to: W, Co, Cu, Al, silicides, or any combination thereof. The remaining area of ​​the interconnect layer 112 may be formed using a dielectric material, including but not limited to: silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The word lines 204 of the first wafer 120 may be coupled to peripheral circuitry 108 in the second wafer 104 via word line contacts 116 in the interconnect layer 112, bonding contacts 115 in the bonding interface 106, and interconnects 111 in the interconnect layer 110. The bonding contacts 115 may be used to co-bond the first wafer 102 to the second wafer 104.

[0057] The first wafer 102 can be bonded face-to-face to the top of the second wafer 104 at bonding interface 106. In this case, as a result of hybrid bonding (also known as “metal / dielectric hybrid bonding”), bonding interface 106 is disposed between interconnect layers 110 and 112. Hybrid bonding is a direct bonding technique (e.g., forming a bond between surfaces without using intermediate layers such as solder or adhesive) and can simultaneously achieve metal-to-metal bonding and dielectric-to-dielectric bonding.

[0058] Figure 3C The third stage of forming the memory device 300 is illustrated, which includes removing the top surface of the first wafer 102 to expose the first via 11, i.e., removing the carrier wafer 52 portion of the first wafer 102. For example, the carrier wafer 52 can be removed from the first wafer 102 by chemical mechanical processing (CMP) or other suitable methods.

[0059] Following one or more high-temperature processes, sacrificial material 12 is removed from the first via 11 and / or semiconductor structure 140 to expose the first electrode 13. The high-temperature process can be performed at any stage of the manufacturing process prior to the removal of the sacrificial material 12. A high-k dielectric material is then deposited on the first electrode 13 to form an isolation layer 15.

[0060] Since the high-k material does not undergo any high-temperature processes during the entire manufacturing process, its crystal structure and / or crystal phase remain unchanged. Generally, compared to any high-temperature process involving the same material, the high-k material will have a higher dielectric constant and a smaller average crystal size. For example, the high-k material included in the final capacitor structure 10 may have a dielectric constant of about 5 or greater (e.g., about 5.5 or greater, about 6 or greater, about 6.5 or greater, about 7 or greater). In some embodiments, the high-k material may have a dielectric constant of about 20 or greater. In some embodiments, the high-k material may have a dielectric constant of about 25 or greater. For example, the high-k material may have a dielectric constant in the range of about 25 to 40. The high-k material may also satisfy one or more size conditions based on the absolute and / or relative size of its crystals. Specifically, the smallest crystal of the high-k material corresponds to the smallest size d, and the largest crystal of the high-k material corresponds to the largest size D. In some embodiments, the number of large crystals in the high-k material accounts for less than 20% of the total number of crystals, wherein the large crystals have a dielectric constant between... The dimension between D and [other dimensions]. In other embodiments, the number of large crystals in the high-k material accounts for less than 15% of the total number of crystals, wherein the large crystals have a dimension between [a certain value]. The dimension between d and D. In other embodiments, the average size of all crystals in the high-k material is between d and D. between.

[0061] Figure 3D The fourth stage of forming the memory device 300 is illustrated, which may include additional manufacturing steps that can be performed to produce the final memory architecture. A second electrode 14 is formed on the isolation layer 15 to produce the final vertical capacitors 10, i.e., each capacitor 10 has a first electrode 13 and a second electrode 14 separated by the isolation layer 15. The isolation layer 15 insulates the first electrode 13 and the second electrode 14 from each other. The second electrode 14 may be made of any suitable conductive material (e.g., TiN and / or silicon germanium (SiGe)). In some embodiments, the second electrode 14 may be grounded.

[0062] The conductive layer 30 may be deposited on the second electrode 14 and / or the semiconductor structure 140. Depositing the conductive layer 30 may include forming contacts 31 between bonding interfaces 106 for communication with peripheral circuitry 108 of the second wafer 104. The conductive layer 30 and contacts 31 may comprise any suitable conductive material, including but not limited to: W, Co, Cu, Al, silicides, or any combination thereof. Alternatively or additionally, a pad output interconnect layer 103 may be deposited on the conductive layer 30 (or one or more layers deposited on the conductive layer 30) for pad output purposes, i.e., interconnecting with external devices using contact pads 32 on which bonding leads can be soldered.

[0063] Generally, any suitable deposition method (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), low-pressure CVD (LPCVD), metal-organic CVD (MOCVD), sputtering, atomic layer deposition (ALD), or combinations thereof) can be used to deposit the first electrode 13, sacrificial material 12, isolation layer 15, second electrode 14, conductive layer 30, pad output interconnect layer 103, and / or other material layers.

[0064] Figure 4A A flowchart of an exemplary process 400 for manufacturing a memory device including capacitors is shown. Process 400 generally involves one or more high-temperature processes. Each capacitor includes a first electrode and a second electrode separated by an insulating layer. The insulating layer generally comprises a high-k dielectric material, such as Al2O3, HfO2, ZrO2, TiO2, or combinations thereof.

[0065] Process 400 includes: providing a first semiconductor wafer. The first wafer includes a sacrificial material and a first electrode disposed in an array of first vias. The first electrode is in contact with the sacrificial material (410).

[0066] Process 400 includes: hybrid bonding a first wafer to a second semiconductor wafer (420) including CMOS devices (e.g., peripheral circuitry). Generally, hybrid bonding involves one or more high-temperature processes.

[0067] Process 400 includes: removing sacrificial material to expose the first electrode (430).

[0068] Process 400 includes: depositing an isolation layer (440) on the first electrode.

[0069] Process 400 includes: forming a second electrode (450) on the isolation layer.

[0070] In some embodiments, process 400 includes: depositing a conductive layer on a second electrode, and forming a pad output structure (460) connected to the conductive layer and the CMOS device.

[0071] Figure 4B A flowchart of an exemplary process 410 for providing a first semiconductor wafer is shown.

[0072] Process 410 includes: providing an array wafer comprising a sacrificial material and a first electrode disposed in an array of first holes. The first electrode is in contact with the sacrificial material (412).

[0073] Process 410 includes forming a first semiconductor wafer (414) by bonding an array wafer to a carrier wafer and thinning the array wafer. The top surface of the array wafer is bonded to the bottom surface of the carrier wafer, and the bottom surface of the array wafer is thinned and / or polished.

[0074] In some embodiments, process 410 includes: thermally treating the first wafer (416). For example, thermal treatment can be used to form one or more components of a memory device, such as bit lines.

[0075] Figure 4C A flowchart of an exemplary process 420 for co-bonding a first semiconductor wafer of process 410 with a second semiconductor wafer including a CMOS device is shown.

[0076] Process 420 includes: co-bonding an array wafer with a second wafer (422). A thinned bottom surface of the array wafer portion of the first wafer is bonded to the top surface of the second wafer at a bonding interface.

[0077] Process 420 includes: removing the carrier wafer from the first wafer to expose the array wafer (424).

[0078] Figure 5A This is a top view depicting an example of a processed first wafer 102 used to manufacture a memory device with vertical capacitors. Each capacitor in the resulting memory device includes a first electrode and a second electrode separated by an insulating layer. The steps for producing such capacitors are explained below. Figure 5B This is an exemplary cross-sectional view of a first semiconductor wafer 102. The first wafer 102 can be used to fabricate at least two different capacitor structures, referred to herein as "cylinder capacitors" and "cup capacitors," which involve one or more high-temperature processes. Figures 6A-6L The steps for manufacturing cylindrical capacitors for memory devices, starting from the first wafer 102, are outlined. Figures 7A-7E The steps for manufacturing a cup-shaped capacitor for a memory device, starting from the first wafer 102, are outlined.

[0079] The first wafer 102 includes a transistor array region 150, which includes a plurality of vertical transistors 210. The vertical transistors 210 are provided in the form of a semiconductor body 124 and a gate structure including a gate dielectric 126 and a gate electrode 114. The semiconductor body 124 is separated by a dielectric material 130 (in some cases, an air gap), which electrically isolates adjacent vertical transistors 210.

[0080] The first wafer 102 also includes an array of first vias 11 vertically penetrating the semiconductor structure 140 disposed above the transistor array region 150. The first vias 11 correspond to the structure of the resulting vertical capacitor. For example, contacts 20 interface the first vias 11 with the semiconductor body 124, allowing bits stored in the resulting capacitor to be selected and / or switched by the vertical transistors 210. The semiconductor structure 140 includes alternating layers of a first dielectric material 41 and a second dielectric material 42. In this example, the alternating layers include two layers of first dielectric material 41-1 and 41-2 and three layers of second dielectric material 42-1, 42-2, and 42-3. Generally, any number of layers can be included in the semiconductor structure 140, and more than two dielectric materials can be used if desired. In this example, the first dielectric material 41 and the second dielectric material 42 are different materials and can include any suitable dielectric material, such as silicon oxide (SiO2) or silicon nitride (Si3N4).

[0081] Figure 6A This is a top view showing the first stage of forming a memory device 600 with cylindrical capacitors (which may be operatively and / or structurally similar to memory device 100, memory device 200 and / or memory device 300). Figure 6BThis is a cross-sectional view showing the first stage. The first stage includes: forming a first electrode 13 (e.g., TiN) in the first hole 11 and filling the first hole 11 with a filler material 16 (e.g., polysilicon, dielectric material). The filler material 16 is also deposited on the top layer of the second dielectric material 42-1 to adequately cover the first electrode 13. In this case, the first electrode 13 is lined in the first hole 11 and recessed to establish a relatively uniform material layer within the first hole 11, but the first hole 11 can be filled in a different manner. For example, depending on the construction of the vertical capacitor, the first electrode 13 can be partially lined in the first hole 11 or partially filled. Different first holes 11 can also be filled differently as needed. Furthermore, in this embodiment, a sacrificial material 12 is included in the semiconductor structure 140, and the filler material 16 is generally a different material from the sacrificial material 12. More specifically, the first dielectric material 41 is the sacrificial material 12, such that multiple layers of sacrificial materials 12-1 and 12-2 are included in the semiconductor structure 140. As described below, after one or more high-temperature processes, sacrificial layers 12-1 and 12-2 can be patterned and subsequently removed to produce cylindrical capacitors while avoiding high-k dielectric failure.

[0082] Figure 6C This is a cross-sectional view showing a second stage of forming a memory device 600 with cylindrical capacitors. The second stage includes co-bonding a first wafer 102 to a second wafer 104 at a bonding interface 106. Co-bonding generally involves one or more high-temperature processes. For example, additional high-temperature processes and heat treatments may be performed before and / or after co-bonding to form various components of the memory device 600, such as bit lines 206. In some embodiments, the second stage may include intermediate steps before and / or after co-bonding the first wafer 102 to the second wafer 104. For example, an array wafer including a semiconductor structure 140 and a transistor array region 150 may be provided. The array wafer may be bonded to a carrier wafer to form the first wafer 102 and to support the first wafer 102 during the intermediate steps. The array wafer may be thinned and / or polished to provide a clean interface for co-bonding, and the carrier wafer may be removed after co-bonding to expose the array wafer.

[0083] like Figure 6CAs seen, the second wafer 104 includes peripheral circuitry 108 (e.g., CMOS technology) embedded in the substrate 101 and connected via interconnects 111 and bonding interface 106. The second wafer 104 may also include an interconnect layer 110 located near the bonding interface 106 and above the peripheral circuitry 108. After hybrid bonding, the first wafer 102 includes interconnects (e.g., bit line contacts) 113 connected to the interconnects 111 of the second wafer 104 via the bonding interface 106. The first wafer 102 may also include an interconnect layer 112 located near the bonding interface 106.

[0084] Figure 6D This is a top view showing the third stage of forming a memory device 600 with cylindrical capacitors. Figure 6E This is a cross-sectional view showing the third stage. The third stage includes applying a mask 70 on top of the filler material 16 disposed on the semiconductor structure 140. The mask 70 can be used to etch features through one or more layers of the semiconductor structure 140. Here, the mask 70 includes circular spacer holes 73 aligned between the first holes 11. The spacer holes 73 and the perimeter 72 of the mask 70 can be etched to pattern various features in the semiconductor structure 140. Depending on the specific implementation, other mask shapes and / or sizes may also be used. For example, the spacer holes and / or perimeters may be square, rectangular, triangular, polygonal, etc., depending on the desired patterning.

[0085] Figure 6F This is a top view showing the fourth stage of forming a memory device 600 with cylindrical capacitors. Figure 6G This shows a cross-sectional view of the fourth stage (e.g.) Figure 6F (Cross section A-A' shown in the diagram). Figure 6H This shows another cross-sectional view of the fourth stage (e.g.) Figure 6F The fourth stage includes etching a second hole 71 using the spacer body hole 73 of the mask 70 as a guide. The second hole 71 penetrates the semiconductor structure 140. The semiconductor structure 140 is also etched around the first hole 11 along the perimeter 72 of the mask 70, thereby creating an etched perimeter 74 of the semiconductor structure 140. The second hole 71 and the perimeter 74 can be etched using any suitable technique (e.g., a dry etching method). In this example, for example, after etching, the filler material 16 of the excess layer disposed on the semiconductor structure 140 is also removed using CMP or other suitable methods.

[0086] In this embodiment, all layers of the semiconductor structure 140 are etched except for the second dielectric material 42-3 of the underlying layer. However, any number of layers of the semiconductor structure 140 can be etched depending on the desired capacitor configuration. For example, in some embodiments, only the first dielectric material 42-1 of the top layer is etched, which alters the structure of the resulting cylindrical capacitor. After etching, the layers of sacrificial materials 12-1 and 12-2 are removed from the semiconductor structure 140 to expose the first electrode 13. For example, wet etching methods or other suitable material removal processes can be used to remove the sacrificial layers 12-1 and 12-2. Any excess material resulting from the etching is also removed along with the layers of sacrificial materials 12-1 and 12-2, thereby producing... Figure 6G The structure of the semiconductor structure 140 shown is described. The sacrificial layers 12-1 and 12-2 can be removed by etching a second hole 71 in any of the layers of the first dielectric materials 42-1 and 42-2. Alternatively or additionally, the sacrificial layers 12-1 and 12-2 can be removed laterally around the etched perimeter 74 of the semiconductor structure 140.

[0087] Figure 6I This is a top view showing the fifth stage of forming a memory device 600 with cylindrical capacitors. Figure 6J This shows a cross-sectional view of the fifth stage (e.g.) Figure 6I (Cross section A-A' shown in the diagram). Figure 6K This shows another cross-sectional view of the fifth stage (e.g.) Figure 6I The fifth stage includes depositing an isolation layer 15 (e.g., a high-k dielectric material) onto the first electrode 13. Specifically, the isolation layer 15 is deposited onto the first electrode 13 in the etched second via 71. Alternatively or additionally, the isolation layer 15 can be deposited laterally around the first via 11 by means of the etched perimeter 74 of the semiconductor structure 140. Figure 6J As seen, the isolation layer 15 can also be deposited on other exposed surfaces, such as on top of the filler material 16 remaining in the first hole 11 and on layers of the second dielectric materials 42-1, 42-2, and 42-3. Generally, all high-temperature processes (e.g., involving temperatures of approximately 500°C or higher) are completed prior to the deposition of the isolation layer 15. Therefore, the isolation layer 15 is not subjected to temperatures that could cause failure or degradation of the high-k material (e.g., alteration of the crystal structure and / or phase of the high-k material), and thus maintains a relatively high dielectric constant (e.g., a dielectric constant of approximately 5 or greater).

[0088] The second electrode 14 is then formed on the isolation layer 15 in a similar manner (e.g., by deposition through etched second holes 71 and / or by etched perimeters 74, laterally deposited). Here, the second electrode 14 is composed of layers of two different conductive materials 14-1 and 14-2, which may include, for example, TiN and SiGe, respectively. The second electrode 14 may also be composed of a single layer of conductive material (e.g., TiN or SiGe). The first electrode 13 is separated from the second electrode 14 by the isolation layer 15, thereby forming a cylindrical capacitor 10. Due to the vertical geometry of the cylindrical capacitor 10 and the high dielectric constant of the isolation layer 15, the cylindrical capacitor 10 generally has higher quality, for example, higher capacitance and / or reduced wafer area consumption, compared to planar capacitors and / or capacitors manufactured using other methods.

[0089] like Figure 6J As observed, the cylindrical capacitor 10 has a relatively complex 3D structure due to various etching processes, material removal, and deposition steps. For example, the cylindrical capacitor 10 includes a region defined vertically by two layers of second dielectric materials 42-1 and 42-2. This region is defined laterally by two first electrodes 13 of adjacent first holes 11. An insulating layer 15 is supported on a continuous surface facing the two layers of second dielectric materials 42-1 and 42-2 and the two first electrodes 13. A shared second electrode 14 occupies the space defined by this continuous surface, such that conductive material 14-1 is deposited layer by layer on the insulating layer 15, and conductive material 14-2 fills the remaining space. The cylindrical capacitor 10 can be understood as two capacitors corresponding to the two first electrodes 13 and sharing the second electrode 14 between them.

[0090] Figure 6LThis is a cross-sectional view showing an optional sixth stage of forming a memory device 600 with cylindrical capacitors. A first conductive layer 30-1 is deposited on a second electrode 14, followed by the deposition of one or more dielectric layers 33, such as silicon oxide, silicon nitride, etc., on the second electrode 14. The first conductive layer 30-1 may be interfaced with the cylindrical capacitor, and the one or more dielectric layers 33 may provide electrical insulation for the memory device 600. Furthermore, the one or more dielectric layers 33 may fill dielectric regions of the semiconductor structure 140 that have been removed by etching during the fourth stage. A second conductive layer 30-2 is deposited on the one or more dielectric layers 33. The second conductive layer 30-2 is connected to the peripheral circuitry 108 via a bonding interface 106 through a first contact 31-1. The second conductive layer 30-2 may accommodate, for example, a pad output structure including contact pads 32. Alternatively or additionally, a pad output interconnect layer may be deposited on the second conductive layer 30-2. For example, the second contact 31-2 connects the first conductive layer 30-1 and the second conductive layer 30-2, thereby allowing the peripheral circuit 108 to adjust the cylindrical capacitor when the vertical transistor of the memory device 600 is operated.

[0091] Figure 7A This is a top view showing the first stage of forming a memory device 700 with cup-shaped capacitors (which may be operatively and / or structurally similar to memory device 100, memory device 200, memory device 300 and / or memory device 600). Figure 7B This is a cross-sectional view showing the first stage. The first stage includes: forming a first electrode 13 (e.g., TiN) in a first hole 11 and filling the first hole 11 with a sacrificial material 12 (e.g., carbon) to (at least partially) cover the first electrode 13. In this example, the sacrificial material 12 generally provides support for the structure of the resulting cup-shaped capacitor throughout the manufacturing process, particularly during one or more high-temperature processes. Similar to... Figures 6A-6L In the cylindrical capacitor described herein, the first electrode 13 is lined within the first hole 11 and recessed to establish a relatively uniform material layer within the first hole 11, but the first hole 11 can be filled in a different manner. In contrast to the cylindrical capacitor, in this embodiment, the semiconductor structure 140 is not composed of sacrificial material 12. Here, if desired, the semiconductor structure 140 can be a single material, and the layers of the first dielectric material 41 and the second dielectric material 42 can be the same material.

[0092] Figure 7CThis is a cross-sectional view showing the second stage of forming a memory device 700 with cup-shaped capacitors. The second stage includes co-bonding a first wafer 102 to a second wafer 104 at a bonding interface 106. Co-bonding generally involves one or more high-temperature processes. For example, additional high-temperature processes and heat treatments may be performed before and / or after co-bonding to form various components of the memory device 700, such as bit lines 206.

[0093] The second wafer 104 includes peripheral circuitry 108 (e.g., CMOS technology) embedded in the substrate 101 and connected via interconnects 111 and bonding interface 106. The second wafer 104 may also include an interconnect layer 110 located at the bonding interface 106 and above the peripheral circuitry 108. After hybrid bonding, the first wafer 102 includes interconnects (e.g., bit line contacts) 113 that are interconnected with the second wafer 104 at the bonding interface 106. The first wafer 102 may also include an interconnect layer 112 located near the bonding interface 106.

[0094] Figure 7D This is a cross-sectional view illustrating the third stage of forming a memory device 700 with a cup-shaped capacitor. Following one or more high-temperature processes, the third stage includes removing sacrificial material 12 from a first aperture 11 to expose a first electrode 13. For example, the sacrificial material 12 can be removed using an ashing method or other suitable material removal process. The sacrificial material 12 may include carbon, silicon oxide, silicon nitride, and other materials different from the first electrode 13. An isolation layer 15 (e.g., a high-k dielectric material) is then deposited into the first aperture 11 on the first electrode 13. In this example, the isolation layer 15 is also deposited on the semiconductor structure 140. The isolation layer 15 is not subjected to high-temperature processes that could cause the high-k material to fail or deteriorate (e.g., alter the crystal structure and / or phase of the high-k material), and therefore maintains a relatively high dielectric constant (e.g., a dielectric constant of approximately 5 or greater).

[0095] The third stage also includes forming a second electrode 14 (e.g., TiN) on the isolation layer 15. The second electrode 14 fills the first hole 11 and forms a layer over the portion of the isolation layer 15 disposed on the semiconductor structure 140. The first electrode 13 is separated from the second electrode 14 by the isolation layer 15, thereby forming a cup-shaped capacitor 10. Due to the vertical geometry of the cup-shaped capacitor 10 and the high dielectric constant of the isolation layer 15, the cup-shaped capacitor 10 generally has higher quality, for example, higher capacitance and / or reduced wafer area consumption, compared to planar capacitors and / or capacitors manufactured using other methods. A first conductive layer 30-1 is then deposited on the second electrode 14, for example, thereby interfaced with the cup-shaped capacitor 10.

[0096] Figure 7EThis is a cross-sectional view showing the fourth stage of forming a memory device 700 with a cup-shaped capacitor. The fourth stage includes: depositing one or more dielectric layers 33 on a first conductive layer 30-1, for example, to provide electrical insulation for the memory device 700. A second conductive layer 30-2 is deposited on the one or more dielectric layers 33. The second conductive layer 30-2 is connected to the peripheral circuitry 108 via a bonding interface 106 through a first contact 31-1. The second conductive layer 30-2 may accommodate a pad output structure. Alternatively or additionally, a pad output interconnect layer may be deposited on the second conductive layer 30-2. For example, the second contact 31-2 connects the first conductive layer 30-1 and the second conductive layer 30-2, thereby allowing the peripheral circuitry 108 to regulate the cup-shaped capacitor 10 when the vertical transistors of the memory device 700 are operated.

[0097] Figure 8 A block diagram of an exemplary system 1400 including one or more memory devices is shown. System 1400 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game controller, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 8 As shown, system 1400 may include a host 1408 and a memory system 1402 having one or more memory devices 1404 and a memory controller 1406. The host 1408 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 1408 may be configured to send data to or receive data from the memory device 1404.

[0098] Memory device 1404 can be any combination of memory devices disclosed herein, such as NAND flash memory devices, NOR flash memory devices, phase-change memory (PCM) devices, resistive memory devices, RAM devices, DRAM devices, RRAM devices, magnetic memory devices, spin-transfer torque (STT) memory devices, and other devices. Such memory devices with capacitors of superior quality (e.g., increased capacitance) can be manufactured using the methods described in this disclosure. In some embodiments, each memory device 1404 includes a DRAM device. A memory controller 1406 (also referred to as controller circuitry) is coupled to memory device 1404 and host 1408 and is configured to control memory device 1404. For example, controller circuitry can be configured to operate on memory cells of memory device 1404 via word lines and / or bit lines. Memory controller 1406 can manage data stored in memory device 1404 and communicate with host 1408.

[0099] Implementations of the described subject matter may include one or more features, either individually or in combination.

[0100] For example, in a first embodiment, a method of manufacturing a memory device including capacitors, wherein each capacitor includes a first electrode and a second electrode separated by an isolation layer, the method comprising: providing a first wafer including a sacrificial material and a first electrode disposed in a first aperture and in contact with the sacrificial material; co-bonding the first wafer with a second wafer including a complementary metal-oxide-semiconductor (CMOS) device; removing the sacrificial material to expose the first electrode; depositing an isolation layer on the first electrode; and forming a second electrode on the isolation layer.

[0101] The foregoing and other described embodiments may optionally include one or more of the following features:

[0102] A first feature, which may be combined with any of the following features, wherein providing the first wafer includes: providing an array wafer including a sacrificial material and a first aperture; forming a first wafer including an array wafer and a carrier wafer, wherein forming the first wafer includes: bonding the array wafer to the carrier wafer; and thinning the array wafer, and wherein co-bonding the first wafer to a second wafer includes: co-bonding the array wafer to the second wafer; and removing the carrier wafer from the first wafer to expose the array wafer.

[0103] The second feature, which may be combined with any of the preceding or following features, further includes: depositing a conductive layer on the second electrode; and forming a pad output structure connected to the conductive layer and the CMOS device.

[0104] The third feature may be combined with any of the preceding or following features, wherein the first wafer includes a semiconductor structure comprising alternating layers of sacrificial material and dielectric material, and wherein the sacrificial material and dielectric material are different dielectric materials, and a first hole penetrates the alternating layers.

[0105] The fourth feature may be combined with any of the preceding or following features, wherein removing the sacrificial material to expose the first electrode includes: forming a second hole between the first holes that penetrates into the alternating layers; and removing the layers of sacrificial material to expose the first electrode.

[0106] The fifth feature may be combined with any of the preceding or following features, wherein depositing an isolation layer on the first electrode includes: depositing the isolation layer into the second hole and depositing it around the first hole, wherein the isolation layer is deposited on the first electrode, deposited on a layer of dielectric material, and deposited on a filler material included in the first hole.

[0107] The sixth feature may be combined with any of the preceding or following features, wherein: the sacrificial material comprises silicon oxide (SiO2) and the dielectric material comprises silicon nitride (Si3N4); or the sacrificial material comprises Si3N4 and the dielectric material comprises SiO2.

[0108] The seventh feature may be combined with any of the preceding or following features, wherein providing the first wafer includes: filling the first aperture with a filler material to cover the first electrode, wherein the sacrificial material and the filler material are different materials.

[0109] The eighth feature may be combined with any of the preceding or following features, wherein the first wafer includes a semiconductor structure, the semiconductor structure includes a first aperture, and wherein providing the first wafer includes filling the first aperture with a sacrificial material to cover the first electrode.

[0110] The ninth feature may be combined with any of the previous or following features, wherein depositing the isolation layer on the first electrode includes: depositing the isolation layer into the first hole on the first electrode.

[0111] The tenth feature may be combined with any of the preceding or following features, wherein the sacrificial material includes carbon.

[0112] The eleventh feature may be combined with any of the preceding or following features, wherein the insulating layer comprises at least one of alumina, hafnium oxide, or zirconium oxide.

[0113] The twelfth feature may be combined with any of the preceding or following features, wherein the first electrode comprises titanium nitride (TiN).

[0114] The thirteenth feature may be combined with any of the preceding or following features, wherein the second electrode comprises TiN and silicon germanium (SiGe).

[0115] For example, in a second embodiment, a method of manufacturing a memory device including capacitors, wherein each capacitor includes a first electrode and a second electrode separated by an isolation layer, the method comprising: providing a first wafer including a sacrificial material and a first electrode disposed in a first aperture and in contact with the sacrificial material; heat-treating the first wafer; removing the sacrificial material to expose the first electrode; depositing an isolation layer on the first electrode; and forming a second electrode on the isolation layer.

[0116] The foregoing and other described embodiments may optionally include one or more of the following features.

[0117] A first feature, which may be combined with any of the following features, wherein providing the first wafer includes: providing an array wafer including a sacrificial material and a first aperture; forming a first wafer including an array wafer and a carrier wafer, wherein forming the first wafer includes: bonding the array wafer to the carrier wafer; and thinning the array wafer; and co-bonding the first wafer to a second wafer including a complementary metal-oxide-semiconductor (CMOS) device, wherein co-bonding the first wafer to the second wafer includes: co-bonding the array wafer to the second wafer; and removing the carrier wafer from the first wafer to expose the array wafer.

[0118] The second feature, which may be combined with any of the preceding or following features, further includes: depositing a conductive layer on the second electrode; and forming a pad output structure connected to the conductive layer and the CMOS device.

[0119] The third feature may be combined with any of the preceding or following features, wherein the first wafer includes a semiconductor structure comprising alternating layers of sacrificial material and dielectric material, wherein the sacrificial material and dielectric material are different dielectric materials, and wherein a first hole penetrates the alternating layers.

[0120] The fourth feature may be combined with any of the preceding or following features, wherein removing the sacrificial material to expose the first electrode includes: forming a second hole between the first holes, the second hole penetrating the alternating layers; and removing the layers of sacrificial material to expose the first electrode.

[0121] The fifth feature may be combined with any of the preceding or following features, wherein depositing an isolation layer on the first electrode includes: depositing the isolation layer into the second hole and depositing it around the first hole, wherein the isolation layer is deposited on the first electrode, deposited on a layer of dielectric material, and deposited on a filler material included in the first hole.

[0122] The sixth feature may be combined with any of the preceding or following features, wherein: the sacrificial material comprises silicon oxide (SiO2) and the dielectric material comprises silicon nitride (Si3N4); or the sacrificial material comprises Si3N4 and the dielectric material comprises SiO2.

[0123] The seventh feature may be combined with any of the preceding or following features, wherein providing the first wafer includes: filling the first aperture with a filler material to cover the first electrode, wherein the sacrificial material and the filler material are different materials.

[0124] The eighth feature may be combined with any of the preceding or following features, wherein the first wafer includes a semiconductor structure, the semiconductor structure includes a first aperture, and wherein providing the first wafer includes filling the first aperture with a sacrificial material to cover the first electrode.

[0125] The ninth feature may be combined with any of the previous or following features, wherein depositing an isolation layer on the first electrode includes: depositing the isolation layer on the semiconductor structure and depositing it into the first hole on the first electrode.

[0126] The tenth feature may be combined with any of the preceding or following features, wherein the sacrificial material includes carbon.

[0127] The eleventh feature may be combined with any of the preceding or following features, wherein the insulating layer comprises at least one of alumina, hafnium oxide, or zirconium oxide.

[0128] The twelfth feature may be combined with any of the preceding or following features, wherein the first electrode comprises titanium nitride (TiN).

[0129] The thirteenth feature may be combined with any of the preceding or following features, wherein the second electrode comprises TiN and silicon germanium (SiGe).

[0130] The fourteenth feature may be combined with any of the preceding or following features, wherein the heat treatment is carried out at a temperature of 500°C or higher.

[0131] In a third embodiment, a memory device includes: a first wafer including capacitors, wherein each capacitor includes a first electrode and a second electrode separated by an isolation layer, and wherein the isolation layer includes a dielectric material having a dielectric constant of 5 or greater; and a second wafer including a complementary metal-oxide-semiconductor (CMOS) device, wherein the second wafer is co-bonded with the first wafer.

[0132] The foregoing and other described embodiments may optionally include one or more of the following features.

[0133] The first feature can be combined with any of the following features, wherein the dielectric material includes a minimum crystal with a minimum size and a maximum crystal with a maximum size, and wherein the crystals in the dielectric material satisfy one or more size conditions, the one or more size conditions including at least one of the following: the number of large crystals in the dielectric material accounts for less than 20% of the total number of crystals, wherein the large crystals have a size between 2 / 3*(minimum size + maximum size) and the maximum size; the number of large crystals in the dielectric material accounts for less than 15% of the total number of crystals, wherein the large crystals have a size between 3 / 4*(minimum size + maximum size) and the maximum size; or the average size of the crystals in the dielectric material is between the minimum size and 1 / 2*(minimum size + maximum size).

[0134] The second feature, which may be combined with any of the following features, further includes two separated layers of material, wherein the capacitor includes a first capacitor and a second capacitor sharing a shared second electrode, and wherein a dielectric material is supported on a continuous surface formed by the first electrode of the first capacitor, the first electrode of the second capacitor and the separated two layers of material, and wherein the shared second electrode is supported in a space defined by the dielectric material supported on the continuous surface.

[0135] The third feature can be combined with any of the following features, wherein the capacitor includes a first hole, and wherein the first hole is lined with a first electrode, lined with a dielectric material, and filled with a second electrode.

[0136] In a fourth embodiment, a system includes: a memory device comprising: a first wafer including capacitors, wherein each capacitor includes a first electrode and a second electrode separated by an isolation layer, wherein the isolation layer includes a dielectric material having a dielectric constant of 5 or greater; and a second wafer including a complementary metal-oxide-semiconductor (CMOS) device, wherein the second wafer is co-bonded to the first wafer; and a memory controller electrically connected to the memory device, wherein the memory controller is configured to control the memory device.

[0137] The breadth and scope of this disclosure should not be limited to any of the exemplary embodiments described above, but should be defined solely by the following claims and their equivalents. Therefore, other embodiments are also within the scope of the claims.

Claims

1. A method for manufacturing a memory device including a capacitor, wherein, Each capacitor includes a first electrode and a second electrode separated by an isolation layer, and the method includes: A first wafer is provided, the first wafer comprising: Sacrificial materials; and The first electrode is disposed in the first hole and is in contact with the sacrificial material; The first wafer is co-bonded with a second wafer including a complementary metal-oxide-semiconductor (CMOS) device; After the first wafer and the second wafer are mixed and bonded, the sacrificial material is removed to expose the first electrode; Deposit the isolation layer on the first electrode; and The second electrode is formed on the isolation layer.

2. The method according to claim 1, wherein, Providing the first wafer includes: Provide an array wafer, the array wafer comprising: The sacrificial material; and The first hole; Forming a first wafer comprising the array wafer and a carrier wafer, wherein forming the first wafer includes: Bonding the array wafer to the carrier wafer; and The array wafer is thinned; and The process of co-bonding the first wafer and the second wafer includes: The array wafer is mixed-bonded with the second wafer; and The carrier wafer is removed from the first wafer to expose the array wafer.

3. The method according to any one of the preceding claims further comprises: A conductive layer is deposited on the second electrode; as well as A pad output structure is formed that connects to the conductive layer and the CMOS device.

4. The method according to claim 1, wherein, The first wafer includes a semiconductor structure comprising alternating layers of sacrificial material and dielectric material, wherein the sacrificial material and the dielectric material are different dielectric materials, and the first via penetrates the alternating layers.

5. The method according to claim 4, wherein, Removing the sacrificial material to expose the first electrode includes: A second hole is formed between the first holes, penetrating into the alternating layers; and Remove the layer of the sacrificial material to expose the first electrode.

6. The method according to claim 5, wherein, Depositing the isolation layer on the first electrode includes: The isolation layer is deposited into the second hole and around the first hole, wherein the isolation layer is deposited on the first electrode, on the layer of the dielectric material, and on the filler material included in the first hole.

7. The method according to any one of claims 4-6, wherein: The sacrificial material comprises silicon oxide (SiO2), and the dielectric material comprises silicon nitride (Si3N4); or The sacrificial material includes Si3N4, and the dielectric material includes SiO2.

8. The method according to any one of claims 1-2, wherein, Providing the first wafer includes: The first hole is filled with a filler material to cover the first electrode, wherein the sacrificial material and the filler material are different materials.

9. The method according to claim 1, wherein, The first wafer includes a semiconductor structure including the first aperture, and wherein providing the first wafer includes filling the first aperture with the sacrificial material to cover the first electrode.

10. The method according to claim 9, wherein, Depositing the isolation layer on the first electrode includes: The isolation layer is deposited into the first hole on the first electrode.

11. The method according to any one of claims 9-10, wherein, The sacrificial material includes carbon.

12. The method according to any one of claims 1-2, wherein, The insulating layer comprises at least one of alumina, hafnium oxide, or zirconium oxide.

13. The method according to any one of claims 1-2, wherein, The first electrode comprises titanium nitride (TiN).

14. The method according to any one of claims 1-2, wherein, The second electrode comprises TiN and silicon germanium (SiGe).

15. A method of manufacturing a memory device including a capacitor, wherein, Each capacitor includes a first electrode and a second electrode separated by an isolation layer, and the method includes: A first wafer is provided, the first wafer comprising: Sacrificial materials; and The first electrode is disposed in the first hole and is in contact with the sacrificial material; The first wafer is subjected to heat treatment; Remove the sacrificial material to expose the first electrode; Deposit the isolation layer on the first electrode; and The second electrode is formed on the isolation layer.

16. The method according to claim 15, wherein, Providing the first wafer includes: Provide an array wafer, the array wafer comprising: The sacrificial material; and The first hole; Forming a first wafer comprising the array wafer and a carrier wafer, wherein forming the first wafer includes: Bonding the array wafer to the carrier wafer; and Thinning of the array wafer; and The first wafer is co-bonded with a second wafer including a complementary metal-oxide-semiconductor (CMOS) device, wherein the co-bonding of the first wafer and the second wafer includes: The array wafer is mixed-bonded with the second wafer; and The carrier wafer is removed from the first wafer to expose the array wafer.

17. The method of claim 16, further comprising: A conductive layer is deposited on the second electrode; as well as A pad output structure is formed that connects to the conductive layer and the CMOS device.

18. The method according to claim 15, wherein, The first wafer includes a semiconductor structure comprising alternating layers of sacrificial material and dielectric material, wherein the sacrificial material and the dielectric material are different dielectric materials, and wherein the first via penetrates the alternating layers.

19. The method according to claim 18, wherein, Removing the sacrificial material to expose the first electrode includes: A second hole is formed between the first holes, the second hole penetrating the alternating layers; and Remove the layer of the sacrificial material to expose the first electrode.

20. The method according to claim 19, wherein, Depositing the isolation layer on the first electrode includes: The isolation layer is deposited into the second hole and around the first hole, wherein the isolation layer is deposited on the first electrode, on the layer of the dielectric material, and on the filler material included in the first hole.

21. The method according to any one of claims 18-20, wherein: The sacrificial material comprises silicon oxide (SiO2), and the dielectric material comprises silicon nitride (Si3N4); or The sacrificial material includes Si3N4, and the dielectric material includes SiO2.

22. The method according to any one of claims 15-20, wherein, Providing the first wafer includes: The first hole is filled with a filler material to cover the first electrode, wherein the sacrificial material and the filler material are different materials.

23. The method according to claim 15, wherein, The first wafer includes a semiconductor structure including the first aperture, and wherein providing the first wafer includes filling the first aperture with the sacrificial material to cover the first electrode.

24. The method according to claim 23, wherein, Depositing the isolation layer on the first electrode includes: The isolation layer is deposited on the semiconductor structure and deposited into the first hole on the first electrode.

25. The method according to any one of claims 23-24, wherein, The sacrificial material includes carbon.

26. The method according to any one of claims 15-20, wherein, The insulating layer comprises at least one of alumina, hafnium oxide, or zirconium oxide.

27. The method according to any one of claims 15-20, wherein, The first electrode comprises titanium nitride (TiN).

28. The method according to any one of claims 15-20, wherein, The second electrode comprises TiN and silicon germanium (SiGe).

29. The method according to any one of claims 15-20, wherein, The heat treatment is carried out at a temperature of 500°C or higher.

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