Vertical structure management in three-dimensional semiconductor devices

Abstract

Systems, devices, and methods for managing vertical structures in three-dimensional (3D) semiconductor devices are provided. In one aspect, a method includes: providing a semiconductor substrate; and forming an isolation region between a plurality of adjacent vertical transistors in the semiconductor substrate. Each of the plurality of adjacent vertical transistors extends in a vertical direction. A corresponding isolation region between two adjacent vertical transistors is disposed in a horizontal direction perpendicular to the vertical direction. The corresponding isolation region includes a conductive material, and the length of the conductive material in the corresponding isolation region is greater than the length of the vertical gate of each of the two adjacent vertical transistors in the vertical direction.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and processes for manufacturing semiconductor devices. Background Technology

[0002] Semiconductor devices (e.g., memory devices) can have various structures to increase the density of memory cells and lines on a chip. For example, three-dimensional (3D) memory devices are attractive because they can increase array density by stacking more layers within a similar footprint. 3D memory devices generally include a memory array of memory cells and peripheral circuitry to facilitate the operation of the memory array. Memory cells can include vertical structures, such as vertical transistors. Summary of the Invention

[0003] This disclosure describes methods, devices, systems, and techniques for managing vertical structures in three-dimensional (3D) semiconductor devices.

[0004] One aspect of this disclosure is characterized by a method comprising: providing a semiconductor substrate; and forming an isolation region between a plurality of adjacent vertical transistors in the semiconductor substrate. Each of the plurality of adjacent vertical transistors extends in a vertical direction, and a corresponding isolation region between two adjacent vertical transistors is disposed in a horizontal direction perpendicular to the vertical direction. The corresponding isolation region comprises a conductive material, and the length of the conductive material in the corresponding isolation region is greater than the length of the vertical gate of each of the two adjacent vertical transistors in the vertical direction.

[0005] In some embodiments, forming an isolation region between a plurality of adjacent vertical transistors in a semiconductor substrate includes: forming a plurality of trenches in the semiconductor substrate, the plurality of trenches being disposed along the horizontal direction and each of the plurality of trenches extending in a vertical direction; and forming a corresponding isolation region by depositing conductive material in an intermediate trench between two adjacent trenches used to form the two adjacent vertical transistors.

[0006] In some embodiments, the method further includes forming the two adjacent vertical transistors by depositing an isolation material in the two adjacent trenches and then depositing at least one conductive layer on the isolation material deposited in the two adjacent trenches to form the vertical gates of the two adjacent vertical transistors. Along the vertical direction, the length of the at least one conductive layer deposited in each of the two adjacent trenches is less than the length of the conductive material filled in the intermediate trench.

[0007] In some embodiments, the semiconductor substrate includes a first side and a second side opposite to the first side. Forming an isolation region between adjacent vertical transistors in the semiconductor substrate includes forming the isolation region from the first side of the semiconductor substrate between adjacent vertical transistors. In some embodiments, the method further includes etching the semiconductor substrate from the second side to expose conductive material in the corresponding isolation region without exposing the vertical gates of the two adjacent vertical transistors.

[0008] In some embodiments, etching the semiconductor substrate from a second side comprises etching the semiconductor substrate in an etch region in a vertical direction from the surface of the semiconductor substrate. The etch region has a bottom edge and an etch depth from the surface of the semiconductor substrate to the bottom edge. In the vertical direction, the etch depth is greater than a first distance between the surface of the semiconductor substrate and the end of the conductive material filled in the intermediate trench, and less than a second distance between the surface of the semiconductor substrate and the end of at least one conductive layer deposited in each of the two adjacent trenches. In some embodiments, the etch region has two opposing edges located within the two adjacent trenches in a horizontal direction.

[0009] In some embodiments, the method further includes forming a corresponding conductive interconnect in a second side of the semiconductor substrate that contacts the conductive material exposed in the corresponding isolation region. In some embodiments, the method further includes forming a plurality of bit lines from the second side of the semiconductor substrate.

[0010] In some embodiments, the method includes: depositing an isolation material to fill a portion of each of the plurality of trenches in a vertical direction; patterning a photoresist to cover two adjacent trenches and expose an intermediate trench; etching the isolation material deposited in the intermediate trench; depositing a conductive material in the intermediate trench to form a corresponding isolation region; and removing the photoresist and depositing the at least one conductive layer on the isolation material deposited in the two adjacent trenches to form the vertical gates of the two adjacent vertical transistors.

[0011] In some embodiments, the method includes cutting at least one conductive layer deposited in each of the two adjacent trenches to form two separate vertical gates of a pair of independent vertical transistors in the trenches.

[0012] In some embodiments, the method further includes: forming an array structure in a first region, the array structure including a plurality of memory cell strings, each memory cell in the plurality of memory cell strings including a corresponding vertical transistor. The plurality of adjacent vertical transistors and the isolation region in the semiconductor substrate are formed in a second region adjacent to the first region.

[0013] In some embodiments, forming the array structure includes forming corresponding vertical transistors of the plurality of memory cell strings by depositing at least one conductive layer in corresponding trenches. Along the vertical direction, the length of the at least one conductive layer deposited in the corresponding trench in the first region is greater than the length of the vertical gate of each of the two adjacent vertical transistors in the second region.

[0014] In some embodiments, the method includes: depositing an isolation material to fill portions of each of two adjacent trenches for the two adjacent vertical transistors in a second region and a corresponding trench for a memory cell in a first region in a vertical direction; patterning a photoresist to cover the two adjacent trenches and expose the corresponding trenches; etching the isolation material deposited in the corresponding trenches; removing the photoresist to expose the two adjacent trenches; and depositing at least one conductive layer on the isolation material deposited in the two adjacent trenches to form vertical gates of the two adjacent vertical transistors, and depositing the at least one conductive layer in the corresponding trenches to form vertical transistors for the memory cells.

[0015] Another aspect of this disclosure is characterized by a semiconductor device comprising: a semiconductor substrate; a plurality of vertical transistors disposed in the semiconductor substrate in a horizontal direction, each of the plurality of vertical transistors extending in a vertical direction perpendicular to the horizontal direction; and a plurality of isolation regions disposed in the semiconductor substrate, each of the plurality of isolation regions being located in a horizontal direction between two adjacent vertical transistors. The isolation regions comprise a conductive material, and in the vertical direction, the length of the conductive material in the isolation regions is greater than the length of the vertical gate of each of the two adjacent vertical transistors.

[0016] In some embodiments, the isolation region includes a conductive material filled in an intermediate trench between two adjacent trenches corresponding to the two adjacent vertical transistors. The vertical gate of each of the two adjacent vertical transistors includes at least one conductive layer on the isolation material filled in a portion of the respective trench in the two adjacent trenches. In the vertical direction, the length of the at least one conductive layer in each of the two adjacent trenches is less than the length of the conductive material filled in the intermediate trench.

[0017] In some embodiments, the semiconductor substrate includes opposing first and second sides. The plurality of isolation regions and the plurality of vertical transistors are located on the first side of the semiconductor substrate. The semiconductor device further includes conductive interconnects formed in the second side of the semiconductor substrate. Each of the conductive interconnects is in contact with a conductive material in a corresponding isolation region of the plurality of isolation regions, and each of the conductive interconnects has an end in the vertical direction from the second side of the semiconductor substrate that is higher than the end of at least one conductive layer in each of the two adjacent trenches.

[0018] In some embodiments, the semiconductor device further includes a plurality of bit lines located on a second side of the semiconductor substrate, each of the plurality of bit lines being coupled to a corresponding vertical transistor. In some embodiments, in each of the two adjacent trenches, the two vertical gates of a pair of independent vertical transistors are separated by an insulating material filling the trench.

[0019] In some embodiments, the semiconductor device further includes: an array structure located in a first region, the array structure including a plurality of memory cell strings, each memory cell in the plurality of memory cell strings including a vertical transistor having a vertical gate. The plurality of isolation regions and the plurality of vertical transistors are formed in a second region of the semiconductor substrate adjacent to the first region along a third direction perpendicular to the vertical and horizontal directions.

[0020] In some embodiments, along the vertical direction, the length of the vertical gate of the vertical transistor of the memory cell in the first region is greater than the length of the vertical gate of each of the two adjacent vertical transistors in the second region. In some embodiments, the length of the vertical transistor of the memory cell in the first region is greater than the length of the conductive material in the isolation region of the second region.

[0021] In some implementations, along the third direction, the vertical gate of the vertical transistor of the memory cell in the first region is in direct contact with the first isolation layer, while the vertical gate of each of the two adjacent vertical transistors in the second region is separated from the second isolation layer by a passivation layer.

[0022] Another aspect of this disclosure is characterized by a system comprising: a memory device; and a controller coupled to the memory device and configured to control the memory device. The memory device includes: a semiconductor substrate; a plurality of vertical transistors located in the semiconductor substrate in a horizontal direction, each of the plurality of vertical transistors extending in a vertical direction perpendicular to the horizontal direction; and a plurality of isolation regions located in the semiconductor substrate. Each of the plurality of isolation regions is located in the horizontal direction between two adjacent vertical transistors. The isolation regions comprise a conductive material, and in the vertical direction, the length of the conductive material in the isolation regions is greater than the length of the vertical gate of each of the two adjacent vertical transistors.

[0023] In some embodiments, the isolation region includes a conductive material filled in an intermediate trench between two adjacent trenches corresponding to the two adjacent vertical transistors. The vertical gate of each of the two adjacent vertical transistors includes at least one conductive layer on the isolation material filled in a portion of the respective trench in the two adjacent trenches, and the length of the at least one conductive layer in each of the two adjacent trenches is less than the length of the conductive material filled in the intermediate trench in the vertical direction.

[0024] The embodiments of this disclosure can provide one or more of the following technical advantages and / or benefits. For example, multiple trenches can be formed in a semiconductor substrate. An isolation material (e.g., oxide) can be filled in the bottom portion of the trenches in the connection region, and a vertical gate can be formed on the isolation material filled in the trench. This allows control over the depth of the vertical gate or the dicing depth of the vertical gate, and correspondingly, better control over the process window of the gate dicing process. Furthermore, the isolation region in an intermediate trench between adjacent trenches for forming vertical gates can include a conductive material (e.g., metal) filled in the intermediate trench, while no isolation material is present in the bottom portion of the intermediate trench. Thus, the semiconductor substrate can be etched from the back side to expose the conductive material in the isolation region without exposing the vertical gates in adjacent trenches, during which the isolation material deposited in the adjacent trenches acts as a stop layer. Similarly, each conductive layer (e.g., metal) for forming the vertical gate of the memory cell can be exposed from the back side of the semiconductor substrate and each conductive layer can be diced into two separate blocks to serve as the vertical gate of the memory cell. By etching the conductive material in the isolation region and the conductive layer for forming the vertical gates of the memory cells in the array region together, this technique reduces fabrication costs and complexity, eliminates problems or risks associated with metal punching from the front side of the semiconductor substrate (e.g., difficulty in controlling line wiggling), and optimizes the fabrication process (e.g., omitting one or more processing operations, such as costly oxide recess operations). The technique also allows control over the area used for outward coupling from the back side of the 3D semiconductor structure, thereby expanding the processing window and simplifying or optimizing the fabrication process of 3D semiconductor devices while reducing fabrication costs.

[0025] The technology can be applied to various types of semiconductor devices, volatile memory devices such as DRAM memory devices, or non-volatile memory (NVM) devices, such as NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change memory (PCM) such as phase-change random access memory (PCRAM), spin-transfer torque (STT)-magnetoresistive random access memory (MRAM), and others. The technology can also be applied to charge-trapping based memory devices (e.g., silicon-oxide-nitride-oxide-silicon (SONOS) memory devices) and floating-gate based memory devices. The technology can also be applied to three-dimensional (3D) memory devices. The technology can also be applied to various memory types, such as SLC (single-level cell) devices, MLC (multi-level cell) devices (e.g., two-level cell devices), TLC (three-level cell) devices, QLC (four-level cell) devices, or PLC (five-level cell) devices. Additionally or alternatively, the technology can be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC) or solid-state drives (SSDs), embedded systems, and others.

[0026] Details of one or more embodiments of the subject matter of this disclosure are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. Attached Figure Description

[0027] The accompanying drawings, which are incorporated herein and form a part of this disclosure, illustrate various aspects of this disclosure and, together with the description, further serve to explain the principles of this disclosure and enable those skilled in the art to make and use this disclosure.

[0028] Figure 1 A cross-sectional view of an exemplary 3D semiconductor device is shown.

[0029] Figure 2A A perspective view of an exemplary 3D semiconductor device is shown.

[0030] Figure 2B It shows Figure 2A A top view of an exemplary 3D semiconductor device.

[0031] Figures 3A-3C Cross-sectional views of an exemplary 3D semiconductor structure at different locations along a first lateral direction are shown.

[0032] Figure 3D-3E It shows Figures 3A-3C Cross-sectional views of an exemplary 3D semiconductor structure at different locations along the second lateral direction.

[0033] Figures 4A-4E The diagram shows cross-sectional views of a 3D semiconductor structure at various stages of the fabrication process.

[0034] Figure 5 This is a flowchart of an exemplary process for forming a 3D semiconductor device.

[0035] Figure 6 A block diagram of an exemplary system having one or more semiconductor devices is shown.

[0036] Similar reference numerals and names in the accompanying figures denote similar elements. It should also be understood that the various exemplary embodiments shown in the figures are merely illustrative and not necessarily drawn to scale. Detailed Implementation

[0037] Figure 1 A side view of a cross-section of an exemplary 3D semiconductor device 100 is shown. The 3D semiconductor device 100 may be a 3D dynamic random access memory (DRAM). It should be understood that... Figure 1 This is for illustrative purposes only and may not reflect the actual device structure (e.g., interconnects) in practice. In some embodiments, the 3D semiconductor device 100 is a bonded chip including a first semiconductor structure 102 and a second semiconductor structure 104 stacked on top of the first semiconductor structure 102. The first semiconductor structure 102 and the second semiconductor structure 104 may be connected at a bonding interface 106 therebetween.

[0038] like Figure 1 As shown, the first semiconductor structure 102 may include a substrate 110, which may include silicon (e.g., single-crystal silicon, c-Si), SiGe, GaAs, Ge, SOI, or any other suitable material. The first semiconductor structure 102 may include peripheral circuitry 112 located on and / or within the substrate 110. In some embodiments, the peripheral circuitry 112 includes a plurality of transistors 114 (e.g., planar transistors and / or 3D transistors). Trench isolation (e.g., shallow trench isolation (STI)) and doped regions (e.g., wells, sources, and drains of transistors 114) may also be formed on or within the substrate 110. In some examples, the peripheral circuitry 112 is formed using complementary metal-oxide-semiconductor (CMOS) technology, and the first semiconductor structure 102 may also be formed on a semiconductor die, which may be referred to as a control die or a CMOS die.

[0039] In some embodiments, the first semiconductor structure 102 further includes an interconnect layer 116 located above the peripheral circuit 112 to transmit electrical signals to and from the peripheral circuit 112. The interconnect layer 116 may include multiple interconnects (also referred to herein as “contacts”), including lateral interconnects and VIA contacts. The interconnect layer 116 may further include one or more interlayer dielectric (ILD) layers, within which interconnects and via contacts may be formed. That is, the interconnect layer 116 may include interconnects and via contacts located within multiple ILD layers. In some embodiments, the peripheral circuit 112 is coupled to each other via interconnects in the interconnect layer 116. The interconnects in the interconnect layer 116 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layers may be formed using dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0040] like Figure 1 As shown, the first semiconductor structure 102 has a front side and a back side, and the first semiconductor structure 102 may further include a bonding layer 118 on the back side located at the bonding interface 106 and above the interconnect layer 116 and the peripheral circuitry 112. The bonding layer 118 may include a plurality of bonding contacts 119 and a dielectric material electrically isolating the bonding contacts 119. The bonding contacts 119 may include a conductive material, such as Cu. The remaining region of the bonding layer 118 may be formed using a dielectric material (e.g., silicon oxide). The bonding contacts 119 in the bonding layer 118 and the surrounding dielectric material may be used for hybrid bonding. Similarly, as... Figure 1 As shown, the second semiconductor structure 104 may also include a bonding layer 120 at the bonding interface 106 and above the bonding layer 118 of the first semiconductor structure 102. The bonding layer 120 may include a plurality of bonding contacts 121 and a dielectric material electrically isolating the bonding contacts 121. The bonding contacts 121 may include a conductive material, such as Cu. The remaining regions of the bonding layer 120 may be formed using a dielectric material (e.g., silicon oxide). The bonding contacts 121 in the bonding layer 120 and the surrounding dielectric material may be used for hybrid bonding. The bonding contacts 121 may contact the bonding contacts 119 at the bonding interface 106. In some embodiments, the bonding layer 120 includes a dielectric layer opposite a memory cell (e.g., a DRAM cell) 124, wherein a bit line 123 is located between the dielectric layer and the memory cell 124, such as... Figure 1 As shown in the figure. The dielectric layer may include a bonding interface 106 having bonding contacts 121.

[0041] The second semiconductor structure 104 can be bonded face-to-face to the top of the first semiconductor structure 102 at the bonding interface 106. In some embodiments, the bonding interface 106 is disposed between the bonding layers 120 and 118 as a result of hybrid bonding (also known as “metal / dielectric hybrid bonding”), a direct bonding technique (e.g., forming a bond between surfaces without the use of intermediate layers such as solder or adhesive), and can simultaneously achieve metal-to-metal bonding and dielectric-to-dielectric bonding. In some embodiments, the bonding interface 106 is where the bonding layers 120 and 118 meet and bond. In some examples, the bonding interface 106 can be a layer of a certain thickness comprising the top surface of the bonding layer 118 of the first semiconductor structure 102 and the bottom surface of the bonding layer 120 of the second semiconductor structure 104.

[0042] In some embodiments, the second semiconductor structure 104 further includes an interconnect layer 122, including bit lines 123, located above the bonding layer 120 for transmitting electrical signals. The interconnect layer 122 may include multiple interconnects, such as mid-process (MEOL) interconnects and back-end process (BEOL) interconnects. In some embodiments, the interconnects in the interconnect layer 122 may also include local interconnects such as bit lines 123 and word line contacts (not shown). The interconnect layer 122 may further include one or more ILD layers, within which interconnect lines and via contacts may be formed. The interconnects in the interconnect layer 122 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layer may be formed using a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0043] In some embodiments, peripheral circuitry 112 includes a word line driver / row decoder coupled to word line contacts in interconnect layer 122 via bonding contacts 121 and 119 in bonding layers 120 and 118 and interconnect layer 116. In some embodiments, peripheral circuitry 112 includes a bit line driver / column decoder coupled to bit lines 123 and bit line contacts in interconnect layer 122 via bonding contacts 121 and 119 in bonding layers 120 and 118 and interconnect layer 116. In some embodiments, bit line 123 is a metal bit line, contrasting with semiconductor bit lines (e.g., doped silicon bit lines). For example, bit line 123 may include W, Co, Cu, Al, or any other suitable metal having a higher conductivity than doped silicon. In some embodiments, bit line contacts are ohmic contacts, contrasting with Schottky contacts.

[0044] In some embodiments, bit line 123 is made of a composite conductive material, which may be based on a metallic material (e.g., W, Co, Cu, Al) and a semiconductor material (e.g., Si). For example, the composite conductive material may include metal silicides such as WSi, CoSi, CuSi, AlSi, or any other suitable metal silicide having a higher conductivity than doped silicon.

[0045] In some embodiments, the second semiconductor structure 104 includes a DRAM device, wherein memory cells are provided above the interconnect layer 122 and the bonding layer 120 in the form of an array of DRAM cells 124. That is, the interconnect layer 122, including bit lines 123, may be disposed between the bonding layer 120 and the array of DRAM cells 124. The bit lines 123 in the interconnect layer 122 may be coupled to a string of DRAM cells 124. In some embodiments, the second semiconductor structure 104 is formed on a semiconductor die, and this semiconductor die may be referred to as an array die.

[0046] In some embodiments, the semiconductor device may include a plurality of array dies (e.g., an array die on which a second semiconductor structure 104 is formed) and a CMOS die (e.g., a CMOS die on which a first semiconductor structure 102 is formed). The plurality of array dies and the CMOS die may be stacked and bonded together. The CMOS die may be coupled to each of the plurality of array dies respectively and may drive each of the plurality of array dies respectively, thereby causing them to operate in a manner similar to that of the semiconductor device. The semiconductor device may be any suitable device. In some examples, the semiconductor device includes at least a first wafer and a second wafer face-to-face bonded. The array die may be disposed on the first wafer together with other array dies, and the CMOS die may be disposed on the second wafer together with other CMOS dies. The first wafer and the second wafer may be bonded together, thereby enabling the array die on the first wafer to be bonded to the corresponding CMOS die on the second wafer. In some examples, the semiconductor device is a chip having at least the array dies and CMOS dies bonded together. In an example, the chip is obtained by dicing the bonded wafers together. In another example, the semiconductor device is a semiconductor package comprising one or more semiconductor chips assembled on a packaging substrate.

[0047] Each DRAM cell 124 may include a vertical transistor 126 and a capacitor 128 coupled to the vertical transistor 126. The DRAM cell 124 may be a 1T1C cell consisting of one transistor and one capacitor. It should be understood that the DRAM cell 124 may have any suitable configuration, such as a 2T1C cell, a 3T1C cell, etc. The vertical transistor 126 may be a MOSFET for switching the corresponding DRAM cell 124. In some embodiments, the vertical transistor 126 includes a vertically (z-direction) extending semiconductor body 130 (an active region capable of forming a channel therein) and a gate structure 136 contacting one side of the semiconductor body 130. In a single-gate vertical transistor, the semiconductor body 130 may have a cuboid or cylindrical shape, and in a plan view, the gate structure 136 may be adjacent to one side of the semiconductor body 130, for example, as shown in the figure. Figure 1 As shown in the diagram. In some embodiments, the vertical transistor 126 has a structure including two or more gates, such as a dual-gate structure, a tri-gate structure, or a gate all-around (GAA) structure. In some embodiments, the gate structure 136 includes a gate electrode 134 and a gate dielectric 132 laterally located between the gate electrode 134 and the semiconductor body 130 in the bit line direction (e.g., in the Y direction). In some embodiments, the gate dielectric 132 is adjacent to one side of the semiconductor body 130, and the gate electrode 134 is adjacent to the gate dielectric 132.

[0048] like Figure 1 As shown, in some embodiments, the semiconductor body 130 has two ends located in the vertical direction (z-direction). Figure 1The semiconductor body 130 has an upper and lower end portion, and at least one end extends into the ILD layer beyond the gate dielectric 132 in the vertical direction (z-direction). In some embodiments, one end (e.g., the upper end portion) of the semiconductor body 130 is flush with the corresponding end (e.g., the upper end portion) of the gate dielectric 132. In some embodiments, both ends (upper and lower) of the semiconductor body 130 extend into the ILD layer beyond the gate electrode 134 in the vertical direction (z-direction), respectively. That is, the semiconductor body 130 may have a vertical profile (e.g., depth) larger than the vertical profile dimension (e.g., depth) of the gate electrode 134 (e.g., in the z-direction), and neither the upper nor lower end portion of the semiconductor body 130 is flush with the corresponding end portion of the gate electrode 134. Thus, short circuits between the bit line 123 and the word line / gate electrode 134 or between the word line / gate electrode 134 and the capacitor 128 can be avoided. The vertical transistor 126 may further include a source and a drain (both referred to as 138, as their positions may be interchangeable) respectively disposed at two ends (upper and lower ends) of the semiconductor body 130 in the vertical direction (z-direction). In some embodiments, one of the source and drain 138 (e.g., in...) Figure 1 At the upper end of the middle) it is coupled to capacitor 128, and the other of the source and drain 138 (e.g., in Figure 1 The lower end of the transistor 126 is coupled to bit line 123. That is, the vertical transistor 126 can have a first end facing the positive z-direction and a second end facing the negative z-direction opposite to the first end, such as... Figure 1 As shown in the image.

[0049] In some embodiments, the semiconductor body 130 includes a semiconductor material such as monocrystalline silicon, polycrystalline silicon, amorphous silicon, Ge, any other semiconductor material, or any combination thereof. In one example, the semiconductor body 130 may include monocrystalline silicon. The source and drain 138 may be doped with an N+ type dopant (e.g., phosphorus (P) or arsenic (As)) or a P type dopant (e.g., boron (B) or gallium (Ga)) at a desired doping level. In some embodiments, a silicide layer (e.g., a metal silicide layer) is formed between the source / drain 138 of the vertical transistor 126 and the bit line 123 as a bit line contact, or formed between the source / drain 138 of the vertical transistor 126 and the first electrode of the capacitor 128 as a capacitor contact 142, thereby reducing contact resistance. In some embodiments, the gate dielectric 132 comprises a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al₂O₃, HfO₂, Ta₂O₅, ZrO₂, TiO₂, or any combination thereof. In some embodiments, the gate electrode 134 comprises a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicides, or any combination thereof. In some embodiments, the gate electrode 134 comprises multiple conductive layers, for example, a W layer situated above a TiN layer. In one example, the gate structure 136 may be a “gate oxide / gate polysilicon” gate, wherein the gate dielectric 132 comprises silicon oxide and the gate electrode 134 comprises doped polysilicon. In another example, the gate structure 136 may be an HKMG, wherein the gate dielectric 132 comprises a high-k dielectric and the gate electrode 134 comprises a metal.

[0050] As described above, since the gate electrode 134 can be a word line portion or extends as a word line in the word line direction (e.g., the X direction), the second semiconductor structure 104 of the 3D semiconductor device 100 (e.g., a memory device) can also include multiple word lines, each extending in the word line direction. In other words, the gate electrode 134 is also referred to as a word line 134. Each word line 134 can be coupled to a row of DRAM cells 124. That is, the bit line 123 and the word line 134 can extend in two perpendicular lateral directions, and the semiconductor body 130 of the vertical transistor 126 can extend in a vertical direction perpendicular to the two lateral directions followed by the extension of the bit line 123 and the word line 134. The word line 134 contacts a word line contact portion (not shown). In some embodiments, the word line 134 includes a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, the word line 134 includes multiple conductive layers, such as a W layer located above a TiN layer, as shown in the figure. Figure 1 As shown in the image.

[0051] In some implementations, such as Figure 1 As shown, a vertical transistor 126 extends vertically through and contacts the word line 134, and the source or drain 138 of the vertical transistor 126 at its lower end contacts the bit line 123 (or a bit line contact, if present). Accordingly, due to the vertical arrangement of the vertical transistor 126, the word line 134 and the bit line 123 can be arranged in different planes in the vertical direction, which simplifies the wiring of the word line 134 and the bit line 123. In some embodiments, the bit line 123 is arranged vertically between the bonding layer 120 and the word line 134, and the word line 134 is arranged vertically between the bit line 123 and the capacitor 128. The word line 134 can be coupled to the peripheral circuitry 112 in the first semiconductor structure 102 via word line contacts (not shown) in the interconnect layer 122, bonding contacts 121 and 119 in the bonding layers 120 and 118, and interconnects in the interconnect layer 116. Similarly, bit lines 123 in interconnect layer 122 can be coupled to peripheral circuits 112 in the first semiconductor structure 102 via bonding contacts 121 and 119 in bonding layers 120 and 118, and interconnects in interconnect layer 116.

[0052] In some implementations, the vertical transistors 126 may be arranged in a mirror-symmetric manner to increase the density of DRAM cells 124 in the bit-line direction (e.g., the Y direction). Figure 1As shown, two adjacent vertical transistors 126 in the bit line direction are mirror-symmetrical with respect to the trench isolation 160. That is, the second semiconductor structure 104 may include a plurality of trench isolations 160, each extending parallel to word line 134 in the word line direction (X direction) and disposed between the semiconductor bodies 130 of two adjacent rows of vertical transistors 126. In some embodiments, rows of vertical transistors 126 separated by trench isolations 160 are mirror-symmetrical with respect to the trench isolations 160. The trench isolations 160 may be formed using a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. It should be understood that the trench isolations 160 may include air gaps, each laterally disposed between adjacent semiconductor bodies 130. The air gaps may be formed due to the relatively small spacing of the vertical transistors 126 in the bit line direction (e.g., the Y direction). On the other hand, the relatively large dielectric constant of air in the air gap (e.g., approximately four times that of silicon oxide) compared to some electrolytes (e.g., silicon oxide) can improve the insulation effect between the vertical transistors 126 (and the rows of DRAM cells 124). Similarly, in some embodiments, air gaps are also formed laterally in the bit line direction between the word line / gate electrodes 134, depending on the spacing of the word line / gate electrodes 134 in the bit line direction. In some embodiments, as an alternative to having air gaps in the trench isolation 160, conductive material (e.g., a metal such as W) is filled into the trench isolation 160 and surrounded by a dielectric material. As described in more detail below, the conductive material in the trench isolation 160 can be coupled outward from the back side of the second semiconductor structure 104.

[0053] like Figure 1As shown, in some embodiments, capacitor 128 includes a first electrode 144 located above the source or drain 138 of vertical transistor 126 (e.g., the upper end of semiconductor body 130) and coupled to the source or drain 138 via capacitor contact 142. In some embodiments, capacitor contact 142 is an ohmic contact, such as a metal silicide contact, contrasting with a Schottky contact. For example, capacitor contact 142 may include metal silicides such as WSi, CoSi, CuSi, AlSi, or any other suitable metal silicide having a higher conductivity than doped silicon. Capacitor 128 may also include a capacitor dielectric located above and in contact with the first electrode 144 and a second electrode located above and in contact with the capacitor dielectric. That is, capacitor 128 may be a vertical capacitor, wherein the electrodes and capacitor dielectric are stacked vertically (in the Z direction), and the capacitor dielectric may be sandwiched between the electrodes. In some embodiments, each first electrode is coupled to the source or drain 138 of a corresponding vertical transistor 126 in the same DRAM cell, while all second electrodes are coupled to a common plate 146 coupled to ground (e.g., common ground). The capacitor 128 may have a first end facing the negative z-direction and a second end facing the positive z-direction opposite the first end, such as... Figure 1 As shown in the diagram. In some embodiments, the first end of capacitor 128 is coupled to the first terminal of vertical transistor 126 via an ohmic contact (e.g., capacitor contact 142 made of metal silicide material). Figure 1 As shown, the second semiconductor structure 104 may further include a capacitor contact 147 (e.g., a conductor) in contact with the common plate 146, thereby coupling the capacitor 128 to the peripheral circuit 112 or directly to ground. In some embodiments, the capacitor contact 147 (e.g., a conductor) extends in the z-direction from the dielectric layer of the bonding layer 120, thereby coupling to the second end of the capacitor 128 via the common plate 146, such as... Figure 1 As shown in the figure. In some embodiments, the ILD layer forming capacitor 128 has the same dielectric material, such as silicon oxide, as the two ILD layers to which semiconductor body 130 extends.

[0054] It should be understood that the structure and configuration of capacitor 128 are not limited to Figure 1Examples are provided, and any suitable structure and configuration may be included, such as planar capacitors, stacked capacitors, multi-fin capacitors, cylindrical capacitors, slotted capacitors, or substrate-plate capacitors. In some embodiments, the capacitor dielectric includes a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al₂O₃, HfO₂, Ta₂O₅, ZrO₂, TiO₂, or any combination thereof. It should be understood that in some examples, capacitor 128 may be a ferroelectric capacitor used in an FRAM cell, and the capacitor dielectric may be replaced by a ferroelectric layer having a ferroelectric material such as PZT or SBT. In some embodiments, the electrodes include conductive materials, including but not limited to W, Co, Cu, Al, TiN, TaN, polycrystalline silicon, silicides, or any combination thereof.

[0055] like Figure 1 As shown, a vertical transistor 126 extends vertically through and contacts a word line 134. The source or drain 138 of the vertical transistor 126 at its lower end contacts a bit line 123, and the source or drain 138 of the vertical transistor 126 at its upper end is coupled to a capacitor 128. That is, due to the vertical arrangement of the vertical transistor 126, the bit line 123 and the capacitor 128 can be arranged in different planes in the vertical direction, and the vertical ends of the vertical transistor 126 coupled to the DRAM cell 124 are located opposite each other in the vertical direction. In some embodiments, the bit line 123 and the capacitor 128 are arranged on opposite sides of the vertical transistor 126 in the vertical direction. This simplifies the wiring of the bit line 123 and reduces the coupling capacitance between the bit line 123 and the capacitor 128 compared to a DRAM cell where the bit line and capacitor are arranged on the same side of a planar transistor.

[0056] like Figure 1 As shown, in some embodiments, the vertical transistor 126 is disposed vertically between the capacitor 128 and the bonding interface 106. That is, the vertical transistor 126 can be arranged closer to the peripheral circuitry 112 and the bonding interface 106 of the first semiconductor structure 102 than the capacitor 128. Since the bit line 123 and the capacitor 128 are coupled to opposite ends of the vertical transistor 126, the bit line 123 (as part of the interconnect layer 122) is disposed vertically between the vertical transistor 126 and the bonding interface 106. Therefore, the interconnect layer 122, including the bit line 123, can be arranged close to the bonding interface 106 to reduce interconnect wiring distance and complexity.

[0057] In some embodiments, the second semiconductor structure 104 further includes a substrate 148 disposed above the DRAM cell 124. The substrate 148 may be a portion of a carrier wafer. It should be understood that in some examples, the substrate 148 may not be included in the second semiconductor structure 104.

[0058] like Figure 1 As shown, the second semiconductor structure 104 may further include a pad-out interconnect layer 150 located above the substrate 148 and the DRAM cell 124. The pad-out interconnect layer 150 may include interconnects located within one or more ILD layers, such as contact pads 154. The pad-out interconnect layer 150 and the interconnect layer 122 may be formed on opposite sides of the DRAM cell 124. A capacitor 128 may be disposed vertically between the vertical transistor 126 and the pad-out interconnect layer 150. In some embodiments, the interconnects in the pad-out interconnect layer 150 are capable of transmitting electrical signals between the 3D semiconductor device 100 and external circuitry, for example, to achieve the purpose of pad out.

[0059] In some embodiments, the second semiconductor structure 104 further includes one or more contacts 152 extending through the substrate 148 and a portion of the pad-out interconnect layer 150, thereby coupling the pad-out interconnect layer 150 to the DRAM cell 124 and the interconnect layer 122. Therefore, peripheral circuitry 112 can be coupled to the DRAM cell 124 via interconnect layers 116 and 122 and bonding layers 120 and 118, and peripheral circuitry 112 and DRAM cell 124 can be coupled to external circuitry via the contacts 152 and the pad-out interconnect layer 150. The contact pads 154 and contacts 152 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In one example, the contact pads 154 may include Al, and the contacts 152 may include W. In some embodiments, the contacts 152 include vias surrounded by dielectric spacers (e.g., having silicon oxide), thereby electrically isolating the vias from the substrate 148. Depending on the thickness of the substrate 148, the contact portion 152 may be an ILV with a depth on the submicron level (e.g., between 10 nm and 1 μm), or a TSV with a depth on the micron or tens of micron level (e.g., between 1 μm and 100 μm).

[0060] Although not shown, it should be understood that the pad leads of 3D memory devices are not limited to those shown in the figure. Figure 1The second semiconductor structure 104, which has DRAM cells 124, is shown as an extension, and can also be extended from the first semiconductor structure 102, which has peripheral circuitry 112. Although not shown, it should be understood that the air gaps between word lines 134 and / or between semiconductor bodies 130 can be partially or completely filled with a dielectric. Although not shown, it should be understood that more than one array of DRAM cells 124 can be stacked one on top of the other, thereby vertically increasing the number of DRAM cells 124.

[0061] In some implementations, instead of such Figure 1 The diagram shows a substrate 148 positioned above a DRAM cell 124, and a second semiconductor structure 104 including a substrate disposed below the DRAM cell 124. This substrate may be a portion of a carrier wafer. The DRAM cell 124 may be formed in the front side of the substrate, and a bit line 123 may be formed in the back side of the substrate. The bit line 123 can be electrically coupled to the DRAM cell 124 (e.g., the source or drain 138 at the end of a vertical transistor 126) through the substrate. As described in more detail below, conductive material filling the trench isolation 160 may be exposed from the back side of the substrate and coupled to, for example, conductive interconnects.

[0062] Figure 2A A perspective view of an exemplary 3D semiconductor device 200 is shown. The 3D semiconductor device 200 can be used with... Figure 1 The 3D semiconductor device 100 is similar to or the same as, or related to Figure 1 A portion of the 3D semiconductor device 100 (e.g., Figure 1 The second semiconductor structure 104) is similar to or the same as, or related to Figure 1 The structure of the 3D semiconductor device 100 in the intermediate fabrication process is similar to or the same as that of the semiconductor device 100.

[0063] like Figure 2A As shown, the 3D semiconductor device 200 has a front side 201 and a back side 203 along the vertical direction (Z direction). The 3D semiconductor device 200 includes multiple bit lines 202 separated by an insulating material 204 (e.g., oxide) on the back side 203. The bit lines 202 can be connected to… Figure 1 Bit lines 123 are similar to or the same as bit lines 202. Bit line 202 may be separated along the X direction and extended along the Y direction.

[0064] The 3D semiconductor device 200 may include strings of memory cells on its front side 201. Each string of memory cells may be coupled to a corresponding bit line 202. The memory cells may be connected to... Figure 1 The DRAM cell 124 is similar to or the same as the memory cell 124. This memory cell may include vertical transistors (e.g., Figure 1 The vertical transistor 126) and the capacitor coupled to the vertical transistor (e.g., Figure 1 (Capacitor 128). In some embodiments, the gate structure of the two vertical transistors 212, 214 (e.g., Figure 1 The gate structure 136 can be formed in the trench structure 210 and separated by an isolation material 216 (e.g., oxide) in the trench structure 210. Along the X direction, adjacent trench structures 210 (or adjacent vertical transistors in adjacent trench structures 210) can be separated by an isolation region 220 (e.g., Figure 1 The trench isolation 160 is separated. As discussed in more detail below, the isolation region 220 may include conductive material located between adjacent trench structures 210 and surrounded by dielectric material in the trench.

[0065] Figure 2B Shown in the XY plane Figure 2A An exemplary 3D semiconductor device 200. The 3D semiconductor device 200 may include a first region 200a (e.g., an array region) and one or more second regions 200b (e.g., connection regions) adjacent to the first region 200a along the X direction. Figure 2B As shown, the first region 200a is located between the second region 200b on the left and the second region 200b on the right (e.g., along the X direction). The second regions 200b on the left and right may be symmetrical with respect to the first region 200a. Figure 2B The diagram shows the boundary line 205 located between the first region 200a and the corresponding second region 200b.

[0066] Multiple bit lines 202 extend along the Y direction and are arranged along the X direction. As described above, due to the gate electrodes of vertical transistors 212 and 214 (e.g., Figure 1 The gate electrode 134 may be a word line portion or extend as a word line in the word line direction (e.g., the X direction), and thus the 3D semiconductor device 200 (e.g., a memory device) may also include multiple word lines, each extending in the word line direction. Each word line may be coupled to a row of vertical transistors. Vertical transistors 212, 214 may be coupled to two different word lines. In some embodiments, the first region 200a includes memory cells (e.g., Figure 1 An array of memory cells 124), and one or more second regions 200b include one or more conductive contacts configured to be coupled to each of the plurality of word lines respectively.

[0067] In some implementations, such as Figure 2B As shown, the trench structure 210 includes two letter lines 230a and 230b formed on the inner surface of the trench structure 210 and separated by an insulating material 216 (e.g., Figure 1(Word line 134). In some cases, a dielectric layer 215 (e.g., including SiN) may be disposed between the inner surface and the word lines 230a, 230b. In some embodiments, each word line 230a, 230b is coupled to the gate electrode of a corresponding vertical transistor (e.g., vertical transistors 212, 214). In some embodiments, the gate electrodes of the corresponding vertical transistors are connected together to form word lines 230a, 230b.

[0068] Each word line 230a, 230b may include one or more layers, such as a high-k dielectric layer, an intermediate layer (e.g., TiN), and a metal layer (e.g., W). The word lines 230a, 230b may be formed by cutting one or more layers formed in the trench structure 210. In some embodiments, the one or more layers may be cut at the ends of the trench structure 210. In some embodiments, for example, as... Figure 2B As shown, one or more layers are cut at positions away from the two ends 210a, 210b of the trench structure 210. Each word line 230a, 230b may have a U-shape around the corresponding end of the trench structure 210. Each word line 230a, 230b may be outwardly coupled via a corresponding conductive pad 232a, 232b adjacent to the corresponding end 210a, 210b of the trench structure 210, thereby giving the corresponding conductive pad 232a, 232b a large area.

[0069] In some implementations, for example, such as Figure 2B As shown, word lines 230a extend around a first end 210a located in the right second region 200b of the trench structure 210, and conductive pads 232a are adjacent to and electrically coupled to the first end 210a in the right second region 200b. Similarly, word lines 230b extend around a second end 210b located in the left second region 200b of the trench structure 210, and conductive pads 232b are adjacent to and electrically coupled to the second end in the left second region 200b. In some embodiments, to increase the area of ​​the conductive pads and avoid overlap between conductive pads, adjacent conductive pads 232a in the right second region 200b may be at different distances from the first end 210a of the trench structure 210, and adjacent conductive pads 232b in the left second region 200b may be at different distances from the second end 210b of the trench structure 210.

[0070] As described above, the isolation region 220 is located between adjacent trench structures 210 and may include a conductive material (e.g., metal) surrounded by an isolation material. Furthermore, as described in more detail below, the conductive material in the isolation region 220 may be exposed / etched, for example, by etching from the back side 203, without exposing the word lines 230a, 230b in the trench structures 210. The conductive material of the isolation region 220 may be coupled to conductive interconnects 240. The conductive interconnects 240 may be externally coupled via conductive pads 242. Adjacent conductive pads 242 may be arranged adjacent to opposite ends of the isolation region 220 (e.g., one end in the left second region 200b and one end in the right second region 200b). In some embodiments, conductive pads 232a and 232b for outward coupling of word lines 230a and 230b are located on the front side 201 of the 3D semiconductor device 200, and conductive pad 242 for outward coupling of conductive interconnects 240 is located on the back side 203 of the 3D semiconductor device 200. In some embodiments, conductive pads 232a and 232b and conductive pad 242 are located on the same side, for example, on the front side 201 of the 3D semiconductor device 200, for example, as... Figure 2B As shown in the image.

[0071] For illustrative purposes, such as in Figures 3A-3E as well as Figures 4A-4E The diagram provides a more detailed description, showing cross-sectional views at positions A, B, and C along the X direction, and cross-sectional views at positions A, D, and E along the Y direction. Figures 3A-3E as well as Figures 4A-4E The structure shown can be formed prior to the formation of conductive pads 232a, 232b and / or conductive pad 242. Note that positions A, B, and C are all located within trench structure 210, where positions A and B are located in the second region 200b and C is located in the first region 200a; positions A and E are located at adjacent trench structures 210, and D is located at isolation region 220. Positions A, D, and E can have the same position in the X direction. In some examples, such as... Figure 2B As shown, position A spans both sides of word line 230b, and position B spans only one side of word line 230b and the space between word lines 230a and 230b. For comparison and / or for convenience, the cross-sectional views at positions A, B, and C are presented together below, and the cross-sectional views at positions A, D, and E are presented together below. Due to the periodicity of the trench structure 210, the cross-sectional views at positions A and E may be identical.

[0072] Figures 3A-3C Cross-sectional views of an exemplary 3D semiconductor structure 300 at different locations A, D, and E along a first lateral direction (e.g., the Y direction) are shown. Figure 3D-3E It shows Figures 3A-3C Cross-sectional views of an exemplary 3D semiconductor structure 300 at different positions A, B, and C along a second lateral direction (e.g., the X direction). The 3D semiconductor structure 300 can be used with... Figure 2A-2B The 3D semiconductor device 200 or a structure of the 3D semiconductor device 200 in an intermediate fabrication process is similar to or identical to that of the 3D semiconductor device 200. For example, the 3D semiconductor structure 300 may be a structure before the conductive material in the isolation region located between adjacent trench structures is outwardly coupled and / or before at least one conductive layer in the trench structure is cut to form two separate vertical gates. Note that positions A, B, C, D, and E are defined as being similar to or identical to those of the 3D semiconductor device 200 or a structure of the 3D semiconductor device 200 in an intermediate fabrication process. Figure 2B The positions shown are the same.

[0073] like Figure 3A As shown, the 3D semiconductor structure 300 includes a plurality of trench structures 310 located in a semiconductor substrate 301, for example, the trench structures 310 are formed from the front side of the semiconductor substrate 301. Adjacent trench structures 310 are separated by corresponding isolation regions 320 that may be formed in intermediate trenches between adjacent trench structures 310. The trench structures 310 may be connected with... Figure 2A-2B The trench structure 210 is similar to or the same as that of the trench. The isolation region 320 can be similar to... Figure 1 trench isolation 160 or Figure 2A-2B The isolation areas are similar to or the same as those in 220.

[0074] In some implementations, for example, such as Figure 3B As shown, the trench structure 310 and the isolation region 320 are formed based on corresponding trenches 313 and 323. The trenches 313 and 323 may have the same depth along the vertical direction (e.g., the Z direction). An isolation layer 302 (e.g., comprising an oxide) may first be formed on the inner surface of the trenches 313 and 323. Subsequently, a dielectric layer 304 (e.g., comprising SiN) may be formed on the isolation layer 302 in the trenches 313 and 323. Figure 4B-4E As discussed in more detail, the trench structure 310 includes an insulating material 306 deposited from the bottom of the trench 313 into a portion of the trench 313. At least one conductive layer 312 may be deposited on top of the insulating material 306 deposited in this portion of the trench 313. The at least one conductive layer 312 may be cut to form a vertical transistor (e.g., Figure 1 Vertical transistor 126 or Figure 2A The two independent vertical gates of the vertical transistors 212 and 214 (e.g., Figure 1 (Gate electrode 134). In some embodiments, a dielectric layer 303 is formed in an isolation layer 302 between adjacent trenches. The dielectric layer 303 may include a dielectric material, such as SiN.

[0075] In some examples, at least one conductive layer 312 includes an intermediate layer 312a (e.g., including TiN) and a metal layer 312b (e.g., including W). The trench structure 310 may include a high-k dielectric layer located between the at least one conductive layer 312 (e.g., intermediate layer 312a) and the dielectric layer 304. As discussed above, the at least one conductive layer 312 can be used as the gate electrode of a vertical transistor (e.g., Figure 1 The gate electrode 134) and / or word line (e.g., Figure 2B At least a portion of the word lines 230a, 230b. The gate electrode, dielectric layer 304, and isolation layer 302 can form the gate structure of a vertical transistor (e.g., Figure 1 (Gate structure 136).

[0076] In the vertical direction, the insulating material 306 deposited in this portion of trench 313 has a length (or thickness), for example, from the bottom surface of trench 313 to the bottom surface of the at least one conductive layer 312 (or vertical gate electrode) in trench 313. This length can be approximately tens of nm, for example, in the range of 10 nm to 100 nm. Therefore, the length of the at least one conductive layer 312 or the length of the vertical gate electrode to be formed is smaller than the depth of trench 313 than the length of the deposited insulating material 306. In contrast, the isolation region 320 includes a conductive material (e.g., a metal such as W) 322 that can be deposited from the bottom of trench 323 into trench 323. Figure 4D-4E As discussed in more detail, there is no insulating material 306 in trench 323, and the deposited conductive material 322 may have a length (or thickness or depth) from the bottom surface to the top surface of trench 323, which may be equal to the depth of trench 323. Since trenches 313 and 323 may have the same depth, the length of the conductive material 322 deposited throughout trench 323 in the vertical direction is greater than the length of the insulating material 306 deposited in that portion of trench 313, and also greater than the length of the at least one conductive layer 312 or the length of the vertical gate electrode.

[0077] The at least one conductive layer 312 may also be formed on top of the isolation region 320, for example, on top of the conductive material 322 deposited in the trench 323. An isolation layer 308 may be deposited on the at least one conductive layer 312. The isolation layer 308 may include an isolation material, such as an oxide. Figure 3B As shown, the isolation layer 308 can be formed in the trench 313 of the trench structure 310 and on top of the isolation region 320.

[0078] The 3D semiconductor structure 300 can be flip-chipped, so that the back side of the semiconductor substrate 301 faces upward, for example, to facilitate further processing. Figure 3C As shown, the semiconductor substrate 301 can be etched from the back side to expose the conductive material 322 in the isolation region 320 or the trench 323. Since the length of the conductive material 322 filling the trench 323 is greater than the length of at least one conductive layer 312 formed in the trench 313, the end of the conductive material 322 is closer to the back surface (e.g., the top surface) of the semiconductor substrate 301 than the end of the at least one conductive layer 312 in the trench 313.

[0079] like Figure 3C As shown, the semiconductor substrate 301 can be etched in the etching region 330. The etching region 330 may have a top edge z1 (e.g., the surface of the semiconductor substrate 301) and a bottom edge z2, and an etching depth d from the surface or top edge z1 to the bottom edge z2 of the semiconductor substrate. In the vertical direction, the etching depth d is greater than a first distance between the surface or top edge z1 of the semiconductor substrate 301 and the end 322z of the conductive material 322 filled in the trench 323, and less than a second distance between the surface or top edge z1 of the semiconductor substrate 301 and the end 312z of at least one conductive layer 312 deposited in the trench 313. In some embodiments, the etching region 330 has two opposing edges Y1, Y2 located within two adjacent trenches 313 in the horizontal direction (e.g., the Y direction). Because the etching region can extend into the adjacent trenches 313 without etching the vertical gate electrode, the etching window becomes larger compared to a structure without the isolation material 306 deposited in the trenches 313. In some implementations, the semiconductor substrate 301 is etched in an even larger etch region / window that spans multiple trench structures 310 and isolation regions 320 along the Y direction.

[0080] In some implementations, such as Figure 3A As shown, the 3D semiconductor structure 300 includes a first region 300a (e.g., Figure 2B First region 200a) and second region 300b (e.g., Figure 2B The second region 200b), which has a boundary line 305 along the X direction (e.g., Figure 2B Boundary line 205).

[0081] Figure 3D-3E Cross-sectional views of an exemplary 3D semiconductor structure 300 at different locations A, B, and C along the X-direction are shown. Figure 3DAs shown, positions A and B are located in a second region 300b (e.g., a connection region), while position C is located in a first region 300a (e.g., an array region). The trench structure 350 at position C is configured as a vertical gate for a vertical transistor of a memory cell in the second region 300b. Figure 4C-4E As described in more detail below, similar to isolation region 320, no isolation material 306 is deposited in trench 353 of trench structure 350. Furthermore, a dielectric layer 304 may not be formed in trench 353. At least one conductive layer 312 is conformally formed on isolation layer 302 in trench 353. Therefore, the length of the at least one conductive layer 312 in trench 353 (or the vertical gate formed in trench structure 350) is greater than the length of the at least one conductive layer 312 in trench 313 (or the vertical gate formed in trench structure 310).

[0082] The trench structure 340 at location B may be similar to or the same as the trench structure 310 at location A. The trench structure 340 includes an insulating material 306 filled in the bottom of the trench 343, at least one conductive layer 312 on top of the insulating material 306 filled in the trench 343, and an insulating layer 308 on the at least one conductive layer 312 in the trench 343. Because there is a dielectric layer 304 in the trench 343 and no dielectric layer 304 in the trench 353, the surface of the at least one conductive layer 312 adjacent to the trench 353 may be lower than the surface of the at least one conductive layer 312 adjacent to the trench 343, for example, as... Figure 3E As shown in the image.

[0083] In some embodiments, the semiconductor substrate 301 is etched from the back side of the semiconductor substrate 301 in an etch region / window located in the second region 300b but not in the first region 300a (e.g., not exceeding the boundary line 305 in the X direction). In some embodiments, the semiconductor substrate 301 is etched from the back side of the semiconductor substrate 301 in an etch region / window located in both the second region 300b and the first region 300a, thereby exposing and / or etching the conductive material 322 in the isolation region 320 in the second region 300b for outward coupling, and enabling the etching or cutting of at least one conductive layer 312 in the bottom of the trench 353 in the first region 300a to form the vertical gate of the vertical transistor of the memory cell. By etching the conductive material 322 in the isolation region 320 together with at least one conductive layer 312 for forming the vertical gate of the memory cell in the first region, the techniques implemented in this disclosure can reduce manufacturing costs and manufacturing difficulty, eliminate problems or risks caused by metal stamping from the front side of the semiconductor substrate (e.g., difficulty in controlling due to wire twisting), and optimize the manufacturing process (e.g., omitting one or more processing operations, such as costly oxide recess operations).

[0084] Figures 4A-4E Cross-sectional views of an exemplary 3D semiconductor structure at various stages of the fabrication process are shown. This 3D semiconductor structure can be used with... Figures 3A-3B The 3D semiconductor structure 300 is similar to or the same as that described above. Note that this is for illustrative purposes only. Figures 4A-4E Each of these figures includes a cross-sectional view of the corresponding structure in Figures (a) and (b). Figure (a) shows the cross-sectional views of the corresponding structure at positions A, D, and E in the YZ plane, while Figure (b) shows the cross-sectional views of the corresponding structure at positions A, B, and C in the XZ plane. The definitions of positions A, B, C, D, and E are... Figure 2B and Figures 3A-3E The definitions are the same.

[0085] Figure 5 This is a flowchart of an exemplary process 500 for forming a 3D semiconductor device. This 3D semiconductor device can be used with... Figure 1 The 3D semiconductor device 100 is similar to or the same as, or a part of, the 3D semiconductor device 100 (e.g., Figure 1 The second semiconductor structure 104) is similar to or the same as, or related to Figure 1 The structure of the 3D semiconductor device 100 in the intermediate fabrication process is similar to or the same as that of the 3D semiconductor device 100. Figure 2A-2B 3D semiconductor devices 200 are similar to or the same as, or related to Figures 3A-3E The 3D semiconductor structure is similar to or the same as, or related to, the 3D semiconductor structure 300. Figure 4EThe 3D semiconductor structure 400e is similar to or the same. See reference... Figures 4A-4E To describe process 500. Process 500 may include forming Figures 4A-4E The process of fabricating a 3D semiconductor structure. Process 500 includes operations (or steps) that can be performed in any suitable order and / or in any combination. The terms "operation" and "step" are used interchangeably to describe the processes in this disclosure.

[0086] In operation 510, a semiconductor substrate 401 is provided. The semiconductor substrate 401 can be coupled with… Figures 3A-3E The semiconductor substrate 301 is similar to or the same as the semiconductor substrate 401. The semiconductor substrate 401 may include silicon (e.g., single-crystal silicon, c-Si), SiGe, GaAs, Ge, SOI, or any other suitable material.

[0087] In operation 520, an isolation region 420 is formed between a plurality of adjacent vertical transistors in a semiconductor substrate. The isolation region 420 may be, for example... Figure 1 trench isolation 160, Figure 2A-2B The isolation area 220 or Figures 3A-3E The isolation region is 320. The vertical transistor can be, for example... Figure 1 Vertical transistor 126 or Figure 2A Vertical transistors 212 and 214. Each of the plurality of adjacent vertical transistors extends along a vertical direction (e.g., the Z direction), and a corresponding isolation region between two adjacent vertical transistors is disposed along a first lateral direction (e.g., the Y direction) perpendicular to the vertical direction. The corresponding isolation region includes a conductive material (e.g., Figures 3A-3E The conductive material 322), and along the vertical direction, the length of the conductive material in the corresponding isolation region is greater than the length of the vertical gate of each of the two adjacent vertical transistors, for example, as Figures 3A-3E As shown in the image.

[0088] In some embodiments, operation 520 includes sub-operations 522, 524, and 526. In sub-operation 522, a plurality of trenches are formed in the semiconductor substrate 401 (e.g., 413, 423, 443, and 453 at locations A, B, C, D, and E), for example, as... Figure 4A As shown in the diagram. Grooves 413, 423, 443, and 453 can respectively connect with... Figures 3A-3EThe trenches 313, 323, 343, and 353 are similar or identical. These trenches extend in a vertical direction. These trenches may have the same depth in the vertical direction (e.g., the Z direction) and / or the same width in a first lateral direction (e.g., the Y direction) and / or the same width in a second lateral direction (e.g., the X direction). The semiconductor substrate 401 may have a front side and a back side, and the plurality of trenches may be formed from the front side of the semiconductor substrate 401. In some embodiments, one or more layers (e.g., an isolation layer 402a and a dielectric layer 403) are deposited on the surface of the front side of the semiconductor substrate 401, and the deposited one or more layers are patterned and etched through to the semiconductor substrate 401 to form the trenches.

[0089] In some implementations, for example, such as Figure 4A As shown, isolation layer 402 (e.g., Figures 3A-3E An isolation layer 302 is conformally formed on the inner surface of each of the trenches 413, 423, 443, and 453. The isolation layer 402 may include an isolation material, such as an oxide. A dielectric layer 404 (e.g., Figures 3A-3E A dielectric layer 304 is formed on the isolation layer 402 within and outside trenches 413, 423, 443, and 453. The dielectric layer 404 may include a dielectric material, such as SiN. Figures (a) and (b) illustrate a trench structure 400a after the isolation layer 402 and the dielectric layer 404 are formed in trenches 413, 423, 443, and 453. The semiconductor substrate 401 may include a first region forming an array region (e.g., Figure 2B First area 200a or Figures 3A-3E The first region 300a) and the second region forming the connecting region (e.g., Figure 2B Second area 200b or Figures 3A-3E The second region 300b). The first and second regions have a boundary line 405 (e.g., Figure 2B Boundary line 205 or Figures 3A-3E Boundary line 305).

[0090] In some embodiments, process 500 further includes depositing an insulating material 406 (e.g., an oxide) to fill portions of each of trenches 413, 423, 443, and 453 in a vertical direction. The resulting structure 400b includes the insulating material 406 deposited in portions of trenches 413, 423, 443, and 453, respectively, for example, as... Figure 4B As shown in the diagram, the deposited insulating material 406 may have a length (or thickness) in the vertical direction from the bottom of trenches 413, 423, 443, 453. This length may be approximately tens of nm, for example, in the range of 10 nm to 100 nm.

[0091] In some embodiments, process 500 further includes: patterning photoresist 430 to cover two adjacent trenches 413 at locations A and E and expose an intermediate trench 423 at location D along the Y direction, and expose a trench 453 at location C in the first region, and cover trenches 413 and 443 at locations A and B along the X direction in the second region. For example... Figure 4C As shown in Figures (a) and (b), in the formed structure 400c, photoresist 430 is inserted into trenches 413, 443 to fill trenches 413, 443 and cover the surfaces adjacent to trenches 413, 443, while no photoresist 430 is present in the intermediate trench 423 in the second region and in the trench 453 in the first region.

[0092] In some embodiments, process 500 further includes, for example, etching the insulating material 406 deposited in the intermediate trench 423 in the second region and in the trench 453 in the first region by wet etching. For example, process 500 may further etch the dielectric layer 404 deposited in the intermediate trench 423 in the second region and in the trench 453 in the first region by wet etching. Note that the insulating layer 402 in the trenches 423, 453 remains unetched. Figure 4D Etching is shown Figure 4C The structure 400d is formed after structure 400c. It shows that the isolation material 406 and the deposited dielectric layer 404 deposited in trenches 423 and 453 are etched away, while the isolation material 406 and the deposited dielectric layer 404 deposited in trenches 413 and 443 are still protected by photoresist 430.

[0093] In operation 524, a corresponding isolation region 420 is formed by depositing conductive material 462 in an intermediate trench 423 between two adjacent trenches 413. For example... Figure 4E As shown in Figure (a), conductive material 462 can be filled in intermediate trench 423. In some embodiments, a dielectric layer 464 is deposited on the isolation layer 402 in intermediate trench 423 before the conductive material 462 is filled in intermediate trench 423. In some embodiments, during the deposition of dielectric layer 464 and conductive material 462 in intermediate trench 423, trench 453 in the first region is protected from deposition, for example, by forming another photoresist in the first region. After the isolation region 420 is formed, the photoresist 430 is removed.

[0094] In operation 526, at least one conductive layer 412 is deposited on the formed structure. This at least one conductive layer 412 can be conformally deposited on top of the dielectric layer 404 and the insulating material 406 deposited in the trenches 413, 443. The at least one conductive layer 412 can also be deposited on the isolation region 420, and can conformally be deposited on the insulating layer 402 in the trench 453 of the first region. The at least one conductive layer 412 can be... Figures 3A-3E At least one conductive layer 312 is similar to or identical to the conductive layer 412. In some embodiments, at least one conductive layer 412 includes an intermediate layer 412a (e.g., Figures 3A-3E The intermediate layer 312a) and the metal layer 412b (e.g., Figures 3A-3E (Metal layer 312b). In some embodiments, a high-k dielectric layer may be deposited on the isolation layer 402 in the trench 453 and on the dielectric layer 404 in the trenches 413 and 443 before depositing the at least one conductive layer 412.

[0095] In some embodiments, process 500 further includes depositing an isolation layer 408 on at least one conductive layer 412. Figure 4E The structure 400e formed after the deposition of the isolation layer 408 is shown. Structure 400e can be combined with... Figures 3A-3E The 3D semiconductor structure is the same as 300. For example, Figure 4E The illustration (a) can be compared with Figure 3A The same as diagram (b), and Figure 4E The diagram (b) can be compared with Figure 3E The same. Structure 400e may include trench structures 410 at locations A and E (e.g., Figures 3A-3E The trench structure 310), the isolation area 420 at location D (e.g., Figures 3A-3E The isolation area 320), the trench structure 440 at location B (for example, Figures 3A-3E The trench structure 340), and the trench structure 450 (e.g., Figures 3A-3E The trench structure is 350.

[0096] As noted above, in the vertical direction, the length of at least one conductive layer 412 deposited in adjacent trenches 413 is less than the length of the conductive material 462 filled in the intermediate trench 423, for example, as Figure 4E As shown in Figure (a). The length of at least one conductive layer 412 deposited in trenches 413, 443 in the second region is also less than the length of the at least one conductive layer 412 in trench 453 in the first region, as shown in Figure (a). Figure 4E As shown in illustration (b).

[0097] In some embodiments, as noted above, along the vertical direction, since there is a dielectric layer 404 in trench 443 and no dielectric layer 404 in trench 453, the surface of the at least one conductive layer 412 adjacent to trench 453 can be lower than the surface of the at least one conductive layer 412 adjacent to trench 443. For example, as Figure 4E As shown in illustration (b) in the figure.

[0098] In some embodiments, process 500 further includes: for each of trench structures 410, 440, 450, dicing at least one conductive layer 412 deposited in trenches 413, 443, 453 to form two separate vertical gates (e.g., for each of trench structures 410, 440, 450) of a pair of independent vertical transistors in trenches 413, 443, 453. Figure 1 The gate electrode 134), for example, such as Figure 2B As shown in the diagram. The vertical gate can be coupled to a word line or serve as a word line (e.g., Figure 2B The portion of word lines 230a, 230b). Accordingly, the length of each of the vertical gates in trenches 413, 443 in the second region is less than the length of the conductive material 462 in the isolation region 420, and less than the length of the vertical gate in trench 453 in the first region.

[0099] In some embodiments, process 500 further includes etching the semiconductor substrate 401 from the back side of the semiconductor substrate 401 to expose the conductive material 462 in the corresponding isolation region 420, without exposing the vertical gates (or at least one deposited conductive layer 412) of two adjacent vertical transistors in the adjacent trench structure 410, for example, as Figure 3C As shown in the figure. In some embodiments, along the vertical direction, from the surface of the semiconductor substrate 401 (e.g., Figure 3C z1 in the etched area (e.g., Figure 3C The semiconductor substrate is etched in the etch region 330. The etch region has a bottom edge (e.g., Figure 3C z2) and the etching depth from the surface of the semiconductor substrate to the bottom edge (e.g., Figure 3C (d) In the vertical direction, the depth is greater than the surface of the semiconductor substrate 401 and the end of the conductive material filling the intermediate trench 423 (e.g., Figure 3C The first distance between the surface of the semiconductor substrate and the end of at least one conductive layer deposited in each of the two adjacent trenches 413 (e.g., 322z) is smaller than the distance between the surface of the semiconductor substrate and the end of at least one conductive layer deposited in each of the two adjacent trenches 413 (e.g., Figure 3C The second distance between 312z in the middle. In some embodiments, the etched area has two opposing edges located within two adjacent trenches in the horizontal direction (e.g., Figure 3C(Y1, Y2 in the text).

[0100] In some embodiments, process 500 further includes: forming corresponding conductive interconnects in the back side of semiconductor substrate 401 that contact the exposed conductive material 462 in the corresponding isolation region 420 (e.g., Figure 2B The conductive interconnect 240). In some embodiments, process 500 further includes: forming a plurality of bit lines on the back side of semiconductor substrate 401 (e.g., Figure 1 bit line 123 or Figure 2A-2B Bit line 202).

[0101] In some implementations, process 500 includes: forming an array structure in a first region. The array structure may include multiple memory cells (e.g., Figure 1 The memory cells 124 are strung together. Each memory cell includes a corresponding vertical transistor (e.g., Figure 1 Vertical transistor 126 or Figure 2A Vertical transistors 212, 214). Isolation region 420 and trench structures 410, 440 are formed in a second region adjacent to the first region.

[0102] Figure 6 A block diagram of a system 600 having one or more semiconductor devices (e.g., memory devices) according to one or more embodiments of the present disclosure is shown. System 600 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other electronic device having storage components located therein. Figure 6 As shown, system 600 may include a host device 608 and a memory system 602, the memory system 602 having one or more 3D memory devices 604 and a memory controller 606. The host device 608 may include a processor of an electronic device, such as a central processing unit (CPU), or may include a system-on-a-chip (SoC), such as an application processor (AP). The host device 608 may be configured to send data to or receive data from one or more 3D memory devices 604.

[0103] 3D memory device 604 can be any 3D memory device disclosed herein, for example, Figure 1 , Figure 2A-2B The 3D memory device depicted or based on Figures 3A-3BA 3D memory device 604 is a 3D semiconductor structure 300. In some embodiments, the 3D memory device 604 includes NAND flash memory. A memory controller 606 (also known as controller circuitry) is coupled to the 3D memory device 604 and a host device 608. Consistent with embodiments of this disclosure, the 3D memory device 604 may include a plurality of conductive interconnects that pass through a cover layer and contact conductive pads in a conductive pad layer, and the memory controller 606 may be coupled to the 3D memory device 604 through at least one of the plurality of conductive interconnects. The memory controller 606 is configured to control the 3D memory device 604. For example, the memory controller 606 may be configured to operate a plurality of channel structures via word lines. The memory controller 606 may manage data stored in the 3D memory device 604 and communicate with the host device 608.

[0104] In some embodiments, the memory controller 606 is designed / configured to operate in a low duty cycle environment, such as a Secure Digital (SD) card, Compact Flash (CF) card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In some embodiments, the memory controller 606 is designed / configured to operate in a high duty cycle environment, such as an SSD or embedded multimedia card (eMMC), used as a data storage component in mobile devices such as smartphones, tablets, and laptops, as well as in enterprise storage arrays. The memory controller 606 may be configured to control the operation of the 3D memory device 604, such as read, erase, and program (or write) operations. The memory controller 606 may also be configured to manage various functions related to storing or to be stored in the 3D memory device 604, including but not limited to bad block management, garbage collection, logic-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 606 is further configured to process error correction codes (ECC) related to data read from or written to the 3D memory device 604. The memory controller 606 may also perform any other appropriate function, such as formatting the 3D memory device 604.

[0105] The memory controller 606 can communicate with external devices (e.g., host device 608) according to a specific communication protocol. For example, the memory controller 606 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, High Speed ​​PCI (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.

[0106] The memory controller 606 and one or more 3D memory devices 604 can be integrated into various types of storage devices, for example, contained within the same package (such as a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 602 can be implemented and packaged into different types of end electronic products. Figure 6 In one example shown, the memory controller 606 and a single 3D memory device 604 can be integrated into the memory card. The memory card can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc.

[0107] The embodiments, actions, and operations of the subject matter described in this disclosure can be implemented in digital electronic circuits as computer software or firmware, computer hardware (including the structures disclosed in this disclosure and their equivalents), or one or more combinations thereof. Embodiments of the subject matter described in this disclosure can be implemented as one or more computer programs, for example, one or more modules of computer program instructions encoded on a computer program carrier for execution by a data processing device or for controlling the operation of the data processing device. The carrier can be a tangible, non-transitory computer storage medium. Alternatively, or additionally, the carrier can be an artificially generated propagation signal, such as a machine-generated electrical signal, optical signal, or electromagnetic signal, generated to encode information for transmission to a suitable receiving device for execution by the data processing device. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of or part thereof. The computer storage medium is not a propagation signal.

[0108] It should be noted that in this disclosure, references to "an embodiment," "an embodiment," "an exemplary embodiment," "some implementations," etc., indicate that the described implementation may include specific features, structures, or characteristics, but not every implementation necessarily includes that specific feature, structure, or characteristic. Furthermore, such wording does not necessarily refer to the same implementation. Moreover, when a specific feature, structure, or characteristic is described in connection with an implementation, implementing such a feature, structure, or characteristic in conjunction with other implementations, whether explicitly described or not, is within the knowledge scope of those skilled in the art.

[0109] Generally, terminology should be understood at least partly by its usage in context. For example, the word "one or more" as used herein can be used, at least partly according to context, to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, words such as "a," "one," or "described" can be understood to express either a singular or a plural usage, at least partly according to context. Furthermore, the word "based on" can be understood not necessarily to express an exclusive set of factors, but rather to allow for the existence of other factors that are not necessarily explicitly stated, at least partly according to context.

[0110] It should be readily understood that the meanings of "on," "above," and "on top of" in this disclosure should be interpreted in the broadest sense, thus "on" not only means being directly on something, but also includes the meaning of having an intermediate feature or layer between them when being on something. Furthermore, "above" or "on top of" not only means being above or on something, but also includes the meaning of being above or on something without any intermediate feature or layer between them (i.e., being directly on something).

[0111] Furthermore, for ease of explanation, spatial relative terms such as "below," "under," "down," "above," and "above" may be used herein to describe the relationship of an element or feature to one or more other elements or features as shown in the figures. Spatial relative terms are intended to encompass different orientations of the apparatus in use or process steps, other than those shown in the figures. The apparatus may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0112] As used herein, the term "substrate" refers to the material on which subsequent layers of material are added. A substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed, and therefore semiconductor devices are formed on the top side of the substrate, unless otherwise specified. The bottom surface is opposite the top surface, and therefore the bottom side of the substrate is opposite the top side. The substrate itself can be patterned. The material added to the top of the substrate can be patterned, or it can remain unpatterned. Furthermore, the substrate can comprise a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0113] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, while the top side is relatively far from the substrate. A layer may extend over the entirety of the underlying or upper structure, or it may have a smaller extent than the underlying or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between any set of horizontal planes between, or at, the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may contain one or more layers therein, and / or may have one or more layers located on, above, and / or below it. A single layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers (in which contacts, interconnects, and / or vertical interconnect channels (VIAs) are formed) and one or more dielectric layers.

[0114] As used herein, the term "nominal / nominally" refers to a desired or target value, along with a range of values ​​higher and / or lower than the desired value, for a characteristic or parameter of a component or process step set during the design phase of a product or process. As used herein, this range may be attributable to slight variations in manufacturing processes or tolerances. As used herein, the term "approximately" indicates that the value of a given quantity may vary based on a specific technology node associated with the semiconductor device in question. Based on a specific technology node, the term "approximately" may indicate that the value of a given quantity varies within, for example, 10-30% of that value (e.g., ±10%, ±20%, or ±30%).

[0115] In this disclosure, the terms "horizontal / horizontally / laterally" refer to a lateral surface that is nominally parallel to the substrate, and the terms "vertical" or "perpendicularly" refer to a lateral surface that is nominally perpendicular to the substrate.

[0116] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as “memory strings,” e.g., NAND strings) located on a laterally oriented substrate, such that the memory strings extend vertically relative to the substrate.

[0117] This disclosure provides numerous different implementations or examples of various features for carrying out the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to constitute limitation. For example, the formation of a first feature on or above a second feature as described below can include implementations where the first and second features are in direct contact, and can also include implementations where an additional feature can be formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples in this disclosure. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or configurations discussed.

[0118] The descriptions of the specific embodiments described above can be easily modified and / or adjusted for various applications. Therefore, based on the teachings and guidance provided herein, it is intended that such adjustments and modifications fall within the meaning of the disclosed embodiments and their equivalents.

[0119] Although this disclosure contains many specific implementation details, these should not be construed as limiting the scope of the claimed protection, which is defined by the claims themselves, but should only be understood as descriptions of features specific to particular embodiments. Certain features described in the context of multiple individual embodiments in this disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, while certain features may be described above as functioning in a particular combination and even initially claimed accordingly, one or more features from the claimed combination may be removed from that combination in certain circumstances, and the claims may relate to sub-combinations or variations thereof.

[0120] Similarly, although the operations are depicted in a specific order in the accompanying drawings and are described in a specific order in the claims, this should not be construed as requiring the operations to be performed in the specific order shown or in a sequential manner, or as requiring all of the shown operations to be performed, in order to obtain the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the division of various system modules and components in the embodiments described above should not be construed as requiring such division in all embodiments, and it should be understood that the described program components and systems can generally be integrated together into a single software product or packaged into multiple software products.

[0121] Specific embodiments of this subject matter have been described. Other embodiments are also within the scope of the appended claims. For example, the actions set forth in the claims can be performed in different orders and still achieve the desired result. As an example, the processes shown in the accompanying drawings do not necessarily require the specific order or sequence shown to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous.

[0122] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but only by the appended claims and their equivalents.

Claims

1. A method for use in a semiconductor device, comprising: Provide semiconductor substrates; as well as An isolation region is formed between multiple adjacent vertical transistors in the semiconductor substrate. Each of the plurality of adjacent vertical transistors extends in a vertical direction, and the corresponding isolation region between two adjacent vertical transistors is provided in a horizontal direction perpendicular to the vertical direction. The corresponding isolation region comprises a conductive material, and wherein, along the vertical direction, the length of the conductive material in the corresponding isolation region is greater than the length of the vertical gate of each of the two adjacent vertical transistors. The semiconductor substrate includes a first side and a second side opposite to the first side, and The method further includes: etching the semiconductor substrate from the second side of the semiconductor substrate to expose the conductive material in the corresponding isolation region without exposing the vertical gates of the two adjacent vertical transistors.

2. The method according to claim 1, wherein, Forming the isolation region between the plurality of adjacent vertical transistors in the semiconductor substrate includes: A plurality of trenches are formed in the semiconductor substrate, the plurality of trenches being disposed along the horizontal direction, and each of the plurality of trenches extending along the vertical direction; and The corresponding isolation region is formed by depositing the conductive material in the intermediate trench between two adjacent trenches used to form the two adjacent vertical transistors.

3. The method according to claim 2, further comprising: The two adjacent vertical transistors are formed by depositing an isolation material in the two adjacent trenches and then depositing at least one conductive layer on the isolation material deposited in the two adjacent trenches to form the vertical gate of the two adjacent vertical transistors. Wherein, along the vertical direction, the length of at least one conductive layer deposited in each of the two adjacent trenches is less than the length of the conductive material filled in the intermediate trench.

4. The method of claim 3, wherein, Forming the isolation region between the adjacent vertical transistors in the semiconductor substrate includes forming the isolation region between the adjacent vertical transistors in the semiconductor substrate from a first side of the semiconductor substrate.

5. The method of claim 2, wherein, Etching the semiconductor substrate from the second side of the semiconductor substrate includes: The semiconductor substrate is etched from its surface along the vertical direction in the etching region. The etched area has a bottom edge and an etch depth from the surface of the semiconductor substrate to the bottom edge. Wherein, along the vertical direction, the etching depth is greater than a first distance between the surface of the semiconductor substrate and the end of the conductive material filled in the intermediate trench, and less than a second distance between the surface of the semiconductor substrate and the end of at least one conductive layer deposited in each of the two adjacent trenches.

6. The method of claim 1, further comprising: A corresponding conductive interconnect is formed in the second side of the semiconductor substrate, which contacts the conductive material exposed in the corresponding isolation region.

7. The method of claim 1, further comprising: Multiple bit lines are formed from the second side of the semiconductor substrate.

8. The method according to any one of claims 3 to 5, wherein, The method includes: The insulating material is deposited to fill a portion of each of the plurality of trenches along the vertical direction; The photoresist is patterned to cover the two adjacent trenches and expose the middle trench; Etch the insulating material deposited in the intermediate trench; The conductive material is deposited in the intermediate trench to form the corresponding isolation region; and The photoresist is removed, and at least one conductive layer is deposited on the insulating material deposited in the two adjacent trenches to form the vertical gate of the two adjacent vertical transistors.

9. The method of any one of claims 3 to 5, wherein, The method includes: For each of the two adjacent trenches, at least one conductive layer deposited in the trench is cut to form two separate vertical gates of a pair of independent vertical transistors in the trench.

10. The method according to any one of claims 3 to 5, further comprising: An array structure is formed in a first region, the array structure comprising multiple strings of memory cells, each memory cell in the multiple strings of memory cells comprising a corresponding vertical transistor. The plurality of adjacent vertical transistors and the isolation region in the semiconductor substrate are formed in a second region adjacent to the first region.

11. The method of claim 10, wherein, Forming the array structure includes: The corresponding vertical transistors of the plurality of memory cell strings are formed by depositing the at least one conductive layer in the corresponding trenches. Wherein, along the vertical direction, the length of at least one conductive layer deposited in the corresponding trench in the first region is greater than the length of the vertical gate of each of the two adjacent vertical transistors in the second region.

12. The method according to claim 11, wherein, The method includes: The insulating material is deposited to fill a portion of each of the two adjacent trenches for the two adjacent vertical transistors in the second region and the corresponding trench for the memory cell in the first region along the vertical direction. The photoresist is patterned to cover the two adjacent trenches and expose the corresponding trenches; Etch the insulating material deposited in the corresponding trenches; Remove the photoresist to expose the two adjacent trenches; and At least one conductive layer is deposited on the isolation material deposited in the two adjacent trenches to form the vertical gate of the two adjacent vertical transistors, and at least one conductive layer is deposited in the corresponding trench to form the vertical transistor for the memory cell.

13. A semiconductor device, comprising: Semiconductor substrate; A plurality of vertical transistors are located in the semiconductor substrate in a horizontal direction, each of the plurality of vertical transistors extending in a vertical direction perpendicular to the horizontal direction; as well as A plurality of isolation regions are located in the semiconductor substrate, each of the plurality of isolation regions being situated along the horizontal direction between two adjacent vertical transistors among the plurality of vertical transistors. The isolation region comprises a conductive material, and wherein, along the vertical direction, the length of the conductive material in the isolation region is greater than the length of the vertical gate of each of the two adjacent vertical transistors. The semiconductor substrate includes a first side and a second side opposite to the first side. Wherein, the vertical gate of each of the two adjacent vertical transistors includes at least one conductive layer on an insulating material filled in a portion of a corresponding trench in two adjacent trenches corresponding to the two adjacent vertical transistors, and The semiconductor device further includes: Conductive interconnects formed in the second side of the semiconductor substrate, wherein each conductive interconnect is in contact with the conductive material in a corresponding isolation region of the plurality of isolation regions, and along the vertical direction from the second side of the semiconductor substrate, each conductive interconnect has an end higher than the end of the at least one conductive layer in each of the two adjacent trenches.

14. The semiconductor device of claim 13, wherein, The isolation region includes the conductive material filled in the intermediate trench between the two adjacent trenches corresponding to the two adjacent vertical transistors, and Wherein, along the vertical direction, the length of at least one conductive layer in each of the two adjacent trenches is less than the length of the conductive material filling the intermediate trench.

15. The semiconductor device of claim 13, wherein, in, The plurality of isolation regions and the plurality of vertical transistors are located on the first side of the semiconductor substrate.

16. The semiconductor device of claim 14 or 15, further comprising: An array structure located in the first region, the array structure comprising multiple strings of memory cells, each memory cell in the multiple strings of memory cells comprising a vertical transistor having a vertical gate. The plurality of isolation regions and the plurality of vertical transistors are formed in a second region of the semiconductor substrate adjacent to the first region along a third direction perpendicular to the vertical direction and the horizontal direction.

17. The semiconductor device of claim 16, wherein, Along the vertical direction, the length of the vertical gate of the vertical transistor of the memory cell in the first region is greater than the length of the vertical gate of each of the two adjacent vertical transistors in the second region.

18. The semiconductor device of claim 16, wherein, Along the third direction, the vertical gate of the vertical transistor of the memory cell in the first region is in direct contact with the first isolation layer, while the vertical gate of each of the two adjacent vertical transistors in the second region is separated from the second isolation layer by a passivation layer.

19. A memory system comprising: Memory devices, including: Semiconductor substrate; A plurality of vertical transistors are located horizontally in the semiconductor substrate, each of the plurality of vertical transistors extending in a vertical direction perpendicular to the horizontal direction; and A plurality of isolation regions are located in the semiconductor substrate, each of the plurality of isolation regions being situated between two adjacent vertical transistors along the horizontal direction, wherein the isolation region comprises a conductive material, and wherein, along the vertical direction, the length of the conductive material in the isolation region is greater than the length of the vertical gate of each of the two adjacent vertical transistors; and A controller, coupled to and configured to control the memory device. The semiconductor substrate includes a first side and a second side opposite to the first side. Wherein, the vertical gate of each of the two adjacent vertical transistors includes at least one conductive layer on an insulating material filled in a portion of a corresponding trench in two adjacent trenches corresponding to the two adjacent vertical transistors, and The memory device further includes: Conductive interconnects formed in the second side of the semiconductor substrate, wherein each conductive interconnect is in contact with the conductive material in a corresponding isolation region of the plurality of isolation regions, and along the vertical direction from the second side of the semiconductor substrate, each conductive interconnect has an end higher than the end of the at least one conductive layer in each of the two adjacent trenches.

20. The memory system of claim 19, wherein, The isolation region includes the conductive material filled in an intermediate trench between two adjacent trenches corresponding to the two adjacent vertical transistors, and Wherein, along the vertical direction, the length of at least one conductive layer in each of the two adjacent trenches is less than the length of the conductive material filling the intermediate trench.

Images