Novel device architecture of resistive random access memory

Abstract

An access transistor array for a memory device includes a plurality of active regions (AAs) formed on a substrate. Each active region includes a drain region and a source region arranged in a first direction (Y), and a polysilicon gate (PO) extends through the active region in a second direction (X) to separate the drain region from the source region. Adjacent source regions in the second direction are connected, and adjacent drain regions in the second direction are separated by shallow trench isolation (STI) structures. According to the structure, the spacing between the polycrystalline silicon gates (PO) is reduced, so that the total area required by each memory unit is reduced, and the memory density is improved.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is a continuation of an international patent application filed with the State Intellectual Property Office of China on November 26, 2024 and having an international patent application number of PCT / CN2024 / 134493. The above application is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention generally relates to a novel process technology of resistive random access memory, and more specifically to an embedded memory integration technology capable of reducing the size of a bit unit. Background Art

[0004] Resistive random access memory (RRAM) is a non-volatile memory that can change its resistance to a low resistance state (LRS) or a high resistance state (HRS) by applying a suitable voltage to the memory. The difference in resistance (the difference between LRS and HRS) can be used to store digital data "0" and "1".

[0005] In the semiconductor industry, as the demand for storage density and cost-effective manufacturing processes increases, the size of the memory bit cell (i.e., the smallest unit in which a memory can store one bit of information) becomes a key factor affecting the economic viability of memory chips. Reducing the bit cell size directly affects the overall chip area, allowing more chips to be manufactured on a single wafer, thereby reducing production costs.

[0006] Current RRAM architectures have difficulty minimizing the bit cell size without sacrificing performance and reliability. Traditionally, the bit cell size is reduced by designing or processing with more margins (e.g., by shortening the distance between devices). This makes the process more susceptible to defects and thus affects the yield of the memory chip.

[0007] On the other hand, three-dimensional (3D) memory integration is at another level of complexity. Although RRAM integration through methods such as 3D stacking can definitely increase storage density, such processes are not yet mature and still require a lot of research and development.

[0008] Therefore, an improved RRAM device architecture is needed to solve the above problems by reducing the bit cell size while maintaining or improving performance indicators and chip yield. Innovation in this area will help develop more compact and cost-effective memory chips, which is in line with the industry's pursuit of higher density and higher scalability in non-volatile storage technology. Summary of the invention

[0009] In one general aspect, an access transistor array may include a plurality of active areas (AA) formed on a substrate, each active area including a drain region and a source region arranged along a first direction (Y) and a polysilicon gate (PO) extending through the active area along a second direction (X) and separating the drain region and the source region. The access transistor array may further include a connection structure, wherein adjacent source regions in the second direction are connected, and adjacent drain regions in the second direction are separated by a shallow trench isolation (STI) structure. Other implementation forms of this aspect include corresponding computer systems, apparatuses, and computer programs recorded in one or more computer storage devices, each for performing operations in the corresponding method.

[0010] A specific implementation scheme may include one or more of the following technical features. In the access transistor array, each drain region may include a drain contact, and adjacent source regions in the second direction share the same source contact. In the access transistor array, the drain contacts in adjacent drain regions in the first direction are connected to a bit line, and adjacent source regions in the second direction are connected to the same source contact through a source line. In the access transistor array, the length of the source region in the first direction may be at least 10% smaller than the length of the drain region in the first direction, or at least 20% smaller. The bit line is perpendicular to the source line. In addition, in the access transistor array, the distance between two adjacent polysilicon gates sandwiched between the source region may be at least 10% smaller than the distance between two adjacent polysilicon gates sandwiched between the drain region, or at least 20% smaller. The memory device may be a back-end-of-line (BEOL) memory, or a resistive random access memory (RRAM). The source line may be connected to a first metal layer in the memory device that is closest to the substrate. In addition, the access transistor array may include a word line, wherein the word line is constructed to be parallel to the source line.

[0011] In one general aspect, a method may include: providing a plurality of active areas (AA) on a substrate, each active area including a drain region and a source region arranged along a first direction (Y). The method may further include: forming a polysilicon gate (PO) extending through the active area along a second direction (X) and separating the drain region and the source region. In addition, the method may include: forming a shallow trench isolation (STI) structure extending along the first direction and separating adjacent drain regions in the second direction. The method may further include: connecting adjacent source regions in the second direction and separating adjacent drain regions in the second direction with a shallow trench isolation (STI) structure. In addition, the method may include: forming a memory device above the substrate. Other embodiments of this aspect include corresponding computer systems, apparatuses, and computer programs recorded in one or more computer storage devices, each of which is used to perform the operations in the method.

[0012] Specific implementations may include one or more of the following technical features. The method may further include: forming a drain contact in each of the drain regions, wherein a bit line is connected to each column of drain contacts in the first direction. The method may further include: for each row of source regions in the second direction, forming a source contact and connecting a source line to the row of source regions. Specific implementations of the technology may include hardware, methods or processes, or tangible computer media.

[0013] In one general aspect, an access transistor array may include a plurality of active areas (AA) formed on a substrate, each active area including a drain region and a source region arranged along a first direction (Y) and a polysilicon gate (PO) extending through the active area along a second direction (X) and separating the drain region and the source region. The access transistor array may further include a connection structure, wherein adjacent drain regions in the second direction are connected to each other at the connection structure, and adjacent source regions in the second direction are separated by a shallow trench isolation (STI) structure. Each source region may include a source contact, and adjacent drain regions in the second direction may share the same drain contact. The source contacts in adjacent source regions in the first direction may be connected to a source line, and adjacent drain regions in the second direction may be connected to the same drain contact via a drain line. Specific implementation forms of the technology may include hardware, methods or processes, or tangible computer media. Other implementation forms of this aspect include corresponding computer systems, apparatuses, and computer programs recorded in one or more computer storage devices, each for performing operations in the corresponding method. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Non-limiting embodiments of the present invention will be more readily understood by reference to the following drawings.

[0015] Figure 1 Schematic diagram of the common RRAM device architecture in the industry.

[0016] Figure 2 FIG. 4 is a schematic diagram of a novel RRAM device architecture using a shared active area (AA) layout according to an embodiment of the present invention.

[0017] Figures 3 to 6 FIG. 4 is a schematic diagram comparing different aspects of a conventional RRAM device architecture and a novel RRAM device architecture adopting a shared active region layout according to an embodiment of the present invention.

[0018] Figure 7 FIG. 1 is a schematic diagram of various layers in a novel RRAM device architecture adopting a shared active area layout according to an embodiment of the present invention.

[0019] Figure 8FIG. 1 is a flowchart of a manufacturing process of a RRAM using a shared active region layout according to an embodiment of the present invention. DETAILED DESCRIPTION

[0020] Resistive random access memory (RRAM) is an emerging non-volatile storage technology that stores data by changing the resistance of storage cells. This innovative architecture has the advantages of high density, low power consumption, and fast switching speed, making it a very promising candidate for future memory applications.

[0021] At the heart of the RRAM device architecture is the bit cell, which consists of a storage element sandwiched between two electrodes. The storage element typically consists of a material whose resistance can be reversibly changed by applying a voltage, allowing it to represent binary data.

[0022] The key to the function of RRAM devices lies in the following key components:

[0023] Active Area (AA): The region in a semiconductor substrate where transistors are formed. These transistors are used as selection devices in RRAM to enable or control access to memory cells. The memory switching itself occurs in RRAM during the back end of line (BEOL) of the semiconductor device.

[0024] Shallow Trench Isolation (STI) structure: The STI structure is used to electrically isolate active regions of adjacent cells.

[0025] Polysilicon Gate (Poly or PO): The polysilicon gate controls the flow of current in the underlying transistor associated with each memory cell. By applying a voltage to the gate, the conductivity of the channel between the source and drain can be adjusted, effectively turning the transistor on or off. This gating mechanism is critical for accessing the memory cell during read and write operations.

[0026] Source and drain contacts of a transistor: These two contacts provide a path for current to enter and leave the channel of the transistor. The transistor source is the end where carriers (electrons or holes) enter the channel, while the transistor drain is the end where carriers leave the channel.

[0027] Figure 1 Schematic diagram of a common RRAM device architecture in the industry, wherein a shallow trench isolation (STI) structure 108 separates an active area (AA) 100 along the X direction. The isolation structure serves as an insulating barrier to prevent electrical interference between adjacent active areas, so that each memory cell can operate independently without crosstalk or leakage current affecting adjacent cells.

[0028] like Figure 1As shown, within each active area 100, the contacts are arranged in the Y direction in a specific pattern as follows: first the drain contact 120, then the source contact 110, and then another drain contact 120. This alternating arrangement sequence runs through the entire active area 100. The drain contact and the source contact are critical to the operation of the transistor and help the current flow during read and write operations. In the Y direction, each drain contact 120 is separated from the adjacent source contact 110 by an X-direction polysilicon gate (Poly) 102. Such a polysilicon gate acts as a control electrode for the transistor, effectively dividing each active area into a clear drain region and source region. The polysilicon gate 102 adjusts the conductivity between the drain region and the source region so that the memory can be accessed or isolated from other parts of the circuit.

[0029] In this architecture, each bit cell includes at least a drain region and a source region to form the basic unit required for data access. Figure 1 As shown, bit cell #1 (104) and bit cell #2 (106) share a source contact in the same active area 100. The purpose of designing this source sharing structure is to make adjacent bit cells more densely packed without sacrificing their respective functions. By sharing the source, the routing of the connection structure is simplified and the number of required contacts and interconnect structures can be reduced, thereby improving the overall performance of the memory array.

[0030] Figure 2 Schematic diagram of a novel RRAM device architecture 200 using a shared active area layout according to an embodiment of the present invention. In this architecture, each active area (such as 202, 204 and 206) is connected along the X direction, and a common source contact 210 located on one side of the active area is electrically connected to the active area along the X direction. This design choice avoids the need to set a source contact in the active area and between each polysilicon gate (such as 212 and 214).

[0031] By moving the source contact from between the polysilicon gates to one side of the active area (at Figure 2 In a specific embodiment, the source contact is located on one side of the active area 202 while remaining on the active area, which can reduce the spacing of the polysilicon gates (PO), thereby bringing the transistors closer together and effectively reducing the distance between adjacent polysilicon gates. By reducing the spacing, the layout of the bit cell is made more compact, thereby reducing the total area required for each memory cell.

[0032] The common source contact 210 located on one side of the active area provides the necessary electrical connection to enable the transistor to operate normally. Even if the source contact is not located between the polysilicon gates, the transistor can still operate normally because the interconnected active areas provide a common path for carriers. Figure 2In the illustrated embodiment, source contact 210 is located on one side of the active region and is disposed adjacent to polysilicon gates 212 and 214 and is shared by bit cells #1-#6.

[0033] and Figure 1 Compared with the prior art design shown, by moving the source contact from between the polysilicon gates to one side of the multiple active regions, the distance between the POs (e.g., the distance between 212 and 214) is reduced by at least 10%. The saved area can achieve higher storage density, so that more bit cells can be accommodated in the same silicon area. Higher density is conducive to meeting the requirements of applications such as mobile devices and high-performance computing systems that require large storage space in a limited space.

[0034] also, Figure 2 The shared active area layout improves manufacturing efficiency. By reducing the number of source contacts within each individual active area and using a shared source contact between multiple active areas, the overall complexity of the architecture is reduced, which can reduce manufacturing costs and potentially improve yield due to a lower probability of defects.

[0035] It should be noted that the source contact needs to be electrically connected to the source area and therefore must be located on the active area. The source area is the semiconductor doped area of ​​the active area. The contact cannot be formed on an isolation area such as a shallow trench isolation (STI) structure, but must be located on the active semiconductor material to ensure proper conductivity. In order to accommodate the source contact on one side of the active area 202, the active area 202 can be enlarged or shaped to have additional space on one side. This adjustment allows the source contact to be located on the active area 202, but at the same time outside the space between the polysilicon gates. By enlarging the active area 202 in this way, the source contact is still located in the active area of ​​the substrate, so that the spacing between the polysilicon gates (PO) can be reduced while maintaining electrical integrity.

[0036] Figure 3 Shown is a prior art 300 (similar to Figure 1 305. A comparison between a bit cell in the prior art (shown in FIG. 306 ) and a bit cell in a RRAM device architecture using a shared active area layout 305. By eliminating the source contact in the active area, the spacing between adjacent polysilicon gates (PO) is effectively reduced. For example, Figure 3 As shown, the pitch 310 of the prior art 300 is reduced to a pitch 320 within the shared active area layout 305. In some embodiments, by reducing the PO to PO pitch, the total area of ​​the bit cell is reduced by at least 10%. In other embodiments, by reducing the PO to PO pitch, the area reduction rate of the bit cell can reach 20%.

[0037] Figure 4 For the prior art 400 (similar to Figure 1Another difference between the prior art 400 and the RRAM device architecture using the shared active area layout 405 is that in the prior art 400, the active areas are not connected along the X direction, while in the RRAM device architecture using the shared active area layout 405, the active areas are connected along the X direction, and the common source contact is located on one side of the multiple active areas.

[0038] Figure 5 For the prior art 500 (similar to Figure 1 Another difference between the prior art 500 and the RRAM device architecture using the shared active area layout 505 is that the source contacts are distributed in each active area and are not located in the active area ( Figure 5 In contrast, in the RRAM device architecture using the shared active area layout 505, the source contact is moved to one side of the main active area and is shared by the main active areas along the X direction.

[0039] Figure 6 For the prior art 600 (similar to Figure 1 Another difference between the prior art 600 and the RRAM device architecture using the shared active area layout 605 is shown in the prior art 600. In the prior art 600, the bit line and the source line extend parallel to each other, and the bit line includes a drain contact in each active area, and the source line includes a source contact in each active area. Figure 6 In the embodiment, both the bit line and the source line extend along the Y direction. In contrast, in the RRAM device architecture using the shared active area layout 605, the bit line and the source line are arranged vertically. Figure 6 As shown, the bit lines extend in the Y direction, while the source lines extend in the X direction.

[0040] Reference again Figure 2 , Figure 2 The layout shown is one implementation of a new RRAM device architecture using a shared active area (AA) layout, and is not the only structure that can achieve the desired technology improvements. It should be understood by those skilled in the art that when the drain and source regions are interchanged, the advantages of reducing the PO to PO spacing and the bit cell size can be similarly achieved.

[0041] exist Figure 2 In the illustrated embodiment, the source contact is moved to one side of the active area, effectively eliminating the need to place the source contact between the active area or PO. This move reduces the PO-to-PO spacing by at least 10%, making the bit cell layout more compact and increasing storage density. By placing the common source contact on one side of the active area, the necessary electrical connection is maintained to ensure that the transistor can operate normally without sacrificing performance.

[0042] Similarly, in an alternative embodiment, the drain contact is moved out of the active region, while the source contact remains in the active region. For example, the RRAM device may include multiple active regions formed on a substrate, each active region including a drain region and a source region arranged along a first direction (Y). A polysilicon gate extends through each active region along a second direction (X) to separate the drain region from the source region. In this design, in the second direction, adjacent drain regions are connected to each other, while adjacent source regions are separated by an STI structure.

[0043] In this alternative embodiment, each source region includes a source contact, and adjacent drain regions share the same drain contact along the second direction. This structure enables the drain contact to be moved to one side of the active region, thereby effectively reducing the PO to PO spacing in a manner similar to the above embodiment. In the first direction, the source contacts in adjacent source regions are connected to the source line. In the second direction, adjacent drain regions are connected via the drain line through the shared drain contact.

[0044] In this alternative embodiment, the drain region length is at least 10%, or even 20%, smaller than the source region length in the first direction. This intentional sizing helps reduce the overall bit cell size, thereby increasing storage density and achieving efficient use of substrate area.

[0045] These variations demonstrate the flexibility of the novel RRAM device architecture in optimizing layout efficiency. Whether or not the source or drain contacts are moved to one side of the active region, the key goal of minimizing the bit cell size by reducing the PO to PO spacing can be achieved. Designers can adjust the structure and relative dimensions of the drain and source regions in the manner described in the claims to tune the architecture to meet specific design requirements or manufacturing constraints, further improving the competitiveness of RRAM technology.

[0046] Figure 7 Shown is a layered structure diagram of a RRAM device using a shared active region layout according to some embodiments, and a cross-sectional view of an active region, a polysilicon gate, a drain region, and a source region therein.

[0047] Figure 7 The RRAM device shown includes a word line 700 disposed at the uppermost layer. The word line is used as a control line for selecting a memory cell during a read / write operation, and is used to directly switch the RRAM between a high resistance state (HRS) and a low resistance state (LRS) by applying an appropriate required voltage level.

[0048] Below the word line 700 is a bit line 710 including a metal layer M2. The metal layer acts as a channel for data signals, connects the RRAM cell to peripheral circuits, and allows read and write currents to flow. Directly below the metal layer M2 is a via V1, which is a vertical interconnect structure that establishes an electrical connection between the bit line and the RRAM stack below it. By using the via V1, efficient signal transmission can be ensured and vertical integration is promoted, thereby helping to achieve compactness of the device.

[0049] The RRAM stack is located below the via V1 and is the core component responsible for data storage. The stack includes multiple layers, including electrode material layers and resistance switching layers sandwiched between the electrode material layers, which work together to enable the RRAM to switch between different resistance states. Through resistance switching, binary information can be stored, where the high resistance state and the low resistance state represent the binary digits "0" and "1", respectively.

[0050] Below the RRAM stack is the RRAM bottom electrode (BE) 720, which is critical for achieving a stable electrical interface. Below the bottom electrode 720 is the metal layer M1 730, which is labeled as the "RRAM landing structure" in the figure.

[0051] The source contacts on the metal layer M1 are located in the same plane as the RRAM landing structure 730 and are connected to the source regions formed in the active area (AA) on the substrate. These source regions in the active area are used as source lines for multiple memory cells to share. By forming source lines in the active area and connecting them through the source contacts on M1, the design reduces the need to set source contacts in each active area, thereby optimizing the layout and improving storage density.

[0052] The metal layer M1 (RRAM landing structure) 730 is connected to the drain region on the semiconductor substrate by a contact (CT). The drain region is part of a transistor structure that includes a gate oxide layer and a polysilicon (poly) gate located between the drain region and the source region. The polysilicon gate controls the conductivity of the channel in the substrate, allowing the transistor to act as a switch to allow or not allow current to flow depending on the gate voltage.

[0053] The gate oxide layer is located just above the substrate to provide the necessary insulation between the gate electrode and the silicon below it, ensuring that the gate can modulate the channel without direct electrical contact.

[0054] exist Figure 7 In the layered structure diagram of the RRAM device shown, the cross-sections of the active region, source region, drain region and polysilicon gate are all rectangular.

[0055] Figure 8FIG. 1 is an example of a manufacturing process flow of an RRAM using a shared active area layout according to an embodiment of the present invention. In some implementations, Figure 8 One or more process flow boxes in can be executed by the device.

[0056] like Figure 8 As shown, the process 1200 may include: providing a plurality of active regions on a substrate, each active region having a drain region and a source region arranged along a first direction (Y) (block 1210). For example, the device may provide a plurality of active regions on a substrate in the manner described above, each active region having a drain region and a source region arranged along a first direction (Y).

[0057] like Figure 8 As further shown, the process 1200 may include forming a polysilicon gate (PO) extending through the active region along the second direction (X) and separating the drain region from the source region (block 1220). For example, the device may form a polysilicon gate (PO) extending through the active region along the second direction (X) and separating the drain region from the source region in the manner described above.

[0058] like Figure 8 As further shown, the process 1200 may include forming a shallow trench isolation (STI) structure extending in a first direction and separating adjacent drain regions in a second direction (block 1230). For example, the device may form an STI structure extending in a first direction and separating adjacent drain regions in a second direction in the manner described above.

[0059] like Figure 8 As further shown, the process 1200 may include: forming: adjacent source regions in the second direction are connected to each other, and adjacent drain regions in the second direction are separated by a shallow trench isolation (STI) structure (block 1240). For example, the device may perform the forming step in the manner described above, wherein adjacent source regions in the second direction are connected to each other, and adjacent drain regions in the second direction are separated by the STI structure (block 1240).

[0060] like Figure 8 As further shown, the process 1200 may include forming a memory device on a substrate (block 1250). For example, the apparatus may form a memory device on a substrate in the manner described above.

[0061] Process 1200 may include other implementations, such as a single implementation or any combination of multiple implementations described below and / or in combination with one or more other processes described elsewhere herein. In a first implementation, process 1200 further includes: forming a drain contact in each drain region, and forming a bit line connecting each column of drain contacts along a first direction.

[0062] In a second implementation alone or in combination with the first implementation, the process 1200 further includes: for each row of source regions in the second direction, forming a source contact, and forming a source line connected to the row of source regions.

[0063] Although Figure 8 A flow block embodiment of process 1200 is shown, but in some implementations, Figure 8 The process 1200 may include more process blocks, fewer process blocks, different process blocks, or a different arrangement of process blocks than those shown. Additionally or alternatively, two or more process blocks of the process 1200 may be performed in parallel.

[0064] The process flow of the embodiment of the present invention can also be applied to other back-end-of-line (BEOL) memories, including but not limited to conductive bridging random access memory (CBRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM) and phase change random access memory (PCRAM).

[0065] The above description of the illustrated embodiments of the present invention (including the description in the Abstract) is not intended to be exhaustive or to limit the invention to the exact forms disclosed. Although specific embodiments and examples of the present invention are described herein for illustrative purposes, various equivalent modifications may be made within the scope of the present disclosure, as will be appreciated by those skilled in the relevant art. Other embodiments may have layers arranged in a different order than the illustrated embodiments, or may increase or decrease the number of layers based on the illustrated embodiments.

[0066] Although the above operations are described as multiple independent operations in order to describe the operations in a manner that is most helpful for understanding the present invention, the order of description should not be understood as implying that the operations must be sequence-dependent. Specifically, the operations do not necessarily need to be performed in the order described.

[0067] In this specification, the words "above", "above", "below", "between" and "on" are used to indicate the relative position of a material layer or component to other layers or components. For example, when a layer is described as being deposited "above", "on" or "below" another layer, it means that the layer can be in direct contact with the other layer or can have one or more intermediate layers. In addition, when a layer is described as being deposited "between" two layers, it means that the layer can be in direct contact with the two layers or can include one or more intermediate layers. In contrast, when a first layer is described as being "on" a second layer, it means that it is in direct contact with the second layer. Similarly, unless otherwise explicitly stated, when a component is described as being deposited "between" two layers, it means that the component can be in direct contact with the adjacent components or can include one or more intermediate layers.

[0068] In this specification, the words "example" and "illustrative" are used to mean as an example, instance or illustration. In this article, any aspect or design described as an "example" or "illustrative" should not necessarily be understood as being preferred or more advantageous than other aspects or designs. On the contrary, the purpose of using the words "example" or "illustrative" is to state the concept in a specific way. In this specification, the word "or" is intended to mean "or" in an inclusive sense, not "or" in an exclusive sense. That is, unless otherwise specified or clearly seen from the context, "X includes A or B" is intended to mean any one of the natural inclusive permutations and combinations. That is, if: "X includes A"; "X includes B"; or X includes A and B at the same time, "X includes A or B" is satisfied in any of the above situations. In addition, "one" or "an" used in this specification and the appended claims can be generally understood as "one or more", unless otherwise clearly specified or clearly seen from the context as a single. In addition, "an embodiment" or "an embodiment" used in the text is not intended to mean the same embodiment unless it is described as having this meaning. In this specification, the words "first", "second", "third", "fourth" etc. are intended to be used as marks to distinguish different elements, and do not necessarily have the ordinal meaning represented by their numerical parts.

Claims

1. An access transistor array for a memory device, characterized in that: include: A plurality of active regions are formed on the substrate, each of the active regions comprising a drain region and a source region arranged along a first direction and a polysilicon gate extending through the active region along a second direction and separating the drain region from the source region, Wherein, adjacent source regions in the second direction are connected, and adjacent drain regions in the second direction are separated by a shallow trench isolation structure.

2. The access transistor array according to claim 1, wherein: Each drain region includes a drain contact, and adjacent source regions in the second direction share a same source contact.

3. The access transistor array according to claim 1, wherein: Each drain contact in the adjacent drain regions in the first direction is connected to a bit line through a resistive random access memory stack, and the adjacent source regions in the second direction are connected to the same source contact through a source line.

4. The access transistor array according to claim 3, wherein: A length of the source region in the first direction is at least 10% smaller than a length of the drain region in the first direction.

5. The access transistor array according to claim 3, wherein: A length of the source region in the first direction is at least 20% smaller than a length of the drain region in the first direction.

6. The access transistor array according to claim 3, wherein: The bit line is perpendicular to the source line.

7. The access transistor array according to claim 3, wherein: A distance between two adjacent polysilicon gates sandwiching the source region is at least 10% smaller than a distance between two adjacent polysilicon gates sandwiching the drain region.

8. The access transistor array according to claim 3, wherein: A distance between two adjacent polysilicon gates sandwiching the source region is at least 20% smaller than a distance between two adjacent polysilicon gates sandwiching the drain region.

9. The access transistor array according to claim 1, wherein: The storage device is a back-end process memory.

10. The access transistor array according to claim 1, wherein: The memory device is a resistive random access memory.

11. The access transistor array according to claim 1, wherein: The source line is connected to a first metal layer in the memory device that is closest to the substrate.

12. The access transistor array according to claim 11, wherein: Also included is a word line, wherein the word line is configured to be parallel to the source line.

13. A method for manufacturing a memory device, characterized in that: include: A plurality of active regions are arranged on the substrate, wherein each active region includes a drain region and a source region arranged along a first direction; forming a polysilicon gate extending through the active region along a second direction and separating the drain region from the source region; forming a shallow trench isolation structure extending along the first direction and separating adjacent drain regions in the second direction; The adjacent source regions in the second direction are connected, and the adjacent drain regions in the second direction are separated by a shallow trench isolation structure; A memory device is formed on the substrate.

14. The method according to claim 13, characterized in that Also includes: A drain contact is formed in each of the drain regions, and a bit line is formed, wherein the bit line is connected to each of the drain contacts through the RRAM stack.

15. The method according to claim 13, characterized in that Also includes: For each row of source regions in the second direction, a source contact is formed and a source line connected to the row of source regions is formed.

16. An access transistor array for a memory device, characterized in that: include: A plurality of active regions are formed on a substrate, wherein each active region includes a drain region and a source region arranged along a first direction and a polysilicon gate extending through the active region along a second direction and separating the drain region from the source region, Wherein, adjacent drain regions in the second direction are connected, and adjacent source regions in the second direction are separated by a shallow trench isolation structure.

17. The access transistor array according to claim 16, wherein: Each source region includes a source contact, and adjacent drain regions in the second direction share a same drain contact.

18. The access transistor array according to claim 16, wherein: Source contacts in adjacent source regions in the first direction are connected to source lines, and adjacent drain regions in the second direction are connected to the same drain contact through drain lines.

19. The access transistor array according to claim 18, wherein: A length of the drain region in the first direction is at least 10% smaller than a length of the source region in the first direction.

20. The access transistor array according to claim 18, wherein: A length of the drain region in the first direction is at least 20% smaller than a length of the source region in the first direction.

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