Novel transistor device

Abstract

Provided is a novel transistor device. A vertical transistor is described having collector and emitter regions of a first type semiconductor and a base region including a sub-region of a second type semiconductor and a first type channel extending between the collector and emitter regions, the channel extending through the sub-region, and all side surfaces of about the whole length are surrounded by the sub-partitions.

Description

Background Art

[0001] WO2022 / 123261 describes a lateral bipolar junction transistor (bipolar junction transistor) having a channel type that interconnects the collector and the emitter, the channel type being the same as the semiconductor type of the emitter and the collector. Due to the characteristics of the channel, the transistor device exhibits many advantageous electrical characteristics over conventional lateral bipolar junction transistors (BJTs), including improved current gain.

[0002] In the described PNP variant, a lightly doped P channel is produced by counter-doping the N-type well. Because the channel needs to have a very shallow depth, the channel is essentially located at the surface of the wafer, where the doping can be most accurately controlled.

[0003] The idea of ​​the present invention is to produce a vertical equivalent of the lateral transistor disclosed in WO2022 / 123261. Summary of the invention

[0004] According to a first aspect of the present invention, there is provided a transistor device having: a collector region provided by a first region of a first type semiconductor; a collector terminal associated with the collector region; an emitter region provided by a second region of the first type semiconductor; an emitter terminal associated with the emitter region; a base region provided by a third region of a semiconductor located between and bordering the collector region and the emitter region; a base terminal associated with the base region; wherein the base region comprises: a sub-region of the second type semiconductor; and a channel of the first type semiconductor; wherein the base terminal contacts the sub-region; and the sub-region is in contact with the channel. The sub-division surrounds the channel so that the interface between the sub-division and the channel extends continuously around the channel, typically substantially to the entire length of the channel.

[0005] As described in detail in WO2022 / 123261, the entire contents of which are incorporated by reference, unlike a substantially conventional BJT semiconductor structure, the presence of a channel allows unipolar conduction between the collector terminal and the emitter terminal. This enables the transistor to have improved gain characteristics compared to a BJT transistor having a conventional structure. This is believed to be because the channel provides a conduction path between the emitter region and the collector region without running through a diode junction, thereby providing a relatively low resistance.

[0006] The structure of the transistor allows for unique operation in a number of different modes.

[0007] For example, when the device is implemented in a circuit under a first condition, that is, a voltage (V ce ) and the base terminal is floating or shorted to the emitter terminal, the current between the collector terminal and the emitter terminal may be at least predominantly due to unipolar conduction;

[0008] When the device is implemented in a circuit under a second condition, i.e., when the voltage applied between the emitter terminal and the collector terminal is lower than the first threshold voltage and the base terminal is floating or shorted to the emitter terminal, a depletion region can be formed around the first diode junction that is sufficient to clamp the channel so that there is essentially no current between the collector terminal and the emitter terminal of the device.

[0009] When the device is implemented in a circuit under the third condition, i.e., a voltage is applied between the emitter and collector terminals and a voltage (V be ) so that the current passes through the base terminal, the current between the collector terminal and the emitter terminal is at least mainly due to bipolar conduction.

[0010] V ce The value of the threshold voltage depends on the thickness of the channel, and the length of the channel extending between the emitter and collector regions, and therefore typically also on the separation distance between the emitter and collector regions.

[0011] The presence of the channel allows the transistor to be switched "on", i.e., there is a de minimis current through the collector terminal at a value of |Vbe| less than the forward bias voltage |(Vft)| of the base emitter diode junction. When "on" in this case, no current flows through the base terminal. The benefits of this feature are described in detail in WO2022 / 123261.

[0012] Therefore, the device can be used in a suitable beImplemented in a circuit that selectively switches between |Vbe1| and |Vbe2|, where |Vbe1| is selected to be less than |Vft| to provide unipolar conduction, and |Vbe2| is selected to be greater than or equal to |Vft| to provide bipolar conduction.

[0013] Switching between a substantially exclusively unipolar conduction mode and a mode that includes bipolar conduction has two benefits compared to operating only in the unipolar conduction mode: overshoot is minimized, and known voltage limits are enforced.

[0014] If switching between two Vbe voltages where the current between collector and emitter is entirely due to unipolar conduction, the voltage may overshoot when switching to the larger |Vbe| due to the surge charge appearing at the base of the transistor. This creates a delay as the overshooting Vbe returns to the larger |Vbe| as the charge discharges / charges back from the base. This has the effect of limiting the maximum switching frequency because as the switching frequency increases the circuit will attempt to switch while the larger |Vbe| is still overshooting. This problem is encountered in MOSFETs and JFETS where the current between the gate and drain terminals is entirely unipolar.

[0015] In contrast, when switching to a voltage Vbe (where |Vbe|>|Vft|) such that part of the current between collector and emitter is due to bipolar conduction, the forward biased base-emitter junction causes the base current to increase rapidly as Vbe increases above Vft. This has the effect of clamping the larger |Vbe|, minimizing overshoot and thus increasing the maximum possible switching frequency.

[0016] Another explanation is that if operating in pure unipolar mode, such as a JFET, it is possible to pull the base voltage (gate voltage for a JFET) from rail to rail. However, in bipolar mode, when |Vbe|>|Vft|, there is a base current that resists the pull to the rail and limits the Vbe voltage, meaning that the voltage swing is at most from one rail to Vbe2. Smaller voltage swings allow for faster switching speeds.

[0017] The appropriate width of the channel, ie the dimension orthogonal to the first diode junction and the direction of current flow through the channel, will depend on the Vce value at which the transistor is designed to operate and / or the doping concentration of the channel.

[0018] For example, for a transistor adapted to operate in a nominal voltage range between 0 V and |5 V|, a channel width below 0.50 μm and advantageously 0.2 μm or less may be suitable. This range extends to larger values ​​than specified in WO2022 / 123261, since the first diode junction surrounds the channel on all sides and the depletion region will therefore extend radially inwards into the channel from all sides.

[0019] However, for a given operating voltage, the maximum width of the channel allowed in order to turn off the transistor will be significantly smaller than the width of the channel of a JFET designed to operate at a comparable operating voltage.

[0020] The width of a sub-region extending laterally away from the first diode junction on either or both sides may be equal to or greater than five times the width of the channel. In some embodiments, the width of a sub-region may be at least twenty times the width of the channel.

[0021] The net doping concentration of the channel can be equal to or less than (e.g., between 0.01 and 0.1 times) the net doping concentration of the sub-region. This ensures that the depletion region at the first diode junction is preferentially formed in the channel rather than in the sub-region. For example, when the channel is composed of a P-type semiconductor material and the sub-region is composed of an N-type semiconductor material, the net doping concentration of the P-type dopant in the channel can be between 0.01 and 0.1 times the net concentration of the N-type dopant in the sub-region.

[0022] In order to provide good conductivity in the sub-region, the net doping concentration of the sub-region can be between 1e16 / cm 3 To 5e17 / cm 3 Between, including the end values.

[0023] Good bipolar conduction characteristics also depend on a relatively small spacing between the collector and emitter regions, so the spacing between the collector and emitter regions can be less than or equal to 1.5 microns, preferably 0.6 microns or less. In one embodiment, the spacing can be 0.3 microns. Typically, the spacing between the collector and emitter regions is equal to the length of the channel, so it may also be less than or equal to 1.5 microns.

[0024] When expressed as a fraction, the ratio of the channel width to the spacing between the collector region and the emitter region may be 2 / 3 or less.

[0025] The channel may be provided by a semiconductor layer of the first type having a lower net doping concentration than the first region of the first type semiconductor and located on the first region of the first type. Preferably, the semiconductor layer is an epitaxial layer, the thickness of which, and therefore the channel length, may be more carefully controlled than using implantation and diffusion processes.

[0026] The sub-region of the second type semiconductor may extend completely through the first type semiconductor layer. The sub-region may define a hole, which is generally centrally located through the sub-region to provide or define a core of the semiconductor layer to provide a channel. The first region of the first type semiconductor may be at least partially provided by a polysilicon layer directly above the first type semiconductor layer.

[0027] A common application of transistor devices is in logic circuits, where a plurality of similar transistors are integrally formed on a single semiconductor chip. Thus, it may be advantageous for two or more transistors to share a common emitter region and an emitter terminal. Thus, the transistor device may include a plurality of transistors, the second region of a first type semiconductor providing a common emitter region for the plurality of transistors; the transistor device including a plurality of sub-regions of a second type extending through the semiconductor layer, each sub-region being laterally spaced apart from the other sub-regions around the semiconductor layer; and a plurality of first regions of the first type semiconductor, each of the plurality of first regions being directly above one of the plurality of sub-regions.

[0028] The emitter terminal, the collector terminal and the base terminal may also be arranged on the same side of the substrate. Alternatively, the emitter terminal may be arranged on a first side of the substrate, while the collector terminal and the base terminal are arranged on an opposite second side of the substrate.

[0029] The semiconductor may be a silicon semiconductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The present invention will now be described by way of example with reference to the following figures, in which:

[0031] Figure 1A is a schematic plan view of a first variant semiconductor layer structure providing a vertical bipolar junction transistor;

[0032] Figure 1B is a schematic diagram of a lateral cross section through a vertical plane QQ;

[0033] Figure 2A is a schematic plan view of a second variant semiconductor layer structure providing a vertical bipolar junction transistor;

[0034] Figure 2B is a schematic lateral cross-sectional view through a vertical plane RR of a second variant semiconductor layer structure;

[0035] Figure 3 is a schematic lateral cross-sectional view illustrating a second variant semiconductor layer structure suitable for fabricating a plurality of integrated vertical bipolar junction transistors sharing a common emitter terminal; and

[0036] Figure 4 It is to explain Figure 1 to Figure 3A graph showing how the operating characteristics of the transistor device in FIG. 1 vary with changes in Vbe and Vce. DETAILED DESCRIPTION

[0037] refer to Figure 1A and Figure 1B , shows a semiconductor structure for implementing a vertical transistor device. The transistor device is considered to be an improvement over the conventional bipolar junction transistor (BJT) device and operates in a similar manner in some respects. For this reason, the terminals of the device are referred to using BJT nomenclature.

[0038] The device in this example is of PNP type and is not shown to scale, and is composed of doped silicon semiconductor material to provide a collector region 1, an emitter region 2 and a base region 3. The base region 3 is located between the collector region 1 and the emitter region 2.

[0039] The collector region 1 and the emitter region 2 are both P-type semiconductors, and by convention, the emitter region 2 can be more doped than the collector region 1. For example, the net doping concentration of the collector region 1 can be greater than or equal to 1×10 18 cm -3 , the net doping concentration at the emitter region 2 may be greater than or equal to 2×10 18 cm -3 Alternatively, they may have substantially the same net doping concentration. The collector terminal C (see Figure 1A ) is connected to the collector region 1, the emitter terminal E is connected to the emitter region 2, and the base terminal B is connected to the base region 3.

[0040] Compared with the traditional BJT, the base region 3 of the transistor device is composed of two regions of different types of semiconductors: a first region of N-type material (hereinafter referred to as N-type base region 3A), and a second region of P-type material (hereinafter referred to as channel 3B).

[0041] The base terminal B is connected to the base region 3 through the N-type base region 3A. The N-type base region 3A directly interfaces with the channel to form a PN junction 4. The N-type base region 3A also directly interfaces with both the collector region 1 and the emitter region 2 to form corresponding PN junctions 5 and 6.

[0042] The channel 3B extends between the collector region 1 and the emitter region 2 and directly borders the two. Compared with the collector region 1 and the emitter region 2, the channel 3B has a very small net doping concentration. For example, the net doping concentration of the channel 3B may be less than or equal to 5×10 16 cm -3 .

[0043] Furthermore, the channel 3B has a lateral width, ie, a dimension extending orthogonally from the NP junction 4 to the N-type base region 3A, which is significantly smaller than a conventional channel dimension of a junction field effect transistor (JFET). In one embodiment, the lateral width may be 0.2 microns.

[0044] The net concentration of N dopants in the N-type base region 3A may be about 1e17 / cm 3 .

[0045] The spacing between the collector and emitter regions (which is equal to the length of the channel 3B) may be less than or equal to 1.5 microns, advantageously equal to or less than 0.8 microns. In one embodiment, it is about 0.3 microns.

[0046] The semiconductor structure for realizing the above-mentioned features is described below.

[0047] A relatively low-doped P layer 101 is provided on the P-type substrate 100 providing the emitter region 1, and the net doping concentration of the P layer is less than or equal to 5×10 16 cm -3 .

[0048] A square ring-shaped N-type region 102 providing the base subregion 3A extends completely through the P layer 101 and partially into the substrate 100. The N-type region 102 defines a centrally located hole that extends completely through the N-type region 102 between the top and bottom sides of the P layer to define a portion 101A of the P layer 101, thereby providing a channel 3B isolated from the remainder of the P layer 101.

[0049] The N-type region 102 may be in a shape other than a square ring, for example, a ring, a rectangular ring or an irregular ring. The hole does not need to be located directly in the center of the N-type region 102, but is preferably located completely within the periphery 102A of the N-type region 102 to ensure that the channel 3B is isolated from the rest of the P layer 101.

[0050] like Figure 1A As shown, generally, the P-type layer 101 will extend laterally around all sides of the N-type region 102 .

[0051] A first oxide layer 104 is located on top of the P layer 101A. A first window 105 is formed through the first oxide layer 104. A P-type region 106 is provided in part by a polysilicon layer 107 formed on the P layer 101 through the window 105, and in part by a converted portion 106A of the epitaxial layer 101, the P-type region 106 being located directly above and in contact with the portion 101A and the N-type region 102 to define an interface 5. A portion 107A of the polysilicon layer extends over the first oxide layer 104, thereby providing a conductive track to interconnect the collector terminal into a circuit.

[0052] The second oxide layer 108 is located over the first oxide layer 104 and the polysilicon layer 107 to isolate the polysilicon layer 107 from the patterned metal layer 110. A second window 111 passing through the first oxide layer 104 and the second oxide layer 108 allows the metal layer 110 to directly contact the N-type region 102 to provide a base contact B. In this example, the junction between the metal layer 110 and the N-type region 102 provides a Schottky diode.

[0053] Another metal layer 112 is provided on the side of the substrate 100 opposite to the side where the P layer 101 is located to provide an emitter contact E. Figure 1B Not shown in FIG. 1 , the portion of substrate 100 immediately adjacent to metal layer 112 is more heavily doped to provide a good ohmic contact.

[0054] An example manufacturing process is now described. A P layer 101 is grown epitaxially on a P-type substrate 100. The thickness X of the epitaxial layer is selected to define the desired channel length, thereby defining the spacing between the collector region and the emitter region.

[0055] Subsequently, a first implantation and diffusion process is used to transform a region of P layer 101 and a portion of substrate 100 directly thereunder using a mask defining a square ring pattern to form a square ring-shaped N-type region 102 and define channel 3B and diode junctions 4 and 6 .

[0056] A first oxide layer 104 is deposited on the surface of the P layer 101. A first mask and etching process is used to form a first window 105. A polysilicon pattern is then deposited over the window 105 and the first oxide layer 104 to provide a polysilicon layer 107. Using a second mask, the polysilicon material is doped with a P dopant and diffused downward to form a portion 106A and a collector-base diode junction 5 within the epitaxial layer 101. A short anneal, such as 10 seconds, is performed after the P dopant is implanted to repair the crystal structure of the polysilicon and the silicon wafer.

[0057] A second oxide layer 108 is deposited over the first oxide layer 104 and the polysilicon layer including the P-type region 106. A second mask and etching process is used to form a second window 111 through the first oxide layer 104 and the second oxide layer 108. A metal layer 110 is deposited over the second oxide layer 108, including through the second window 111 to form a Schottky junction with the base region 102, and to form a conductive track over the second oxide layer 108 to interconnect the base into a circuit.

[0058] Furthermore, the back side of the substrate is metallized to form a layer 112 providing an emitter terminal E.

[0059] Figure 2A and Figure 2BA variant embodiment is shown, in which the emitter terminal E is arranged on the same side of the substrate 100 as the emitter terminal and the collector terminal.

[0060] The metal contact 112 on the second side of the semiconductor chip is omitted, and instead a metal region 113 formed by a third window 114 through the first oxide layer 104 and the second oxide layer 108 is provided, the metal region 113 directly intersects with a P+ region 115, and the P+ region 115 extends through the P layer 101 and into the P substrate 100 to provide an emitter contact. A portion of the metal region 113A extends above the oxide layer to provide a trace connecting the emitter to the circuit. The P+ region 115 is laterally spaced apart from the base region 102, separated by a portion 101B of the P layer 101.

[0061] Another mask may be used to form the P+ region 115 through additional implantation and diffusion steps. The metal region 113 may be deposited using the same process steps as the metal layer 110 is deposited.

[0062] It is preferred to form the P layer 101 using epitaxy, since the layer thickness can be controlled very accurately; however, in principle the layer could be formed by doping the substrate with an N dopant if the doping could be controlled accurately enough.

[0063] The emitter region of any embodiment can be shared by multiple integrated transistor devices. Figure 3 Shown based on Figure 2A and Figure 2B The semiconductor structure of the two transistors is implemented.

[0064] The aforementioned manufacturing method is used to form a plurality of laterally spaced, independent annular N-type regions 102X, 102Y across the P layer 101. A separate channel 101AX, 101AY is provided through each region, and a separate collector region 106X, 106Y is formed above each region. The substrate 100 and the P+ region 115 provide an emitter common to the two transistors.

[0065] It should be understood that Figure 1A and Figure 1B The embodiments of can be similarly varied to provide multiple separate vertical transistors sharing a common emitter region.

[0066] In any of the above embodiments, the substrate 101 may be provided by a semiconductor wafer and / or another epitaxial layer.

[0067] In any variation of the above examples, the N-type base region 102 may include a region having a relatively high N-type net doping concentration, for example, about 118 / cm 3 or 1e19 / cm 3The N+ sub-region of the embodiment of the present invention directly borders the metal layer 110. This variant is preferred when it is necessary to establish an ohmic contact with the base region 3 instead of a Schottky diode. In this case, the metal layer 110 can be replaced by a polysilicon layer.

[0068] In one variation, substrate 100 may be used as a collector region and P-type region 106 may be used as an emitter. However, this arrangement is less desirable when multiple transistors are required to share a common emitter.

[0069] The N-type sub-region 3A may not extend completely through the epitaxial layer 101. This may be necessary if the epitaxial layer 101 is thicker than the required spacing between the emitter and collector. Although this may reduce the performance of the transistor, it may be acceptable in cases where a very small base width is required.

[0070] It should be understood that the various devices described above may also be implemented as NPN devices having an N-type channel, an emitter region and a collector region, and a P-type base sub-region.

[0071] Operation Mode

[0072] refer to Figure 4 , and Figures 1 to Figure 3 The operating characteristics or modes of any of the related devices change depending on the voltage across the collector terminal and the emitter terminal (Vce) and depending on the voltage across the base terminal and the emitter terminal (Vbe).

[0073] For a PNP device, such as the one shown in Figure 1, regardless of the operating mode, it is usually operated with a negative Vce, that is, the voltage applied to the collector is more negative than the voltage applied to the emitter, and Vbe can be either positive or negative, where the base-emitter junction forward threshold voltage Vft is negative. Any current through the base terminal will be negative (in other words, current is drawn out through the base terminal). In contrast, an NPN device is usually operated with a positive Vce, has a positive Vft, and any current through the base will be positive (in other words, current is pushed into the device through the base).

[0074] The five operating modes are shown as K, J, L, M and N. When the device is "off" and no current is passing through any of the terminals, the device operates in region K. When the device is "on", it can operate in one of modes J, L, M and N.

[0075] When the device is "on" (i.e., there is current between the collector and the emitter) and there is no or almost no (deminimus) current through the base terminal (i.e., Ib = 0A), excluding any temporary switching current due to capacitive effects, the device operates in region L or M. When the device is "on" (i.e., there is non-zero current between the collector and the emitter) and there is current through the base terminal (i.e., Ib<0A), the device operates in region J or N.

[0076] Operate with |Vce|<|Vt|

[0077] When the transistor device 1 is operated with |Vce| less than |Vt|, the transistor device 1 acts as a normally "off" device. In other words, when Vbe is zero, there is no current between the emitter 2 and the collector 3 (the device is "off" (operating in the (K) region)).

[0078] If |Vbe| increases so that the base-emitter diode junction 5B becomes forward biased (i.e., Vbe becomes more negative than -Vft for a PNP transistor; Vbe becomes more positive than Vft for an NPN transistor), the device switches "on" and operates in the "on" majority bipolar region J, in which current is drawn through the base terminal and the current between the collector and emitter is primarily due to bipolar conduction.

[0079] Alternatively, if |Vbe| increases in the opposite direction, causing the base-emitter diode junction 5B to become more reverse biased (i.e., Vbe becomes more positive for a PNP transistor; Vbe becomes more negative for an NPN transistor), the device then remains "off" (operating in region (K)).

[0080] When |Vce| is greater than |Vt'| and less than |Vt|, the device operates in a manner similar to when |Vce| is less than |Vt'|, except that as |Vbe| approaches but is less than |Vft|, the device enters the "on" predominantly unipolar operation region L, in which the device is "on" with zero current through the base terminal, and the current between the collector and emitter is primarily due to unipolar conduction.

[0081] As |Vbe| becomes greater than |Vft|, the device enters a transition region N where the unipolar conduction current is maximum and the bipolar conduction current increases until the bipolar conduction current is greater than the unipolar conduction current, whereby the device operates in the "on" main bipolar conduction region J.

[0082] Advantageously, the normally "off" device can be switched "on" and operated in the L region at a Vbe lower than that of existing BJTs, and advantageously lower than the forward voltage (Vft) of the base emitter diode junction. When operated in region L, the device has a significantly higher current gain than when operated in the J region at the same Vce, but the value of the maximum collector current is smaller. Due to the significantly lower Vbe, when the device is operated in the L region, it has a significantly higher current gain than existing BJTs - approaching infinite gain, because the current through the base terminal is essentially zero.

[0083] Operate with |Vce|>|Vt|

[0084] When transistor device 1 operates with |Vce| greater than threshold voltage |Vt|, transistor device 1 acts as a normally "on" device. In other words, when Vbe is zero, for example because the base terminal is floating or tied to the emitter, the current between the emitter and the collector exceeds the minimum current.

[0085] When |Vce| is greater than |Vt| and Vbe is zero or close to zero, the transistor operates in an "on" predominantly unipolar operating region M where the current through the base terminal is zero and the current between the collector and emitter is primarily due to unipolar conduction.

[0086] As |Vbe| increases above Vft, causing the base-emitter diode junction 5B to become forward biased (i.e., Vbe becomes more negative than -Vft for a PNP transistor and more positive than Vft for an NPN transistor), the device operates in a transition region N, where unipolar conduction reaches a maximum and bipolar conduction increases. As |Vbe| increases further, the proportion of Ice attributable to bipolar conduction becomes greater than the proportion attributable to unipolar conduction current, and operation is then primarily bipolar (region J) "on".

[0087] The magnitude of Vbe required to operate in the J region increases as the magnitude of Vce increases.

[0088] Alternatively, if |Vbe| increases in the opposite direction, such that the base-emitter diode junction 5B becomes more reverse biased (i.e., Vbe becomes more positive for a PNP transistor; Vbe becomes more negative for an NPN transistor), the device will switch "off" (operate in region K).

[0089] Between the "off" region K and the "on" main unipolar regions L and M is a transition region O, in which the operation of the device is unpredictable or difficult to control. For example, if the collector current in the "off" region K is less than 1nA, and the collector current in the "on" regions L and M is on the order of 1uA or more, then the collector current in the transition region O will be on the order of 10nA to 100nA.

[0090] The collector region 2 and the emitter region 3 of the device 1 have a spacing of distance X (see FIG. 1 ), which controls the length of the channel 4B. The values ​​of Vt and Vt' are related to the spacing X between the emitter region and the collector region. As the value of X increases, the magnitude of |Vt| and |Vt'| also increases. In order to make the device have good bipolar conduction characteristics when operating in this J region, the maximum value of X is usually 1.5 microns.

[0091] The nominal operating voltage range of a circuit determines the range of Vce values ​​that will be applied to the transistors therein. For typical logic circuits in which the device is typically expected to be used, the nominal operating voltage range may be between 0V and |5V|.

Claims

1. A transistor device having: a collector region provided by a first region of a first type semiconductor; a collector terminal associated with said collector region; an emitter region provided by a second region of said first type semiconductor; an emitter terminal associated with the emitter region; a base region provided by a third region of semiconductor located between and bordering the collector region and the emitter region; a base terminal associated with the base region; The base region comprises: sub-divisions of the second type semiconductor; and a channel of the first type semiconductor; wherein the base terminal contacts the sub-region; The sub-region interfaces with the channel to provide a first diode junction, and interfaces with both the emitter region and the collector region to form respective second and third diode junctions; The channel interfaces with and is interconnected with the collector region and the emitter region; The net doping concentration of the channel is less than the net doping concentration of the emitter region and the collector region; the channel extends a certain distance away from the first diode junction; The spacing between the collector region and the emitter region is less than or equal to 1.5 micrometers; The sub-partition surrounds the channel such that an interface between the sub-partition and the channel extends continuously around the channel.

2. The transistor device according to claim 1, comprising: a semiconductor layer of a first type having a lower net doping concentration than the first region of the first type semiconductor and located on the second region of the first type; a sub-region of the second type semiconductor extending completely through the semiconductor layer, the sub-region comprising a through hole providing a core of the semiconductor layer to provide the channel; as well as The first region of the first type semiconductor is at least partly provided by a polysilicon layer directly above the first type semiconductor layer.

3. The transistor device according to claim 2 comprises a plurality of transistors, wherein the second region of the first type semiconductor provides a common emitter region for the plurality of transistors; the transistor device comprises a plurality of sub-partitions of the second type extending through the semiconductor layer, each sub-partition being laterally spaced apart from other sub-partitions around the semiconductor layer; and a plurality of first regions of the first type semiconductor, each of the plurality of first regions being directly above one of the plurality of sub-partitions.

4. A method for manufacturing the transistor according to claim 1, comprising: (i) providing a substrate of a first semiconductor type to provide an emitter region or a collector region of the transistor; (ii) forming a first layer of the first semiconductor type on the substrate; The first layer has a lower net doping concentration than the substrate; (iii) forming a third region of a second semiconductor type, the third region extending through the first layer to interface with the substrate and surrounding to isolate a portion of the first layer from a remainder of the first layer to provide a channel; (iv) forming a region of the first semiconductor type above the third region, the region directly intersecting the third region and the channel. The method of claim 4 , comprising forming the first layer on the substrate using an epitaxial method.

6. The method of claim 4 or 5, comprising depositing a polysilicon layer on the first layer and performing a masking and doping process to form a region of the first semiconductor type.

7. A method according to claim 4, 5 or 6, comprising forming the third region using a mask and doping process.

8. The method according to claim 6 or 7 includes depositing a first oxide layer on the first layer; forming a first window through the first oxide layer directly above the third region and the channel, and depositing the polysilicon layer on the first layer through the first window.

9. The method according to claim 8 includes depositing a second oxide layer above the polysilicon layer and the first oxide layer, forming a second window through the first oxide layer and the second oxide layer directly above the third region; and depositing a metal or semiconductor material on the third region through the second window to form a base contact.

10. A method according to any one of the preceding claims, wherein the first layer is provided on a first side of the substrate and an emitter terminal is formed on an opposing second side of the substrate.

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