Staggered pitch stacked vertical transfer field effect transistor

Abstract

A method of forming a semiconductor structure consisting of a first plurality of vertical transport field effect transistors (11B) in a lower semiconductor layer and a second plurality of vertical transport field effect transistors (11A) in an upper semiconductor layer. The second plurality of vertical transfer field effect transistors are horizontally offset from the first plurality of vertical transfer field effect transistors by half a touch gate pitch between adjacent vertical transfer field effect transistors in the same semiconductor layer.

Description

Background Art

[0001] The present invention relates generally to semiconductor device field technology, and more particularly to vertical transfer field effect transistors formed in different semiconductor device layers, and more particularly to adjacent vertical transfer field effect transistors on different semiconductor layers having a half-contact gate pitch.

[0002] With continued pressure for improved semiconductor chip performance, various approaches are being explored to provide more semiconductor chip functionality while maintaining similar semiconductor chip size to drive more functions and more semiconductor devices in each semiconductor chip without compromising wafer utilization. One approach to providing more semiconductor chip functionality and more semiconductor devices per chip is the stacking of semiconductor logic devices. Vertically stacking semiconductor devices is emerging as a common practice, particularly in memory devices, to provide better semiconductor device functionality as the semiconductor devices are closer to each other, and to provide improved wafer utilization. The emerging practice of vertically stacking semiconductor logic devices utilizing one high performance semiconductor logic device directly above another semiconductor logic device can improve semiconductor chip performance and provide effective wafer utilization. Summary of the invention

[0003] Embodiments of the present invention disclose a semiconductor structure having a first plurality of vertical transfer field effect transistors in a lower semiconductor layer and a second plurality of vertical transfer field effect transistors in an upper semiconductor layer, wherein each of the second plurality of vertical transfer field effect transistors is horizontally offset from at least one of the first plurality of vertical transfer field effect transistors as a horizontal distance of half a touch gate pitch between adjacent transistors in the same semiconductor layer. Embodiments of the present invention disclose a semiconductor structure, wherein adjacent transistors in the second plurality of vertical transfer field effect transistors in the upper semiconductor layer are each horizontally spaced by a touch gate pitch. Embodiments of the present invention provide straight vertical contact points for connecting the vertical transfer field effect transistors in the lower semiconductor layer to interconnect wiring above the vertical transfer field effect transistors in the upper semiconductor layer. Providing straight vertical gate contact points for the lower semiconductor layer results in better electrical performance for the first vertical transfer field effect transistor in the lower semiconductor layer, and provides a simpler manufacturing process to form straight vertical gate contact points without the need for a lateral etching process. In addition, embodiments of the present invention provide a semiconductor structure, wherein the first vertical transfer field effect transistor has a gate contact point over an active gate (COAG), which reduces the unit area of ​​the transistor.

[0004] An embodiment of the present invention discloses a semiconductor structure, including a first vertical transfer field effect transistor in a lower semiconductor layer, and a second vertical transfer field effect transistor in an upper semiconductor layer, wherein the second vertical transfer field effect transistor in the upper semiconductor layer is horizontally offset from the first vertical transfer field effect transistor in the lower semiconductor layer by half a contact gate pitch. An embodiment of the present invention provides a straight vertical contact point that connects the vertical transfer field effect transistor in the lower semiconductor layer to the interconnect wiring above the vertical transfer field effect transistor in the upper semiconductor layer. Providing a straight vertical gate contact point in the lower semiconductor layer results in better electrical performance for the first vertical transfer field effect transistor in the lower semiconductor layer to form a straight vertical gate contact point without the need for a lateral etching process. In addition, an embodiment of the present invention provides a vertical transfer field effect transistor having a first type of field effect transistor in the lower semiconductor layer and a vertical transfer field effect transistor having a second type of field effect transistor in the upper semiconductor layer.

[0005] An embodiment of the present invention discloses a semiconductor structure having one or more vertical transfer field effect transistors in an upper semiconductor layer spaced apart by a touch gate spacing and one or more vertical transfer field effect transistors in a lower semiconductor layer also spaced apart by a touch gate spacing. The vertical transfer field effect transistors in the lower semiconductor layer are a first type of field effect device, and the vertical field effect transistors in the upper semiconductor layer are a second type of field effect device. An embodiment of the present invention provides that the vertical transfer field effect transistors in the upper semiconductor layer are offset from the vertical transfer field effect transistors in the lower semiconductor layer by half a touch gate spacing. Each vertical transfer field effect transistor of the vertical transfer field effect transistor has a straight vertical contact point connected to an interconnect wiring above the vertical transfer field effect transistor in the upper semiconductor layer. An embodiment of the present invention provides a straight vertical contact point with each of the vertical transfer field effect transistors, because the vertical transfer field effect transistor in the upper semiconductor layer is horizontally offset by half the contact gate spacing from the adjacent vertical transfer field effect transistor in the lower semiconductor layer, thereby allowing spacing between adjacent vertical transfer field effect transistors in the upper semiconductor layer, which is located directly above each of the vertical transfer field effect transistors in the vertical transfer field effect transistor in the lower semiconductor layer. Providing a straight vertical contact point from the vertical transfer field effect transistor improves the manufacturing yield and improves the electrical performance of the vertical transfer field effect transistor. In addition, an embodiment of the present invention provides a semiconductor structure in which the first vertical transfer field effect transistor has a gate contact point (COAG) above the source gate, which reduces the unit area of ​​the transistor.

[0006] An embodiment of the present invention discloses a semiconductor structure having a first pair of vertical transfer field effect transistors in a lower semiconductor layer and a second pair of vertical transfer field effect transistors in an upper semiconductor layer, wherein each pair of transistors in the second pair of vertical transfer field effect transistors in the upper semiconductor layer is horizontally offset by half a contact gate spacing from at least one vertical transfer field effect transistor in the lower semiconductor layer. In addition, an embodiment of the present invention provides a semiconductor structure, wherein the second pair of vertical transfer field effect transistors in the upper semiconductor layer are first type field effect transistors connected in series, and the first pair of vertical transfer field effect transistors in the lower semiconductor layer are second type field effect transistors connected in parallel. An embodiment of the present invention provides a first pair of vertical transfer field effect transistors in the lower semiconductor layer and a second pair of vertical transfer field effect transistors forming a dual-input NOR circuit. Each of the vertical transfer field effect transistors in the lower semiconductor layer has a straight vertical contact point with an interconnect wiring above the second pair of vertical transfer field effect transistors. The ability to provide straight vertical contact points improves both the manufacturing process and electrical performance of the vertical transfer field effect transistors when horizontal or lateral jumps are required to avoid the vertical transfer field effect transistors residing directly above each of the lower vertical transfer field effect transistors. In addition, embodiments of the present invention provide a bottom conductive plane and a power rail, the bottom conductive plane connected to at least one of the first pair of vertical transfer field effect transistors in the lower semiconductor layer, the power rail is above at least one of the second pair of vertical transfer field effect transistors in the upper semiconductor layer, and connects them to the vertical transfer field effect transistor. Providing contact points from the first pair of vertical transfer field effect transistors in the lower semiconductor layer to the bottom conductive plane and providing contact points from the second pair of vertical transfer field effect transistors in the upper semiconductor layer to the power rail improves the electrical performance of the vertical transfer field effect transistor device.

[0007] Embodiments of the present invention provide a semiconductor structure having a first pair of vertical transfer field effect transistors in a lower semiconductor layer and a second pair of vertical transfer field effect transistors in an upper semiconductor layer, wherein each pair of vertical transfer field effect transistors in the second pair of vertical transfer field effect transistors in the upper semiconductor layer is horizontally offset by half a contact gate pitch from at least one vertical transfer field effect transistor in the lower semiconductor layer. Embodiments of the present invention provide a first pair of vertical transfer field effect transistors connected in series in the lower semiconductor layer and a second pair of vertical transfer field effect transistors connected in parallel in the upper semiconductor layer. Embodiments of the present invention provide a first pair of vertical transfer field effect transistors in the lower semiconductor layer and a second pair of vertical transfer field effect transistors forming a dual-input NAND circuit. In addition, embodiments of the present invention provide a straight vertical contact point connecting the vertical transfer field effect transistor in the lower semiconductor layer to an interconnect wiring above the vertical transfer field effect transistor in the upper semiconductor layer. Providing a vertical gate contact point in the lower semiconductor layer results in better electrical performance for the first vertical transfer field effect transistor in the lower semiconductor layer, and provides a simpler manufacturing process for forming a straight vertical gate contact point without the need for a lateral etching process. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects, features and advantages of various embodiments of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings.

[0009] Figure 1 is a cross-sectional view of a semiconductor structure of a generally vertically stacked vertical transfer semiconductor device in accordance with an embodiment of the present invention.

[0010] Figure 2A is a cross-sectional view of a semiconductor structure after forming two stacked vertical transfer field effect transistors (VTFETs) on different semiconductor structure layers with a contact gate pitch (CGP) offset according to an embodiment of the present invention.

[0011] Figure 2B is a cross-sectional view of a semiconductor structure having four stacked VTFETs according to an embodiment of the present invention, wherein each top VTFET is horizontally spaced half a CGP from an adjacent bottom VTFET.

[0012] Figure 3 is a top view of a semiconductor structure formed using two stacked VTFETs with a half-pitch CGP offset between the top VTFET and the bottom VTFET in accordance with an embodiment of the present invention.

[0013] Figure 4 According to an embodiment of the present invention Figure 3 A cross-sectional view of the semiconductor structure depicted in FIG.

[0014] Figure 5 According to an embodiment of the present invention Figure 3 A cross-sectional view of the semiconductor structure through X2-X2 in the inverter depicted in FIG.

[0015] Figure 6 According to an embodiment of the present invention Figure 3 A cross-sectional view of the semiconductor structure through X3-X3 in the inverter depicted in FIG.

[0016] Figure 7 According to an embodiment of the present invention Figure 3 A cross-sectional view of the semiconductor structure through Y1-Y1 in the inverter depicted in FIG.

[0017] Figure 8 According to an embodiment of the present invention Figure 3 A cross-sectional view of the semiconductor structure through Y2-Y2 in the inverter depicted in FIG.

[0018] Fig. 9 is a circuit diagram of an inverter unipolar strength transistor device composed of a dual-input NOR circuit according to an embodiment of the present invention.

[0019] Fig. 10A According to an embodiment of the present invention Fig. 9 Top view of the unipolar strength transistor structure.

[0020] Fig. 10B According to an embodiment of the present invention Fig. 9 Bottom view of the unipolar strength transistor structure.

[0021] Fig.11 is a circuit diagram of a unipolar strength transistor device composed of a dual-input NAND circuit according to an embodiment of the present invention.

[0022] Fig. 12A According to an embodiment of the present invention Fig.11 Top view of the unipolar strength transistor structure.

[0023] Fig. 12B According to an embodiment of the present invention Fig.11 Bottom view of the unipolar strength transistor structure. DETAILED DESCRIPTION

[0024] Embodiments of the present invention recognize that a three-dimensional integrally directly stacked vertical field effect transistor (VTFET) typically includes an n-channel FET (FET) and a p-channel FET (PFET). Embodiments of the present invention recognize that typically stacked VTFETs are stacked directly above or below each other in different semiconductor layers to form a three-dimensional integrally directly stacked VTFET. Conventionally, embodiments of the present invention recognize that in vertically stacked VTFETs, the spacing between gates in adjacent devices in the same semiconductor layer is typically referred to as a contact gate pitch (CGP) or a contact point hole pitch (CPP). In a conventionally formed vertically stacked VTFET, adjacent VTFETs residing in the same semiconductor have a spacing of 1 CGP between gates, and a VTFET located directly above or below an adjacent VTFET in another semiconductor layer also has a horizontal gate whose gate spacing is 1 CGP. Therefore, in a conventional vertically stacked VTFET, the horizontal distance between adjacent VTFETs in different semiconductor layers is also 1 CGP.

[0025] Embodiments of the present invention provide a semiconductor structure having adjacent semiconductor devices in different semiconductor layers, wherein a first semiconductor device in an upper semiconductor layer is horizontally spaced or offset from a second semiconductor device in a lower semiconductor layer by a distance of half a CGP. Alternative embodiments of the present invention provide a semiconductor structure having adjacent semiconductor devices in different semiconductor layers, wherein a first semiconductor device in an upper semiconductor layer is horizontally spaced or offset from a second semiconductor device in a lower semiconductor layer by a distance in the range of 0.3 to 0.7 CGP. The horizontal distance between a first semiconductor device and a third semiconductor device in the same semiconductor layer is 1 CGP gate pitch. Although embodiments of the present invention disclose that the first semiconductor device and the second semiconductor device are vertical transfer field effect (VTFET) devices, in other embodiments of the present invention, the first semiconductor device may be a memory device or another type of logic device, and the second semiconductor device may be one of a memory device or a logic device.

[0026] Embodiments of the present invention also provide a semiconductor structure having four or more VTFETs residing in two different semiconductor layers, wherein each of the VTFETs residing in the lower semiconductor layer is horizontally spaced half a CGP from each adjacent upper VTFET. Alternative embodiments of the present invention also provide a semiconductor structure having four or more VTFETs residing in a number of different semiconductor layers, wherein each of the VTFETs residing in the lower semiconductor layer is horizontally spaced in the range of 0.3 to 0.7 CGP from each adjacent upper VTFET. Embodiments of the present invention provide four VTFET devices, wherein the two top VTFET devices residing in the upper semiconductor layer and the two bottom VTFET devices in the lower semiconductor layer each have a spacing of 1 CGP from adjacent devices in the same semiconductor layer. When compared to a conventional planar VTFET device layout, embodiments of the present invention provide a semiconductor structure having an improved semiconductor device density.

[0027] Embodiments of the present invention provide a VTFET device having 1 CGP in the same semiconductor layer, but the VTFET device in a different semiconductor layer is offset from the VTFET device in the different semiconductor layer by a smaller horizontal distance of half a CGP, which is above or below it. In this way, the VTFET device in the lower semiconductor layer is horizontally spaced half a CGP from the adjacent VTFET device of the upper semiconductor device. In addition, since the VTFET device in the lower semiconductor layer is offset from the VTFET device in the upper semiconductor device by half a CGP, the gate contact from the lower VTFET device can be formed using a vertical etching path to a contact interconnect wiring structure or other semiconductor device formed above the upper VTFET device. Embodiments of the present invention create a straight vertical gate contact directly connected to the semiconductor interconnect wiring or semiconductor element above the upper VTFET device. Compared with conventional vertically stacked VTFET devices, the straight vertical gate contact directly contacting the interconnect wiring above the upper VTFET device provides better electrical performance, where the gate contact from the bottom VTFET device jumps around the VTFET device directly above it to connect to the interconnect wiring above the upper VTFET device. The straight vertically etched gate contacts provided by embodiments of the present invention provide shorter signal paths without horizontal jumps in interconnect wiring connecting lower VTFET devices to upper semiconductor devices.

[0028] In addition, providing a vertically etched path for forming a gate contact reduces the gate contact formation steps compared to conventional vertically stacked VTFET devices, where horizontal and lateral etching may be required to form a jump to the path for the upper VTFET device directly above each VTFET device in the lower VTFET device. Therefore, in addition to providing improved electrical performance of the lower VTFET device compared to conventional vertically stacked VTFET devices, embodiments of the present invention provide a semiconductor structure and a method for forming the semiconductor structure that improves manufacturing yield (e.g., requires fewer gate contact formation processes). Using a vertical etching process to form a gate contact from a bottom VTFET device connected to an interconnect wiring above the upper VTFET device is simpler than the semiconductor manufacturing process used to form a bottom gate contact in a conventional vertically stacked VTFET device. Conventional vertically stacked VTFET devices typically use a lateral etching process and a vertical path etching process to form a bottom gate contact that surrounds the upper VTFET device directly above the lower VTFET device to connect to the interconnect wiring of the upper VTFET device. In addition, the straight vertical gate contact reduces routing congestion above the bottom VTFET device and provides more routing capabilities above the heat sink in the bottom VTFET device compared to traditional vertically etched VTFETs, where the lateral elements or pathways for the gate contacts of the bottom VTFET device create routing congestion above the heat sink of the bottom VTFET device.

[0029] Embodiments of the present invention also disclose an optional etch stop between the gate contact and the top source / drain or gate of a VTFET device. The optional etch stop provides an option for forming a larger top source / drain, which can be used as an enlarged landing platform for the gate contact. The enlarged landing platform provides improved yields during gate contact formation.

[0030] Embodiments of the present invention also provide a semiconductor structure in which a gate contact can be formed directly above the active region of the gate and directly above the heat sink in the channel region. As known to those skilled in the art, forming a gate contact directly above the gate above the active region of a VTFET device is beneficial for device electrical performance.

[0031] In addition, embodiments of the present invention disclose a semiconductor structure formed of a dual-input NAND circuit formed of a pair of p-type (PFET) VTFET devices connected in parallel in an upper semiconductor layer and offset by half a CGP from a pair of n-type (NFET) VTFET devices connected in series in a lower semiconductor layer. Embodiments of the present invention disclose a semiconductor structure consisting of a dual-input NOR circuit having a pair of PFET VTFET devices connected in series and two NFET VTFET devices connected in parallel. Embodiments of the present invention also disclose a transistor inverter using a single CGP stack of two VTFET device layouts.

[0032] Specific embodiments of the claimed structures and methods are disclosed herein. The method steps described below do not form a complete process flow for manufacturing an integrated circuit, such as a semiconductor device. The present embodiment can be combined with the technology currently used in the art for semiconductor chip manufacturing, and only limited processes in the commonly practiced process are included because it is necessary for the understanding of the described embodiments. The accompanying drawings represent a cross-sectional portion of a semiconductor chip having one or more vertically stacked semiconductor devices after manufacturing, and these figures are not drawn to scale, but are drawn to illustrate the features of the described embodiments. The specific structural and functional details disclosed herein are not described as limiting, but are merely described as a representative basis for teaching a person skilled in the art to variously adopt the methods and structures disclosed herein. In the description, details of known features and technologies may be omitted to avoid unnecessarily obscuring the present embodiment.

[0033] References in this specification to "one embodiment," "another embodiment," "yet another embodiment," "an embodiment," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes the particular feature, structure, or characteristic. Furthermore, these statements do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is understood that it is known to those skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly described.

[0034] For ease of description below, the terms "upper layer", "lower layer", "right", "left", "vertical", "horizontal", "top", "bottom" and their derivatives refer to the disclosed structures and methods as oriented in the accompanying drawings. The terms "covering", "on top of", "over", "on", "positioned on", or "positioned above" mean that a first element is presented above a second element, wherein the first element may be presented between the first element and the second element, such as an interface structure. The term "direct contact point" means connecting a first element to a second element without any intermediate element conductive, insulating or semiconducting layer at the interface of the two elements.

[0035] The description of various embodiments of the present invention has been presented for illustrative purposes and is not intended to be exhaustive or to limit the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terms used herein are selected to best explain the principles, practical applications, or technical improvements of the embodiments through existing technology in the market, so that other technicians among those of ordinary skill in the art can understand the embodiments disclosed herein.

[0036] In order to show the presentation of embodiments of the present invention, in the following detailed description, for the purpose of presentation and explanation, some of the processing steps, materials or operations known in the art may be combined, and may not be described in detail in some cases. In addition, for the sake of brevity, and in order to maintain the attention to the salient features of the elements of the present invention, the description of the previously discussed materials, processes and structures may not be repeated with respect to subsequent drawings. In other cases, some known processing steps or operations may not be described. It should be understood that the following description mainly focuses on the salient features or elements of various embodiments of the present invention.

[0037] Figure 1 is a cross-sectional view of a semiconductor structure 100 for a conventional VTFET device according to an embodiment of the present invention. Figure 1A prior art arrangement of four vertically stacked VTFET devices is shown, wherein each of the adjacent VTFETs has a spacing of 1 CGP with an adjacent VTFET in the same semiconductor layer. In addition, the four vertically stacked VTFET devices (VTFETs 8A-D) have a horizontal distance of 1 CGP with another adjacent VTFET in the same semiconductor layer. For example, VTFET 8A has 1 CGP with adjacent VTFET 8C, and VTFET 8B has 1 CGP with adjacent VTFET 8D. In addition, each of the four vertically stacked VTFET devices (VTFETs 8A-D) has a horizontal distance of 1 CGP with an adjacent VTFET in the semiconductor layer above or below. For example, VTFET 8A has 1 CGP with adjacent VTFET 8D in the semiconductor layer below, and VTFET 8C has 1 CGP with adjacent VTFET 8B in the semiconductor layer below.

[0038] As known to those skilled in the art, the contact gate pitch (CGP) is generally the distance between two adjacent semiconductor devices in the same semiconductor layer. In some cases, the CGP may be the same distance as the contact point hole pitch (CPP). As described later, the CGP may also be referred to as the horizontal distance between the heat sinks under the gates in the same semiconductor layer. For purposes of the present invention, the CGP is also used for the horizontal distance from gate to gate or heat sink to heat sink for semiconductor devices residing in different semiconductor layers.

[0039] As depicted in the accompanying drawings, Figure 1 The VTFET 8A, VTFET 8B, VTFET 8C and VTFET 8D are included. Figure 1 In FIG. 8 , VTFET 8A and VTFET 8C reside in the same upper semiconductor layer and have a contact gate pitch or 1 CGP (i.e., the horizontal distance from gate to gate on adjacent devices). Figure 1 , each of VTFET 8A, VTFET 8B, VTFET 8C, and VTFET 8D consists of a source / drain (S / D) 1, a heat sink 2, a gate 3, and a gate contact 6. VTFET 8B and VTFET 8D reside in the same underlying semiconductor layer and also have 1 CGP between each other. Figure 1 As depicted in , VTFET 8A is vertically stacked directly above VTFET 8B, and VTFET 8C is located directly above VTFET 8D. Figure 1 As depicted in FIG, the four conventional vertically stacked VTFETs are each located directly above or below each other in the upper or lower semiconductor layer. Figure 1 In the prior art depicted in , there is no horizontal offset or a horizontal distance between VTFET 8A and VTFET 8B or between VTFET 8C and VTFET 8D, which are located in different semiconductor layers (ie, they are located directly above or below each other).

[0040] Furthermore, in the four conventional vertically stacked VTFET devices, VTFET 8B and VTFET 8D cannot have any wiring levels from the gate contact to those located above VTFET 8A or VTFET 8C (in Figure 1 8A or VTFET 8C, respectively. Figure 1 In the depicted conventional vertically stacked VTFETs, if VTFET 8B and VTFET 8D are not directly connected to the VTFET above them, the gate contact 6 from VTFET 8B and VTFET 8D must have a bounce or lateral extension (not shown), such as a horizontal via or the like, connected to the vertical portion of the gate contact in order to bypass VTFET 8A or VTFET 8C to reach the wiring level above VTFET 8A or VTFET 8C, respectively. Figure 1 not depicted in the ).

[0041] Figure 2A 2 is a cross-sectional view of semiconductor structure 200A after forming VTFET 11A and VTFET 11B in different semiconductor structure layers according to an embodiment of the present invention. For purposes of the present invention, the terms "CGP" and "pitch" may refer to the horizontal distance between adjacent VTFETs in the same semiconductor layer, and the terms "offset", "swing" and "CGP" may refer to the horizontal distance between adjacent VTFETs but residing in different semiconductor layers. As depicted in the accompanying drawings, Figure 2A It includes VTFET 11A and VTFET 11B connected by back end of line (BEOL) or middle of line (MOL) interconnect wiring, which is labeled as interconnect wiring 7.

[0042] exist Figure 2A , 1 CGP is depicted above wiring 7, where 1 CGP will be an adjacent VTFET (not depicted) in the same semiconductor layer. Figure 2A The horizontal distance or offset is also depicted as half a CGP between VTFET 11A in the upper semiconductor layer and VTFET 11B in the lower semiconductor layer. As previously discussed, in alternative embodiments, the horizontal distance or offset may be 0.3 to 0.7 CGP between VTFET 11A in the upper semiconductor layer and VTFET 11B in the lower semiconductor layer. Figure 2A As shown in , half CGP for the horizontal distance between heat sink 2T and heat sink 2B will essentially be the same half CGP offset or spacing between the leftmost edge of gate 3T in VTFET 11A and the leftmost edge of gate 3B in VTFET 11B residing in different semiconductor layers or levels. VTFET 11A and VTFET 11B in different semiconductor layers have a spacing or horizontal offset of half CGP, which is the horizontal distance from heat sink 2T to heat sink 2B and from gate 3T to gate 3B.

[0043] exist Figure 2A In the embodiment, the VTFET 11A includes at least the bottom S / D 21 connected to the portion of the interconnection wiring 7, the heat sink 2T, the gate 3T, and the gate contact 6T, and the VTFET 11B includes at least the S / D 21 connected to the portion of the interconnection wiring 7, the heat sink 2B, the gate 3B, the etching stop 5, and the gate contact 6B. Figure 2A In the embodiment, the two heat sinks 2T and 2B reside in different semiconductor layers. Figure 2A As depicted, VTFET 11A is located in a semiconductor layer that is located above VTFET 11B. In an embodiment, the different semiconductor layers are adjacent to each other, and no other semiconductor devices reside between VTFET 11A and VTFET 11B. In various embodiments, VTFET 11A is horizontally offset from VTFET 11B by half a CGP in a semiconductor layer above the semiconductor layers of VTFET 11A and VTFET 11B.

[0044] As depicted in the accompanying drawings, semiconductor structure 200A also provides gate contacts 6T and 6B that can be directly connected to interconnect wiring 7 using straight vertically etched via holes or contact holes filled with metal to form gate contact 6B and gate contact 6T. In other words, by horizontally offsetting VTFET 11B from VTFET 11A by half a CGP, gate contact 6B can be directly connected using a vertically etched via to interconnect wiring 7 without horizontal jumps or additional horizontal wiring elements. In semiconductor structure 200A, using a vertically etched and filled gate contact via to form gate contact 6B provides advantages in electrical performance (e.g., shorter electrical paths) and manufacturing yield (e.g., fewer processes and no lateral etching), when compared to conventional vertically stacked VTFET devices that require horizontal jumps to directly connect to interconnect wiring above an upper vertically stacked VTFET. As previously discussed, with Figure 2A Unlike the VTFET 11B depicted in FIG. Figure 1The bottom VTFET 8B and VTFET 8D in FIG. 8A cannot use the gate contact 6 to directly connect to the interconnect wiring above the VTFET 8A and VTFET 8C.

[0045] In addition, Figure 1 The conventional vertically stacked VTFET device depicted in does not include an etch stop 5 between the gate 3B and the gate contact 6B in the VTFET 11B. As discussed in detail below, the etch stop 5 is an optional VTFET element that facilitates the formation of the gate contact 6B in the VTFET 11B.

[0046] although Figure 2A VTFET 11A and VTFET 11B are depicted, but in other embodiments, VTFET 11A and VTFET 11B can each be another type of semiconductor device. For example, the semiconductor device in the position of VTFET 11A can be a memory device, and the semiconductor device in the position of VTFET 11B can be another memory device or another logic device (e.g., a planar FET).

[0047] Figure 2B 2 is a cross-sectional view of a semiconductor structure 200B having four VTFETs according to an embodiment of the present invention, wherein VTFET 11A and VTFET 11C each have a horizontal distance of half the CGP from the adjacent bottom VTFET 11B and VTFET 11D. As depicted in the figure, Figure 2B The VTFET 11A and VTFET 11C are formed in a semiconductor structure layer above the semiconductor structure layer of VTFET 11B and VTFET 11D. As depicted in the figure, the horizontal distance between VTFET 11A and VTFET 11B is half of the CGP.

[0048] exist Figure 2B , VTFET 11A and VTFET 11C each include one of the bottom S / D 21 connected to the interconnection wiring 7, one of the heat sink 2T, one of the gate 3T, and one of the gate contact 6T, and VTFET 11B and VTFET 11D each include one of the bottom S / D 21 connected to the interconnection wiring 7, one of the heat sink 2B, one of the gate 3B, one of the etching stop 5, and one of the gate contact 6B. As depicted in the drawings, Figure 2B The present invention includes four heat sinks (for example, two of the heat sinks 2T and two of the heat sinks 2B) and a VTFET formed on each heat sink. Figure 2B In the example, gate contact 6T can provide an input signal to gate 3T in VTFET 11A, and gate contact 6B can provide an output signal to interconnect wiring 7, although the locations of signal input and output may be different in other examples. Interconnect wiring 7 can be a wiring in an interconnect wiring that is in a middle of line (MOL) or end of line (BEOL) interconnect wiring structure. Figure 2B As depicted in , there are two parts of wiring 7.

[0049] The two top devices VTFET 11A and VTFET 11C are located above and adjacent to the semiconductor layer having VTFET 11B and VTFET 11D (eg, other semiconductor devices do not reside between VTFET 11A and VTFET 11B). Figure 2B As depicted in FIG. 1 , the VTFET 11A in the upper semiconductor layer has a 1 CGP spacing from the VTFET 11C in the same semiconductor layer (the left edge of the gate 3T in the VTFET 11A is 1 CGP from the left edge of the gate 3T in the VTFET 11C). Similarly, the spacing between the VTFET 11B and the VTFET 11D in the lower semiconductor layer is 1 CGP ( Figure 2B (not depicted in FIG. 1 ). For example, for advanced technology nodes, 1 CGP is typically in the range of 30 nanometers to 100 nanometers. In an exemplary example, as shown here, 1 CGP can be 40 nanometers. In addition, Figure 2B The horizontal distance depicted in is half the CGP between the gate 3T in VTFET 11A and the gate 3B in VTFET 11B in a semiconductor layer lower than VTFET 11A. For example, VTFET 11A in the upper level of semiconductor structure 200B has a horizontal distance of 20 nanometers (e.g., gate 3T to gate 3B), and the half CGP distance depicted is from VTFET 11A to VTFET 11B, but in other examples, the horizontal distance or offset from VTFET 11A to VTFET 11B is not limited to 20 nanometers. Figure 2B , the VTFET 11B in the upper semiconductor layer has a horizontal distance or offset of half the CGP from the VTFET 11C in the lower semiconductor layer. In other words, the VTFETs in different layers of the semiconductor structure 200B are Figure 2B Each adjacent VTFET of the same layer has a horizontal distance or offset of half the CGP from each adjacent VTFET of another semiconductor layer, and Figure 2B Each adjacent VTFET in has a horizontal distance or offset of 1 CGP. Figure 2B Two VTFETs in each semiconductor layer are depicted, but in other examples there may be more than two VTFETs in each semiconductor layer.

[0050] Furthermore, in various embodiments of the present invention, VTFET 11A, VTFET 11B, VTFET 11C, and VTFET 11D all have straight vertical gate contacts with wiring 7 (i.e., each of gate contacts 6T in VTFET 11A and VTFET 11C and gate contacts 6B in VTFET 11C and VTFET 11D is a straight vertical connection with an interconnect wiring depicted as wiring 7). Figure 2A As depicted in FIG. 1 , gate contact 6T and gate contact 6B do not require horizontal beating or horizontal portions of gate contacts 6B and 6T to connect to semiconductor structures or wiring above VTFET 11A or VTFET 11C. As previously discussed, the straight vertical gate contacts provide improved electrical performance and an improved manufacturing process for lower-level VTFETs 11B and 11D because no lateral beating or elements are required in the gate contacts of VTFET 11B and 11D.

[0051] Figure 3 3 is an isometric top view 300 of a semiconductor structure having 33 and VTFET 34 formed according to an embodiment of the present invention. As depicted in the accompanying drawings, Figure 3 The wiring includes Vdd 20, ground 24, ground connection 54, VTFET 33 having gate contact 26T and output connection 28, VTFET 34 having gate contact 26B and output connection 28B, wiring 27 and wiring 29. VTFET 33 and VTFET 34 are each marked by an arrow. In addition, Figure 3 Shows that later Figures 4 to 8 The positions of the cross sections X1-X1, X2-X2, X3-X3, Y1-Y1 and Y2-Y2 depicted in. As known to those skilled in the art, for example, an inverter is a NOT gate that flips the input, for example, from input 1 to output 0 or vice versa.

[0052] Figure 3 VTFET 33 is shown, which is formed on heat sink 22T and is offset from VTFET 34 on heat sink 22B by half CGP. Figure 3As shown in the figure, the left edge of the gate 23T on the heat sink 22T of the VTFET 33 in the upper semiconductor layer is horizontally spaced or offset from the left edge of the gate 23B on the heat sink 22B in the VTFET 34 by half a contact gate pitch (e.g., half a CGP). As depicted in the figure, the VTFET 33 and the VTFET 34 include a bottom S / D 31 and a top S / D 41. In various embodiments, the VTFET 33 is an n-type field effect (NFET) device, and the VTFET 34 is a p-type field effect (PFET) device. In an embodiment, the VTFET 33 is a PFET, and the VTFET is an NFET.

[0053] Figure 4 According to an embodiment of the present invention Figure 3 FIG. 4 is a cross-sectional view 400 through X1-X1 of the inverter shown in FIG. As depicted in the accompanying drawings, Figure 4 The semiconductor structure 400 includes a ground 24, a wiring 27, a VTFET 33, and a VTFET 34, which have gate contacts 26T and 26B, respectively. As depicted in the figure, the heat sink 22B resides in a device layer of the semiconductor structure lower than the heat sink 22T (e.g., the lower device layer is located directly below the semiconductor layer of the heat sink 22T without any additional semiconductor devices residing between the VTFET 33 and the VTFET 34). In the semiconductor structure 400, the VTFET 33 is adjacent to the VTFET 34 and is located at the VTFET 34, wherein the horizontal distance or offset between the VTFET 33 and the VTFET 34 in different semiconductor layers is half a CGP (e.g., where 1 CGP would be the distance between the gates in the VTFETs in the same semiconductor layer).

[0054] like Figure 4 As depicted, VTFET 33 includes gate contact 26T connected to wiring 27, gate 23T on heat sink 22T, where heat sink 22T resides on bottom S / D 31. As depicted in the figure, VTFET 34 includes bottom S / D 31, gate contact 26B, gate 23B on heat sink 22B, gate contact 26B connected to wiring 27, and etch stop 35. Etch stop 35, which is an optional element in VTFET 34, resides above gate 23B and below gate contact 26B. In some examples (not depicted), etch stop 35 is not present in VTFET 34. In one embodiment, VTFET 33 is a PFET formed on heat sink 22, which can receive a signal from gate contact 26T, and VTFET 34 is an NFET formed on heat sink 22B, which can receive a signal from gate contact 26B.

[0055] Figure 5According to an embodiment of the present invention Figure 3 A cross-sectional view 500 through X2-X2 of the inverter shown in FIG. As depicted in the accompanying drawings, Figure 5 The semiconductor structure 500 includes ground 24, wiring 29, output connection 28T, output connection 28B, VTFET 33, and VTFET 34, which have top S / D 41 above heat sink 22B and below etch top 35. As depicted in the figure, heat sink 22B can reside on a device layer of the semiconductor structure lower than heat sink 22T. In semiconductor structure 500, VTFET 33 is adjacent to VTFET 34 and above VTFET 34, wherein the horizontal distance or offset between gate 23T in VTFET 33 and gate 23B in VTFET 34 is half a CGP.

[0056] exist Figure 5 , VTFET 33 includes output connection 28T, which is connected to wiring 29, top S / D 41, heat sink 22T on bottom S / D 31, and gate 23T. Figure 5 As depicted in , VTFET 34 includes output connection 28B connected to wiring 29 , etch stop 35 over top S / D 41 , heat sink 22B, gate 23B, and bottom S / D 31 over ground 24 .

[0057] Etch stop 35 is an optional element of VTFTET 34. As depicted in the figure, top S / D 41 is an enlarged contact landing platform. The enlarged contact landing platform (top S / D 41) below the etch stop layer 35 reduces VTFTET 34 manufacturing and helps improve device yield. The enlarged contact landing platform is Figure 5 Optional features of the semiconductor structure depicted in FIG. Forming an etch stop 35 , an optional element of the present invention, helps to form an enlarged contact landing platform for the top S / D 41 .

[0058] Figure 6 According to an embodiment of the present invention Figure 3 A cross-sectional view 600 through X3-X3 in the inverter depicted in FIG. As depicted in the accompanying drawings, Figure 6 Includes Vdd 20, ground connection 54, bottom S / D 31 below Vdd 20, and bottom S / D 31 and ground 24 above ground connection 54. Figure 3 In the cross-sectional view 600 through X3-X3 of the inverter of FIG. 6A , Vdd 20 resides above ground 24. In some embodiments, Vdd 20 is a Vdd power rail.

[0059] Figure 7 According to an embodiment of the present invention Figure 3A cross-sectional view 700 through Y1-Y1 in the inverter depicted in FIG. As depicted in the accompanying drawings, Figure 7 Includes VTFET 33, wiring 27, wiring 29, Vdd 20 above ground 24 below VTFET 33. VTFET 33 includes bottom S / D 31 below heat sink 22T, gate 23T above and around portion of heat sink 22T, gate contact 26T on gate 23T connected to wiring 27, top S / D 41 above portion of heat sink 22T, and output connection 28T connected to wiring 29. Figure 7 Portions of the inverter are depicted as extending along the inverter through the heat sink 22T and over the ground 24 (eg, the cross-sectional view 700 bisects or passes through the VTFET 33). Additionally, Figure 7 1 depicts an example of a contact over active area, also referred to as a contact or gate over active gate (COAG), where a contact such as gate contact 26T may be formed as gate 23T over heat sink 22T on VTFET 33. As known to those skilled in the art, COAG may reduce the cell area of ​​a vertical transfer field effect transistor (e.g., may reduce device size).

[0060] Figure 8 According to an embodiment of the present invention Figure 3 FIG. 8 is a cross-sectional view 800 through Y2-Y2 of the inverter shown in FIG. As depicted in the accompanying drawings, Figure 8 The VTFET 34 includes wiring 27, wiring 29, ground connection 54, ground 24, VTFET 34 with top S / D 41 below optional etch stop 35 on the right side of VTFET 34, bottom S / D 31, gate 23B on and around a portion of heat sink 22B, gate contact 26B above etch stop 35 on the left portion of gate 23B, gate contact 26B connected to wiring 27, and output connection 26B on the rightmost etch stop 35. Output connection 26B is connected to wiring 29. Figure 8 , VTFET 34 is located above and connected to ground 24. As previously discussed, top S / D 41 can be an enlarged landing platform below optional etch stop 35, wherein the enlarged landing platform and etch stop layer 35 facilitate the formation of output connection 28B (e.g., can provide an improved yield for the formation of output connection 28). In some embodiments, etch stop 35 acts as an intermediate connection to the enlarged landing platform for gate contact 26B and output connection 28B. Figure 8 As depicted in , etch stop 35 is located below gate contact 26 and output connection 28B.

[0061] Figure 8VTFET 34 is depicted as extending along heat sink 22B. VTFET 34 is connected to ground 24 by ground connection 54. Figure 7 Similar to the semiconductor structure depicted in Figure 8 The semiconductor structure depicted in also allows a COAG (wherein a contact such as gate contact 26B) to be formed to gate 23B above heat sink 22B in the active region of VTFET 34. Thus, in various embodiments, a COAG is provided in VTFET 33 on heat sink 22B (e.g., top heat sink), an inverter, and may be provided on a lower level semiconductor device layer of VTFET 34 depicted as an inverter. Furthermore, as depicted, the wiring above each of the active heat sinks is open for cell-to-cell connections.

[0062] Fig. 9 , Fig. 10A and Fig. 10B Three views (eg, circuit schematic, top view, and bottom view) of four VTFETs are shown that are connected in series using two PFET VTFETs (ie, Fig. 10A VTFET 92A and VTFET 92C) and two NFETs VTFET (i.e., Fig. 10B VTFET 92B and VTFET 92D) are formed on two different semiconductor layers to create a dual-input NOR circuit. Fig. 10A and 10B As depicted in , VTFET 92A and VTFET 92C (top PFET VTFET) are each offset by half a CGP from VTFET 92B and VTFET 92D (adjacent PFET VTFET), which reside on a heat sink in a lower semiconductor layer than VTFET 92A and VTFET 92C.

[0063] like Fig. 10A and 10B As depicted, Fig. 10A Superimposed on Fig. 10B When on, form Fig. 9 The four VTFETs of the two input NOR circuit are covered or used Fig. 10A and Fig. 10B In one example, when one CGP is 40 nanometers, as shown later in Fig. 10A and 10B Depicted Fig. 9The area of ​​the two dual-input NOR circuits may be 80 nanometers (cell height) by 80 nanometers. In other examples, the area of ​​the dual-input NOR circuits may be different.

[0064] Fig. 9 900 is a circuit schematic diagram of a single strength transistor device composed of a dual-input NOR circuit according to an embodiment of the present invention. The circuit schematic diagram 900 depicts an example of a dual-input NOR circuit 1X or a single strength transistor formed by using four VTFETs. As depicted in the circuit schematic diagram 900, the dual-input NOR circuit is composed of two PFETs VTFET connected in series and two NFETs VTFET connected in parallel. The two PFETs VTFET are formed in the upper semiconductor layer and later in Fig. 10A Two NFETs VTFET are formed below the PFETs VTFET, offset by half a CGP from each of the PFETs VTFET, and later in Fig. 10B In other embodiments, the top VTFET device is an NFET VTFET and the bottom two VTFETs are PFET VTFETs, or the top VTFET device is a mix of NFET and PFET devices and the bottom VTFET is a mix of NFET and PFET devices.

[0065] As depicted in the accompanying drawings, Fig. 9 The first PFET VTFET receives an input signal A, as depicted in the accompanying drawings. Fig. 9 In the embodiment, the first PFET VTFET is connected in series to the second PFET VTFET. The second PFET VTFET receives an input signal B and is connected to Fig. 9 The first and second NFETs in VTFET. Fig. 9 As depicted in , a first NFET VTFET is connected in parallel with a second NFET VTFET, wherein the first NFET VTFET receives an input signal A, and the second NFET VTFET receives an input signal B. Fig. 9 As depicted in FIG. 1 , the output of the second PFET VTFET and the two NFET VTFET outputs are connected to form an output signal C. The two NFET VTFETs are connected to a ground voltage or ground, which is Fig. 9 The mark Vss in the.

[0066] Fig. 9 The first PFET in the VTFET is later in Fig. 10A depicted as PFET VTFET 92A, and Fig. 9The second PFET VTFET in the Fig. 10A is depicted as PFET VTFET 92C. In addition, Fig. 10B The later depicted in Fig. 10B The first NFET of the 92B is the VTFET and Fig. 10B The second NFET VTFET is labeled 92D.

[0067] Fig. 10A According to an embodiment of the present invention, a dual-input NOR circuit is formed Fig. 9 100A isometric top view of a single strength transistor. As depicted in the accompanying figure, the isometric top view 100A includes two sections of wiring 87, wiring 89, ground 84, Vdd80, contact point 95, two of the gate contacts 86T, two gate contacts 86B, output connection 88T, output connection 88B, PFET VTFET 92A and PFET VTFET 92C. PFET VTFET 92A and PFET VTFET 92C are located above NFET VTFET 92B and NFET VTFET 92D in the lower semiconductor layer and are offset from them by half a CGP. NFET VTFET 92C and NFET VTFET 92D are later Fig. 10B Depicted in Fig. 10A In FIG. 1 , the PFET VTFET 92A and the PFET VTFET 92C in the same semiconductor layer are spaced apart by 1 CGP.

[0068] exist Fig. 10A , the PFET VTFET 92A is composed of a gate 83T on a heat sink 82T on a bottom S / D 81 and a top S / D 61 above the heat sink 82T. The PFET VTFET 92A receives a signal input A ( Fig. 9 ). The other rightmost portion of wiring 87 also connects gate contact 86T to gate contact 86B. PFET VTFET 92A can be connected to Fig. 9 The output signal C in question is sent to the output connection 88T associated with the PFET VTFET 92C via the shared bottom S / D 81, to the PFET VTFET 92C. Fig. 10B As discussed, gate contact 86B provides signal input A to NFET VTFET 92B located in the lower semiconductor layer. Contact 95 connects top S / D 61 to Vdd 80 (Vdd 80 may also be referred to as a Vdd power rail).

[0069] exist Fig. 10A, PFET VTFET 92C is depicted to the right of PFET VTFET 92A. As shown, PFETVTFET 92C consists of the rightmost gate 83T on the rightmost heat sink 82T, the bottom S / D 81 under the rightmost heat sink 82T, and the top S / D 61 on the heat sink 82T. In various embodiments, the top S / D 61 in PFET VTFET 92A is connected to the contact point 95 connected to Vdd 80 (Vdd power rail). As previously described with reference to Fig. 9 As discussed, PFETVTFET 92B and PFET VTFET 92A are connected in series.

[0070] The gate contact 86T in the PFET VTFET 92C is above the rightmost gate 83T and receives the signal input B. The gate contact 86T is connected to the second portion of the wiring 87. As shown in the figure, the gate contact 86T in the PFET VTFET 92C is connected to the NFET VTFET 92D ( Fig. 10A The gate contact 86B on the gate 83B of the NFET VTFET 92D (not shown) can provide a gate contact 86B to the NFET VTFET 92D. Fig. 10B ) provides signal input B. As shown, gate contact 86B is located in the middle between PFET VTFET 92A and PFET VTFET 92C, where, as shown, PFET VTFET 92A and PFET VTFET 92C are separated by 1 CGP. In other words, in PFET VTFET 92A or PFET VTFET 92C, each gate contact 86T is horizontally separated from at least one outer edge of gate 83T by half a CGP. As previously described, PFET VTFET92A is connected in series with PFET VTFET 92C so that the output of PFET VTFET 92A is fed into PFET VTFET 92C, and the output of PFET VTFET 92C is fed into output connection 88T. Output connection 88T is connected to output connection 88B through wiring 89.

[0071] In addition, if Fig. 10A As shown in FIG. 1 , the distance between the gate 83T in the PFET VTFET 92A and the gate 83T in the PFETVTFET 92C located on the same semiconductor layer is 1 CGP. Fig. 10A The horizontal distance around the edge of the box is half the CGP. Fig. 10A The surrounding frame is directly above Fig. 10B In other words, Fig. 10A Directly in Fig. 10Babove, and Fig. 10A VTFET 92A and VTFET 92C in the upper semiconductor device layer shown in FIG. Fig. 10B The combination of VTFET 92B and VTFET 92D in the lower semiconductor device layer shown in FIG. Fig. 9 A two-input NOR circuit.

[0072] Fig. 10B According to an embodiment of the present invention, a dual-input NOR circuit is formed Fig. 9 A bottom isometric view 1000B of a single strength transistor. As shown, Fig. 10B The NFETs VTFET 92B and 92D are formed on a lower semiconductor layer than the PFETs VTFET 92A and VTFET 92D (e.g., the PFETs VTFET 92A and VTFET 92C are formed in a semiconductor layer directly above the semiconductor layer including the NFETs VTFET 92B and VTFET 92D). As shown, the VTFETs 92B and VTFET 92D are spaced 1 CGP apart and are horizontally offset by half a CGP from the VTFETs 92A and VTFET 92C, respectively.

[0073] like Fig. 10B As shown, one CGP separates the leftmost edge of gate 83B of NFET VTFET 92B from gate 83B of NFET VTFET92D. In addition, as shown, NFET VTFET 92B is 1 CGP away from the edge of the box, which indicates where the next NFET VTFET can be formed. As previously described, Fig. 10B The edge of the box in Fig. 10A In this case, the horizontal distance or offset from PFET VTFET 92A to NFET VTFET 92B is half a CGP (i.e., Fig. 10B 1 CGP minus Fig. 10A half CGP shown in ).

[0074] exist Fig. 10BIn the figure, NFET VTFET 92B is to the left of NFET VTFET 92D. NFETVTFET 92B on the bottom S / D 91 consists of gate 83B on the leftmost heat sink 82B and the top S / D 71, and as described above, the leftmost of gate contact 86B receives signal input A from wiring 87. Output connection 88B is on a portion of NFET VTFET 92B and is connected to a portion of NFET VTFET 92D, as shown. Output connection 88B can receive an output signal from the top S / D 71.

[0075] In addition, if Fig. 10B As shown, NFET VTFET 92D is formed by gate 83B on the rightmost heat sink 82B above bottom S / D 91. Heat sink 82B is below top S / D 71, wherein the rightmost gate contact 86B is located on gate 83B of NFET VTFET92D and receives signal input B (e.g., by Fig. 10A The wiring 87 above is provided). As previously referred to Fig. 9 As discussed, NFET VTFET 92B and NFET VTFET 92D are connected in parallel, and the outputs of both are connected to output connection 88B.

[0076] Fig.11 1 is a circuit schematic 1100 of a single transistor strength device consisting of a two-input NAND circuit according to an embodiment of the present invention. Circuit schematic 1100 depicts an example of a 1X or single strength transistor consisting of a two-input NAND circuit formed using four VTFETs, which are later described in Fig. 12A and 12B 122A, PFETVTFET 122C, NFET VTFET 122B, and NFET VTFET 122D. As shown in the circuit schematic 1100, the two-input NAND circuit is composed of two PFET VTFETs connected in parallel and two NFET VTFETs connected in series. The two PFET VTFETs are formed in the upper semiconductor layer and are later connected in the Fig. 12A The two NFETs VTFET are formed below the two PFETs VTFET and are horizontally offset from the two PFETs VTFET by a horizontal distance of half CGP, as shown in FIG. Fig. 12A and 12B discussed. Fig. 12B The two NFETs VTFET are described in more detail in .

[0077] As described, Fig.11A power supply voltage labeled Vdd is included, which is connected to the first PFET VTFET with an input signal A and to the second PFET VTFET with an input signal B, wherein the first PFET VTFET and the second PFET VTFET are connected in parallel as described. Fig.11 As shown, the first NFET VTFET receives an input signal A, and the second NFET VTFET receives an input signal B, wherein, Fig.11 As shown, the first and second NFETs VTFET are connected in series. Fig.11 As shown, the output from each of the two PFETs VTFET and the output from the first NFET VTFET are sent to the output signal C by the second NFET VTFET because, as described above, the first NFET VTFET is connected in series with the second NFET VTFET. In other words, the output signal C includes the output from each of the four VTFETs. The first NFET VTFET is connected to the output of the first NFET VTFET. Fig.11 The ground voltage marked as Vss in the figure.

[0078] Fig.11 The first PFET VTFET is described later as Fig. 12A PFET VTFET 122A, Fig.11 The second PFET VTFET is described later as Fig. 12A In addition, later in Fig. 12B It is shown in Fig. 12B The first NFET VTFET and the Fig. 12B The second NFET VTFET is labeled 122D.

[0079] Fig. 12A According to an embodiment of the present invention Fig.11 1200A is a top view of a single transistor with dual input NAND circuitry shown in FIG. 1200A. Top view 1200A is an isometric top view through various semiconductor layers (e.g., through interlayer dielectric materials). As depicted, top view 1200A includes ground 94, Vdd 90, two gate contacts 96B, two output connections 98T, gate contacts 96T, output connections 98B, two portions of wiring 97, wiring 99, PFET VTFET 122A, and PFETVTFET 122C. As depicted, top view 1200A includes ground 94, Vdd 90, two gate contacts 96B, two output connections 98T, gate contacts 96T, output connections 98B, two portions of wiring 97, wiring 99, PFET VTFET 122A, and PFET VTFET 122C. Fig.11As shown, PFET VTFET 122A and PFET VTFET 122C are connected in parallel, and wherein the top S / D 121 on PFET VTFET 122A and the output connection 98T on PFET VTFET 122C are connected by wiring 99. PFET VTFET 122A and PFET VTFET 122D reside in a semiconductor layer above NFET VTFET 122B and NFET VTFET 122D. As previously described with respect to Fig. 9 As discussed, the output signal C comes from wiring 99 and includes Fig. 12A The outputs of both output connection 98T and output connection 98B depicted in FIG.

[0080] also, Fig. 12A 1 CGP distance between PFET VTFET 122A and PFET VTFET 122C is shown in FIG. 1 , and the PFET VTFET 122A and the description Fig. 12A The edges of the box are half the CGP distance apart. Fig. 10A and Fig. 10B , Fig. 12A and Fig. 12B Depicted are views of different semiconductor layers directly above and below each other, where Fig. 12A Around the edge of the BOX and Fig. 12B The edges of the surrounding BOX are aligned vertically and are directly above and below each other.

[0081] exist Fig. 12A , the PFET VTFET 122A on the bottom S / D 101 consists of a gate 93T on the leftmost heat sink 192T and a top S / D 121 above the heat sink 92T. The leftmost gate contact 96T receives a signal input A from a portion of a wiring 97, wherein a second portion of the wiring 97 is connected to the gate contact 96B. In the PFET VTFET 122A, the top S / D 121 is below the output connection 98T. Fig. 9 The output signal C shown receives the Fig. 12A The outputs of NFET VTFET 122D are shown with two output connections 98T and output connection 98B all connected via wiring 99 .

[0082] In addition, Fig. 12A , PFET VTFET 122C is located to the right of PFET VTFET 122A. As depicted, PFET VTFET 122C includes a gate 93T on the rightmost heat sink 192T on the bottom S / D 101, with the rightmost portion of gate 93T having a gate contact 96T. Fig. 12AAs shown, the gate contact 96B is connected to a portion of the interconnect wiring 97. Fig. 12A and Fig.11 As shown, the rightmost gate contact 96T above the PFET VTFET 122C receives the signal input B from the interconnect wiring 97. When the PFET VTFET 122A and the PFET VTFET 122C are connected in parallel (i.e., as previously described with respect to Fig.11 122C sends the output to the output connection 98T using the interconnect wiring 99 that connects from the PFET VTFET 122C to the output connection 98T. Fig. 12A As shown, wiring 99 is also connected to output connection 98B. As depicted, the top S / D 121 in each of PFET VTFET 122A and PFET VTFET 122C is connected to Vdd 90, which may be a shared Vdd power rail.

[0083] Fig. 12B According to an embodiment of the present invention Fig.11 A bottom isometric view 1200B of a single strength transistor with a two-input NAND circuit. As shown, Fig. 12B Included are ground connection 105, ground 94, contact 95B, NFET VTFET 122B and NFET VTFET 122D, which have gate contact 96B and output connection 98B. Fig. 12B Shown in the ratio Fig. 12A PFET VTFET 122A and PFET VTFET 122C are shown with NFET VTFET 122B and NFETVTFET 122D formed on a lower semiconductor level.

[0084] exist Fig. 12B , the NFET VTFET 122B on the bottom S / D 111 includes a gate 93B on the far left of the heat sink 192B, a gate contact 96B receiving a signal input A, and a contact 95B on the top S / D 131 connected to a ground connection 105, which is connected to a ground 94. As shown in FIG. Fig.11 As discussed, NFET VTFET 122B and NFET VTFET 122D are connected in series, and output connection 98B is connected to NFET VTFET 122D as shown.

[0085] Methods as described herein can be used for the manufacture of integrated circuit chips or semiconductor chips. Manufacturers can distribute the resulting semiconductor chips in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as bare chips, or in packaged form. In the latter case, the semiconductor chip is mounted in a single chip package (e.g., a plastic carrier with lead wiring fixed to a motherboard or other higher-level carrier) or in a multi-chip package (e.g., a ceramic carrier with one or both of surface interconnects or buried interconnects). In any case, the semiconductor chip is then integrated with other semiconductor chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product including a semiconductor chip, ranging from toys and other low-end applications to advanced computer products with displays, memories, keyboards, or other input devices and central processing units.

[0086] In a preferred embodiment of the present invention described herein, a semiconductor structure is provided, the semiconductor structure comprising: a first vertical transfer field effect transistor in a lower semiconductor layer; and a second vertical transfer field effect transistor in an upper semiconductor layer, wherein the first vertical transfer field effect transistor is offset from the second vertical transfer field effect transistor by half the contact gate spacing of the second vertical transfer field effect transistor. Preferably, the first vertical transfer field effect transistor has a straight vertical contact point and the second vertical transfer field effect transistor has a straight vertical contact point. Preferably, the first vertical transfer field effect transistor is a first type field effect transistor and the second vertical transfer field effect transistor is a second type field effect transistor. Preferably, the offset is half the contact gate spacing of the second vertical transfer field effect transistor. Preferably, the offset is in the range between 0.3 and 0.7 of the contact gate spacing of the second vertical transfer field effect transistor.

[0087] In another preferred embodiment of the present invention described herein, there is provided a semiconductor structure comprising: one or more vertical transfer field effect transistors in an upper semiconductor layer, wherein the one or more vertical transfer field effect transistors in the first semiconductor layer are separated by a gate pitch of a contact point; one or more vertical transfer field effect transistors in a lower semiconductor layer, wherein the one or more vertical transfer field effect transistors in the lower semiconductor layer are separated by a gate pitch of a contact point; and wherein the one or more vertical transfer field effect transistors in the upper semiconductor layer are offset from the one or more vertical transfer field effect transistors in the lower semiconductor layer. Preferably, the one or more vertical transfer field effect transistors in the lower semiconductor layer have straight vertical contacts connected to interconnect wiring above the one or more vertical transfer field effect transistors in the upper semiconductor layer. Preferably, the one or more vertical transfer field effect transistors in the lower semiconductor layer each have a contact point over an active gate (COAG). Preferably, the one or more vertical transfer field effect transistors in the lower semiconductor layer are first type field effect transistors, and wherein the one or more vertical transfer field effect transistors in the upper semiconductor layer are second type field effect transistors. Preferably, the offset is in the range between 0.3 and 0.7 of the contact gate pitch. In another preferred embodiment of the present invention described herein, there is provided a semiconductor structure comprising: a first pair of vertical transfer field effect transistors in a lower semiconductor layer; a second pair of vertical transfer field effect transistors in an upper semiconductor layer, wherein each of the second pair of vertical transfer field effect transistors in the upper semiconductor layer is horizontally offset by half a contact gate pitch from at least one vertical transfer field effect transistor in the lower semiconductor layer; and wherein the first pair of vertical transfer field effect transistors in the lower semiconductor layer are vertical transfer field effect transistors of the first type connected in parallel, and the second pair of vertical transfer field effect transistors in the upper semiconductor layer are vertical transfer field effect transistors of the second type connected in series. Preferably, each of the first pair of vertical transfer field effect transistors in the lower semiconductor layer and each of the second pair of vertical transfer field effect transistors in the upper semiconductor layer have a straight vertical contact point to the interconnect wiring above the second pair of vertical transfer field effect transistors. The structure may also include: a bottom conductive plane connected to at least one of the first pair of first type vertical transfer field effect transistors in the lower semiconductor layer; and a power rail above and connected to at least one of the second pair of second type vertical transfer field effect transistors in the upper semiconductor layer. Preferably, the first pair of vertical transfer field effect transistors and the second pair of vertical transfer field effect transistors in the lower semiconductor layer form a dual-input NOR circuit.The structure may also include: a first pair of vertical transfer field effect transistors in the lower semiconductor layer; a second pair of vertical transfer field effect transistors in the upper semiconductor layer, wherein each of the second pair of vertical transfer field effect transistors in the upper semiconductor layer is horizontally offset from at least one vertical transfer field effect transistor in the lower semiconductor layer by half a contact gate pitch; and wherein the first pair of vertical transfer field effect transistors in the lower semiconductor layer are vertical transfer field effect transistors of the first type connected in series, and the second pair of vertical transfer field effect transistors in the upper semiconductor layer are vertical transfer field effect transistors of the second type connected in parallel. Preferably, each of the first pair of vertical transfer field effect transistors in the lower semiconductor layer and each of the second pair of vertical transfer field effect transistors in the upper semiconductor layer have a straight vertical contact point to the interconnect wiring above the second pair of vertical transfer field effect transistors. Preferably, the first pair of vertical transfer field effect transistors in the lower semiconductor layer and the second pair of vertical transfer field effect transistors form a dual-input NAND circuit.

Claims

1. A semiconductor structure, comprising: a first plurality of vertical transfer field effect transistors in the lower semiconductor layer; as well as A second plurality of vertical transfer field effect transistors in the upper semiconductor layer, wherein the second plurality of vertical transfer field effect transistors are offset from the first plurality of vertical transfer field effect transistors.

2. The semiconductor structure of claim 1, wherein each of the second plurality of vertical transfer field effect transistors in the upper semiconductor layer is horizontally offset from the first plurality of vertical transfer field effect transistors in the lower semiconductor layer by half a contact gate pitch.

3. A semiconductor structure according to claim 1, wherein each of the second plurality of vertical transfer field effect transistors in the upper semiconductor layer has a horizontal distance from an adjacent vertical transfer field effect transistor in the second plurality of vertical transfer field effect transistors in the upper semiconductor layer that is a contact gate spacing.

4. The semiconductor structure of claim 1, wherein each of the first plurality of vertical transfer field effect transistors in the underlying semiconductor layer has one or more contacts having a direct in-line vertical connection.

5. The semiconductor structure of claim 4, wherein the one or more contacts having the direct in-line vertical connection each reside between two adjacent vertical transfer field effect transistors of the second plurality of vertical transfer field effect transistors in the upper semiconductor layer. 6 . The semiconductor structure of claim 1 , wherein each of the first plurality of vertical transfer field effect transistors in the underlying semiconductor layer has a gate contact over active gate (COAG).

7. The semiconductor structure of claim 1, wherein said second plurality of vertical transfer field effect transistors have at least one gate contact over active gate (COAG).

8. The semiconductor structure of claim 1, wherein the second plurality of vertical transfer field effect transistors in the upper semiconductor layer are horizontally offset from the first plurality of vertical transfer field effect transistors in the lower semiconductor layer by a range between 0.3 and 0.7 contact gate pitches.

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