Display substrate and display device

Abstract

The invention discloses a display substrate and a display device. The display substrate comprises a substrate body (10) and a plurality of pixel driving circuits arranged on the substrate body (10). The display substrate further comprises a first level signal input layer and an electrostatic discharge layer (20), at least part of the electrostatic discharge layer (20) is located on the side, facing the substrate (10), of the pixel driving circuit, and the electrostatic discharge layer (20) is coupled with the first level signal input layer.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] With the continuous development of display technology, the application fields of display products are becoming more and more extensive, and people's requirements for the quality and yield of display products are becoming higher and higher.

[0003] During the actual production of display products, static electricity is generated during processes such as side cutting, binding, die bonding, film application and tearing. To prevent excessive static electricity from accumulating inside the display product and causing circuit damage, relevant technologies include an electrostatic discharge (ESD) structure inside the display product, including a circuit structure.

[0004] Summary of the Invention

[0005] An object of the present disclosure is to provide a display substrate and a display device.

[0006] In order to achieve the above objectives, the present disclosure provides the following technical solutions:

[0007] A first aspect of the present disclosure provides a display substrate, comprising: a base substrate and a plurality of pixel driving circuits arranged on the base substrate; the display substrate further comprises a first-level signal input layer and an electrostatic release layer, at least a portion of the electrostatic release layer is located on a side of the pixel driving circuit facing the base substrate, and the electrostatic release layer is coupled to the first-level signal input layer.

[0008] Optionally, the first level signal input layer includes a power layer, and the electrostatic release layer is coupled to the power layer.

[0009] Optionally, the first level signal input layer includes a cathode layer, and the electrostatic release layer is coupled to the cathode layer.

[0010] Optionally, the first-level signal input layer includes a light-shielding layer, at least part of the light-shielding layer is located between the pixel driving circuit layer and the base substrate, the pixel driving circuit includes a plurality of transistors, the transistors include an active layer, and the orthographic projection of the light-shielding layer on the base substrate at least partially overlaps with the orthographic projection of the active layer included in at least part of the transistors on the base substrate; the electrostatic release layer is coupled to the light-shielding layer.

[0011] Optionally, at least part of the electrostatic release layer is located between the light-shielding layer and the base substrate, and the electrostatic release layer and the light-shielding layer are coupled through a via; or, the electrostatic release layer and the light-shielding layer are arranged on the same layer, and the electrostatic release layer and the light-shielding layer are directly overlapped.

[0012] Optionally, an overlapping area between an orthographic projection of the electrostatic release layer on the base substrate and an orthographic projection of the light shielding layer on the base substrate is less than or equal to 10% of an area of ​​the electrostatic release layer.

[0013] Optionally, the display substrate further includes a light-shielding layer, at least a portion of which is located between the pixel driving circuit layer and the base substrate; the orthographic projection of the electrostatic release layer on the base substrate does not overlap with the orthographic projection of the light-shielding layer on the base substrate.

[0014] Optionally, the display substrate includes a power layer and a cathode layer; the power layer includes a plurality of power lines arranged along a first direction, the power lines include at least a portion extending along a second direction, and the first direction intersects the second direction; the cathode layer includes a plurality of cathode lines arranged along the first direction, the cathode lines include at least a portion extending along the second direction;

[0015] The electrostatic release layer is formed in a grid shape, and includes a plurality of first grid portions extending along a first direction, and a plurality of second grid portions extending along a second direction; the orthographic projection of at least one of the second grid portions on the base substrate at least partially overlaps with the orthographic projection of the power line on the base substrate; and / or the orthographic projection of at least one of the second grid portions on the base substrate at least partially overlaps with the orthographic projection of the cathode line on the base substrate.

[0016] Optionally, the display substrate includes a plurality of clock signal lines arranged along a second direction, the clock signal lines include at least a portion extending along the first direction, and the pixel driving circuit is coupled to the corresponding clock signal lines; the orthographic projection of the first grid portion on the base substrate at least partially overlaps with the orthographic projection of the clock signal lines on the base substrate.

[0017] Optionally, the electrostatic release layer includes a plurality of first openings, and the orthographic projection of the boundary of the first opening on the base substrate includes a curved edge portion; the orthographic projection of the first opening on the base substrate at least partially overlaps with the orthographic projection of the pixel driving circuit on the base substrate.

[0018] Optionally, the electrostatic release layer includes a plurality of second openings, and the orthographic projection of the boundaries of the second openings on the base substrate includes a straight edge; the orthographic projection of the second openings on the base substrate does not overlap with the orthographic projection of the pixel driving circuit on the base substrate.

[0019] Optionally, the orthographic projection of the boundary of the second opening on the substrate includes at least one sawtooth portion.

[0020] Optionally, the pixel driving circuit includes a driving transistor and a storage capacitor, a first plate of the storage capacitor is coupled to the gate of the driving transistor, and a second plate of the storage capacitor is coupled to the power layer;

[0021] The orthographic projection of the second electrode on the base substrate has an overlapping area with the orthographic projection of the electrostatic release layer on the base substrate. In the overlapping area, the second electrode and the electrostatic release layer are coupled through a via.

[0022] Optionally, the display substrate further includes a first conductive connection portion, the first conductive connection portion is coupled to the power line, and at least a portion of the first conductive connection portion is located on a side of the power line facing away from the base substrate;

[0023] An orthographic projection of the first conductive connection portion on the base substrate and an orthographic projection of the electrostatic release layer on the base substrate have an overlapping area, and the first conductive connection portion and the electrostatic release layer are coupled through a via in the overlapping area.

[0024] Optionally, the display substrate further includes a first conductive connection portion and a second conductive connection portion, at least a portion of the second conductive connection portion is located on the side of the first conductive connection portion facing away from the base substrate; the first conductive connection portion is coupled to the second conductive connection portion and the power supply layer, respectively; the orthographic projection of the second conductive connection portion on the base substrate has an overlapping area with the orthographic projection of the electrostatic release layer on the base substrate, and in the overlapping area, the second conductive connection portion and the electrostatic release layer are coupled through a via.

[0025] Optionally, the display substrate further includes a third conductive connection portion, the third conductive connection portion is coupled to the cathode layer, and at least a portion of the third conductive connection portion is located on a side of the cathode layer facing away from the base substrate;

[0026] The orthographic projection of the third conductive connection portion on the base substrate has an overlapping area with the orthographic projection of the electrostatic release layer on the base substrate. In the overlapping area, the third conductive connection portion and the electrostatic release layer are coupled through a via.

[0027] Optionally, the display substrate further includes a first connecting electrode and a third conductive connecting portion, at least a portion of the first connecting electrode is located on the side of the third conductive connecting portion facing away from the base substrate; the third conductive connecting portion is coupled to the first connecting electrode and the cathode layer, respectively; the orthographic projection of the first connecting electrode on the base substrate has an overlapping area with the orthographic projection of the electrostatic release layer on the base substrate, and in the overlapping area, the first connecting electrode and the electrostatic release layer are coupled through a via.

[0028] Optionally, an orthographic projection of the cathode layer on the base substrate and an orthographic projection of the electrostatic release layer on the base substrate have an overlapping area, and the cathode layer and the electrostatic release layer are coupled through a via in the overlapping area.

[0029] Optionally, the electrostatic release layer is made of indium tin oxide material or amorphous silicon.

[0030] Based on the technical solution of the above-mentioned display substrate, a second aspect of the present disclosure provides a display device including the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0032] FIG1 is a circuit schematic diagram of a pixel driving circuit provided by an embodiment of the present disclosure;

[0033] FIG2 is a schematic diagram of the layout of an electrostatic release layer provided in an embodiment of the present disclosure;

[0034] FIG3 shows the layout position relationship between the electrostatic release layer and the pixel driving circuit layout area according to an embodiment of the present disclosure;

[0035] FIG4 is a schematic diagram of the layout of the electrostatic release layer in FIG3 ;

[0036] FIG5 is a schematic diagram of the layout of the light shielding layer in FIG3;

[0037] FIG6 is a schematic diagram of the layout of the conductive layer in FIG3 ;

[0038] FIG7 is a schematic diagram of a first layout of an electrostatic release layer provided in an embodiment of the present disclosure;

[0039] FIG8 is a schematic diagram of a second layout of an electrostatic release layer provided in an embodiment of the present disclosure;

[0040] FIG9 is a schematic diagram of a third layout of an electrostatic release layer provided in an embodiment of the present disclosure;

[0041] FIG10 is a schematic diagram of a fourth layout of an electrostatic release layer provided in an embodiment of the present disclosure;

[0042] FIG11 is a schematic diagram of a fifth layout of an electrostatic release layer provided in an embodiment of the present disclosure;

[0043] FIG12 is a schematic diagram of a sixth layout of an electrostatic release layer provided in an embodiment of the present disclosure;

[0044] FIG13 is a schematic diagram of a first layout of two adjacent pixel driving circuits in a display substrate provided by an embodiment of the present disclosure;

[0045] FIG14 is a schematic diagram of the layout of FIG13 with the conductive layer removed;

[0046] FIG15 is an enlarged schematic diagram of portion A1 in FIG14 ;

[0047] FIG16 is a schematic diagram of the layout of the electrostatic release layer and the light shielding layer in FIG14;

[0048] FIG17 is a first cross-sectional schematic diagram of a display substrate provided by an embodiment of the present disclosure;

[0049] FIG18 is a flowchart of a manufacturing process of a structure in which a second electrode plate is coupled to a light shielding layer according to an embodiment of the present disclosure;

[0050] FIG19 is a schematic diagram of a second layout of two adjacent pixel driving circuits in a display substrate provided by an embodiment of the present disclosure;

[0051] FIG20 is an enlarged schematic diagram of the same position as portion A1 of FIG13 in FIG19;

[0052] FIG21 is a second cross-sectional schematic diagram of a display substrate provided by an embodiment of the present disclosure;

[0053] FIG22 is a third cross-sectional schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0054] FIG23 is a fourth cross-sectional schematic diagram of a display substrate provided by an embodiment of the present disclosure;

[0055] FIG24 is a flowchart of a manufacturing process of a structure in which a cathode layer and a light shielding layer are coupled, provided by an embodiment of the present disclosure;

[0056] FIG25 is a schematic diagram of a first layout of three adjacent pixel driving circuits in a display substrate provided by an embodiment of the present disclosure;

[0057] FIG26 is a schematic diagram of the layout of the light shielding layer in FIG25;

[0058] FIG27 is a fifth cross-sectional schematic diagram of a display substrate provided by an embodiment of the present disclosure;

[0059] FIG28 is a flowchart of a manufacturing process of a structure in which a second conductive connection portion is coupled to a light shielding layer according to an embodiment of the present disclosure;

[0060] FIG29 is a schematic diagram of a second layout of three adjacent pixel driving circuits in a display substrate provided by an embodiment of the present disclosure;

[0061] FIG30 is a sixth cross-sectional schematic diagram of the display substrate provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0062] In order to further illustrate the display substrate and the display device provided by the embodiments of the present disclosure, a detailed description is given below with reference to the accompanying drawings.

[0063] In order to prevent excessive static electricity from accumulating inside display products and causing circuit damage, related technologies will set up an ESD structure including a circuit structure inside the display product. However, this ESD structure is difficult to completely prevent electrostatic damage caused by ESD during processes such as die bonding.

[0064] Referring to Figures 2 to 6 and 17, an embodiment of the present disclosure provides a display substrate, including: a base substrate 10 and a plurality of pixel driving circuits arranged on the base substrate 10 (for example, located in the layout area 40 as shown in Figure 3, including a transistor structure TFT); the display substrate also includes a first-level signal input layer (for example, including a power supply layer VDD) and an electrostatic release layer 20, at least a portion of the electrostatic release layer 20 is located on the side of the pixel driving circuit facing the base substrate 10, and the electrostatic release layer 20 is coupled to the first-level signal input layer.

[0065] It should be noted that Figure 2 also illustrates the shift register unit GOA included in the display substrate, the red light-emitting element R corresponds to the position of the coupled pixel driving circuit, the green light-emitting element G corresponds to the position of the coupled pixel driving circuit, and the blue light-emitting element B corresponds to the position of the coupled pixel driving circuit.

[0066] Exemplarily, the multiple pixel driving circuits are distributed in an array on the base substrate 10. The multiple pixel driving circuits are divided into multiple rows of pixel driving circuits and multiple columns of pixel driving circuits. The multiple rows of pixel driving circuits are arranged along a first direction, and each row of pixel driving circuits includes multiple pixel driving circuits arranged along a second direction. The multiple columns of pixel driving circuits are arranged along a second direction, and each column of pixel driving circuits includes multiple pixel driving circuits arranged along the first direction. Exemplarily, the first direction and the second direction intersect. For example, the first direction includes the longitudinal direction, and the second direction includes the transverse direction.

[0067] Exemplarily, the display substrate further includes a cathode layer VSS, which can be used to transmit a negative power supply signal, but is not limited thereto. The display substrate further includes a plurality of light-emitting elements, and the light-emitting elements can be of various types. For example, each light-emitting element includes three light-emitting units, and the three light-emitting units can be selected from a red light-emitting unit, a green light-emitting unit, and a blue light-emitting unit. The light-emitting element includes a first pin and three second pins. The first pin is coupled to the cathode layer VSS, and the three second pins correspond one-to-one to the three light-emitting units. The second pins are coupled to corresponding pixel driving circuits and receive driving signals provided by the pixel driving circuits. Each light-emitting unit can be independently controlled to emit light under the drive of the corresponding pixel driving circuit. For example, each light-emitting element includes a light-emitting unit, and the light-emitting unit can be a red light-emitting unit, a green light-emitting unit, or a blue light-emitting unit. The light-emitting element includes a first pin and a second pin. The first pin is coupled to the cathode layer VSS, and the second pin is coupled to the corresponding pixel driving circuit and receives driving signals provided by the pixel driving circuit. The light-emitting unit can be independently controlled to emit light under the drive of the corresponding pixel driving circuit.

[0068] Exemplarily, the display substrate further includes a first-level signal input layer, and the first-level signal input layer is used to transmit a first-level signal with a stable potential.

[0069] Exemplarily, the display substrate further includes an electrostatic release layer 20. The electrostatic release layer 20 is made of a high-resistance material such as indium tin oxide (ITO) or amorphous silicon, but is not limited thereto. At least a portion of the electrostatic release layer 20 is located on a side of the pixel driving circuit facing the base substrate 10. The electrostatic release layer 20 can be directly or indirectly coupled to the first level signal input layer.

[0070] Exemplarily, an ITO conductive film layer is plated on the base substrate 10 , with a thickness ranging from 40 nm to 100 nm, including end values, and the ITO conductive film layer is patterned to form the electrostatic release film layer.

[0071] Based on the specific structure of the display substrate described above, the display substrate provided in the embodiments of the present disclosure includes a first-level signal input layer and an electrostatic release layer 20. At least a portion of the electrostatic release layer 20 is located on the side of the pixel drive circuit facing the base substrate 10, and the electrostatic release layer 20 is coupled to the first-level signal input layer. This configuration ensures that the electrostatic release layer 20 has the same stable first-level signal as the first-level signal input layer. The electrostatic release layer 20 can promptly conduct static electricity generated during the display substrate manufacturing process, effectively preventing ESD damage caused by side cutting, bonding, and die bonding, providing electrostatic protection and improving product yield.

[0072] Furthermore, in the display substrate provided by the embodiment of the present disclosure, the electrostatic release layer 20 is disposed on the side of the pixel drive circuit facing the base substrate 10. This arrangement facilitates shortening the distance between the light-emitting element and the corresponding pixel drive circuit, significantly reducing the difficulty of manufacturing the display substrate. Furthermore, the electrostatic release layer 20 can be manufactured during the array process used to manufacture the display substrate, eliminating the need for a separate additional process to manufacture the electrostatic release layer 20 after the array process is completed. Therefore, the display substrate provided by the embodiment of the present disclosure is relatively easy to manufacture, has a simple manufacturing process, and is conducive to reducing the manufacturing cost of the display substrate.

[0073] Furthermore, in the display substrate provided by the present embodiment, the electrostatic release layer 20 is disposed on the side of the pixel drive circuit facing the base substrate 10. This allows the electrostatic release layer 20 to enhance laser protection. During rear-side laser etching of the display substrate, the electrostatic release layer 20 can reflect some of the laser energy, reducing damage to transistors in the front-side pixel drive circuit. See the last sub-figure in Figure 18 for an illustration of laser reflection.

[0074] As shown in FIG. 13 to FIG. 18 , in some embodiments, the first level signal input layer includes a power layer VDD, and the electrostatic release layer 20 is coupled to the power layer VDD.

[0075] It should be noted that the cross-sectional view along the B1B2 direction in Figure 15 is shown as part A1 in Figure 17. The insulating layer 81 in Figure 18 includes an insulating layer GI0, a first insulating layer GI1, a second insulating layer GI2, and an interlayer insulating layer ILD.

[0076] Exemplarily, the power layer VDD is used to transmit a power signal, and the power signal has a stable potential.

[0077] As shown in Figure 17, exemplarily, the display substrate includes a light-shielding layer LS, a first insulating layer GI1, an active layer Poly, a second insulating layer GI2, a gate metal layer (for example, including the top gate Tg of the transistor structure TFT), an interlayer insulating layer ILD, a source-drain metal layer, a first passivation layer PVX1, a first flat layer PLN1, a conductive layer 50, a second passivation layer PVX2 and a second flat layer PLN2, which are stacked in sequence along a direction away from the base substrate 10.

[0078] Exemplarily, the power layer VDD and the gate metal layer are provided in the same layer and with the same material, but the present invention is not limited thereto.

[0079] Exemplarily, the first insulating layer, the active layer, the second insulating layer, the gate metal layer, the interlayer insulating layer and the source / drain metal layer are used to form the pixel driving circuit.

[0080] In the display substrate provided in the above embodiment, the first-level signal input layer includes a power layer VDD, and the electrostatic release layer 20 is coupled to the power layer VDD. This allows the existing power layer VDD, which is used to transmit stable signals, to be reused as the first-level signal transmission layer, avoiding the need for additional patterning processes. This simplifies the structure and manufacturing process of the display substrate, reducing its manufacturing cost. Furthermore, this arrangement helps reduce IR drop of the power layer VDD, thereby improving display uniformity across the display substrate.

[0081] The above-mentioned setting method enables the electrostatic release layer 20 to have a stable power signal identical to the power layer VDD. The electrostatic release layer 20 can promptly conduct the static electricity generated during the display substrate manufacturing process, effectively preventing ESD damage caused by the side, binding, and solid crystal stages, thereby playing the role of electrostatic protection and improving product yield.

[0082] As shown in FIG. 19 to FIG. 24 , in some embodiments, the first-level signal input layer includes a cathode layer VSS, and the electrostatic release layer 20 is coupled to the cathode layer VSS.

[0083] Exemplarily, the cathode layer VSS is used to transmit a negative power signal, and the negative power signal has a stable potential.

[0084] Exemplarily, the cathode layer VSS and the gate metal layer are provided in the same layer and with the same material, but the present invention is not limited thereto.

[0085] In the display substrate provided in the above embodiment, the first-level signal input layer includes a cathode layer VSS, and the electrostatic release layer 20 is coupled to the cathode layer VSS. This allows the cathode layer VSS, which is already used to transmit stable signals, to be reused as the first-level signal transmission layer, avoiding the need for additional patterning processes. This simplifies the structure and manufacturing process of the display substrate, reducing its manufacturing cost. Furthermore, this arrangement helps reduce IR drop of the cathode layer VSS and improves display uniformity across the display substrate.

[0086] The above-mentioned setting method enables the electrostatic release layer 20 to have a stable signal identical to the cathode layer VSS. The electrostatic release layer 20 can promptly conduct the static electricity generated during the display substrate manufacturing process, effectively preventing ESD damage caused by the side, binding, and solid crystal stages, playing the role of electrostatic protection and improving product yield.

[0087] In some embodiments, the first-level signal input layer includes a light-shielding layer LS, at least a portion of the light-shielding layer LS is located between the pixel driving circuit layer and the base substrate 10, the pixel driving circuit includes a plurality of transistors, the transistors include an active layer, and the orthographic projection of the light-shielding layer LS on the base substrate 10 at least partially overlaps with the orthographic projection of the active layer included in at least part of the transistors on the base substrate 10; the electrostatic release layer 20 is coupled to the light-shielding layer LS.

[0088] As shown in FIG. 17 , the light shielding layer LS may be used to form a bottom gate Bg of a transistor structure TFT, but is not limited thereto.

[0089] Exemplarily, the light-shielding layer LS includes a plurality of first light-shielding patterns and a plurality of second light-shielding patterns. The first light-shielding patterns are coupled to the power layer VDD, providing a stable power signal. The orthographic projections of the second light-shielding patterns on the base substrate 10 overlap with the orthographic projections of the channel portions of the active layer Poly on the base substrate 10. The second light-shielding patterns shield the channel portions of the transistors, thereby ensuring the stability of the transistor's characteristics.

[0090] Exemplarily, the second light-shielding pattern is multiplexed to form a bottom gate of a transistor that it blocks, and the bottom gate of the transistor is coupled to a top gate, but the present invention is not limited thereto.

[0091] Exemplarily, the electrostatic release layer 20 and the light-shielding layer LS are arranged in different layers, at least part of the electrostatic release layer 20 is located between the light-shielding layer LS and the base substrate 10, and the electrostatic release layer 20 and the light-shielding layer LS are coupled through vias; or, the electrostatic release layer 20 and the light-shielding layer LS are arranged in the same layer, and the electrostatic release layer 20 and the light-shielding layer LS are directly overlapped.

[0092] Illustratively, an overlapping area between an orthographic projection of the electrostatic release layer 20 on the base substrate 10 and an orthographic projection of the light shielding layer LS on the base substrate 10 is less than or equal to 20% of an area of ​​the electrostatic release layer 20 .

[0093] Illustratively, an overlapping area between an orthographic projection of the electrostatic release layer 20 on the base substrate 10 and an orthographic projection of the light shielding layer LS on the base substrate 10 is less than or equal to 10% of an area of ​​the electrostatic release layer 20 .

[0094] Illustratively, the overlapping area between the orthographic projection of the electrostatic release layer 20 on the base substrate 10 and the orthographic projection of the light shielding layer LS on the base substrate 10 is less than or equal to 5% of the area of ​​the electrostatic release layer 20 .

[0095] In the display substrate provided in the above embodiment, the first-level signal input layer includes a light-shielding layer LS, and the electrostatic release layer 20 is coupled to the light-shielding layer LS. This allows the existing light-shielding layer LS, which is used to transmit stable signals, to be reused as the first-level signal transmission layer, avoiding the need for additional patterning processes. This simplifies the structure and manufacturing process of the display substrate, reducing its manufacturing cost. Furthermore, this arrangement helps reduce the IR drop of the power layer VDD and improves display uniformity across the display substrate.

[0096] The above-mentioned setting method enables the electrostatic release layer 20 to have the same stable signal as the light-shielding layer LS. The electrostatic release layer 20 can promptly conduct the static electricity generated during the display substrate manufacturing process, effectively prevent ESD damage caused by the side, binding, and solid crystal stages, play the role of electrostatic protection, and improve product yield.

[0097] The above-mentioned setting method ensures that the electrostatic release layer 20 is coupled with the light-shielding layer LS, while minimizing the overlapping area between the orthographic projection of the electrostatic release layer 20 on the base substrate 10 and the orthographic projection of the light-shielding layer LS on the base substrate 10, so that the electrostatic release layer 20 can avoid the light-shielding layer LS over a large area, thereby avoiding the damage to the film formation of the light-shielding layer LS due to the presence of the electrostatic release layer 20.

[0098] As shown in Figures 3 to 5, in some embodiments, the display substrate further includes a light-shielding layer LS, at least a portion of which is located between the pixel driving circuit layer and the base substrate 10; the orthographic projection of the electrostatic release layer 20 on the base substrate 10 does not overlap with the orthographic projection of the light-shielding layer LS on the base substrate 10.

[0099] The above configuration enables the electrostatic release layer 20 to completely avoid the light shielding layer LS, thereby preventing the existence of the electrostatic release layer 20 from damaging the film formation of the light shielding layer LS.

[0100] As shown in FIG13 , FIG14 and FIG16 , in some embodiments, the display substrate includes a power layer VDD and a cathode layer VSS; the power layer VDD includes a plurality of power lines arranged along a first direction (one power line is illustrated in FIG14 ), each power line including at least a portion extending along a second direction, the first direction intersecting the second direction; the cathode layer VSS includes a plurality of cathode lines arranged along the first direction (one cathode line is illustrated in FIG14 ), each cathode line including at least a portion extending along the second direction;

[0101] The electrostatic release layer 20 is formed in a grid shape, and includes a plurality of first grid portions 201 extending along a first direction, and a plurality of second grid portions 202 extending along a second direction; the orthographic projection of at least one of the second grid portions 202 on the base substrate 10 at least partially overlaps with the orthographic projection of the power line on the base substrate 10; and / or the orthographic projection of at least one of the second grid portions 202 on the base substrate 10 at least partially overlaps with the orthographic projection of the cathode line on the base substrate 10.

[0102] Exemplarily, the power lines and the cathode lines are alternately arranged along the first direction.

[0103] Illustratively, the electrostatic release layer 20 includes a plurality of first grid portions 201 extending along a first direction, and a plurality of second grid portions 202 extending along a second direction. The first grid portions 201 and the second grid portions 202 are coupled to define a grid structure.

[0104] Exemplarily, the length of the second grid portion 202 is smaller than the length of the first grid portion 201 , but is not limited thereto.

[0105] The above-mentioned setting of at least one second grid portion 202 on the base substrate 10 has an orthographic projection that at least partially overlaps with the orthographic projection of the power line on the base substrate 10; and / or, the orthographic projection of at least one second grid portion 202 on the base substrate 10 at least partially overlaps with the orthographic projection of the cathode line on the base substrate 10; is conducive to achieving the coupling of the electrostatic release layer 20 with the power layer VDD or the cathode layer VSS, and reducing the difficulty of coupling between the electrostatic release layer 20 and the power layer VDD or the cathode layer VSS.

[0106] The above-mentioned electrostatic release layer 20 is formed into a grid shape, which is conducive to gathering the static electricity generated during the display substrate manufacturing process and conducting the static electricity in time, effectively preventing ESD damage caused by the side, binding, and solid crystal stages, playing the role of electrostatic protection and improving product yield.

[0107] As shown in Figures 13 to 16, in some embodiments, the display substrate includes a plurality of clock signal lines HF arranged along the second direction, the clock signal line HF includes at least a portion extending along the first direction, and the pixel driving circuit is coupled to the corresponding clock signal line HF; the orthographic projection of the first grid portion 201 on the base substrate 10 at least partially overlaps with the orthographic projection of the clock signal line HF on the base substrate 10.

[0108] Exemplarily, the display substrate further includes a plurality of data lines Data, the plurality of data lines Data are arranged along the second direction, the data lines Data include at least a portion extending along the first direction, and the pixel driving circuit is coupled to the corresponding data lines Data.

[0109] Exemplarily, the orthographic projection of the first grid portion 201 on the base substrate 10 at least partially overlaps with the orthographic projection of the clock signal line HF on the base substrate 10; and / or, the orthographic projection of the first grid portion 201 on the base substrate 10 at least partially overlaps with the orthographic projection of the data line Data on the base substrate 10.

[0110] The above configuration is beneficial to improving the stability of the signals transmitted by the clock signal line HF and the data line Data.

[0111] As shown in Figures 8 and 11, in some embodiments, the electrostatic release layer 20 includes a plurality of first openings K1, and the orthographic projection of the boundary of the first opening K1 on the base substrate 10 includes a curved edge portion; the orthographic projection of the first opening K1 on the base substrate 10 at least partially overlaps with the orthographic projection of the pixel driving circuit on the base substrate 10.

[0112] Exemplarily, the curved edge portion is in a circular or elliptical shape, but is not limited thereto.

[0113] In the display substrate provided by the above embodiment, by setting the orthographic projection of the boundary of the first opening K1 on the base substrate 10 to include a curved edge portion, the first opening K1 can be formed into an opening with a smooth boundary similar to a circle or an ellipse. This opening is not easy to accumulate static electricity. In this way, by setting the orthographic projection of the first opening K1 on the base substrate 10 to at least partially overlap with the orthographic projection of the pixel driving circuit on the base substrate 10, it is possible to avoid static electricity from accumulating in the area where the pixel driving circuit is located, causing the pixel driving circuit to directly release static electricity to the static electricity release layer 20, thereby affecting the working stability of the pixel driving circuit and ensuring the yield of the pixel driving circuit.

[0114] As shown in Figures 4, 7, 9, 10 and 12, in some embodiments, the electrostatic release layer 20 includes a plurality of second openings K2, and the orthographic projection of the boundary of the second opening K2 on the base substrate 10 includes a straight edge; the orthographic projection of the second opening K2 on the base substrate 10 does not overlap with the orthographic projection of the pixel driving circuit on the base substrate 10.

[0115] Exemplarily, the orthographic projection of the boundary of the second opening K2 on the base substrate 10 includes a triangle, a rectangle, or other polygons with straight sides, but is not limited thereto.

[0116] As shown in FIG. 9 and FIG. 12 , illustratively, the orthographic projection of the boundary of the second opening K2 on the base substrate 10 includes at least one sawtooth portion 203 , that is, the second opening K2 includes an opening having a sawtooth shape.

[0117] In the display substrate provided by the above embodiment, by setting the orthographic projection of the boundary of the second opening K2 on the base substrate 10 to include a straight edge, the second opening K2 can be formed as an opening with a sharp corner, which is easy to accumulate static electricity. In this way, by setting the orthographic projection of the second opening K2 on the base substrate 10 to not overlap with the orthographic projection of the pixel driving circuit on the base substrate 10, the orthographic projection of the second opening K2 on the base substrate 10 at least partially overlaps with the orthographic projection of the peripheral area of ​​the pixel driving circuit, so that the second opening K2 can attract static electricity in the peripheral area and conduct the static electricity, thereby ensuring the yield of the display substrate.

[0118] As shown in FIG13 to FIG18 , in some embodiments, the pixel driving circuit includes a driving transistor (i.e., a third transistor M3) and a storage capacitor Cs, wherein a first plate Cs1 of the storage capacitor Cs is coupled to the gate of the driving transistor, and a second plate Cs2 of the storage capacitor Cs is coupled to the power supply layer VDD;

[0119] The orthographic projection of the second electrode plate Cs2 on the base substrate 10 overlaps with the orthographic projection of the electrostatic release layer 20 on the base substrate 10. In this overlapping region, the second electrode plate Cs2 is coupled to the electrostatic release layer 20 via via Via3. Simultaneously, the second electrode plate Cs2 is coupled to the power layer VDD via via Via1 and to the light shielding layer LS via via Via2.

[0120] Exemplarily, the second electrode Cs2 is provided in the same layer and with the same material as the source / drain metal layer, but is not limited thereto.

[0121] As shown in Figure 17, exemplarily, there is a first light-shielding pattern (such as the mark LS) between the second electrode Cs2 and the base substrate 10, and there is an electrostatic release layer 20 between the first light-shielding pattern and the base substrate 10. The orthographic projection of the second electrode Cs2 on the base substrate 10 and the orthographic projection of the electrostatic release layer 20 on the base substrate 10 have an overlapping area, and at least a part of the first light-shielding pattern is located in the overlapping area. In the overlapping area, the second electrode and the electrostatic release layer 20 are coupled through a via Via3, and the via Via3 can penetrate the first light-shielding pattern located in the overlapping area.

[0122] The above configuration eliminates the need to change the layout of the pixel driving circuit and the light shielding layer LS. Instead, the electrostatic release layer 20 only needs to be fabricated at a designated location. This helps reduce the overall layout difficulty of the display substrate, simplifies the fabrication process, and saves fabrication costs.

[0123] In some embodiments, the display substrate further includes a first conductive connection portion, the first conductive connection portion is coupled to the power line, and at least a portion of the first conductive connection portion is located on a side of the power line facing away from the base substrate 10;

[0124] The orthographic projection of the first conductive connection portion on the base substrate 10 and the orthographic projection of the electrostatic release layer 20 on the base substrate 10 have an overlapping area, and the first conductive connection portion and the electrostatic release layer 20 are coupled through a via in the overlapping area.

[0125] Exemplarily, the first conductive connection portion is provided in the same layer and material as the source / drain metal layer, but is not limited thereto. This arrangement facilitates shortening the distance between the first conductive connection portion and the electrostatic release layer 20, reducing the difficulty of fabricating the vias connecting the first conductive connection portion and the electrostatic release layer 20, and is applicable to both large and small pixel driving circuits.

[0126] For example, the thickness of the electrostatic release layer 20 and the size of the opening formed therein can be determined according to the ESD protection capability and the upper and lower relationship with the source and drain metal layers.

[0127] In the display substrate provided by the above embodiment, the coupling between the electrostatic release layer 20 and the power line is achieved by providing a first conductive connection portion, which can more flexibly arrange the position of the electrostatic release layer 20 and reduce the layout difficulty of the display substrate.

[0128] As shown in Figures 25 to 28, in some embodiments, the display substrate further includes a first conductive connection portion and a second conductive connection portion 62, at least a portion of the second conductive connection portion 62 is located on the side of the first conductive connection portion facing away from the base substrate 10; the first conductive connection portion is coupled to the second conductive connection portion 62 and the power supply layer, respectively; the orthographic projection of the second conductive connection portion 62 on the base substrate 10 has an overlapping area with the orthographic projection of the electrostatic release layer 20 on the base substrate 10, and in this overlapping area, the second conductive connection portion 62 is coupled to the electrostatic release layer 20 through a via Via5.

[0129] As shown in FIG28 , illustratively, the second conductive connection portion 62 is provided in the same layer and material as the conductive layer 50, but is not limited thereto. In this arrangement, the second conductive connection portion 62 is relatively far from the electrostatic release layer 20, and the via hole Via5 for connecting the second conductive connection portion 62 and the electrostatic release layer 20 has a relatively deep depth. The via hole Via5 penetrates the insulating layer 83 (including the insulating layer GI0, the first insulating layer GI1, the second insulating layer GI2, and the interlayer insulating layer ILD) between the electrostatic release layer 20 and the light shielding layer LS, the first passivation layer PVX1, and the first planar layer PLN1.

[0130] In the display substrate provided by the above embodiment, the coupling between the electrostatic release layer 20 and the power line is achieved by providing the second conductive connection portion 62 , which enables a more flexible layout of the electrostatic release layer 20 and reduces the layout difficulty of the display substrate.

[0131] As shown in FIG23 , in some embodiments, the display substrate further includes a third conductive connection portion 63 , wherein the third conductive connection portion 63 is coupled to the cathode layer VSS, and at least a portion of the third conductive connection portion 63 is located on a side of the cathode layer VSS facing away from the base substrate 10 ;

[0132] The orthographic projection of the third conductive connection portion 63 on the base substrate 10 and the orthographic projection of the electrostatic release layer 20 on the base substrate 10 have an overlapping area, and the third conductive connection portion 63 and the electrostatic release layer 20 are coupled through the via Via7 in the overlapping area.

[0133] Exemplarily, the third conductive connection portion 63 is provided in the same layer and material as the source / drain metal layer, but is not limited thereto. This arrangement facilitates shortening the distance between the third conductive connection portion 63 and the electrostatic release layer 20, reducing the difficulty of fabricating the vias connecting the third conductive connection portion 63 and the electrostatic release layer 20, and is applicable to both large and small pixel driving circuits.

[0134] In the display substrate provided by the above embodiment, the coupling between the electrostatic release layer 20 and the cathode layer VSS is achieved by providing the third conductive connection portion 63 , which enables a more flexible layout of the electrostatic release layer 20 and reduces the layout difficulty of the display substrate.

[0135] As shown in Figures 29 and 30, in some embodiments, the display substrate further includes a first connecting electrode 71 and a third conductive connecting portion 63, at least a portion of the first connecting electrode 71 is located on the side of the third conductive connecting portion 63 facing away from the base substrate 10; the third conductive connecting portion 63 is coupled to the first connecting electrode 71 and the cathode layer VSS, respectively; the orthographic projection of the first connecting electrode 71 on the base substrate 10 has an overlapping area with the orthographic projection of the electrostatic release layer 20 on the base substrate 10, and in this overlapping area, the first connecting electrode 71 and the electrostatic release layer 20 are coupled through the via Via6.

[0136] Exemplarily, the first connection electrode 71 and the conductive layer 50 are provided in the same layer and material, but the present invention is not limited thereto. In this configuration, the first connection electrode 71 is relatively far from the electrostatic release layer 20, and the via hole connecting the first connection electrode 71 and the electrostatic release layer 20 has a relatively deep depth. The via hole penetrates the insulating layer between the electrostatic release layer 20 and the light shielding layer LS, the first insulating layer, the second insulating layer, the interlayer insulating layer, the first passivation layer, and the first planarization layer.

[0137] In the display substrate provided by the above embodiment, the coupling between the electrostatic release layer 20 and the power line is achieved by providing the first connection electrode 71 , which enables a more flexible layout of the electrostatic release layer 20 and reduces the layout difficulty of the display substrate.

[0138] As shown in Figures 19, 22 and 24, in some embodiments, the orthographic projection of the cathode layer VSS on the base substrate 10 and the orthographic projection of the electrostatic release layer 20 on the base substrate 10 have an overlapping area (such as part A2), and in this overlapping area, the cathode layer VSS and the electrostatic release layer 20 are coupled through via Via4.

[0139] It should be noted that Figure 20 is an enlarged schematic diagram of the same location in Figure 19 as portion A1 in Figure 13 , and Figure 20 does not include the conductive layer. In this embodiment, the cross-sectional view along the B1B2 direction in Figure 20 is shown as portion A3 in Figure 21 . It can be seen that in this embodiment, the second electrode plate Cs2 is not coupled to the electrostatic release layer 20.

[0140] It should be noted that the cross-sectional view of the portion A2 in Figure 19 refers to the portion A2 in Figure 22. In Figure 24, the insulating layer 82 includes an insulating layer GI0, a first insulating layer GI1, and a second insulating layer GI2.

[0141] The above configuration eliminates the need to change the layout of the pixel driving circuit and the light shielding layer LS. Instead, the electrostatic release layer 20 only needs to be fabricated at a designated location. This helps reduce the overall layout difficulty of the display substrate, simplifies the fabrication process, and saves fabrication costs.

[0142] As shown in Figures 19 and 21, in some embodiments, the display substrate also includes a cathode layer VSS, multiple first connecting electrodes 71, multiple second connecting electrodes 72 and multiple light-emitting elements; the first connecting electrode 71 is coupled to the cathode layer VSS; the second connecting electrode 72 is coupled to the corresponding pixel driving circuit; the light-emitting element includes a first pin and at least one second pin, the first pin is coupled to the corresponding first connecting electrode 71, and the second pin is coupled to the corresponding second connecting electrode 72.

[0143] Exemplarily, each light-emitting element includes three light-emitting units, which may be a red light-emitting unit, a green light-emitting unit, and a blue light-emitting unit. The light-emitting element includes a first pin and three second pins. The first pin is coupled to the cathode layer VSS. The three second pins correspond one-to-one to the three light-emitting units. The second pins are coupled to corresponding pixel driving circuits to receive driving signals provided by the pixel driving circuits. Each light-emitting unit can be independently controlled to emit light under the drive of the corresponding pixel driving circuit.

[0144] The specific structure of the pixel driving circuit is varied, for example: 7T1C (i.e., 7 transistors and 1 capacitor), 8T1C (i.e., 8 transistors and 1 capacitor), 11T3C (i.e., 11 transistors and 3 capacitors), etc. The following description will take the pixel driving circuit using 11T3C as an example.

[0145] As shown in Figures 1 and 14, the pixel driving circuit includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a storage capacitor Cs, a first capacitor C1, and a second capacitor C2. The ITO shown in Figure 1 represents an electrostatic release layer 20 coupled to the power supply layer VDD.

[0146] The display substrate further includes: a plurality of light emitting control signal lines EM, a plurality of scan lines Gate, a plurality of data lines Data, a plurality of first reset signal lines RST_A, a plurality of second reset signal lines RST_B, a plurality of initialization signal lines Vinit, and a plurality of clock signal lines HF.

[0147] A gate of the first transistor M1 is coupled to the corresponding first reset signal line RST_ARST_A, a first electrode of the first transistor M1 is coupled to the initialization signal line Vinit, and a second electrode of the first transistor M1 is coupled to the gate of the third transistor M3.

[0148] A gate of the second transistor M2 is coupled to the scan line Gate, a first electrode of the second transistor M2 is coupled to a second electrode of the third transistor M3 , and a second electrode of the second transistor M2 is coupled to a gate of the third transistor M3 .

[0149] A gate of the fourth transistor M4 is coupled to the scan line Gate, a first electrode of the fourth transistor M4 is coupled to the corresponding data line Data, and a second electrode of the fourth transistor M4 is coupled to the first electrode of the third transistor M3.

[0150] A gate of the fifth transistor M5 is coupled to the corresponding light emitting control signal line EM, a first electrode of the fifth transistor M5 is coupled to the power line, and a second electrode of the fifth transistor M5 is coupled to the first electrode of the third transistor M3.

[0151] A first electrode of the sixth transistor M6 is coupled to the second electrode of the third transistor M3 , and a second electrode of the sixth transistor M6 is coupled to the corresponding second pin.

[0152] A gate of the seventh transistor is coupled to the corresponding first reset signal line RST_A, a first electrode of the seventh transistor is coupled to the initialization signal line Vinit, and a second electrode of the seventh transistor is coupled to the corresponding second pin.

[0153] A gate of the eighth transistor M8 is coupled to the corresponding first reset signal line RST_A, a first electrode of the eighth transistor M8 is coupled to the corresponding data line Data, and a second electrode of the eighth transistor M8 is coupled to the gate of the ninth transistor M9.

[0154] A first electrode of the ninth transistor M9 is coupled to the corresponding light emitting control signal line EM, and a second electrode of the ninth transistor M9 is coupled to the gate of the sixth transistor M6.

[0155] A gate of the tenth transistor M10 is coupled to the corresponding second reset signal line RST_B, a first electrode of the tenth transistor M10 is coupled to the corresponding data line Data, and a second electrode of the tenth transistor M10 is coupled to the gate of the eleventh transistor M11.

[0156] A first electrode of the eleventh transistor M11 is coupled to the corresponding clock signal line HF, and a second electrode of the eleventh transistor M11 is coupled to the gate of the sixth transistor M6.

[0157] The first capacitor C1 is coupled to the initialization signal line Vinit and the gate of the ninth transistor M9 , respectively. The second capacitor C2 is coupled to the initialization signal line Vinit and the gate of the eleventh transistor M11 , respectively.

[0158] Exemplarily, each transistor in the pixel driving circuit comprises a low-temperature polysilicon transistor. The display substrate comprises a low-temperature polysilicon display substrate, and adopts COG (chip on glass) packaging technology, but is not limited thereto.

[0159] An embodiment of the present disclosure further provides a display device, comprising the display substrate according to any one of claims 1 to 19.

[0160] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane.

[0161] The display substrate provided in the above embodiment includes a first-level signal input layer and an electrostatic release layer. At least a portion of the electrostatic release layer is located on the side of the pixel drive circuit facing the base substrate, and the electrostatic release layer is coupled to the first-level signal input layer. This arrangement ensures that the electrostatic release layer has the same stable first-level signal as the first-level signal input layer. The electrostatic release layer can promptly dissipate static electricity generated during the display substrate manufacturing process, effectively preventing ESD damage during the side, bonding, and die bonding stages, providing electrostatic protection and improving product yield.

[0162] Furthermore, in the display substrate provided in the above embodiment, the electrostatic release layer is disposed on the side of the pixel drive circuit facing the base substrate. This arrangement facilitates shortening the distance between the light-emitting element and the corresponding pixel drive circuit, significantly reducing the difficulty of manufacturing the display substrate. Furthermore, the electrostatic release layer can be manufactured during the array process used to manufacture the display substrate, eliminating the need for a separate process to manufacture the electrostatic release layer after the array process. Therefore, the display substrate provided in the above embodiment is relatively easy to manufacture and has a simple manufacturing process, which helps reduce the manufacturing cost of the display substrate.

[0163] In addition, in the display substrate provided in the above embodiment, the electrostatic release layer is arranged on the side of the pixel driving circuit facing the base substrate, so that the electrostatic release layer can enhance the protection against laser and reduce the damage to the transistors in the front pixel driving circuit when the display substrate is laser-etched on the back.

[0164] The display device provided by the embodiment of the present disclosure also has the above-mentioned beneficial effects when it includes the above-mentioned display substrate, which will not be described in detail here.

[0165] It should be noted that the signal line extending along the X-direction means that the signal line includes a main portion and a secondary portion connected to the main portion, the main portion is a line, a line segment, or a strip-shaped body, the main portion extends along the X-direction, and the length of the main portion extending along the X-direction is greater than the length of the secondary portion extending along other directions.

[0166] It should be noted that the "same layer" in the embodiment of the present disclosure may refer to a film layer on the same structural layer. Or, for example, a film layer in the same layer may be a film layer formed by using the same film forming process to form a specific pattern, and then patterning the film layer using the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0167] In the various method embodiments of the present disclosure, the serial numbers of the steps cannot be used to limit the order of the steps. For ordinary technicians in this field, without paying any creative work, changes to the order of the steps are also within the scope of protection of the present disclosure.

[0168] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the product embodiments. For relevant parts, refer to the description of the product embodiments.

[0169] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect", "couple" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0170] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0171] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0172] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate, comprising: A base substrate and a plurality of pixel driving circuits disposed on the base substrate; The display substrate further includes a first level signal input layer and an electrostatic release layer. At least a portion of the electrostatic release layer is located on a side of the pixel driving circuit facing the base substrate. The electrostatic release layer is coupled to the first level signal input layer.

2. The display substrate according to claim 1, wherein: The first level signal input layer includes a power layer, and the electrostatic release layer is coupled to the power layer.

3. The display substrate according to claim 1, wherein: The first level signal input layer includes a cathode layer, and the electrostatic release layer is coupled to the cathode layer.

4. The display substrate according to claim 1, wherein: The first level signal input layer includes a light shielding layer, at least part of the light shielding layer is located between the pixel driving circuit layer and the base substrate, the pixel driving circuit includes a plurality of transistors, the transistors include an active layer, and an orthographic projection of the light shielding layer on the base substrate at least partially overlaps with an orthographic projection of the active layer included in at least part of the transistors on the base substrate; The electrostatic release layer is coupled to the light shielding layer.

5. The display substrate according to claim 4, wherein: At least part of the electrostatic release layer is located between the light shielding layer and the base substrate, and the electrostatic release layer and the light shielding layer are coupled through a via; or, the electrostatic release layer and the light shielding layer are arranged in the same layer, and the electrostatic release layer and the light shielding layer are directly overlapped.

6. The display substrate according to claim 4, wherein: An overlapping area between an orthographic projection of the electrostatic release layer on the base substrate and an orthographic projection of the light shielding layer on the base substrate is less than or equal to 10% of an area of ​​the electrostatic release layer.

7. The display substrate according to claim 1, wherein: The display substrate further includes a light shielding layer, at least part of which is located between the pixel driving circuit layer and the base substrate; the orthographic projection of the electrostatic release layer on the base substrate does not overlap with the orthographic projection of the light shielding layer on the base substrate.

8. The display substrate according to claim 1, wherein: The display substrate comprises a power layer and a cathode layer; the power layer comprises a plurality of power lines arranged along a first direction, the power lines comprise at least a portion extending along a second direction, the first direction intersecting the second direction; the cathode layer comprises a plurality of cathode lines arranged along the first direction, the cathode lines comprise at least a portion extending along the second direction; The electrostatic release layer is formed in a grid shape, and the electrostatic release layer includes a plurality of first grid portions extending along a first direction, and a plurality of second grid portions extending along a second direction; An orthographic projection of at least one of the second grid portions on the base substrate at least partially overlaps with an orthographic projection of the power line on the base substrate; And / or, an orthographic projection of at least one of the second grid portions on the base substrate at least partially overlaps with an orthographic projection of the cathode line on the base substrate.

9. The display substrate according to claim 8, wherein: The display substrate includes a plurality of clock signal lines arranged along a second direction, the clock signal lines include at least a portion extending along the first direction, and the pixel driving circuit is coupled to the corresponding clock signal lines; the orthographic projection of the first grid portion on the base substrate at least partially overlaps with the orthographic projection of the clock signal lines on the base substrate.

10. The display substrate according to any one of claims 1 to 9, wherein: The electrostatic release layer includes a plurality of first openings, and the orthographic projection of the boundaries of the first openings on the base substrate includes a curved edge portion; the orthographic projection of the first openings on the base substrate at least partially overlaps with the orthographic projection of the pixel driving circuit on the base substrate.

11. The display substrate according to any one of claims 1 to 9, wherein: The electrostatic release layer includes a plurality of second openings, the orthographic projection of the boundaries of the second openings on the base substrate includes a straight edge portion; the orthographic projection of the second openings on the base substrate does not overlap with the orthographic projection of the pixel driving circuit on the base substrate.

12. The display substrate according to claim 11, wherein: An orthographic projection of a boundary of the second opening on the base substrate includes at least one sawtooth portion.

13. The display substrate according to claim 2, wherein: The pixel driving circuit comprises a driving transistor and a storage capacitor, wherein a first plate of the storage capacitor is coupled to a gate of the driving transistor, and a second plate of the storage capacitor is coupled to the power supply layer; The orthographic projection of the second electrode plate on the base substrate has an overlapping area with the orthographic projection of the electrostatic release layer on the base substrate, and the second electrode plate and the electrostatic release layer are coupled through a via in the overlapping area.

14. The display substrate according to claim 2, wherein: The display substrate further comprises a first conductive connection portion, the first conductive connection portion is coupled to the power line, and at least a portion of the first conductive connection portion is located on a side of the power line facing away from the base substrate; The orthographic projection of the first conductive connection portion on the base substrate has an overlapping area with the orthographic projection of the electrostatic release layer on the base substrate, and the first conductive connection portion is coupled to the electrostatic release layer through a via in the overlapping area.

15. The display substrate according to claim 2, wherein: The display substrate also includes a first conductive connection portion and a second conductive connection portion, at least a portion of the second conductive connection portion is located on a side of the first conductive connection portion that is away from the base substrate; the first conductive connection portion is coupled to the second conductive connection portion and the power supply layer, respectively; the orthographic projection of the second conductive connection portion on the base substrate has an overlapping area with the orthographic projection of the electrostatic release layer on the base substrate, and in the overlapping area, the second conductive connection portion is coupled to the electrostatic release layer through a via.

16. The display substrate according to claim 3, wherein: The display substrate further comprises a third conductive connection portion, the third conductive connection portion is coupled to the cathode layer, and at least a portion of the third conductive connection portion is located on a side of the cathode layer facing away from the base substrate; The orthographic projection of the third conductive connection portion on the base substrate has an overlapping area with the orthographic projection of the electrostatic release layer on the base substrate, and the third conductive connection portion is coupled to the electrostatic release layer through a via in the overlapping area.

17. The display substrate according to claim 3, wherein: The display substrate also includes a first connecting electrode and a third conductive connecting portion, at least a portion of the first connecting electrode is located on a side of the third conductive connecting portion that is away from the base substrate; the third conductive connecting portion is coupled to the first connecting electrode and the cathode layer, respectively; the orthographic projection of the first connecting electrode on the base substrate has an overlapping area with the orthographic projection of the electrostatic release layer on the base substrate, and in the overlapping area, the first connecting electrode is coupled to the electrostatic release layer through a via.

18. The display substrate according to claim 3, wherein: The orthographic projection of the cathode layer on the base substrate has an overlapping area with the orthographic projection of the electrostatic release layer on the base substrate, and the cathode layer and the electrostatic release layer are coupled through a via in the overlapping area.

19. The display substrate according to claim 1, wherein: The electrostatic release layer is made of indium tin oxide material or amorphous silicon.

20. A display device comprising the display substrate according to any one of claims 1 to 19.

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