Array substrate, display panel and manufacturing method of array substrate

Abstract

The invention discloses an array substrate, a display panel and a manufacturing method of the array substrate, and belongs to the technical field of display. In the array substrate, in first electrodes and second electrodes of a thin film transistor, the first electrode with higher voltage is arranged between an active layer and a substrate by adopting a lower lap joint structure, and the second electrode with lower voltage is arranged on a first insulating layer by adopting an upper lap joint structure, or the lower lap joint structure is arranged below the first insulating layer; the upper lap joint structure can avoid the situation that the thin film transistor cannot work normally due to the fact that the resistance of the end, located at the second electrode, of the thin film transistor is too large, and the lower lap joint structure can avoid the risk that when the active layer makes contact with the electrode through the via hole, the active layer is prone to being damaged at the via hole. In this way, the problem that the performance of the array substrate is poor in the prior art is solved, and the effect of improving the performance of the array substrate is achieved.

Description

Array substrate, display panel, and method for manufacturing array substrate Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate, a display panel, and a method for manufacturing the array substrate. Background Art

[0002] A display panel is a device that can realize a display function. The display panel includes an array substrate and a display structure. The array substrate is used to control the display structure.

[0003] The current array substrate includes a substrate and a plurality of thin film transistors (TFTs) arranged in an array on the substrate. The thin film transistor includes a source and a drain located on the substrate, a buffer layer covering the source and the drain, an active layer arranged on the buffer layer, a gate insulating layer covering the active layer, and a gate located on the gate insulating layer. The active layer is disconnected from the source and the drain through vias in the buffer layer. The gate can control the active layer so that the source and the drain are conductive through the active layer.

[0004] However, in some cases, the source and drain of the thin film transistor may not be conductive, resulting in poor performance of the array substrate.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide an array substrate, a display panel, and a method for manufacturing the array substrate. The technical solution is as follows:

[0007] According to a first aspect of the present application, an array substrate is provided.

[0008] The array substrate includes a substrate and a plurality of transistors located on the substrate, wherein the transistors include:

[0009] a first electrode, the first electrode being located on the substrate;

[0010] an active layer, the active layer being located on the substrate provided with the first electrode, and the active layer at least covering a partial region of the first electrode;

[0011] a first insulating layer, the first insulating layer being located on a side of the active layer away from the substrate, the first insulating layer having a second polarity opening, an orthographic projection of the second polarity opening on the substrate and an orthographic projection of the active layer on the substrate forming a first overlapping region;

[0012] a gate, the gate being located on a side of the first insulating layer away from the substrate, the gate being located on the first insulating layer, and an orthographic projection of the gate on the substrate and an orthographic projection of the active layer on the substrate having a second overlapping region;

[0013] a second electrode, the second electrode being located on a side of the first insulating layer away from the substrate, or the second electrode being located on a side of the first insulating layer close to the substrate;

[0014] The orthographic projection of the second electrode opening on the substrate overlaps with the orthographic projection of the second electrode on the substrate. The second electrode contacts the active layer. When the transistor is working, the voltage of the first electrode is greater than the voltage of the second electrode.

[0015] Optionally, when the second electrode is located on a side of the first insulating layer away from the substrate, the second electrode contacts the active layer through the second electrode opening, the first insulating layer further includes a first electrode opening, an orthographic projection of the first electrode opening on the substrate and an orthographic projection of the active layer on the substrate form a third overlapping region, and the third overlapping region overlaps with the first electrode;

[0016] The first insulating layer includes a gate insulating layer located between the first electrode opening and the second electrode opening, and the orthographic projection of the edge of the first electrode covered by the active layer on the substrate is located in the orthographic projection of the gate insulating layer on the substrate.

[0017] Optionally, a first distance in a first direction between an edge of the gate insulating layer at the first electrode opening and the gate is positively correlated with the mobility of the active layer, and the first direction is an arrangement direction of the first electrode opening and the second electrode opening;

[0018] A second distance between an edge of the gate insulating layer at the second electrode opening and the gate in the first direction is positively correlated with the mobility of the active layer.

[0019] Optionally, the first distance ranges from 2 microns to 4 microns, and the second distance ranges from 2 microns to 4 microns.

[0020] Optionally, the array substrate includes a buffer layer located between the first electrode and the substrate, and the first electrode and the active layer are both arranged on the buffer layer.

[0021] Optionally, the multiple transistors include multiple driving transistors and multiple switching transistors, the multiple driving transistors include a first driving transistor, and the multiple switching transistors include a first switching transistor;

[0022] The width of the gate insulation layer of the first switch transistor in a first direction is greater than the width of the gate insulation layer of the first drive transistor in the first direction. The first direction is an arrangement direction of the first electrode openings and the second electrode openings.

[0023] Optionally, a first distance in a first direction between an edge of the gate insulation layer at the first pole opening and the gate is greater than a second distance in the first direction between an edge of the gate insulation layer at the second pole opening and the gate, and the first direction is the arrangement direction of the first pole opening and the second pole opening.

[0024] Optionally, a width of the first pole opening in the first direction is greater than a width of the second pole opening in the first direction.

[0025] Optionally, the active layer includes a first end portion, a connecting portion, and a second end portion, and the connecting portion is connected to the first end portion and the second end portion respectively;

[0026] The orthographic projection of the first end portion on the substrate is located in the orthographic projection of the first electrode on the substrate, and the orthographic projection of the second end portion on the substrate is located in the orthographic projection of the second electrode on the substrate. In the second direction, the width of at least one of the first end portion and the second end portion in the second direction is greater than the width of the connecting portion in the second direction, and the second direction is a direction perpendicular to the arrangement direction of the first pole opening and the second pole opening.

[0027] Optionally, the second electrode covers an edge of the second electrode opening away from the gate, and a distance exists between the second electrode and an edge of the second electrode opening close to the gate.

[0028] Optionally, the transistor further includes a first conductive block, the first conductive block is located on the substrate, the active layer overlaps the first conductive block, and an orthographic projection of the first conductive block on the substrate overlaps with the first overlapping region.

[0029] Optionally, the second electrode covers the second pole opening, and the orthographic projection of the second pole opening on the substrate is located in the orthographic projection of the second electrode on the substrate.

[0030] Optionally, the first conductive block and the first electrode are in the same layer structure.

[0031] Optionally, the array substrate further includes a buffer layer, the buffer layer is located between the active layer and the first electrode, the buffer layer has a buffer layer opening, and the partial area of ​​the first electrode is exposed at the buffer layer opening;

[0032] The active layer covers the buffer layer opening and covers the partial area of ​​the first electrode in the buffer layer opening;

[0033] The first insulating layer covers the climbing portion of the active layer, and the climbing portion of the active layer is a portion of the active layer covering the hole wall of the buffer layer opening.

[0034] Optionally, the distance between the second electrode and the gate is in a range of 2 microns to 3 microns.

[0035] Optionally, the transistor further includes a second conductive block, the second conductive block and the first electrode are in the same layer structure, and an orthographic projection of the second conductive block on the substrate overlaps with the first overlapping region.

[0036] Optionally, the transistor satisfies: L+2*T≥7;

[0037] Wherein, L is equal to the width of the gate in the first direction, T is equal to the first distance between the edge of the gate insulation layer at the first pole opening and the gate, and T is equal to the second distance between the edge of the gate insulation layer at the second pole opening and the gate.

[0038] Optionally, the mobility of the active layer is greater than or equal to 20 square centimeters per volt per second.

[0039] Optionally, the active layer is made of indium gallium zinc oxide and has a thickness ranging from 300 angstroms to 500 angstroms.

[0040] According to another aspect of an embodiment of the present application, a display panel is provided, comprising the above-mentioned array substrate.

[0041] According to another aspect of an embodiment of the present application, a method for manufacturing an array substrate is provided, the method comprising:

[0042] obtaining a substrate;

[0043] A plurality of transistors are fabricated on the substrate, the transistors comprising:

[0044] a first electrode, the first electrode being located on the substrate;

[0045] an active layer, the active layer being located on the substrate provided with the first electrode, and the active layer at least covering a partial region of the first electrode;

[0046] a first insulating layer, the first insulating layer being located on a side of the active layer away from the substrate, the first insulating layer having a second polarity opening, an orthographic projection of the second polarity opening on the substrate and an orthographic projection of the active layer on the substrate forming a first overlapping region;

[0047] a gate, the gate being located on a side of the first insulating layer away from the substrate, the gate being located on the first insulating layer, and an orthographic projection of the gate on the substrate and an orthographic projection of the active layer on the substrate having a second overlapping region;

[0048] a second electrode, the second electrode being located on a side of the first insulating layer away from the substrate, or the second electrode being located on a side of the first insulating layer close to the substrate;

[0049] The orthographic projection of the second electrode opening on the substrate overlaps with the orthographic projection of the second electrode on the substrate. The second electrode contacts the active layer. When the transistor is working, the voltage of the first electrode is greater than the voltage of the second electrode.

[0050] The beneficial effects of the technical solutions provided in the embodiments of the present application include at least:

[0051] The first electrode with a larger voltage among the first and second electrodes of the transistor is arranged between the active layer and the substrate using a bottom overlap structure, and the second electrode with a smaller voltage is arranged on the first insulating layer using an top overlap structure, or the bottom overlap structure is arranged below the first insulating layer. When the top overlap structure is adopted, since the degree of conductorization of the side of the active layer away from the substrate is greater than the degree of conductorization of the side close to the substrate, such a structure can reduce the resistance of the active layer contacted by the second electrode, thereby avoiding the situation where the resistance of the transistor at the second pole end is too large and the transistor cannot work normally. When the bottom overlap structure is adopted, the risk of the active layer being easily damaged at the via when contacting the electrode through the via can be avoided. In this way, the problem of poor performance of the array substrate in the related art is solved, and the effect of improving the performance of the array substrate is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0053] FIG1 is a schematic structural diagram of an array substrate;

[0054] FIG2 is a schematic structural diagram of an array substrate provided in an embodiment of the present application;

[0055] FIG3 is a schematic structural diagram of another array substrate provided in an embodiment of the present application;

[0056] FIG4 is a schematic structural diagram of another array substrate provided in an embodiment of the present application;

[0057] FIG5 is a schematic structural diagram of another array substrate provided in an embodiment of the present application;

[0058] FIG6 is a schematic structural diagram of another array substrate provided in an embodiment of the present application;

[0059] FIG7 is a schematic diagram of a top view of the structure of an array substrate provided in an embodiment of the present application;

[0060] FIG8 is a schematic cross-sectional view of the array substrate shown in FIG7 ;

[0061] FIG9 is a schematic top view of the structure of an array substrate provided in an embodiment of the present application;

[0062] FIG10 is a schematic cross-sectional view of the array substrate shown in FIG9 ;

[0063] FIG11 is a schematic top view of the structure of an array substrate provided in an embodiment of the present application;

[0064] FIG12 is a schematic cross-sectional view of the array substrate shown in FIG11 ;

[0065] FIG13 is a schematic top view of another array substrate provided in an embodiment of the present application;

[0066] FIG14 is a diagram showing the relationship between various parameters and resistance at an electrode;

[0067] FIG15 is a schematic structural diagram of another array substrate provided in an embodiment of the present application;

[0068] FIG16 is a diagram showing the relationship between parameters in a transistor;

[0069] FIG17 is a diagram showing the relationship between another parameter in a transistor;

[0070] FIG18 is a flow chart of a method for manufacturing an array substrate provided in an embodiment of the present application.

[0071] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0072] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0073] Figure 1 is a structural schematic diagram of an array substrate, which includes a substrate 11 and a plurality of transistors 12 arranged in an array on the substrate 11. The transistor 12 includes a source 121 and a drain 122 located on the substrate 11, a buffer layer 125 covering the source 121 and the drain 122, an active layer 123 covering the buffer layer 125, a gate insulating layer 124 covering the active layer 123, and a gate 126 located on the gate insulating layer 124. The active layer 123 is disconnected from the source 121 and the drain 122 through a via in the buffer layer 125. The gate 126 can control the active layer 123 so that the source 121 and the drain 122 are conductive via the active layer 123.

[0074] However, in some cases, the source 121 and the drain 122 of the above-mentioned transistor may not be able to conduct. For example, when the transistor is working, the voltage at the drain 122 is lower than the voltage at the source 121. The drain 122 can be the low-voltage end in the transistor. When the resistance of the active layer 123 contacted by the drain 122 is too large, the drain 122 may not be able to conduct, and the transistor may not be able to be turned on and off normally, resulting in poor performance of the array substrate.

[0075] The embodiments of the present application provide an array substrate, a display panel, and a method for manufacturing the array substrate, which can solve some problems existing in the above-mentioned related technologies.

[0076] FIG2 is a schematic diagram of the structure of an array substrate provided in an embodiment of the present application, and FIG3 is a schematic diagram of the structure of another array substrate provided in an embodiment of the present application. Referring to FIG2 and FIG3 , the array substrate 20 includes a substrate 21 and a plurality of transistors 22 located on the substrate 21. The transistors 22 include:

[0077] The first electrode 221 is located on the substrate 21 .

[0078] The active layer 222 is located on the substrate 21 provided with the first electrode 221 , and the active layer 222 at least covers a portion of the first electrode 221 .

[0079] The first insulating layer 223 is located on a side of the active layer 222 away from the substrate 21. The first insulating layer 223 has a second polarity opening k2. The orthographic projection of the second polarity opening k2 on the substrate 21 and the orthographic projection of the active layer 222 on the substrate 21 have a first overlapping region q1. In other words, the active layer 222 is exposed in the second polarity opening k2.

[0080] The gate 225 is located on the side of the first insulating layer 223 away from the substrate 21, and the second electrode 224 contacts the active layer 222 through the second electrode opening k2. The gate 225 is located on the first insulating layer 223, and the orthographic projection of the gate 225 on the substrate 21 and the orthographic projection of the active layer 222 on the substrate 21 have a second overlapping area q2.

[0081] The second electrode 224 is located on the side of the first insulating layer 223 away from the substrate 21 (Figure 2 shows this situation), or the second electrode 224 is located on the side of the first insulating layer 223 close to the substrate 21 (Figure 4 shows this situation); the orthographic projection of the second pole opening K2 on the substrate 21 overlaps with the orthographic projection of the second electrode 224 on the substrate 21, and the second electrode 224 is in contact with the active layer 222.

[0082] When the transistor 22 is operating, the voltage of the first electrode 221 is greater than the voltage of the second electrode 224. That is, the first electrode 221 can be the high-voltage terminal of the transistor 22, and the second electrode 224 can be the low-voltage terminal of the transistor 22. For example, the first electrode 221 can be the drain, and the second electrode 224 can be the source.

[0083] In summary, the array substrate provided in the embodiment of the present application is configured such that the first electrode with a larger voltage among the first and second electrodes of the transistor is arranged between the active layer and the substrate using a bottom overlap structure, and the second electrode with a smaller voltage is arranged on the first insulating layer using an top overlap structure, or the bottom overlap structure is arranged below the first insulating layer. When the top overlap structure is adopted, since the degree of conductorization of the side of the active layer away from the substrate is greater than the degree of conductorization of the side close to the substrate, such a structure can reduce the resistance of the active layer contacted by the second electrode, thereby avoiding the situation where the resistance of the transistor at the second pole end is too large and the transistor cannot work normally. When the bottom overlap structure is adopted, the risk of the active layer being easily damaged at the via when contacting the electrode through the via can be avoided. This solves the problem of poor performance of the array substrate in the related art and achieves the effect of improving the performance of the array substrate.

[0084] The top gate structure is a transistor structure in which the gate is located above the gate insulation layer and the active layer. In the development of this technology, reducing the composition process and saving costs have become a major research direction at this stage. In this regard, the top gate bottom contact (TGBC) structure reduces one composition process compared to the traditional top gate structure and can also realize the lowering of the source and drain metal (the source and drain metal is located below the active layer). This can achieve various effects such as reducing the width of the data line and reducing the logic power consumption of the display panel.

[0085] However, as shown in FIG1 , in a current transistor with a top-gate bottom-contact structure, the side of the active layer 123 close to the substrate 11 is overlapped with the source 121 and the drain 122. However, since the conductorization process for the active layer 123 is performed on the side of the active layer 123 away from the substrate 11, the conductorization effect of the upper surface of the active layer 123 away from the substrate 11 is better than the conductorization effect of the lower surface of the active layer 123 close to the substrate 11. Under such a structure, the overlap resistance of the lower surface of the active layer close to the substrate 11 contacted by the source 121 and the drain 122 is large.

[0086] In this case, at the drain 122, electrons conduct from the lower drain 122 to the upper active layer 123. This allows the high voltage to break through the potential barrier at the lower surface of the less conductive active layer 123, leaving the drain unaffected. However, at the source 121, electrons conduct from the active layer 123 to the lower source 121, and the voltage at the source is lower than that at the drain. Consequently, the potential barrier cannot be broken through at the source, making conduction difficult.

[0087] In the array substrate provided in the embodiment of the present application, this problem can be solved by overlapping the high voltage end at the bottom and overlapping the low voltage end at the top.

[0088] Figure 4 is a structural schematic diagram of another array substrate provided in an embodiment of the present application, wherein the first insulating layer 223 further includes a first pole opening k1, and the orthographic projection of the first pole opening k1 on the substrate 21 and the orthographic projection of the active layer 222 on the substrate 21 have a third overlapping area q3, and the third overlapping area q3 overlaps with the first electrode 221.

[0089] The first insulating layer 223 includes a gate insulating layer gi located between the first electrode opening k1 and the second electrode opening k2. The orthographic projection of the edge s1 of the first electrode 221 covered by the active layer 222 on the substrate 21 is located within the orthographic projection of the gate insulating layer gi on the substrate 21. In the array substrate 20, the portion of the active layer 222 covering the edge s1 of the first electrode 221 (this portion can be considered as the portion of the active layer above the edge s1) may be thinner than the remaining portion of the active layer 222 due to the step difference at the edge of the first electrode 221. This portion may be damaged in subsequent processes. For example, during the manufacture of the first insulating layer 223, the first electrode opening k1 and the second electrode opening k2 are formed. If this portion is located at the first electrode opening k1 or the second electrode opening k2, it may be damaged by the etching process, resulting in abnormal overlap between the active layer 222 and the first electrode 221 or the second electrode 224, thereby affecting the performance of the array substrate 20.

[0090] In the array substrate 20 provided in the embodiment of the present application, the gate insulating layer gi covers the portion of the active layer 222 that covers the edge of the first electrode 221, thereby protecting this portion and preventing damage to this portion during subsequent processes. Furthermore, the gate insulating layer gi of the present application can be fabricated simultaneously with the fabrication of the first insulating layer 223, eliminating the need for a self-aligned gate insulating layer gi patterning process, thereby saving on patterning steps.

[0091] It should be noted that, since the side of the active layer 222 away from the substrate 21 (the upper surface of the active layer in Figure 4) can improve the degree of conductorization under the influence of some film layers above (not shown in Figure 4), on the other hand, the conductorization process can also be implemented by the side of the active layer away from the substrate 21, and thus the degree of conductorization of the side of the active layer 222 away from the substrate 21 is greater than the degree of conductorization of the side of the active layer 222 close to the substrate 21 (the lower surface of the active layer in Figure 4).

[0092] On this basis, although the gate insulating layer gi covering the portion of the active layer 222 covering the edge s1 of the first electrode 221 may affect the conductor effect of the active layer 222, in the array substrate 20 provided in the embodiment of the present application, an upper overlap method is adopted at the second electrode 224, so that the second electrode 224 is in contact with the side of the active layer 222 with a high degree of conductorization away from the substrate 21, so as to ensure the performance of the transistor 22.

[0093] The length L1 of the overlapping area of ​​the orthographic projection of the gate insulating layer gi on the substrate 21 and the orthographic projection of the first electrode 221 on the substrate 21 in the first direction f1 can be greater than or equal to 1 micron. This can avoid the situation where the gate insulating layer gi does not cover the portion of the active layer 222 covering the edge of the first electrode 221 due to process errors. The first direction f1 is the arrangement direction of the first electrode opening k1 and the second electrode opening k2. The first direction f1 can be parallel to the extension direction of the channel of the transistor 22. The channel can be a conductive layer caused by an external electric field in the active layer (the external electric field can be applied by the gate 225), and the conductive layer can be used to conduct the first electrode 221 and the second electrode 224.

[0094] In addition, the transistors involved in the embodiments of the present application may be thin film transistors.

[0095] In an exemplary embodiment, a first distance h1 between an edge s2 of the gate insulating layer gi at the first electrode opening k1 and the gate electrode 225 in the first direction f1 is positively correlated with the mobility of the active layer 222. A second distance h2 between an edge s3 of the gate insulating layer gi at the second electrode opening k2 and the gate electrode 225 in the first direction f1 is positively correlated with the mobility of the active layer 222. In other words, the greater the refractive index of the active layer 222, the greater the first distance h1 and the second distance h2, and the smaller the refractive index of the active layer 222, the smaller the first distance h1 and the second distance h2. In other words, in the array substrate 20 provided in the embodiment of the present application, the first distance h1 and the second distance h2 can be adjusted based on the mobility of the active layer 222. This is because when the first distance h1 and the second distance h2 are too large, the area of ​​the active layer 222 exposed on the first insulating layer 223 is reduced, which may affect the degree of conductivity of the active layer 222. Therefore, the mobility of the active layer 222 can be associated with the first distance h1 and the second distance h2, and the mobility of the active layer 222 is positively correlated with the first distance h1 and the second distance h2. In an exemplary embodiment, the first distance h1 ranges from 2 microns to 4 microns, and the second distance h2 ranges from 2 microns to 4 microns. Within this distance range, the gate insulating layer gi can be prevented from seriously affecting the conductivity of the active layer. In addition, the first distance h1 and the second distance h2 can be equal or unequal, and this is not limited in this embodiment of the present application.

[0096] It should be noted that the portion of the gate insulation layer gi between the edge s2 at the first pole opening k1 and the gate 225, and the portion of the gate insulation layer gi between the edge s3 at the second pole opening k2 and the gate 225, can be respectively referred to as the gate insulation layer tail (GI tail) on both sides of the gate 225.

[0097] In the array substrate 20 provided in the embodiment of the present application, the mobility of the active layer 222 may depend on the material of the active layer. Optionally, the material of the active layer may include a high-mobility oxide, and the mobility may be greater than or equal to 20 square centimeters per volt per second (cm2). 2 V -1 s -1 ), or the mobility may be greater than or equal to 30 square centimeters per volt per second, which is not limited in the present embodiment. In an exemplary embodiment, the material of the active layer may include indium gallium zinc oxide (IGZO) doped with other elements (such as lanthanum (Ln) series elements), or may be an indium gallium zinc oxide film layer formed by atomic layer deposition (ALD) equipment. The thickness of the active layer 222 may range from 300 angstroms to 500 angstroms.

[0098] It should be noted that during the formation process of some current transistors (such as transistors with a top-gate bottom contact structure (TGBC)), large-area etching openings are formed on the insulating layer above the active layer to increase the area of ​​the exposed active layer. The active layer exposed in the openings of the insulating layer can then be subjected to a conductorization process. In the transistors manufactured using this manufacturing process, the size of the active layer exposed by the openings on the insulating layer is large, and the size of the active layer will also increase accordingly, which will cause the overall size of the transistor to be too large, which is not conducive to increasing the density of the transistors in the array substrate, and will also reduce the pixel density of the display panel used by the array substrate.

[0099] In the array substrate provided in the embodiment of the present application, a mobility greater than or equal to 20 square centimeters per volt per second (cm2) can be used. 2 V -1 s -1 ) is used as the material of the active layer, and based on the arrangement of the tail of the gate insulating layer provided in the above embodiment, and the upper overlap scheme at the second electrode, the performance of the transistor can be improved, and during the manufacturing process, the channel position and the tail of the gate insulating layer can be defined by the first electrode opening and the second electrode opening, so that the size of the active layer can be reduced, the density of the transistors in the array substrate can be increased, and the pixel density of the display panel used by the array substrate can be increased.

[0100] Please refer to the transistor of the array substrate shown in Figure 4, the second electrode 224 covers the edge s4 of the second pole opening k2 away from the gate 225, and there is a distance between the second electrode 224 and the edge of the second pole opening k2 close to the gate 225 (the edge is the edge s3 of the gate insulation layer gi at the second pole opening k2).

[0101] For the transistor shown in FIG4 , in a transistor manufacturing process, the gate 225 and the second electrode 224 are formed in a single patterning process, and the etching in the patterning process can be wet etching. Due to the large critical dimension deviation (CD Bias) of the wet etching (the CD Bias can refer to the difference between the size on the patterned photoresist and the size of the pattern below the photoresist after etching), the degree of conductivity of part of the active layer may be reduced, thereby increasing the resistance of the low-voltage end where the second electrode 224 is located, affecting the electrical performance of the transistor. In this regard, please refer to FIG5 , which is a structural schematic diagram of another array substrate provided in an embodiment of the present application. The transistor in the array substrate 20 has been modified based on the transistor shown in FIG4 , wherein the transistor further includes a first conductive block 226, which is located on the substrate 21, and the active layer 222 overlaps the first conductive block 226, and the orthographic projection of the first conductive block 226 on the substrate 21 overlaps with the first overlapping region q1. That is, the first conductive block 226 and the second electrode 224 can be respectively located on both sides of the portion of the active layer 222 exposed by the second electrode opening k2, forming a structure that sandwiches the active layer 222. Under such a structure, there can be a voltage difference between the first conductive block 226 and the second electrode 224, and the first conductive block 226 can sense a voltage. The voltage can act in reverse on the active layer 222 to reduce the resistance of the low-voltage end where the second electrode 224 is located. In addition, the first conductive block 226 is in contact with the active layer 222, and there is a density difference between the first conductive block 226 and the active layer 222. This can improve the conductor effect of the active layer 222, and can also reduce the resistance of the low-voltage end where the second electrode 224 is located, thereby preventing the low-voltage end from failing to conduct, thereby improving the electrical performance of the transistor.

[0102] The first conductive block 226 and the first electrode 221 are in the same layer. The first conductive block 226 and the first electrode 221 can be made of the same material, so that the first conductive block 226 and the first electrode 221 can be formed through a single patterning process. The first conductive block 226 and the first electrode 221 can both comprise metal materials.

[0103] The patterning process involved in the embodiments of the present application may include steps such as coating photoresist, exposing, developing, etching, and stripping the photoresist.

[0104] FIG6 is a schematic diagram of the structure of another array substrate provided in an embodiment of the present application. FIG6 is a structural diagram of the transistor shown in FIG5 with some adjustments. Referring to FIG6 , the second electrode 224 covers the second electrode opening k2, and the orthographic projection of the second electrode opening k2 on the substrate 21 is located within the orthographic projection of the second electrode 224 on the substrate 21. In this structure, the second electrode 224 covers the entire second electrode opening k2.

[0105] The distance L2 that the second electrode 224 covers the gate insulating layer gi in the first direction f1 can be 1 to 2 microns to prevent the second electrode 224 from failing to cover the second electrode opening k2 due to process errors. The distance L3 between the gate electrode 225 and the second electrode 224 in the first direction f1 can be 2 to 3 microns, for example, 2.5 microns. This can reduce the distance between the second electrode 224 and the gate electrode 225, thereby reducing the overall size of the transistor and facilitating an increase in the pixel density (pixels per inch, PPI) of a display panel using this array substrate.

[0106] It should be noted that in the related art, the same gate insulation layer tail (GI Tail) size is used for different types of transistors in the array substrate. However, different types of transistors may have different requirements for the size of the gate insulation layer tail, which in turn leads to poor performance of the array substrate in the related art. Based on this, please refer to Figure 7, which is a schematic diagram of a top view structure of the array substrate provided in an embodiment of the present application (Figure 7 includes a schematic diagram of a top view structure of two types of transistors at two positions), and Figure 8 is a schematic diagram of a cross-sectional structure of the array substrate shown in Figure 7 (Figure 8 includes a schematic diagram of a cross-sectional structure of two types of transistors at two positions corresponding to Figure 7, with the cross-sectional position of STFT1 being AA and the cross-sectional position of DTFT1 being BB). Referring to Figures 7 and 8, the multiple transistors 22 on the array substrate 20 provided in an embodiment of the present application include multiple drive transistors (Drive TFT, DTFT) and multiple switch transistors (Switch TFT, STFT), the multiple drive transistors DTFT include a first drive transistor DTFT1, and the multiple switch transistors STFT include a first switch transistor STFT1.

[0107] The width e1 of the gate insulating layer gi of the first switching transistor STFT1 in the first direction f1 is greater than the width e2 of the gate insulating layer gi of the first driving transistor DTFT1 in the first direction f1. Similar to the above embodiment, the first direction f1 is the arrangement direction of the first electrode openings k1 and the second electrode openings k2. That is, in this structure, the width e1 of the gate insulating layer gi of at least one switching transistor STFT in the array substrate in the first direction f1 is greater than the width e2 of the gate insulating layer gi of a driving transistor DTFT in the first direction f1. That is, in different types of transistors, when the gate electrodes 225 have the same width in the first direction f1, or when they do not have the same width in the first direction f1, the width of the gate insulating layer tail (GI Tail) of the switching transistor STFT in the first direction f1 is greater than the width of the gate insulating layer tail (GI Tail) of the driving transistor DTFT in the first direction f1.

[0108] Of course, the width of the gate insulating layer gi of each switching transistor STFT in the array substrate 20 in the first direction f1 may be greater than the width of the gate insulating layer gi of each driving transistor DTFT in the first direction f1, and this embodiment of the application does not limit this.

[0109] This is because the channel length of a switching transistor is typically short. By increasing the width of the gate insulation layer tail (GI Tail) of the switching transistor (STFT) in the first direction f1, the present application can avoid the problem of the effective channel of the switching transistor being too short due to manufacturing process factors, thereby improving product yield. Furthermore, since the channel length of the driving transistor (DTFT) is typically longer, shortening the width of the gate insulation layer tail (GI Tail) in the first direction f1 will also have a smaller impact. Consequently, by reducing the width of the gate insulation layer tail (GI Tail) of the driving transistor (DTFT) in the first direction f1, the present application can reduce the overall size of the driving transistor (DTFT).

[0110] In an exemplary embodiment, please refer to Figures 9 and 10. Figure 9 is a schematic top view of an array substrate provided in an embodiment of the present application, and Figure 10 is a schematic cross-sectional view of the array substrate shown in Figure 9 (Figure 10 is a schematic cross-sectional view of the array substrate shown in Figure 9 taken at position CC). A first distance h1 between an edge s2 of the gate insulating layer gi at the first electrode opening k1 and the gate electrode 225 in a first direction f1 is greater than a second distance h2 between an edge s3 of the gate insulating layer gi at the second electrode opening k2 and the gate electrode 225 in the first direction f1. The first direction f1 is the direction in which the first electrode opening k1 and the second electrode opening k2 are arranged. In this structure, the size of the gate insulating layer tail (GI Tail) of the transistor at the first electrode 221 (high-voltage side) is greater than the size of the gate insulating layer tail (GI Tail) of the transistor at the second electrode 224 (low-voltage side). This structure can reduce the impact of the first electrode 221 (high-voltage side) on the transistor channel, thereby ensuring the transistor's electrical performance, such as withstand voltage.

[0111] In related art, the size of the gate insulation layer tail (GI Tail) at the source and drain of a transistor is consistent. However, in the transistor provided in the embodiment of the present application, the size of the gate insulation layer tail at the first electrode 221 (high-voltage end) can be increased (or the size of the gate insulation layer tail at the second electrode 224 (low-voltage end) can be reduced) to improve the transistor's electrical performance, such as voltage resistance. This structure can be applied to one or more transistors in the array substrate provided in the embodiment of the present application, and can also be applied to at least one of the switching transistor (STFT) and the driving transistor (DTFT), and this embodiment of the present application is not limited to this.

[0112] In an exemplary embodiment, referring to Figures 11 and 12, Figure 11 is a schematic top view of the array substrate provided in an embodiment of the present application, and Figure 12 is a schematic cross-sectional view of the array substrate shown in Figure 11 (Figure 12 is a schematic cross-sectional view of the array substrate shown in Figure 11 at point DD). The width of the first pole opening k1 in the first direction f1 is greater than the width of the second pole opening k2 in the first direction f1. That is, in this transistor, a first electrode opening k1 located at the first electrode 221 (high-voltage end) and a second electrode opening k2 located at the second electrode 224 (low-voltage end) may be provided on the first insulating layer 223. The active layer 222 is exposed at these two openings, and the width of the first electrode opening k1 in the first direction f1 is greater than the width of the second electrode opening k2 in the first direction f1. Under such a structure, the area of ​​the active layer 222 exposed at the high-voltage end can be greater than the area of ​​the active layer 222 exposed at the low-voltage end. As a result, the high-voltage end will act on the active layer path with greater resistance, achieving a voltage divider effect, thereby improving the voltage resistance of the transistor. The structure shown in Figures 11 and 12 can be applied to one or more transistors in the array substrate provided in the embodiments of the present application, for example, it can be applied to transistors in the array substrate that require high voltage resistance.

[0113] In an exemplary embodiment, please refer to Figure 13, which is a top-down structural schematic diagram of another array substrate provided in an embodiment of the present application (the observation line of sight can be perpendicular to the substrate), wherein the active layer 222 includes a first end d1, a connecting portion d3 and a second end d2, and the connecting portion d3 is respectively connected to the first end d1 and the second end d2.

[0114] The orthographic projection of the first end d1 on the substrate 21 is located within the orthographic projection of the first electrode 221 on the substrate 21, and the orthographic projection of the second end d2 on the substrate 21 is located within the orthographic projection of the second electrode 224 on the substrate 21. In the second direction f2, the width of at least one of the first end d1 and the second end d2 in the second direction is greater than the width of the connecting portion in the second direction. The second direction f2 is perpendicular to the arrangement direction of the first and second electrode openings k1 and k2 (i.e., the first direction f1). The second direction f2 may be perpendicular to the extension direction of the transistor's communication lines.

[0115] Please refer to Figure 14, which is a graph showing the relationship between the distance at the electrode and the resistance (the resistance here may refer to the resistance at the electrode overlapping the active layer). In the graph, the horizontal axis L0.35 indicates that the exposed dimension of the active layer in the first direction is 0.35 microns, the horizontal axis L2 indicates that the exposed dimension of the active layer in the first direction is 2 microns, the horizontal axis L5 indicates that the exposed dimension of the active layer in the first direction is 5 microns, m1 indicates that the distance between the active layer and the electrode overlapping (this distance may be the distance between the active layer and the electrode overlapping in the first direction) is 1 micron, m3 indicates that the distance between the active layer and the electrode overlapping is 3 microns, and m5 indicates that the distance between the active layer and the electrode overlapping is 5 microns. The vertical axis represents the resistance, which can be in ohms. It can be seen that the smaller the exposed dimension of the active layer in the first direction (the smaller the distance between the exposed active layer and the channel), the lower the resistance, and the larger the area of ​​the active layer overlapping the electrode, the lower the resistance.

[0116] Please refer to Figures 13 and 14. By setting the width (width in the second direction) of the connecting portion d3 of the active layer 222 between the first electrode 221 and the second electrode 224 to be smaller, and setting the width (width in the second direction) of the first end d1 and the second end d2 of the active layer 222 overlapping the first electrode 221 and the second electrode 224 to be larger, the resistance of the transistor at the first electrode and the second electrode can be further reduced, thereby improving the electrical performance of the transistor.

[0117] In addition, please refer to Figure 1. In the related art, after the source 121 and the drain 122 are formed, a buffer layer 125 is formed first, and then a via is formed on the buffer layer 125, and an active layer 123 is formed on the buffer layer 125. The active layer 123 is disconnected from the source 121 and the drain 122 through the via on the buffer layer 125. Under this structure, the active layer 123 will have a climbing portion 1231 at the hole wall of the via covering the buffer layer 125. The thickness of the climbing portion 1231 will be smaller than the thickness at other positions of the active layer 123 due to the step difference of the via, and it is easy to be damaged and has poor conductivity.

[0118] In the array substrate provided in the embodiment of the present application, referring to FIG10 , the array substrate further includes a buffer layer 25 located between the first electrode 221 and the substrate 21. The first electrode 221 and the active layer 222 are both disposed on the buffer layer 25. Specifically, in this array substrate, the active layer 222 is disposed after the first electrode 221 is disposed. Consequently, the active layer 222 can directly overlap the first electrode 221 without requiring vias in a film layer such as the buffer layer to contact the first electrode 221. This structure improves the flatness of the overlapped portion between the active layer 222 and the first electrode 221, eliminates the sloped portion typically seen in a via-overlapping structure, and reduces the possibility of resistance anomalies and fractures in the active layer.

[0119] Furthermore, in the transistor shown in Figure 1, the presence of vias in the buffer layer significantly increases the number of vias in the transistor. These vias occupy space in the array substrate and limit the size of the transistor, significantly increasing the difficulty of reducing the size of the transistor. This makes it difficult to use this transistor in high-pixel-density display panels and also limits the increase in pixel density of the display panel. This problem is even more serious in some high-pixel-density organic light-emitting diode display panels due to the presence of internal compensation circuits including transistors and the resulting large number of transistors.

[0120] In the array substrate provided in the embodiment of the present application, the active layer 222 can directly overlap the first electrode 221 without passing through the vias of the buffer layer or other film layers, thereby reducing the number of vias in the transistor and lowering the restrictions of the vias on the size of the transistor. Therefore, the array substrate with the transistor will not affect the improvement of the pixel density of the display panel and can be used in display panels with higher pixel density.

[0121] FIG15 is a schematic structural diagram of another array substrate provided in an embodiment of the present application, wherein the array substrate 20 further includes a buffer layer 25, which is located between the active layer 222 and the first electrode 221. The buffer layer 25 has a buffer layer opening 251, and a portion of the first electrode 221 is exposed at the buffer layer opening 251. The active layer 222 covers the buffer layer opening 251 and also covers the portion of the first electrode 221 within the buffer layer opening 251.

[0122] The first insulating layer 223 covers the climbing portion p1 of the active layer 222 . The climbing portion p1 of the active layer 222 is a portion of the active layer 222 covering the hole wall of the buffer layer 251 .

[0123] This scheme is another structure that is overlapped under the high voltage end of the transistor where the first electrode 221 is located. Unlike some of the above-mentioned transistors, in this transistor, after the first electrode 221 is formed, a buffer layer 25 is formed first, and then an active layer 222 is formed. The active layer 222 can contact the first electrode 221 through the buffer layer opening 251 on the buffer layer 25. In this structure, a recessed structure is formed at the buffer layer opening 251 on the active layer. The recessed structure includes a hole partially covering the buffer layer opening 251. The active layer on the wall, this part of the active layer is the climbing portion p1 of the active layer 222. Due to the large step difference in the covered area of ​​the climbing portion p1 (the step difference at the buffer layer opening 251 is large), the thickness of the climbing portion p1 may be smaller than the portion covering the buffer layer 25. Therefore, in the array substrate shown in Figure 1, this portion is located in the opening of the upper insulating layer and may be damaged by some processes when forming the opening. For example, the active layer may be affected by the etching process, resulting in poor conductivity or even fracture, thereby reducing the electrical performance of the transistor. In the array substrate provided in the embodiment of the present application, by having the first insulating layer 223 cover the climbing portion p1 of the active layer 222, the possibility of damage or even fracture of the climbing portion p1 of the active layer by subsequent etching processes is reduced, thereby improving the reliability and electrical performance of the transistor.

[0124] In addition, the transistor further includes a second conductive block 26. The second conductive block 26 and the first electrode 221 are co-layered, and the orthographic projection of the second conductive block 26 on the substrate overlaps with the first overlapping region q1. The function of the second conductive block 26 can be similar to that of the first conductive block in the array substrate provided in the above-described embodiment. Specifically, the second conductive block 26 and the second electrode 224 can be located on either side of the exposed portion of the active layer 222 and the buffer layer 25, respectively, to form a structure sandwiching the active layer 222 and the buffer layer 25. In this structure, a voltage difference can exist between the first conductive block 226 and the second electrode 224, causing the first conductive block 226 to sense a voltage. This voltage can then act inversely on the active layer 222, thereby reducing the resistance of the low-voltage end where the second electrode 224 is located, reducing the possibility of the low-voltage end failing to conduct, and thereby improving the electrical performance of the transistor.

[0125] The second conductive block 26 and the first electrode 221 may be formed from the same material. The second conductive block 26 and the first electrode 221 may be formed from the same material, so that the second conductive block 26 and the first electrode 221 can be formed through a single patterning process. Both the second conductive block 26 and the first electrode 221 may comprise metal materials.

[0126] In addition, the second conductive block 26 may be disconnected from other circuits in the array substrate 20, so as to adopt a floating conductive structure. This can prevent the second conductive block 26 from being affected by voltages on other circuits and causing adverse effects on transistors.

[0127] Figure 16 is a diagram illustrating the relationship between parameters in a transistor, showing the relationship between the critical dimension deviation (CD Bias, CDB) and ΔL in the gate etching process (ΔL is the vertical axis in Figure 16). Referring to Figure 1 and Figure 16, ΔL represents the dimension of the region in the active layer channel affected by the conductorization process in the first direction f1. When the conductorization process is performed on the exposed portion of the active layer above the first insulating layer, the critical dimension (CD Bias) affects the active layer below the gate, thereby affecting the electrical performance of the transistor.

[0128] As can be seen from Figure 16, the larger the critical dimension, the smaller ΔL will be.

[0129] Figure 17 is a diagram showing the relationship between another parameter in a transistor. Figure 17 shows the relationship between the threshold voltage Vth of a transistor and ΔL (the vertical axis is Vth, in volts). It can be seen that when ΔL becomes smaller, the absolute value of the negative bias of the transistor's threshold voltage Vth will also become smaller. When the absolute value of the negative bias is too large, it may cause various display anomalies such as abnormal brightness. Based on the contents shown in Figures 16 and 17, please refer to Figure 12. In the array substrate provided in the embodiment of the present application, the transistor can meet the following requirements: L+2*T≥7;

[0130] Wherein, L is the dimension of the channel in the first direction f1, and L can be equal to the width of the gate 225 in the first direction f1, T is equal to the first distance h1 between the edge s2 of the gate insulating layer gi at the first electrode opening k1 and the gate 225, and T is equal to the second distance h2 between the edge of the gate insulating layer gi at the second electrode opening k2 and the gate 225. In a transistor of this structure, the dimensions (dimensions in the first direction f1) of the two gate insulating layer tails on both sides of the gate 225 are the same. In addition, in an exemplary embodiment, based on L+2*T≥7, the critical dimension in the etching process for forming the gate can be 4 microns, T can be 2 microns, ΔL can be 1 micron, and the channel dimension L is 4 microns, realizing a short channel transistor. If the dimension of L is to be further reduced, the critical dimension deviation can be further increased to reduce ΔL, thereby achieving the effect of reducing the channel dimension L.

[0131] It has been verified that under such a setting, ΔL in the transistor can be reduced, and the absolute value of the negative bias of the threshold voltage Vth of the transistor can be reduced, thereby improving the electrical performance of the transistor.

[0132] In an exemplary embodiment, L+2*T≥8. Correspondingly, in one transistor, L may be 5 microns and T may be greater than or equal to 1.5 microns. In another transistor, L may be 4 microns and T may be greater than or equal to 1.5 microns. In another transistor, L may be 3.5 microns and T may be greater than or equal to 2.25 microns. The array substrate provided in the embodiment of the present application may include at least one of these transistors, so that transistors with different channel sizes can be provided in one array substrate.

[0133] The contents regarding parameters such as L and T provided in the embodiments of the present application can be applied to one or more array substrates provided in the above embodiments.

[0134] In addition, some examples of critical dimensions and critical dimension deviations in the wet etching process can be found in Table 1.

[0135] Table 1

[0136] As can be seen from Table 1, if the critical dimension (CD) is set to 8 microns and the developed photoresist critical dimension (DICD) is 8.1 microns, the CD bias will also vary under different post-etch pattern critical dimensions (FICD). For example, when the post-etch pattern critical dimension (FICD) is 6.1 microns, the CD bias is 2 microns; when the post-etch pattern critical dimension (FICD) is 5.1 microns, the CD bias is 3 microns. Therefore, the CD bias can be controlled by adjusting the post-etch pattern critical dimension (FICD), and the post-etch pattern critical dimension can be achieved by adjusting the wet etching process time parameters.

[0137] In addition, an embodiment of the present application further provides a display panel, which includes any array substrate provided in the above embodiments. In addition, the display panel may further include a display structure 30 located on the array substrate 11. The array substrate 20 may be used to control the display structure 30. Based on different types of display panels, the display structure 30 may also have different corresponding structures. For example, when the display panel is a self-luminous display panel, the display structure 30 may include multiple light-emitting units 31. The light-emitting units 31 may include organic light-emitting diodes (OLEDs). The display structure 30 may include organic light-emitting diodes of multiple colors, for example, a red organic light-emitting diode for emitting red light, a green organic light-emitting diode for emitting green light, a blue organic light-emitting diode for emitting blue light, etc. The circuit structure in the array substrate 20 may be electrically connected to the organic light-emitting diodes to drive the organic light-emitting diodes to emit light, thereby realizing a display function.

[0138] In addition, the display structure 30 may further include a color filter layer, which may be located on a side of the light emitting unit 31 away from the array substrate. The color filter layer may enhance the color purity of the light emitted by the organic light emitting diode and improve the display effect of the display panel.

[0139] Of course, in another exemplary embodiment, the display structure 30 may include a color filter layer and a plurality of white light emitting diodes for emitting white light, and the color filter layer may be located on a side of the white light emitting diodes away from the array substrate.

[0140] In an exemplary embodiment, the display panel may be a liquid crystal display panel. Accordingly, the display structure may include a liquid crystal layer and a color filter layer. The liquid crystal layer may be located on an array substrate 20. The array substrate 20 may be used to apply a voltage to the liquid crystal layer to control the liquid crystal layer. The color filter layer may be located on a side of the liquid crystal layer away from the array substrate. When the display panel is a liquid crystal display panel, the display panel may cooperate with a backlight assembly to achieve a display function. For example, the backlight assembly may be located on a side of the array substrate 20 away from the liquid crystal layer. The backlight emits light that passes through the array substrate and illuminates the liquid crystal layer. The array substrate may control at least some areas of the liquid crystal layer to be light-transmissive, while other areas are opaque. Light from the backlight assembly can then pass through the light-transmissive areas and illuminate the color filter substrate, thereby transmitting through the color filter substrate to achieve a display function.

[0141] Because the array substrate provided in the embodiments of the present application improves the electrical performance of transistors, it enables transistors to maintain good electrical performance even in high-density arrangements, thus avoiding the problem in related technologies where the yield of display panels is significantly reduced when the pixel density is high. This can further improve the manufacturing yield of display panels at high pixel densities and enhance the display quality of the display panels.

[0142] In summary, the array substrate provided in the embodiment of the present application is configured such that the first electrode with a larger voltage among the first and second electrodes of the transistor is arranged between the active layer and the substrate using a bottom overlap structure, and the second electrode with a smaller voltage is arranged on the first insulating layer using an top overlap structure, or the bottom overlap structure is arranged below the first insulating layer. When the top overlap structure is adopted, since the degree of conductorization of the side of the active layer away from the substrate is greater than the degree of conductorization of the side close to the substrate, such a structure can reduce the resistance of the active layer contacted by the second electrode, thereby avoiding the situation where the resistance of the transistor at the second pole end is too large and the transistor cannot work normally. When the bottom overlap structure is adopted, the risk of the active layer being easily damaged at the via when contacting the electrode through the via can be avoided. This solves the problem of poor performance of the array substrate in the related art and achieves the effect of improving the performance of the array substrate.

[0143] FIG18 is a flow chart of a method for manufacturing an array substrate provided in an embodiment of the present application. The method may include the following steps:

[0144] Step 1701: Obtain a substrate.

[0145] Step 1702: fabricate a plurality of transistors on a substrate.

[0146] Among them, the transistors include:

[0147] a first electrode, the first electrode being located on the substrate;

[0148] an active layer, the active layer being located on the substrate provided with the first electrode, and the active layer covering at least a portion of the first electrode;

[0149] a first insulating layer, the first insulating layer being located on a side of the active layer away from the substrate, the first insulating layer having a second polarity opening, an orthographic projection of the second polarity opening on the substrate and an orthographic projection of the active layer on the substrate forming a first overlapping region;

[0150] a gate, the gate being located on a side of the first insulating layer away from the substrate, the gate being located on the first insulating layer, and an orthographic projection of the gate on the substrate and an orthographic projection of the active layer on the substrate having a second overlapping region;

[0151] a second electrode, the second electrode being located on a side of the first insulating layer away from the substrate, or the second electrode being located on a side of the first insulating layer close to the substrate;

[0152] The orthographic projection of the second pole opening on the substrate overlaps with the orthographic projection of the second electrode on the substrate. The second electrode contacts the active layer. When the transistor is working, the voltage of the first electrode is greater than the voltage of the second electrode. When the transistor is working, the voltage of the first electrode is greater than the voltage of the second electrode.

[0153] In summary, the manufacturing method of the array substrate provided in the embodiment of the present application is such that the first electrode with a larger voltage among the first and second electrodes of the transistor is arranged between the active layer and the substrate using a bottom overlap structure, and the second electrode with a smaller voltage is arranged on the first insulating layer using an upper overlap structure, or the bottom overlap structure is arranged below the first insulating layer. When the upper overlap structure is adopted, since the degree of conductorization of the side of the active layer away from the substrate is greater than the degree of conductorization of the side close to the substrate, such a structure can reduce the resistance of the active layer contacted by the second electrode, thereby avoiding the situation where the resistance of the transistor at the second pole end is too large and the transistor cannot work normally. When the bottom overlap structure is adopted, the risk of the active layer being easily damaged at the via when contacting the electrode through the via can be avoided. In this way, the problem of poor performance of the array substrate in the related art is solved, and the effect of improving the performance of the array substrate is achieved.

[0154] In this application, the term "and / or" simply describes an association between related objects, indicating that three possible relationships exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the related objects are in an "or" relationship.

[0155] In this application, the term "at least one of A and B" simply describes an association relationship between associated objects, indicating that three possible relationships exist. For example, "at least one of A and B" can mean: A exists alone, A and B exist simultaneously, and B exists alone. Similarly, "at least one of A, B, and C" means that seven possible relationships exist, indicating: A exists alone, B exists alone, C exists alone, A and B exist simultaneously, A and C exist simultaneously, C and B exist simultaneously, and A, B, and C exist simultaneously. Similarly, "at least one of A, B, C, and D" means that fifteen possible relationships exist, indicating: A exists alone, B exists alone, C exists alone, D exists alone, A and B exist simultaneously, A and C exist simultaneously, A and D exist simultaneously, C and B exist simultaneously, D and B exist simultaneously, C and D exist simultaneously, C and D exist simultaneously, A, B, and C exist simultaneously, A, B, and D exist simultaneously, A, C, and D exist simultaneously, B, C, and D exist simultaneously, and A, B, C, and D exist simultaneously.

[0156] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it may be the only layer between the two layers or elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0157] In this application, the terms "first", "second", "third" and "fourth" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "plurality" refers to two or more, unless otherwise expressly limited.

[0158] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. An array substrate, characterized in that: The array substrate comprises a substrate and a plurality of transistors located on the substrate, wherein the transistors comprise: a first electrode, the first electrode being located on the substrate; an active layer, wherein the active layer is located on the substrate provided with the first electrode, and the active layer at least covers a partial area of ​​the first electrode; a first insulating layer, the first insulating layer being located on a side of the active layer away from the substrate, the first insulating layer having a second polarity opening, an orthographic projection of the second polarity opening on the substrate and an orthographic projection of the active layer on the substrate having a first overlapping region; A gate, the gate is located on a side of the first insulating layer away from the substrate, the gate is located on the first insulating layer, and an orthographic projection of the gate on the substrate and an orthographic projection of the active layer on the substrate have a second overlapping region; a second electrode, the second electrode being located on a side of the first insulating layer away from the substrate, or the second electrode being located on a side of the first insulating layer close to the substrate; The orthographic projection of the second electrode opening on the substrate overlaps with the orthographic projection of the second electrode on the substrate, the second electrode contacts the active layer, and when the transistor is working, the voltage of the first electrode is greater than the voltage of the second electrode.

2. The array substrate according to claim 1, characterized in that: When the second electrode is located on a side of the first insulating layer away from the substrate, the second electrode contacts the active layer through the second electrode opening, the first insulating layer further comprises a first electrode opening, an orthographic projection of the first electrode opening on the substrate and an orthographic projection of the active layer on the substrate have a third overlapping region, and the third overlapping region overlaps with the first electrode; The first insulating layer includes a gate insulating layer located between the first electrode opening and the second electrode opening, and the orthographic projection of the edge of the first electrode covered by the active layer on the substrate is located in the orthographic projection of the gate insulating layer on the substrate.

3. The array substrate according to claim 2, characterized in that: A first distance between an edge of the gate insulating layer at the first electrode opening and the gate in a first direction is positively correlated with the mobility of the active layer, and the first direction is an arrangement direction of the first electrode opening and the second electrode opening; A second distance between an edge of the gate insulating layer at the second electrode opening and the gate in the first direction is positively correlated with the mobility of the active layer.

4. The array substrate according to claim 2, characterized in that: The plurality of transistors include a plurality of driving transistors and a plurality of switching transistors, the plurality of driving transistors include a first driving transistor, and the plurality of switching transistors include a first switching transistor; The width of the gate insulating layer of the first switch transistor in a first direction is greater than the width of the gate insulating layer of the first drive transistor in the first direction, and the first direction is an arrangement direction of the first electrode openings and the second electrode openings.

5. The array substrate according to claim 2, characterized in that: A first distance in a first direction between an edge of the gate insulation layer at the first pole opening and the gate is greater than a second distance in the first direction between an edge of the gate insulation layer at the second pole opening and the gate, and the first direction is an arrangement direction of the first pole opening and the second pole opening.

6. The array substrate according to claim 2, characterized in that: The array substrate includes a buffer layer between the first electrode and the substrate, and the first electrode and the active layer are both arranged on the buffer layer.

7. The array substrate according to claim 2, characterized in that: The width of the first pole opening in the first direction is greater than the width of the second pole opening in the first direction.

8. The array substrate according to claim 2, characterized in that: The active layer includes a first end, a connecting portion and a second end, wherein the connecting portion is connected to the first end and the second end respectively; The orthographic projection of the first end portion on the substrate is located in the orthographic projection of the first electrode on the substrate, and the orthographic projection of the second end portion on the substrate is located in the orthographic projection of the second electrode on the substrate. In the second direction, the width of at least one of the first end portion and the second end portion in the second direction is greater than the width of the connecting portion in the second direction, and the second direction is a direction perpendicular to the arrangement direction of the first pole opening and the second pole opening.

9. The array substrate according to claim 3, characterized in that: The first distance ranges from 2 micrometers to 4 micrometers, and the second distance ranges from 2 micrometers to 4 micrometers.

10. The array substrate according to any one of claims 1 to 9, characterized in that: The second electrode covers an edge of the second electrode opening away from the grid, and a distance between the second electrode and an edge of the second electrode opening close to the grid is greater than zero.

11. The array substrate according to any one of claims 1 to 9, characterized in that: The transistor further includes a first conductive block, which is located on the substrate, and the active layer overlaps the first conductive block, and an orthographic projection of the first conductive block on the substrate overlaps with the first overlapping region.

12. The array substrate according to claim 11, characterized in that: The second electrode covers the second electrode opening, and an orthographic projection of the second electrode opening on the substrate is located in an orthographic projection of the second electrode on the substrate.

13. The array substrate according to claim 11, characterized in that: The first conductive block and the first electrode are in the same layer structure.

14. The array substrate according to claim 2, characterized in that: The array substrate further includes a buffer layer, the buffer layer is located between the active layer and the first electrode, the buffer layer has a buffer layer opening, and the partial area of ​​the first electrode is exposed at the buffer layer opening; The active layer covers the buffer layer opening and covers the partial region of the first electrode in the buffer layer opening; The first insulating layer covers the climbing portion of the active layer, and the climbing portion of the active layer is a portion of the active layer that covers the hole wall of the buffer layer opening.

15. The array substrate according to claim 14, characterized in that: The transistor further includes a second conductive block, the second conductive block and the first electrode are in the same layer structure, and an orthographic projection of the second conductive block on the substrate overlaps with the first overlapping region.

16. The array substrate according to claim 2, characterized in that: The transistor satisfies: L+2*T≥7; Wherein, L is equal to the width of the gate in the first direction, T is equal to the first distance between the edge of the gate insulation layer at the first pole opening and the gate, and T is equal to the second distance between the edge of the gate insulation layer at the second pole opening and the gate.

17. The array substrate according to any one of claims 1 to 9, characterized in that: The mobility of the active layer is greater than or equal to 20 square centimeters per volt per second.

18. The array substrate according to any one of claims 1 to 9, characterized in that: The material of the active layer includes indium gallium zinc oxide, and the thickness ranges from 300 angstroms to 500 angstroms.

19. A display panel, characterized in that: The display panel comprises the array substrate according to any one of claims 1 to 18.

20. A method for manufacturing an array substrate, characterized in that: The method comprises: obtaining a substrate; A plurality of transistors are fabricated on the substrate, the transistors comprising: a first electrode, the first electrode being located on the substrate; an active layer, wherein the active layer is located on the substrate provided with the first electrode, and the active layer at least covers a partial area of ​​the first electrode; a first insulating layer, the first insulating layer being located on a side of the active layer away from the substrate, the first insulating layer having a second polarity opening, an orthographic projection of the second polarity opening on the substrate and an orthographic projection of the active layer on the substrate having a first overlapping region; A gate, the gate is located on a side of the first insulating layer away from the substrate, the gate is located on the first insulating layer, and an orthographic projection of the gate on the substrate and an orthographic projection of the active layer on the substrate have a second overlapping region; a second electrode, the second electrode being located on a side of the first insulating layer away from the substrate, or the second electrode being located on a side of the first insulating layer close to the substrate; The positive projection of the second electrode opening on the substrate overlaps with the positive projection of the second electrode on the substrate, and the second electrode contacts the active layer. When the transistor is working, The voltage of the first electrode is greater than the voltage of the second electrode.

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