Image sensor devices including superlattices and related methods

Abstract

An image sensor device may include a semiconductor substrate, a pixel region within the semiconductor substrate, the pixel region including a first dopant having a first conductivity type, a first pinning layer on a surface of the substrate, and a second pinning layer in the semiconductor substrate, the first pinned layer includes a second dopant having a second conductivity type different from the first conductivity type, the second pinned layer being adjacent to at least one side of the pixel region and including a superlattice and the second dopant. The superlattice may include a plurality of stacked sets of layers, where each set of layers includes a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer confined within the lattice of an adjacent base semiconductor portion.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor devices and, more particularly, to semiconductor image sensor devices and related methods. Background Art

[0002] Various structures and techniques have been proposed to enhance the performance of semiconductor devices, such as by increasing the mobility of charge carriers. For example, U.S. Patent Application No. 2003 / 0057416 to Currie et al. discloses a strained material layer that includes silicon, silicon-germanium, and relaxed silicon, and also includes an impurity-free region that would otherwise result in performance degradation. The biaxial strain produced in the upper silicon layer changes the carrier mobility, thereby achieving a higher speed and / or lower power device. Published U.S. Patent Application No. 2003 / 0034529 to Fitzgerald et al. discloses a CMOS inverter that is also based on similar strained silicon technology.

[0003] Takagi's U.S. Patent No. 6,472,685 B2 discloses a semiconductor device including silicon and carbon layers sandwiched between silicon layers, so that the conduction band and the valence band of the second silicon layer are subjected to tensile strain. Electrons with a smaller effective mass induced by an electric field applied to a gate electrode are confined in the second silicon layer, and therefore, an n-channel MOSFET is identified to have a higher mobility.

[0004] Ishibashi et al., US Pat. No. 4,937,204, discloses a superlattice in which multiple layers less than 8 monolayers and including fractional or binary or binary compound semiconductor layers are alternately epitaxially grown. The direction of main current flow is perpendicular to the layers of the superlattice.

[0005] U.S. Patent No. 5,357,119 to Wang et al. discloses a Si-Ge short period superlattice that achieves higher mobility by reducing alloy scattering in the superlattice. Along these lines, U.S. Patent No. 5,683,934 to Candelaria discloses an enhanced mobility MOSFET including a channel layer comprising an alloy of silicon and a second material, the second material being present in the silicon lattice in a percentage that places the channel layer under tensile stress.

[0006] Tsu's U.S. Patent No. 5,216,262 discloses a quantum well structure comprising two barrier regions and an epitaxially grown thin semiconductor layer sandwiched between the barriers. Each barrier region consists of alternating SiO2 / Si layers, typically in the range of 2 to 6 monolayers. Much thicker silicon portions are sandwiched between the barriers.

[0007] On September 6, 2000, a paper entitled "Phenomena in silicon nanostructure devices" also by Tsu, published online in Applied Physics and Materials Science & Processing, pp. 391-402, disclosed a semiconductor atomic superlattice (SAS) of silicon and oxygen. It is disclosed that the Si / O superlattice can be used in silicon quantum and light-emitting devices. In particular, a green electroluminescent diode structure was constructed and tested. The current flow in the diode structure is vertical, that is, perpendicular to the layers of the SAS. The disclosed SAS can include semiconductor layers separated by adsorbed substances (such as oxygen atoms and CO molecules). The silicon growth beyond the adsorbed oxygen monolayer is described as epitaxial growth with a relatively low defect density. One SAS structure includes a 1.1nm thick silicon portion of about 8 silicon atomic layers, and another structure has silicon twice that thickness. Tsu's light-emitting SAS structure was further discussed in a paper entitled "Chemical Design of Direct-Gap Light-Emitting Silicon" published by Luo et al. in Physical Review Letters, Vol. 89, No. 7 (August 12, 2002).

[0008] Wang et al., U.S. Patent No. 7,105,895 discloses a barrier building block having thin silicon and oxygen, carbon, nitrogen, phosphorus, antimony, arsenic or hydrogen to reduce the vertical current flowing through the lattice by more than four orders of magnitude. The insulating layer / barrier layer allows low-defect epitaxial silicon to be deposited next to the insulating layer.

[0009] Published British patent application 2,347,520 to Mears et al. discloses that the principles of aperiodic photonic bandgap (APBG) structures can be adapted for electronic bandgap engineering. In particular, the application discloses that material parameters, such as the location of band minima, effective mass, etc., can be adjusted to produce new aperiodic materials with desired band structure properties. It is disclosed that other parameters, such as electrical conductivity, thermal conductivity, and dielectric constant or magnetic permeability, can also be engineered into the material.

[0010] In addition, U.S. Pat. No. 6,376,337 to Wang et al. discloses a method for producing an insulating layer or barrier layer of a semiconductor device, the method comprising depositing a layer of silicon and at least one additional element on a silicon substrate, whereby the deposited layer is substantially free of defects, so that substantially defect-free epitaxial silicon can be deposited on the deposited layer. Alternatively, a monolayer of one or more elements, preferably including oxygen, is adsorbed on the silicon substrate. Multiple insulating layers sandwiched between epitaxial silicon form a barrier composite.

[0011] Despite the existence of such approaches, further enhancements are desired to achieve improved performance of semiconductor devices using advanced semiconductor materials and processing techniques. Summary of the invention

[0012] An image sensor device may include a semiconductor substrate, a pixel region within the semiconductor substrate, a first pinned layer on a surface of the substrate, and a second pinned layer in the semiconductor substrate, the pixel region including a first dopant having a first conductivity type, the first pinned layer including a second dopant having a second conductivity type different from the first conductivity type, the second pinned layer adjacent to at least one side of the pixel region and including a superlattice and the second dopant. The superlattice may include a plurality of stacked layer groups, wherein each layer group includes a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within the lattice of an adjacent base semiconductor portion.

[0013] In an example embodiment, the second pinning layer may extend along opposite sides of the pixel region. More particularly, the second pinning layer may also extend along a bottom of the pixel region. According to another example implementation, the image sensor device may further include an isolation region in the semiconductor substrate adjacent to the second pinning layer. In addition, the second pinning layer may surround the isolation region.

[0014] The first pinning layer may be adjacent to a first end of the pixel region, and the image sensor device may further include a color filter layer on the substrate, the color filter layer adjacent to a second end of the pixel region opposite to the first end. In addition, the image sensor device may further include a lens on the color filter layer.

[0015] In an example embodiment, the image sensor device may further include a transfer gate adjacent to the first pinned layer, a conductive contact spaced apart from the transfer gate, and a conductive via extending between the transfer gate and the conductive contact. In addition, in some embodiments, the second pinned layer may further include fluorine. For example, the base semiconductor portion may include silicon, and the at least one non-semiconductor monolayer may include oxygen.

[0016] In some implementations, the pixel region may include a doped region and an intrinsic region, the doped region including a first dopant, the intrinsic region being between the doped region and the second pinned layer. In an example embodiment, the superlattice may include a first superlattice, and the image sensor device may further include a second superlattice in the intrinsic portion, the second superlattice being similar to the superlattice briefly described above. In some implementations, the second superlattice may at least partially surround the doped region.

[0017] A method for manufacturing an image sensor device may include: forming a pixel region in a semiconductor substrate, the pixel region including a first dopant having a first conductivity type; forming a first pinned layer on a surface of the substrate, the first pinned layer including a second dopant having a second conductivity type different from the first conductivity type; and forming a second pinned layer in the semiconductor substrate, the second pinned layer adjacent to at least one side of the pixel region and including a superlattice and a second dopant. The superlattice may include a plurality of stacked layer groups, wherein each layer group includes a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within the lattice of an adjacent base semiconductor portion.

[0018] In an example embodiment, the second pinning layer may extend along opposite sides of the pixel region. More particularly, the second pinning layer may also extend along a bottom of the pixel region. According to another example implementation, the method may further include an isolation region formed in the semiconductor substrate adjacent to the second pinning layer. In addition, the second pinning layer may surround the isolation region.

[0019] The first pinning layer may be adjacent to a first end of the pixel region, and the method may further include forming a color filter layer on the substrate, the color filter layer adjacent to a second end of the pixel region opposite to the first end. In addition, the method may further include forming a lens on the color filter layer.

[0020] In an example embodiment, the method may further include: forming a transmission gate adjacent to the first pinned layer, forming a conductive contact spaced apart from the transmission gate, and forming a conductive via extending between the transmission gate and the conductive contact. In addition, in some embodiments, the second pinned layer may further include fluorine. For example, the base semiconductor portion may include silicon, and the at least one non-semiconductor monolayer may include oxygen.

[0021] In some implementations, forming the pixel region may include forming an intrinsic region, and forming a doped region including a first dopant in the intrinsic region, wherein the intrinsic region separates the doped region from the second pinned layer. In example embodiments, the superlattice may include a first superlattice, and forming the pixel region may further include forming a second superlattice in the intrinsic portion, the second superlattice being similar to the superlattice briefly described above. In some implementations, the second superlattice may at least partially surround the doped region. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a greatly enlarged schematic cross-sectional view of a superlattice for a semiconductor device according to example embodiments.

[0023] Figure 2 yes Figure 1 A perspective schematic atomic diagram of a portion of the superlattice shown in FIG.

[0024] Figure 3 is a greatly enlarged schematic cross-sectional view of another embodiment of a superlattice according to an example embodiment.

[0025] Figure 4A For bulk silicon as in the prior art and for Figure 1-2 The band structure diagram of the 4 / 1Si / O superlattice shown in Figure 2 is calculated from the γ point (G).

[0026] Figure 4B For bulk silicon as in the prior art and for Figure 1-2 The band structure diagram of the 4 / 1Si / O superlattice calculated from the Z point is shown in Figure 2.

[0027] Figure 4C For bulk silicon as in the prior art and Figure 3 Band structure diagrams of the 5 / 1 / 3 / 1 Si / O superlattice shown in FIG, calculated from both the γ point and the Z point.

[0028] Figure 5 is a schematic cross-sectional view of an image sensor device according to example embodiments.

[0029] Figure 6 is a schematic cross-sectional view of an image sensor device according to another example embodiment.

[0030] Figure 7A to Figure 7E is a series of cross-sectional views illustrating a method of manufacturing an image sensor device according to example embodiments.

[0031] Figure 8A to Figure 8E is a series of cross-sectional views illustrating another method of manufacturing an image sensor device according to example embodiments.

[0032] Fig. 9 is a schematic cross-sectional view of another image sensor device according to example embodiments.

[0033] Fig.10 yes Fig. 9 Schematic cross-sectional view of an alternative embodiment of an image sensor device. DETAILED DESCRIPTION

[0034] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings in which example embodiments are shown. However, embodiments may be implemented in many different forms and should not be construed as being limited to the specific examples described herein. Instead, these embodiments are provided so that this disclosure will be thorough and complete. The same reference numerals always refer to the same elements, and in different embodiments, primes are used to indicate similar elements.

[0035] In general, the present disclosure relates to semiconductor devices having an enhanced semiconductor superlattice therein to provide performance enhancing characteristics. In the present disclosure, the enhanced semiconductor superlattice may also be referred to as an "MST" layer or "MST technology."

[0036] More particularly, the MST technique involves advanced semiconductor materials, such as superlattices 25, described further below. Applicants theorize, but do not wish to be bound by this, that certain superlattices as described herein reduce the effective mass of charge carriers, and that this thereby results in higher charge carrier mobility. Effective mass is variously defined in the literature. As a measure of improvement in effective mass, Applicants use the "conductivity reciprocal effective mass tensor" for electrons and holes, respectively. and

[0037] For electrons, it is defined as:

[0038]

[0039] And for holes, it is defined as:

[0040]

[0041] where f is the Fermi-Dirac distribution, E F is the Fermi energy, T is the temperature, E(k,n) is the energy of an electron in the state corresponding to wave vector k and the nth energy band, the indices i and j refer to the Cartesian coordinates x, y and z, the integration is performed over the Brillouin zone (BZ) and the summation is performed over energy bands above and below the Fermi energy for electrons and holes, respectively.

[0042] Applicants define the conductivity reciprocal effective mass tensor such that for larger values ​​of corresponding components of the conductivity reciprocal effective mass tensor, the tensor component of the conductivity of the material is larger. Again, Applicants theoretically believe, but do not wish to be bound by this, that the superlattice described herein sets the value of the conductivity reciprocal effective mass tensor so as to enhance the conductive properties of the material, such as typically with respect to the preferred direction of charge carrier transport. The reciprocal of the appropriate tensor element is called the conductivity effective mass. In other words, for the purpose of characterizing semiconductor material structures, the conductivity effective mass of electrons / holes, as described above and calculated in the direction of expected carrier transport, is used to distinguish improved materials.

[0043] Applicants have identified improved materials or structures for semiconductor devices. More specifically, Applicants have identified materials or structures having band structures for which the appropriate conductivity effective masses for electrons and / or holes are substantially lower than the corresponding values ​​for silicon. In addition to the enhanced mobility characteristics of these structures, they may also be formed or used in such a manner that they provide piezoelectric, pyroelectric, and / or ferroelectric properties that are beneficial for use in a variety of different types of devices, as further described below.

[0044] Reference now Figure 1 and Figure 2 The material or structure is in the form of a superlattice 25 whose structure is controlled at the atomic or molecular level and can be formed using known atomic or molecular layer deposition techniques. The superlattice 25 includes a plurality of layer groups 45a-45n arranged in a stacked relationship, perhaps with specific reference to Figure 1 This can be best understood by way of a schematic cross-sectional view of the FIG.

[0045] Each layer group 45a-45n of the superlattice 25 illustratively includes a plurality of stacked base semiconductor single layers 46 defining corresponding base semiconductor portions 46a-46n and an energy band modification layer 50 thereon. For clarity of illustration, the energy band modification layer 50 is shown in FIG. Figure 1 It is represented by dots and strokes.

[0046] The energy band modifying layer 50 illustratively comprises a non-semiconductor monolayer constrained within the crystal lattice of an adjacent base semiconductor portion. Figure 2As shown in , "confined within the crystal lattice of adjacent base semiconductor portions" means that at least some of the semiconductor atoms from the opposing base semiconductor portions 46a-46n are chemically bonded together by the non-semiconductor monolayer 50 therebetween. Generally, such formation is made possible by controlling the amount of non-semiconductor material deposited on the semiconductor portions 46a-46n by atomic layer deposition techniques so that not all available semiconductor bonding sites are filled with bonds to non-semiconductor atoms (i.e., less than full or 100% coverage), as further described below. Thus, when an additional monolayer 46 of semiconductor material is deposited on or over the non-semiconductor monolayer 50, the newly deposited semiconductor atoms will fill the remaining empty bonding sites of the semiconductor atoms below the non-semiconductor monolayer.

[0047] In other embodiments, more than one such non-semiconductor monolayer is possible. It should be noted that references herein to non-semiconductor or semiconductor monolayers mean that the material used for the monolayer would be a non-semiconductor or semiconductor if formed in bulk. That is, as will be appreciated by those skilled in the art, a single monolayer of a material such as silicon may not necessarily exhibit the same properties as would be exhibited if formed in bulk or in a relatively thick layer.

[0048] Applicants have theorized, but do not wish to be bound by it, that the band modifying layer 50 and adjacent base semiconductor portions 46a-46n cause the superlattice 25 to have a suitable conductive effective mass for charge carriers in a direction parallel to the layers that is lower than the conductive effective mass that would otherwise exist. Considered from another perspective, the parallel direction is orthogonal to the stacking direction. The band modifying layer 50 can also provide the superlattice 25 with a common band structure while also advantageously serving as an insulator between layers or regions vertically above and below the superlattice.

[0049] In addition, such a superlattice structure can also advantageously act as a barrier to diffusion of dopants and / or materials between layers vertically above and below the superlattice 25. Therefore, it will be appreciated by those skilled in the art that these properties can advantageously allow the superlattice 25 to provide an interface for the high-K dielectric, which not only reduces diffusion of high-K materials into the channel region, but can also advantageously reduce undesirable scattering effects and improve device mobility.

[0050] It is also theorized that semiconductor devices including superlattice 25 may enjoy higher charge carrier mobility based on lower conductivity effective mass than would otherwise be present. In some embodiments, and as a result of the band engineering achieved by the present invention, superlattice 25 may also have a substantially direct band gap that may be particularly advantageous, for example, for optoelectronic devices.

[0051] The superlattice 25 further illustratively includes a capping layer 52 on the upper layer group 45n. The capping layer 52 may include a plurality of base semiconductor monolayers 46. The capping layer 52 may have 2 to 100 base semiconductor monolayers, more preferably 10 to 50 monolayers.

[0052] Each base semiconductor portion 46a-46n may include a base semiconductor selected from a group IV semiconductor, a group III-V semiconductor, and a group II-VI semiconductor. Of course, those skilled in the art will appreciate that the term group IV semiconductor also includes group IV-IV semiconductors. More specifically, for example, the base semiconductor may include at least one of silicon and germanium.

[0053] For example, each band modification layer 50 may include a non-semiconductor selected from oxygen, nitrogen, fluorine, carbon and carbon-oxygen. The non-semiconductor is also expected to be thermally stable during the deposition process of the next layer, so as to facilitate manufacturing. In other embodiments, those skilled in the art will appreciate that the non-semiconductor can be other inorganic or organic elements or compounds compatible with a given semiconductor process. More specifically, for example, the base semiconductor can include at least one of silicon and germanium.

[0054] It should be noted that the term monolayer is meant to include a single atomic layer as well as a single molecular layer. It should also be noted that the band-modifying layer 50 provided by a single monolayer is also meant to include a monolayer in which not all possible sites are occupied (i.e., there is less than full or 100% coverage). For example, with particular reference to Figure 2 Atomic diagram of a semiconductor material, showing a 4 / 1 repeating structure for silicon as the base semiconductor material and oxygen as the band modifier. In the example shown in the diagram, only half of the possible sites for oxygen are occupied.

[0055] In other embodiments and / or when different materials are used, one skilled in the art will appreciate that this one-half occupancy is not necessarily the case. One skilled in the art of atomic deposition will also appreciate that, in fact, even in this schematic diagram, the individual atoms of oxygen in a given monolayer are not precisely arranged along a flat plane. For example, a preferred occupancy range is about one-eighth to one-half of the possible oxygen sites being filled, although other numbers may be used in certain embodiments.

[0056] Silicon and oxygen are currently widely used in conventional semiconductor processes, so manufacturers will be able to easily use these materials described herein. Atomic deposition or monolayer deposition is also now widely used. Thus, those skilled in the art will appreciate that semiconductor devices incorporating superlattices 25 according to the present invention can be easily adopted and implemented.

[0057] Theoretically, but the applicant does not wish to be bound by this, for a superlattice, such as a Si / O superlattice, the number of silicon monolayers should desirably be 7 or less so that the energy bands of the superlattice are common or relatively uniform as a whole to achieve the desired advantages. For Si / O, Figure 1 and Figure 2 The 4 / 1 repeating structure shown in has been modeled to indicate the enhanced mobility of electrons and holes in the X direction. For example, the conductivity effective mass of the electrons (isotropic for bulk silicon) is calculated to be 0.26, and for the 4 / 1 SiO superlattice it is 0.12 in the X direction, resulting in a ratio of 0.46. Similarly, the calculations for holes yield a value of 0.36 for bulk silicon and 0.16 for the 4 / 1 Si / O superlattice, resulting in a ratio of 0.44.

[0058] While this directionally preferred feature may be desirable in certain semiconductor devices, other devices may benefit from a more uniform increase in mobility in any direction parallel to the layer group. Those skilled in the art will appreciate that it may also be beneficial to have increased mobility for both electrons and holes or just one of these types of charge carriers.

[0059] The lower conductivity effective mass of the 4 / 1 Si / O embodiment of the superlattice 25 may be less than two-thirds of the conductivity effective mass that would otherwise occur, and this applies to both electrons and holes. Of course, those skilled in the art will appreciate that the superlattice 25 may also include at least one type of conductivity dopant therein.

[0060] In fact, now refer to Figure 3 , another embodiment of a superlattice 25' according to the present invention having different properties is now described. In this embodiment, a repeating pattern of 3 / 1 / 5 / 1 is shown. More particularly, the lowest base semiconductor portion 46a' has 3 monolayers, while the second lowest base semiconductor portion 46b' has 5 monolayers. This pattern is repeated throughout the superlattice 25'. The band modifying layers 50' can each include a single monolayer. For such a superlattice 25' comprising Si / O, the enhancement of charge carrier mobility is independent of the orientation in the plane of the layers. Figure 3 Those other elements not specifically mentioned in the Figure 1 those elements discussed, and need not be discussed further here.

[0061] In some device embodiments, all base semiconductor portions of the superlattice may be the same number of monolayers thick. In other embodiments, at least some of the base semiconductor portions may be different numbers of monolayers thick. In still other embodiments, all base semiconductor portions may be different numbers of monolayers thick.

[0062] exist Figure 4A to Figure 4C In the paper, the band structure calculated using density functional theory (DFT) is presented. It is well known in the art that DFT underestimates the absolute value of the band gap. Therefore, all bands above the band gap can be shifted by appropriate "scissors". However, the shape of the known bands is much more reliable. The vertical energy axis should be interpreted from this perspective.

[0063] Figure 4A The plots for bulk silicon (shown by the solid line) and for Figure 1 The 4 / 1 Si / O superlattice 25 (indicated by the dashed lines) shown in the figure both have band structures calculated from the γ point (G). The directions relate to the unit cell of the 4 / 1 Si / O structure and not to the conventional unit cell of Si, although the (001) direction in the figure does correspond to the (001) direction of the conventional unit cell of Si, and thus shows the expected location of the Si conduction band minimum. The (100) and (010) directions in the figure correspond to the (110) and (-110) directions of the conventional Si unit cell. Those skilled in the art will appreciate that the bands of Si in the figure are folded to represent them on the appropriate reciprocal lattice directions of the 4 / 1 Si / O structure.

[0064] It can be seen that compared to bulk silicon (Si), the conduction band minimum of the 4 / 1Si / O structure is located at the γ point, while the valence band minimum appears at the edge of the Brillouin zone in the (001) direction, which we call the Z point. It can also be noted that the curvature of the conduction band minimum of the 4 / 1Si / O structure is larger than that of the conduction band minimum of Si due to the band splitting caused by the perturbation introduced by the additional oxygen layer.

[0065] Figure 4B The calculated band structures from point Z are shown both for bulk silicon (solid line) and for the 4 / 1 Si / O superlattice 25 (dashed line). The figure illustrates the enhanced curvature of the valence band in the (100) direction.

[0066] Figure 4C The solid line for bulk silicon and the Figure 3 Figure 2 shows the calculated band structures for both the 5 / 1 / 3 / 1 Si / O structure (dashed lines) and the Z-point for the superlattice 25'. Due to the symmetry of the 5 / 1 / 3 / 1 Si / O structure, the calculated band structures in the (100) and (010) directions are identical. Therefore, the conductivity effective mass and mobility are expected to be isotropic in the plane parallel to the layers, i.e., perpendicular to the (001) stacking direction. Note that in the 5 / 1 / 3 / 1 Si / O case, both the conduction band minimum and the valence band maximum are located at or near the Z-point.

[0067] Although increased curvature is an indication of reduced effective mass, appropriate comparison and distinction can be made through conductivity reciprocal effective mass tensor calculations. This leads applicants to further theorize that the 5 / 1 / 3 / 1 superlattice 25' should be substantially direct bandgap. As will be appreciated by those skilled in the art, the appropriate matrix elements for optical transitions is another indicator of the distinction between direct and indirect bandgap behavior.

[0068] Now see also Figure 5 , the above-described superlattice structure can be advantageously used in the preparation of semiconductor image sensors, such as the preparation of the pinned photodiode (PPD) device 100 shown in the diagram. As background, there are challenges in scaling CMOS image sensors as device dimensions decrease. Various methods are used to help address these challenges, such as deep trench isolation (DTI), fluorine passivation of interface states, low temperature surface treatment prior to low temperature epitaxy, and high-k film passivation for negative charge introduction. However, such processes may have other disadvantages, such as problems with metal generation in high-k (metal oxide) films.

[0069] In the illustrated example, the image sensor device 100 illustratively includes a semiconductor substrate 101, a pixel region 102 in the semiconductor substrate and having a first dopant, the first dopant having a first conductivity type (in this example, N-type). A first pinned layer 103 on the surface of the substrate 101 includes a second dopant, the second dopant having a second conductivity type different from the first conductivity type (in this example, P-type). A shallow trench isolation (STI) region 104 is located in the first pinned layer 103. In addition, a second pinned layer 105 in the semiconductor substrate 101 is adjacent to one or more sides of the pixel region 102, and illustratively includes a superlattice 125 and a semiconductor layer 152 also having a second dopant. The superlattice 125 can be further described above.

[0070] In the illustrated example, the second pinned layer extends along the deep trench isolation (DTI) region 106, the pixel region 102, and the back region of the device 100, which can provide several advantages over conventional approaches. According to one example implementation, the second pinned layer 105 can be formed as a p+ pinned layer by in-situ boron-doped Si epitaxy after deep trench etching, as further discussed below. The second (p+) pinned layer 105 is combined with the superlattice layer 125 to advantageously provide a dopant diffusion barrier between the second pinned layer and the pixel region 102, as well as to help retain these dopants in place to maintain desired operating characteristics. Further details regarding superlattice structures for dopant blocking and retention applications are set forth in U.S. Patents Nos. 10,847,618 and 10,825,901, both of which are also assigned to the present applicant and are hereby incorporated by reference in their entirety.

[0071] The second pinned layer 105 can also provide an electrical connection to the first p+ pinned layer 103 at the surface of the substrate 101 to form a built-in potential between the n-type photodiodes. This advantageously helps avoid the need for high-k films, thereby, for example, reducing the possibility of unwanted metal diffusion into the photodiode region.

[0072] See also Figure 6 In an alternative embodiment of the image sensor device 100', during the formation of the second pinned layer 105', a partial fluorine monolayer may be deposited. For example, during the oxide deposition process, fluorine may diffuse into the oxide / silicon interface (in the case of the Si / O superlattice 125') to passivate the Si dangling bonds at the interface. As will be appreciated by those skilled in the art, passivation of dangling bonds may result in a reduction in GR centers, thereby resulting in a reduction in dark current. The remaining elements 101', 102', 103', 104', 106', and 152' may be the same as described above with reference to FIG. Figure 5 The elements discussed are similar.

[0073] An exemplary low temperature Si epitaxy process for forming the second (p+) pinned layer 105 described above is as follows. Native oxide removal is performed by introducing free radicals formed by a remote plasma of NH3+NF3 at a temperature in the range of 150-250°C. Hydrogen passivation of the Si surface is performed by introducing free radicals formed by a remote plasma of H2 at 350-500°C. Si epitaxy with oxygen monolayer insertion (for Si / O MST films) is performed to form a superlattice 125. For example, a Si precursor of Si2H6 or Si3H8 at a temperature of 400-550°C can be used. The oxygen source can be, for example, diluted O2 or oxygen free radicals formed by a remote plasma of O2 gas at a temperature in the range of 250-600°C. For example, at a temperature in the range of 350-450°C, in-situ boron-doped Si epitaxy with a thickness of 5-30nm can be performed. Example source gases include B2H6+Si2H6 or Si3H8. In the case of the second pinned layer 105', for example, Si epitaxy with a fluorine-inserted monolayer may be performed by a Si epitaxy process using Si2H6 or Si3H8 at 400-450°C. For example, sub-monolayer fluorine doping may be performed using diluted SF6 at a temperature in the range of 200-400°C, or using remote plasma NF3 at a temperature in the range of 250-550°C.

[0074] Go to Figure 7A to Figure 7E , an exemplary method for manufacturing the image sensor device 200 is now described. First, a front surface process is performed to define the pixel region 202, the first pinned layer 203 and the STI region 204, as well as the gate 210 and the metal interconnect layer ( Fig. 7AThe wafer is then bonded to a handle wafer (not shown) and flipped for backside thinning ( Figure 7B ). Deep trench patterning may then be performed, whereby a deep trench 213 adjacent to the right side of the pixel region 202 is produced in the illustrated example.

[0075] The second pinning layer 205 is formed as follows Figure 7C As shown in . For example, native oxide removal is performed at a temperature in the range of 150 to 250°C, such as by remote plasma NH3+NF3. Next, for example, hydrogen passivation of the Si surface is performed at a temperature in the range of 350 to 500°C, such as by remote plasma H2. Then, the superlattice 225 is formed by epitaxial Si monolayer deposition with an inserted oxygen monolayer (in the case of a Si / O superlattice). For example, the Si epitaxial process can be performed with Si2H6 or Si3H8 at a temperature in the range of 400 to 550°C. In one implementation, sub-monolayer oxygen doping can be performed with diluted O2 at a temperature in the range of 500 to 600°C. In another exemplary implementation, for example, oxygen monolayer doping can be achieved with remote plasma O2 at a temperature in the range of 250 to 550°C.

[0076] Then, in-situ boron-doped silicon epitaxy can be performed to form a semiconductor layer 252 with a thickness in the range of about 5 to 30 nm, for example, at a temperature in the range of 350 to 450° C. Example source gases that can be used include B2H6+Si2H6 or Si3H8 to provide, for example, 5E18 to 1E20 / cm 3 In the embodiments described above including fluorine for passivation, for example, in-situ fluorine doped Si epitaxy can be performed with Si2H6 or Si3H8 at a temperature in the range of 400-550°C. For example, different methods can be used, such as sub-monolayer fluorine doping with diluted SF6 at a temperature in the range of 200-400°C. Another method is to use remote plasma NF3 at a temperature in the range of 250-550°C, for example.

[0077] The trenches 213 may then be filled with an insulator to form the DTI region 206, such as an atomic layer deposition (ALD) SiO2 deep trench fill. The color filter 214 deposition is then performed, followed by lens formation ( Fig. 7E ) to complete the image sensor device 200 shown in the diagram.

[0078] According to the current reference Figure 8A to Figure 8EIn another exemplary method described, the metal interconnect layer 211 described above may be replaced with a metal layer 221 that is further separated or spaced from the pixel region 202'. This method may advantageously avoid the need for a low temperature epitaxial process, thereby allowing a conventional epitaxial process to be used instead. More particularly, the formation of the second pinning layer 205' may begin with native oxide removal, such as by DHF wet etching. Hydrogen passivation of the silicon surface may be performed using H2 baking at a temperature in the range of 800 to 900°C. In addition, for example, epitaxial superlattice film growth using Si and oxygen monolayer doping may involve a Si epitaxial process using Si2H6 or Si3H8 at a temperature in the range of 600 to 800°C, followed by sub-monolayer oxygen doping as further described above. For example, an in-situ boron-doped silicon epitaxial process may be performed at a temperature in the range of 600 to 800°C to achieve a thickness in the range of 5 to 30nm, thereby providing a thickness in the range of 5E18 to 1E20 / cm 3 When fluorine passivation is used for interface passivation, in-situ fluorine-doped Si epitaxy can then be performed using a Si epitaxy process at a temperature in the range of 600-800°C using Si2H6 or Si3H8, and sub-monolayer fluorine doping can be performed using thermal NF3 at a temperature in the range of 250-550°C.

[0079] A wafer including a semiconductor substrate 223' and an insulating layer 224' having a contact metal layer 221' therein is bonded to the back side of the insulating layer 212. As shown in the figure, a conductive via 222' electrically connects the transfer gate 210' to the appropriate metal layer 221'.

[0080] Now go to Fig. 9 , another example image sensor device 300 illustratively includes a semiconductor substrate 301 and a pixel region 302 within the semiconductor substrate. More specifically, the pixel region 302 illustratively includes a doped region 302a having a first dopant and an intrinsic (undoped) region 302b, the first dopant having a first conductivity type (in this case, N-type). A first pinned layer 303 on the surface of the substrate 301 includes a second dopant having a second conductivity type (in this case, P-type) different from the first conductivity type. The STI region 304 is within the first pinned layer 303. In addition, a second pinned layer 305 in the semiconductor substrate 301 is adjacent to one or more sides of the pixel region 302, and illustratively includes a superlattice 325 and a semiconductor layer 352 also having a second dopant. The superlattice 325 can be further described above.

[0081] In the illustrated example, the second pinned layer 305 extends along the DTI region 306, the pixel region 302, and the backside region of the device 300, which, as described above, provides several advantages over conventional approaches. Also as described above, the second pinned layer 305 can be formed as a P+ pinned layer by in-situ boron-doped Si epitaxy after deep trench etching, and the second (P+) pinned layer 305 is combined with the superlattice layer 325 to advantageously provide a dopant diffusion barrier between the second pinned layer and the pixel region 302, as well as to help retain these dopants in place to maintain desired operating characteristics.

[0082] Due to the physical separation of the first pinned layer 303 and the second pinned layer 305 (compared to the first pinned layer 103 and the second pinned layer 105 that are in physical contact in the image sensor device 100), and the insertion of the intrinsic region 302b between the N region 302a and the P pinned layer 305a, the image sensor device 300 provides a pinned photodiode plus a PIN photodiode. That is, the intrinsic region 302b physically separates the doped region 302a from the second pinned layer 305. The intrinsic region 302b may include i-Si, SiGe, Si / SiGe, Si / Ge stack, etc., or a combination of such materials, and a superlattice (MST) layer 425 for IR light enhancement.

[0083] More specifically, bulk silicon alone has relatively poor absorption in the wavelength range of 1.3 to 1.55 um. However, incorporating a superlattice 425 into the PIN diode intrinsic region 302b provides significant technical advantages because the MST superlattice material can enhance IR absorption and improve quantum efficiency. For example, ab initio calculations predict that the infrared light absorption of a silicon region incorporating an MST film will increase by approximately 1,000 times compared to bulk silicon alone. In an example configuration, the N-region 302a can be connected to a transfer gate transistor and the second pinned layer 305 is grounded. In an example implementation, the intrinsic region 302b can include i-Si, i-SiGe, or i-SiC and a superlattice 425 to enhance IR absorption.

[0084] Now go to Fig.10, image sensor device 300' provides another example PIN diode with a DTI structure, but here the superlattice layer 425' surrounds or at least partially surrounds the N-region 302a'. As background, the doping profile in an intrinsic device generally needs to be optimized so that the electron-hole generation region remains in an intrinsic state during operation. Phosphorus diffuses very quickly in germanium, resulting in a non-abrupt junction and a higher dopant concentration in the intrinsic region, which effectively increases the device capacitance. However, device 300' advantageously takes full advantage of the superlattice film 425' in the intrinsic region 425' as a diffusion barrier to reduce such diffusion. As described above, the N-region 302a' can be connected to the transfer gate transistor and the second pinned layer 305' is grounded. Again, the intrinsic region 302b' can include i-Si with a superlattice 425', and in another example implementation, the intrinsic region 302b' can include i-Si, i-SiGe or i-SiC and a superlattice 425' to enhance IR absorption.

[0085] As background, a PIN diode is used to convert light energy into electrical energy. The PIN diode has a large depletion region that improves its performance by increasing the volume of light conversion, and it is used in a reverse bias mode. The photocurrent Iph corresponds to the amount of photons absorbed in the i layer to produce electron-hole pairs, where Vsignal = Iph·Rload. With respect to germanium PIN photodiodes, conventionally, photodetectors incorporating compound semiconductor-based materials such as InGaAs are used for wavelengths ranging from the 1.3 μm band to the 1.55 μm band. However, the image sensor device 300, 300' advantageously allows the use of SiGe or Ge and one or more MST superlattice films in the intrinsic region 302b, 302b' to advantageously provide the desired sensitivity to wavelengths from the 1.3 μm band to the 1.55 μm band, but the photodetector cost thereof is relatively low compared to the above-mentioned conventional photodetectors. For example, the near-infrared image sensor implemented by the embodiments presented herein can be used in applications such as IoT devices, robots, AR / VR, and the like.

[0086] With the benefit of the teachings given in the above description and the associated drawings, many modifications and other embodiments of the present invention will occur to those skilled in the art. It should be understood, therefore, that the present invention is not limited to the specific embodiments disclosed, and that various modifications and embodiments are intended to be included within the scope of the appended claims.

Claims

1. An image sensor device, comprising: Semiconductor substrate; a pixel region within the semiconductor substrate, the pixel region comprising a first dopant having a first conductivity type; a first pinned layer on a surface of the substrate, the first pinned layer including a second dopant having a second conductivity type different from the first conductivity type; and A second pinned layer is provided in the semiconductor substrate adjacent to at least one side of the pixel region, the second pinned layer comprising a superlattice and a second dopant, the superlattice comprising a plurality of stacked layer groups, each layer group comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within the lattice of an adjacent base semiconductor portion. 2 . The image sensor device of claim 1 , wherein the second pinned layer extends along opposite sides of the pixel region. 3 . The image sensor device of claim 2 , wherein the second pinned layer extends along a bottom of the pixel region. 4 . The image sensor device of claim 1 , further comprising an isolation region in the semiconductor substrate adjacent to the second pinned layer. 5 . The image sensor device of claim 4 , wherein the second pinning layer surrounds the isolation region.

6. The image sensor device of claim 1, wherein the first pinned layer is adjacent to a first end of the pixel region; and further comprising a color filter layer on the substrate, the color filter layer being adjacent to a second end of the pixel region opposite to the first end.

7. The image sensor device of claim 6, further comprising a lens on the color filter layer.

8. The image sensor device of claim 1, further comprising a transfer gate adjacent to the first pinned layer, a conductive contact spaced apart from the transfer gate, and a conductive via extending between the transfer gate and the conductive contact.

9. The image sensor device of claim 1, wherein the second pinned layer further comprises fluorine.

10. The image sensor device of claim 1, wherein the base semiconductor portion comprises silicon.

11. The image sensor device of claim 1, wherein the at least one non-semiconductor monolayer comprises oxygen. 12 . The image sensor device of claim 1 , wherein the pixel region comprises a doped region and an intrinsic region, the doped region comprising a first dopant, the intrinsic region being between the doped region and the second pinned layer.

13. An image sensor device according to claim 12, wherein the superlattice includes a first superlattice; and also includes a second superlattice in the intrinsic portion, the superlattice including a plurality of stacked layer groups, each layer group including a plurality of stacked basic semiconductor monolayers defining a basic semiconductor portion and at least one non-semiconductor monolayer constrained within the lattice of an adjacent basic semiconductor portion.

14. The image sensor device of claim 13, wherein the second superlattice at least partially surrounds the doped region.

15. A method for manufacturing an image sensor device, comprising: forming a pixel region in a semiconductor substrate, the pixel region comprising a first dopant having a first conductivity type; forming a first pinned layer on a surface of the substrate, the first pinned layer including a second dopant having a second conductivity type different from the first conductivity type; as well as A second pinned layer is formed in the semiconductor substrate on at least one side adjacent to the pixel region, the second pinned layer comprising a superlattice and a second dopant, the superlattice comprising a plurality of stacked layer groups, each layer group comprising a plurality of stacked base semiconductor single layers defining a base semiconductor portion and at least one non-semiconductor single layer constrained within the lattice of an adjacent base semiconductor portion.

16. The method of claim 15, wherein the second pinned layer extends along opposite sides of the pixel region.

17. The method of claim 16, wherein the second pinned layer extends along a bottom of the pixel region.

18. The method of claim 15, further comprising forming an isolation region in the semiconductor substrate adjacent to the second pinned layer.

19. The method of claim 18, wherein the second pinned layer surrounds the isolation region.

20. The method of claim 15, wherein the first pinned layer is adjacent to a first end of the pixel region; and further comprising forming a color filter layer on the substrate, the color filter layer being adjacent to a second end of the pixel region opposite to the first end.

21. The method of claim 20, further comprising forming a lens on the color filter layer.

22. The method of claim 15, further comprising: forming a transfer gate adjacent to the first pinned layer; forming a conductive contact spaced apart from the transfer gate; as well as A conductive via is formed extending between the transfer gate and the conductive contact.

23. The method of claim 15, wherein the second pinned layer further comprises fluorine.

24. The method of claim 15, wherein the base semiconductor portion comprises silicon.

25. The method of claim 15, wherein the at least one non-semiconductor monolayer comprises oxygen.

26. The method of claim 15, wherein forming the pixel region comprises forming an intrinsic region, and forming a doped region comprising a first dopant in the intrinsic region, wherein the intrinsic region separates the doped region from the second pinned layer.

27. A method according to claim 26, wherein the superlattice includes a first superlattice; and wherein forming the pixel region also includes forming a second superlattice in the intrinsic portion, the second superlattice including a plurality of stacked layer groups, each layer group including a plurality of stacked basic semiconductor monolayers defining a basic semiconductor portion and at least one non-semiconductor monolayer constrained within the lattice of an adjacent basic semiconductor portion.

28. The method of claim 27, wherein in some implementations, the second superlattice at least partially surrounds the doped region.

Images