Method for manufacturing plurality of electronic semiconductor chips, electronic semiconductor chip and display

Abstract

The invention relates to a method for producing a plurality of electronic semiconductor chips, comprising the following steps: providing an epitaxial semiconductor layer sequence (1) having a plurality of electronic functional regions (6), which epitaxial semiconductor layer sequence (1) is arranged on or above a substrate (2); -generating a plurality of trenches (9) in the epitaxial semiconductor layer sequence (1), thereby creating a plurality of epitaxial semiconductor layer stacks (10); depositing an absorbing layer (15) on or above the side faces (12) of the epitaxial semiconductor layer stack (10) in the trench (9), the absorbing layer (15) being absorbent for electromagnetic radiation; depositing a further layer (38) on or above the first main surface of the epitaxial semiconductor layer stack (10), the further layer (38) covering the trench (9); generating a bridging element (28) connecting the epitaxial semiconductor layer stack (10) starting from the first main surface (13) to the process wafer (25); and-at least partially removing the substrate (2). In addition, a semiconductor chip and a display are provided.

Description

Technical Field

[0001] A method for manufacturing a plurality of electronic semiconductor chips, a semiconductor chip and a display are provided. Summary of the invention

[0002] The object of the present application is to provide an improved method for manufacturing a plurality of electronic semiconductor chips, in particular for manufacturing electronic semiconductors with low dimensions. In addition, an improved electronic semiconductor chip, in particular with a low edge length, will be provided. Finally, an improved display will be provided, in particular comprising an electronic semiconductor chip with small dimensions.

[0003] These problems are solved by a method having the steps of claim 1 , by an electronic semiconductor chip having the features of claim 10 , by an electronic semiconductor chip having the features of claim 11 and by a display having the features of claim 14 and by a display having the features of claim 15 .

[0004] Improved developments and embodiments of a method for producing a plurality of electronic semiconductor chips, of electronic semiconductor chips and of a display are specified in the respective dependent claims.

[0005] According to an embodiment of the method for producing a plurality of electronic semiconductor chips, an epitaxial semiconductor layer sequence is provided. The epitaxial semiconductor layer sequence comprises a plurality of electronic functional regions. The epitaxial semiconductor layer sequence is arranged on or above a substrate. For example, the epitaxial semiconductor layer sequence comprises silicon or consists of silicon. The layers of the epitaxial layer sequence are stacked on top of each other in a growth direction. A lateral direction is arranged perpendicular to the growth direction.

[0006] The term "above" is used to indicate that elements are thus related to each other, but are not necessarily in direct physical contact with each other. Instead, additional elements may be arranged between them.

[0007] In particular, the method is carried out as a wafer-level batch process for the parallel production of a plurality of electronic semiconductor chips. In particular, the epitaxial semiconductor layer sequence is provided as part of a wafer having a diameter of several inches. Batch processing at the wafer level has the advantage, in particular, of shortening the processing time.

[0008] For example, the substrate is part of a silicon-on-insulator wafer (SOI wafer). Typically, an SOI wafer comprises or consists of a functional layer separated from a handling layer by an oxide layer. If the substrate is part of an SOI wafer, the epitaxial semiconductor layer sequence is, for example, the functional layer, while the substrate is the handling layer.

[0009] Furthermore, the substrate may be a highly doped silicon wafer. The highly doped silicon wafer may be n-doped or p-doped. In particular, the doping concentration of the highly doped silicon wafer is at least 10 16 cm-3 Up to 10 19 .

[0010] According to an embodiment of the method, multiple grooves are generated in the epitaxial semiconductor layer sequence to form multiple epitaxial semiconductor layer stacks. For example, the grooves completely penetrate the epitaxial semiconductor layer sequence so that the substrate is freely accessible. In particular, each groove separates two directly adjacent epitaxial semiconductor layer stacks. The side of the epitaxial semiconductor layer stack simultaneously forms the side of the groove. For example, the grooves are formed by etching (such as dry etching or wet etching). Preferably, each epitaxial semiconductor stack includes at least one electronic functional area. The width of the groove is, for example, between 0.5 micron and 2 microns, including end values. For example, the grooves penetrate the epitaxial semiconductor layer sequence until the substrate. In particular, the grooves completely penetrate the epitaxial semiconductor layer sequence. For example, the substrate forms the bottom surface of the groove.

[0011] The epitaxial layer stack has a first main surface facing away from the substrate and a second main surface opposite to the first main surface. The first main surface and the second main surface are connected to each other via side surfaces arranged along the growth direction.

[0012] According to another embodiment of the method, an absorption layer is deposited on or above the side of the epitaxial semiconductor layer stack in the trench. In particular, the absorption layer is absorptive to electromagnetic radiation. In particular, one absorption layer is arranged on each side of each epitaxial semiconductor layer stack. Preferably, the absorption layer completely covers the side of the epitaxial semiconductor layer stack. However, the thickness of the absorption layer is preferably such that a gap is retained in the lateral direction between two absorption layers arranged in a common trench above the side of different epitaxial semiconductor layer stacks. In other words, the absorption layer does not completely fill the trench.

[0013] According to a further embodiment of the method, a further layer is deposited on or over the first main surface of the epitaxial semiconductor layer stack.As seen in a plan view of the further layer, the further layer covers, in particular completely covers, the trench.

[0014] In particular, the absorption layer comprises a metal material (e.g. tungsten) or consists of the metal material. In addition, the absorption layer may comprise highly doped polysilicon or consist of highly doped polysilicon. For example, the absorption layer has a thickness of at least 50 nanometers. In particular, the absorption layer has a thickness less than 50% of the trench width.

[0015] According to another embodiment of the method, a bridging element is generated, and the epitaxial semiconductor layer stack starting from the first main surface is connected to a processing wafer. The processing wafer may include a crystalline material (such as silicon) or be composed of it. In addition, the processing wafer may include a polymer material (such as a hard plastic or a thermoplastic) or be composed of this polymer material. For example, the processing wafer includes epoxy resin or is composed of epoxy resin. In particular, if the substrate is removed, the processing wafer is configured to mechanically stabilize the wafer compound comprising the epitaxial semiconductor layer stack.

[0016] According to another embodiment of the method, the substrate is at least partially removed. In particular, the substrate is completely removed. For example, the substrate is removed by etching (such as dry etching or wet etching). In addition, mechanical techniques (such as grinding or polishing) can be used to remove the substrate. In particular, chemical mechanical polishing can be used to remove the substrate.

[0017] If an SOI wafer is used, the oxide layer preferably acts as an etch stop layer for the etching process to remove the substrate. If the substrate is part of an SOI wafer, the handle layer can be completely removed, while the oxide layer remains in the wafer compound. In addition, the oxide layer can also be removed.

[0018] If a highly doped silicon wafer is used as substrate, the etching that removes the substrate is stopped, in particular by the doping concentration difference between the substrate and the epitaxial semiconductor layer stack. For example, the etch stop layer of the epitaxial semiconductor layer stack directly adjacent to the substrate needs to be at least 10 18 cm -3 of doping concentration.

[0019] According to another embodiment of the method, the electronic functional area includes or consists of a pn junction, which is configured to detect electromagnetic radiation of a first wavelength range during operation. For example, the first wavelength range is between 400 nanometers and 1100 nanometers and includes a wavelength range of 400 nanometers and 1100 nanometers. In particular, the absorption layer absorbs electromagnetic radiation of the first wavelength range. In this embodiment of the method, a photodiode semiconductor chip as an electronic semiconductor chip is manufactured. In particular, each electronic functional area includes one or more pn junctions for detecting electromagnetic radiation of the first wavelength range during operation. In this embodiment of the method, the absorption layer especially absorbs ambient light to enhance the sensitivity of the pn junction.

[0020] According to a further embodiment of the method, the electronic functional area comprises or consists of an integrated circuit which is configured, for example, for controlling the light-emitting diode chip during operation.

[0021] According to a further embodiment of the method, the absorber layer is electrically conductive. For example, the absorber layer comprises or consists of a metal such as tungsten. The metal absorber layer (eg comprising or consisting of tungsten) may be deposited by atomic layer deposition (ALD).

[0022] If the absorber layer is electrically conductive, an electrically insulating layer is particularly preferably arranged between the side faces of the epitaxial semiconductor layer stack and the absorber layer. The electrically insulating layer between the epitaxial semiconductor layer stack and the absorber layer prevents short circuits of electronic functional areas during operation of the finished electronic semiconductor chip.

[0023] For example, the electrically insulating layer comprises an oxide or a nitride (such as silicon oxide or silicon nitride) or consists of an oxide or a nitride. The electrically insulating layer is deposited, for example, by liquid phase chemical vapor deposition (LPCVD). If the electrically insulating layer is arranged between the epitaxial semiconductor layer stack and the absorption layer on the side or above the epitaxial semiconductor layer stack, the thickness of the absorption layer and the electrically insulating layer together is, for example, at least 50 nanometers. In particular, the trench is not completely filled with the absorption layer and the electrically insulating layer. In other words, the sum of the thickness of the absorption layer and the electrically insulating layer is less than half the trench width.

[0024] According to another embodiment of the method, the other layer is a passivation layer and / or a release layer. The other layer may consist only of a release layer. Alternatively, the other layer may be a layer sequence comprising or consisting of a passivation layer and a release layer. In this case, the passivation layer is deposited before the release layer. For example, the passivation layer is deposited on the insulating layer, and the release layer is deposited on the passivation layer. The passivation layer is deposited, for example, by plasma enhanced chemical vapor deposition (PECVD) or sub-atmospheric chemical vapor deposition (SACVD). For example, the release layer comprises or consists of amorphous silicon. The passivation layer in particular comprises or consists of an electrically insulating material.

[0025] According to a further embodiment of the method, the step of generating the bridge element comprises: depositing a release layer over the first main surface of the epitaxial semiconductor layer stack, the release layer covering, in particular completely covering, the groove as seen in plan view. Furthermore, generating a recess in the release layer, the recess completely penetrating the release layer. In particular, the recess is arranged in the release layer starting from the side of the epitaxial semiconductor layer stack.

[0026] According to another embodiment of the method, a polymer layer is deposited on the release layer. In particular, the material of the polymer layer fills, preferably completely fills, the recess in the release layer. After the polymer layer is deposited, the release layer is removed so that the epitaxial semiconductor layer stack is connected to the processing wafer by a bridging element. The bridging element is formed in particular by the material of the polymer layer in the recess of the release layer. For example, the polymer layer includes benzocyclobutene (BCB) or is composed of benzocyclobutene. For example, the polymer layer is deposited by a spin coating process.

[0027] According to a further embodiment of the method, an adhesive layer is deposited between the polymer layer and the release layer. The adhesive layer has an enhanced adhesion to the polymer layer compared to the adhesion between the polymer layer and the release layer.

[0028] According to a further embodiment of the method, a handle wafer is deposited on or over the polymer layer before removing the substrate.

[0029] According to a further embodiment of the method, a filter layer is deposited on or above the second main surface of the epitaxial semiconductor layer stack. The filter layer covers, particularly preferably completely covers, the groove. According to a further embodiment of the method, the filter layer above the groove is removed, for example by etching, to expose the release layer in the groove. For example, the filter layer filters a portion of the electromagnetic radiation in the first wavelength range. For example, the filter layer is an interference filter layer.

[0030] According to an embodiment of the method, the electronic functional area comprises a pn junction configured to detect electromagnetic radiation of the first wavelength range during operation. In other words, the electronic functional area is a photodiode. Preferably, the filter layer is an interference filter layer that filters a portion of the electromagnetic radiation of the first wavelength range.

[0031] Using this method, multiple electronic semiconductor chips can be manufactured. In particular, the method generates multiple discrete electronic semiconductor chips that are only connected to the processing wafer via the bridging element. The polymer bridging element is particularly small. For example, the size of the bridging element is several microns, for example, between 1 micron and 5 microns and including 1 micron and 5 microns. Therefore, the electronic semiconductor chip can be easily removed from the processing wafer, for example, by a polymer stamp. For example, the adhesion of the polymer stamp made of polydimethylsiloxane (PDMS) to the electronic semiconductor chip is greater than the mechanical connection force applied by the bridging element. In this way, the electronic semiconductor chip can be removed from the processing wafer and transferred to other elements, such as electrical connection carriers, such as printed circuit boards (PCBs) by the polymer stamp. In particular, the polymer stamp allows the electronic semiconductor chip with small size to be transferred to other elements very accurately from the processing wafer. For example, the thickness of the electronic semiconductor chip does not exceed 20 microns, and the edge length of the electronic semiconductor chip does not exceed 100 microns.

[0032] Using the present method, it is particularly easy to deposit an absorption layer on or above the side of the epitaxial semiconductor layer stack. This is achieved in particular by filling the trench with the absorption layer. The absorption layer on the side of the epitaxial semiconductor layer stack is particularly preferably at least to reduce the light penetrating into the electronic functional area. This is particularly advantageous if the electronic functional area comprises a pn junction or an integrated circuit or consists of a pn junction or an integrated circuit. The absorption layer preferably blocks electromagnetic radiation (such as light) from penetrating into the pn junction or the integrated circuit. The sensitivity of such a photodiode comprising a pn junction or the reliability of an electronic semiconductor chip comprising an integrated circuit as an electronic functional area is enhanced.

[0033] Furthermore, using the present method, a high performance interference filter can be easily integrated on or above the first main surface of the epitaxial semiconductor layer stack. Using the present method, an electronic semiconductor chip can be manufactured. Therefore, the features and embodiments disclosed in conjunction with the method can also be implemented by the electronic semiconductor chip, and vice versa.

[0034] According to one embodiment, an electronic semiconductor chip comprises: an epitaxial semiconductor layer stack having an electronic functional region, the electronic functional region comprising a pn junction, the pn junction being configured to detect electromagnetic radiation in a first wavelength range during operation. For example, the pn junction is configured to detect electromagnetic radiation in a wavelength range between 400 nm and 1100 nm. In particular, the epitaxial semiconductor layer stack comprises or consists of silicon.

[0035] According to a further embodiment of the electronic semiconductor chip, the absorption layer covers the side of the epitaxial semiconductor layer stack. The absorption layer absorbs electromagnetic radiation of the first wavelength range. For example, the absorption layer absorbs all or only some wavelengths from the first wavelength range. In addition, the absorption layer may absorb only a certain proportion of the electromagnetic radiation intensity or the entire electromagnetic radiation intensity.

[0036] According to another embodiment, the electronic semiconductor chip includes at least two electrical mounting pads, which are configured for the electronic semiconductor chip to be connected to another element such as a connection carrier. The electrical mounting pads are arranged at the rear side surface of the electronic semiconductor chip. The rear side surface of the electronic semiconductor chip extends parallel to the first main surface and the second main surface of the epitaxial semiconductor layer stack. For example, the electronic semiconductor chip is connected to another connection carrier by welding the electrical mounting pads.

[0037] According to a further embodiment, the electronic semiconductor chip comprises a radiation entrance surface, which is configured to transmit electromagnetic radiation to be detected to a functional electronic region such as a pn junction. In particular, the radiation entrance surface is arranged on a front side surface of the electronic semiconductor chip opposite to the back side surface. The front side surface and the back side surface of the electronic semiconductor chip are connected to each other via a side surface of the electronic semiconductor chip.

[0038] For example, the absorber layer at least partially forms a side surface of the electronic semiconductor chip. In particular, the absorber layer is freely accessible at the side surface of the electronic semiconductor chip.

[0039] The electronic functional area may also include an integrated circuit. In particular, the integrated circuit is configured to control the light emitting diode chip.

[0040] According to a further embodiment, the electronic semiconductor chip comprises an electrical mounting surface configured for mounting a light emitting diode chip to be controlled, wherein the electrical mounting surface is arranged on a front side surface of the electronic semiconductor chip opposite to the rear side surface. For example, the mounting surface comprises at least two electrical connection areas, which are configured for an electrically conductive and mechanically stable connection of the LED chip to be controlled.

[0041] According to a further embodiment, the thickness of the electronic semiconductor chip does not exceed 20 micrometers.

[0042] According to a further embodiment, the edge length of the electronic semiconductor chip does not exceed 100 micrometers.

[0043] In particular, the light-emitting diode chips to be controlled are micro-LEDs.

[0044] Broadly speaking, a micro-LED can be considered as any light emitting diode (LED) with particularly small dimensions, typically not a laser.

[0045] Typically and in addition to the size, it is a very important criterion that the growth substrate is removed from the micro-LED so that a typical height of such a micro-LED is, for example, in the range of 1.5 micrometers to 10 micrometers. Furthermore, the electronic semiconductor chip described in the present invention can be substrate-free, in particular growth-free. The electronic semiconductor chip has a height in the range of, for example, 1.5 micrometers to 10 micrometers.

[0046] In principle, a micro-LED does not necessarily have to have a rectangular radiation emitting surface. Typically, for example, an LED may have a radiation emitting surface, wherein any lateral extent of the radiation emitting surface in a plan view of the layers of the layer stack is less than or equal to 100 microns or less than or equal to 70 microns. Furthermore, the electronic semiconductor chip described in the present invention may have a substrate area with a lateral extension less than or equal to 100 microns or less than or equal to 70 microns. For example, the edge length of the electronic semiconductor chip is less than or equal to 100 microns or less than or equal to 70 microns.

[0047] For example, in the case of rectangular micro-LEDs, edge lengths of less than or equal to 70 micrometers or less than or equal to 50 micrometers are often cited as criteria, in particular in a plan view of a layer of the layer stack.

[0048] In most cases, such micro-LEDs are arranged on a wafer in a detachable holding structure, which allows for a non-destructive arrangement of the μLEDs.

[0049] Currently, micro-LEDs are mainly used in displays. Micro-LEDs form pixels or sub-pixels and emit light of a defined color. The small pixel size and high density at close range make micro-LEDs particularly suitable for small monolithic displays for AR applications, especially data glasses. In addition, other applications are being developed, especially for use in data communications or pixelated lighting applications.

[0050] Different spellings of micro-LED can be found in the relevant literature, such as μLED, μ-LED, uLED, u-LED or micro light-emitting diode.

[0051] The electronic semiconductor chip is configured in particular to be incorporated into a display. Therefore, embodiments and features described in conjunction with the electronic semiconductor chip are also disclosed in conjunction with the display, and vice versa.

[0052] According to an embodiment, the display comprises an electronic semiconductor chip. In particular, the electronic semiconductor chip comprises a pn junction configured to detect a parameter of electromagnetic radiation, such as ambient light. For example, the electronic semiconductor chip is configured to measure the intensity or spectral composition of the ambient light.

[0053] According to a further embodiment, the display comprises: a light emitting diode chip, which emits electromagnetic radiation in the second wavelength range during operation. For example, the light emitting diode chip is a micro-LED. Particularly preferably, the display comprises a plurality of light emitting diode chips, which form pixels of the display. For example, the light emitting diode chips emit light of different colors, such as red light, green light and / or blue light. For example, one pixel of the display comprises at least one red light emitting chip, at least one green light emitting chip and at least one blue light emitting chip.

[0054] According to a further embodiment of the display, the electronic functional area of ​​the epitaxial semiconductor layer stack of the electronic semiconductor chip comprises an integrated circuit configured to control the light emitting diode chip. In this case, the electronic semiconductor chip and the light emitting diode chip are particularly preferably stacked on top of each other.

[0055] Particularly preferably, the light emitting diodes also have very low dimensions, such as a thickness of no more than 20 micrometers and an edge length of no more than 100 micrometers. If the electronic semiconductor chip and the light emitting diode chip are integrated in a common display, they preferably have the same or similar dimensions. Preferably, the dimensions of the electronic semiconductor chip do not exceed the center-to-center spacing between consecutive light emitting diode chips.

[0056] The electronic semiconductor chip may also be configured for use in augmented reality, virtual reality applications and / or micro-projectors, in particular for controlling light emitting diode chips or detecting electromagnetic radiation, such as ambient light. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Further advantageous embodiments and developments of the method for producing a plurality of electronic semiconductor chips, of the electronic semiconductor chip and of the display result from the exemplary embodiments described below in conjunction with the figures.

[0058] Figures 1 to 36 Stages of a method for manufacturing a plurality of electronic semiconductor chips according to an exemplary embodiment are schematically illustrated.

[0059] Fig.37 and Fig.38 An electronic semiconductor chip according to an exemplary embodiment is schematically shown.

[0060] Fig.39 A schematic cross-sectional view of an electronic semiconductor chip according to a further exemplary embodiment is shown.

[0061] Fig.40 Stages of a method for producing a plurality of electronic semiconductor chips according to a further exemplary embodiment are shown.

[0062] Fig.41 A display according to an exemplary embodiment is shown.

[0063] In the drawings, identical or similar elements and functionally identical elements are denoted by the same reference numerals. The drawings and the proportions of the elements shown in the drawings should not be regarded as being shown to scale. On the contrary, individual elements (especially layers) may be shown exaggerated in magnitude for better presentation and / or better understanding. DETAILED DESCRIPTION

[0064] according to Figures 1 to 36 In a first step, an epitaxial semiconductor layer sequence 1 ( Figure 1 and Figure 2 ). An epitaxial semiconductor layer sequence 1 is arranged on a substrate 2. An oxide layer 3 is arranged between the substrate 2 and the epitaxial semiconductor layer sequence 1. Currently, the epitaxial semiconductor layer sequence 1 is based on silicon.

[0065] The epitaxial layers of the epitaxial semiconductor layer sequence 1 are stacked on top of one another in a growth direction GD. Perpendicular to the growth direction GD, a lateral direction LD extends.

[0066] Currently, the epitaxial semiconductor layer sequence 1 and the substrate 2 and the oxide layer 3 are part of a SOI wafer, for example, with a diameter of about 8 inches. The substrate 2 is a handle layer of the SOI wafer and the epitaxial semiconductor layer sequence 1 is a functional layer of the SOI wafer.

[0067] For example, the epitaxial semiconductor layer sequence 1 is p-doped. For example, the epitaxial semiconductor layer sequence 1 is p-doped with at least one of the following elements: B, In. The p-doping concentration is, for example, between 10 12 cm -3 with 10 14 cm -3 between.

[0068] In the p-type doped epitaxial semiconductor layer sequence 1, an n-type doping region 4 is arranged, for example, by ion implantation or ion diffusion, to form a pn junction 5 as an electronic functional region 6 in the epitaxial semiconductor layer sequence 1. For example, the n-type doping region 4 includes one of the following chemical elements as an n-type dopant: P, As, Sb. The n-type doping concentration is, for example, between 10 12 cm -3 with 10 14 cm -3 between.

[0069] Figure 1 The example shows Figure 2 2 is a cross-sectional view of an extract of an SOI wafer having three electronic functional regions 6 along the line AA' in FIG. 2. However, the SOI wafer as a whole includes a greater number of electronic functional regions 6 (eg, several hundred or several thousand).

[0070] Figure 2 It is shown as an example Figure 1 1 and a perspective view of only one electronic functional area 6 of an epitaxial semiconductor layer sequence 1. In addition, further method steps are respectively shown in a sectional view along the line AA' of an excerpt of a wafer with three electronic functional areas 6 and in a perspective view of one functional area 6. The line AA' indicating the section of the sectional view is shown in the corresponding corresponding perspective view.

[0071] In a further step, an n-doped contact region 7 is inserted into the n-doped region 4, for example by ion implantation or ion diffusion. In addition, a p-doped contact region 8 ( Figure 3 and Figure 4 ).

[0072] Then, trenches 9 are generated in the epitaxial semiconductor layer sequence 1 to form a plurality of epitaxial semiconductor layer stacks 10 ( Figure 5 and Figure 6 ). In the present case, the trench 9 penetrates the epitaxial semiconductor layer sequence 1 as far as the substrate 2 . In particular, the trench 9 completely penetrates the epitaxial semiconductor layer sequence 1 and the oxide layer 3 .

[0073] In a further step, an electrical insulating layer 11 is deposited on the side surfaces 12 of the epitaxial semiconductor layer stack 10. The electrical insulating layer 11 completely covers the side surfaces 12 of the epitaxial semiconductor layer stack 10. For example, in a first step, the material of the electrical insulating layer 11 is applied to the entire surface of the wafer compound so that in addition to the first main surface 13 and the side surfaces 12 of the epitaxial semiconductor layer stack 10, the bottom surface 14 of the trench 9 is also covered. The material of the electrical insulating layer 11 is etched back so that the electrical insulating layer 11 only covers the side surfaces 12 of the epitaxial semiconductor layer stack 10 and the first main surface 13 of the epitaxial semiconductor layer stack 10, while the bottom surface 14 of the trench 9 is free of the electrical insulating layer 11 ( Figure 7 and Figure 8 ).

[0074] Then, an absorber layer 15 is applied over the side faces 12 of the epitaxial semiconductor layer stack 10. The absorber layer 15 completely covers the side faces 12 of the epitaxial semiconductor layer stack 10, such as for example Fig. 9 and Fig.10 As shown in . For example, the absorption layer 15 is made of tungsten and is conductive. The electrical insulation layer 11 isolates the absorption layer 15 from the epitaxial semiconductor layer stack 10 to prevent short circuits.

[0075] In order to deposit the absorption layer 15 on or above the side faces 12 of the epitaxial semiconductor stack 10, tungsten is deposited over the entire surface of the wafer compound and in particular on or above the epitaxial semiconductor layer stack 10 and on the bottom surface 14 of the trench 9. Then, tungsten is removed above the first main surface 13 of the epitaxial semiconductor layer stack 10 and from the bottom surface 14 of the trench 9. In this way, only the side faces 12 of the epitaxial semiconductor layer stack 10 are completely covered by the absorption layer 15.

[0076] The insulating layer 11 and the absorption layer 15 form a layer sequence on the side surface 12 of the epitaxial semiconductor layer stack 10. The layer sequence does not completely fill the trench 9 in the lateral direction LD. On the contrary, there is still a gap 16 between two directly adjacent layer sequences deposited on directly adjacent epitaxial semiconductor layer stacks 10. In other words, the epitaxial semiconductor layer stacks 10 are laterally separated from each other by the gap 16.

[0077] like Fig.11 and Fig.12 As shown in FIG. 1 , a further layer 38 (in particular a passivation layer 17 ) is deposited, covering the first main surface 13 of the epitaxial semiconductor layer stack 10 and the trenches 9 . Figures 1 to 10In the plan view of the wafer compound formed by the method steps, the passivation layer 17 forms a closed surface. In particular, the gap 16 between two directly adjacent epitaxial semiconductor layer stacks 10 is covered by the passivation layer 17, but is not filled by the passivation layer 17. For example, the passivation layer 17 includes an electrically insulating material (such as an oxide or a nitride), or is composed of an electrically insulating material. For example, the passivation layer 17 has a thickness between 50 nanometers and 800 nanometers.

[0078] For example Fig.13 and Fig.14 As shown in FIG. 1 , an opening 18 is etched in the passivation layer 17 and the insulating layer 11. The opening 18 completely penetrates the passivation layer 17 and the insulating layer 11. The opening 18 is filled with a tungsten plug 19 for electrical connection of the epitaxial semiconductor layer stack 10. Then, a metal contact layer 20 ( Fig.15 and Fig.16 ).

[0079] Then, a release layer 21 is deposited over the first main surface 13 of the epitaxial semiconductor layer stack 10. Figure 1 and Fig.16 The wafer compound formed during the described method steps is completely covered by a release layer 21. The release layer 21 is made of amorphous silicon, for example, and has a thickness comprised between 100 and 800 nanometers.

[0080] Then, the recess 22 is formed in the release layer 21. In particular, the recess 23 is formed starting from the side surface 12 of the epitaxial semiconductor layer stack 10 ( Fig.19 and Fig. 20 ). To explain the formation of the recess 22 in more detail, the line AA' indicating the cross section of the cross-sectional view in the perspective view is moved from the formation area of ​​the electrical mounting pad to the recess 22 in the perspective view of the method steps described below.

[0081] The recess 22 completely penetrates the release layer 21 , so that the underlying passivation layer 17 is directly accessible through the recess 22 .

[0082] like Fig.21 and Fig. 22 As shown in FIG, an adhesion layer 23 is deposited on the release layer 21. The adhesion layer 23 has better adhesion to the subsequently deposited polymer layer 24 and then the release layer 17. Therefore, the adhesion layer enhances the adhesion of the to-be-deposited polymer layer 24. The adhesion layer 23 comprises, for example, silicon dioxide or another dielectric material, or consists of silicon dioxide or another dielectric material and has a thickness between 50 nanometers and 200 nanometers.

[0083] In a further step, a polymer layer 24 (for example comprising BCB or consisting of BCB) is applied by spin coating to the entire wafer compound ( Fig.23 and Fig.24 ). For example, the polymer layer 24 has a thickness between 5 micrometers and 100 micrometers.

[0084] Then, the handle wafer 25 is connected to the polymer layer 24 ( Fig.25 and Fig.26 ).

[0085] Then, flip the wafer compound, such as Fig. 27 and Fig.28 It is schematically shown in FIG.

[0086] Then, the substrate 2 is removed, for example, by grinding, polishing or etching. During the etching of the substrate 2, the oxide layer 3 forms an etching stop layer (see Fig.29 and Fig.30 ). After the substrate 2 is removed, the epitaxial semiconductor layer stacks 10 are separated from one another by gaps 16. The passivation layer 17 is freely accessible through the gaps 16.

[0087] The oxide layer 3 can also be removed in a separate step or can remain in the wafer compound. Currently, the oxide layer 3 remains in the wafer compound.

[0088] After the substrate 2 is removed, a filter layer 26 is applied over the first main surface 13 of the epitaxial semiconductor layer stack 10. The filter layer 26 is applied on the oxide layer 3 and first completely covers the oxide layer 3 ( Fig.31 and Fig.32 ). The filter layer 26 is currently located in the interference filter layer.

[0089] A further etching step (for example a mesa etching step) is performed so that the release layer 21 is exposed in the region of the trench 9 ( Fig.33 and Fig.34 ).

[0090] Then, the release layer 21 ( Fig.35 and Fig.36 ). A wafer compound is achieved in which discrete electronic semiconductor chips 27 are connected to the handling wafer 25 only via bridge elements 28 formed of polymer material in recesses 22 in the release layer 21. The electronic semiconductor chips 27 can be transferred to other elements, such as a connection carrier, by means of the polymer stamp.

[0091] according to Fig.37 and Fig.38 The electronic semiconductor chip 27 of the exemplary embodiment may be utilized Figures 1 to 36 The method of the exemplary embodiment is manufactured.

[0092] according to Fig.37 and Fig.38The electronic semiconductor chip 26 of the exemplary embodiment of comprises an epitaxial semiconductor layer stack 10 having an electronically functional region 6. The electronically functional region 6 consists of a pn junction 5 which is configured for detecting electromagnetic radiation of a first wavelength range during operation.

[0093] The first main surface 13 and the side faces 12 of the epitaxial semiconductor layer stack 10 are completely covered by an electrically insulating layer 11, such as a silicon oxide layer. An absorption layer 15 is deposited above the side faces 12 of the epitaxial semiconductor layer stack 10 on the electrically insulating layer 11. The absorption layer 15 now completely covers the side faces 12 of the epitaxial semiconductor layer stack 10. The absorption layer 15 absorbs electromagnetic radiation of a first wavelength range to be detected by the pn junction 5 during operation. For example, the absorption layer 15 consists of tungsten or highly doped polysilicon.

[0094] On a second main surface 29 of the epitaxial semiconductor layer stack 10 , which is opposite the first main surface 13 of the epitaxial semiconductor layer stack 10 , an oxide layer 3 , for example a silicon dioxide layer, is arranged.

[0095] A passivation layer 17 is applied over the first main surface 13 of the epitaxial semiconductor layer stack 10 on the electrically insulating layer 11. Openings 18 are arranged in the insulating layer 11 and the passivation layer 17, which are filled with tungsten plugs 19 and are electrically conductively connected to the further p-doped regions 4 and the n-doped regions 7 in the epitaxial semiconductor layer stack 10. Furthermore, according to Fig.37 and Fig.38 The electronic semiconductor chip 27 of the exemplary embodiment of FIG. 2 comprises a metal contact layer 20 on a tungsten plug 19 . The tungsten plug 19 and the metal contact layer 20 form an electrical mounting pad 30 at a rear side surface 31 of the electronic semiconductor chip 27 .

[0096] Furthermore, the electronic semiconductor chip 27 comprises a filter layer 26. The surface of the filter layer 26 forms a radiation entrance surface 32 of the electronic semiconductor chip 26, which is configured to transmit electromagnetic radiation to be detected. The radiation entrance surface 32 is arranged on a front side surface 33 of the electronic semiconductor chip 27 opposite the rear side surface 31.

[0097] Fig.37 and Fig.38 The electronic semiconductor chip has small dimensions. In particular, the thickness D of the electronic semiconductor chip does not exceed 20 micrometers, while the edge length EL of the electronic semiconductor chip is at most 100 micrometers.

[0098] According to Fig.37 and Fig.38 The electronic semiconductor chip 27 of the exemplary embodiment is compared according to Fig.39The electronic semiconductor chip 27 of the exemplary embodiment of the embodiment of the present invention comprises an electronic functional area 6 consisting of an integrated circuit 34. The integrated circuit 34 is in particular configured to control a light emitting diode chip 35. The front side surface 33 of the electronic semiconductor chip 26 comprises an electrical mounting surface 36 which is configured for mounting a light emitting diode chip 35 to be controlled by the integrated circuit 34.

[0099] Fig.40 The following schematically shows the stages of a method according to a further exemplary embodiment. In particular, the epitaxial semiconductor layer sequence 1 is connected to the Figure 1 Compared to the method steps shown in , the sequence is applied directly to the substrate 2 without an oxide layer 3 in between. In this case, the substrate 2 is, for example, a highly doped silicon substrate 2, which can be removed by etching (for example dry or wet chemical etching). During the method, an etching stop after the removal of the substrate 2 is achieved by the contrast formed by the high concentration of dopants in the substrate 2 compared to the low concentration of dopants in the epitaxial semiconductor layer sequence 1. For example, the dopant in the substrate 2 has a concentration of about 10 14 cm -3 The concentration of the dopant in the epitaxial semiconductor layer sequence 2 is about 10 16 cm -3 concentration.

[0100] from Fig.40 Starting from the method steps shown in Figures 3 to 36 The electronic semiconductor chip 27 is described as being manufactured, omitting the oxide layer 3 .

[0101] according to Fig.41 The display of the exemplary embodiment of comprises a connection carrier 36 , such as a printed circuit board. A plurality of electronic semiconductor chips 27 are applied to the connection carrier 36 , in particular via electrically conductive and mechanically stable electrical mounting pads 30 arranged on the rear side surfaces 31 of the electronic semiconductor chips 27 .

[0102] Some electronic semiconductor chips 26 include an integrated circuit 34 as an electronic functional area 6, such as, for example Fig.39 As shown in . On the electrical mounting surface 36 of the electronic semiconductor chip including the integrated circuit 34 a light emitting diode chip is mounted.

[0103] The electronic semiconductor chip 27 (and in particular the integrated circuit 34 of the electronic semiconductor chip 27 ) is configured to control the light-emitting diode chip 35 during operation of the display.

[0104] The electronic semiconductor chip 27 and the light emitting diode chip 35 have similar or equal dimensions, so that they can be stacked on top of each other in an easy manner.

[0105] In addition, according to Fig.41The display of the exemplary embodiment of comprises an electronic semiconductor chip 27' having a pn junction 5 for light detection as an electronic functional area 6. The electronic semiconductor chip 27' is arranged laterally in a stack of electronic semiconductor chips 27 having an integrated circuit 34 and a light-emitting diode chip 35 and is configured, for example, to measure ambient light.

[0106] This application claims the priority of German application DE 102022131371.9, the disclosure content of which is incorporated herein by reference.

[0107] The invention is not limited to the description of the embodiments. Instead, the invention includes every new feature and every combination of features, in particular every combination of features in the claims, even if this feature or combination of features itself is not explicitly mentioned in the claims or the embodiments.

[0108] Reference numerals

[0109] 1 Epitaxial semiconductor layer sequence

[0110] 2 Substrate

[0111] 3 Oxide layer

[0112] 4 n-type doping region

[0113] 5 pn junction

[0114] 6 Electronic Function Area

[0115] 7 n-type doped contact region

[0116] 8 p-type doped contact region

[0117] 9 Grooves

[0118] 10 Epitaxial semiconductor layer stack

[0119] 11 Electrical insulation layer

[0120] 12 Side view of epitaxial semiconductor layer stack

[0121] 13. First main surface of epitaxial semiconductor layer stack

[0122] 14 Bottom surface of groove

[0123] 15 Absorption layer

[0124] 16 Gap

[0125] 17 Passivation layer

[0126] 18 Opening

[0127] 19 Tungsten Plug

[0128] 20 Metal contact layer

[0129] 21 Release layer

[0130] 22 recess

[0131] 23 Adhesion layer

[0132] 24 Polymer layer

[0133] 25 Processing wafer

[0134] 26 Filter layer

[0135] 27, 27' Electronic semiconductor chips

[0136] 28 Bridge Element

[0137] 29 Second main surface of the epitaxial semiconductor layer stack

[0138] 30 Electrical mounting pads

[0139] 31 Rear surface

[0140] 32 Radiation incident surface

[0141] 33 Front side surface of electronic semiconductor chip

[0142] 34 Integrated Circuits

[0143] 35 LED chips

[0144] 36 Electrical mounting surface

[0145] 37 Connecting carrier

[0146] 38 Additional Layers

[0147] GD Growth Direction

[0148] LD Transverse Direction

[0149] D Thickness

[0150] EL Edge length.

Claims

1. A method for manufacturing a plurality of electronic semiconductor chips (27, 27'), comprising the following steps: - providing an epitaxial semiconductor layer sequence (1) having a plurality of electronically functional regions (6), said epitaxial semiconductor layer sequence (1) being arranged on or above a substrate (2), - generating a plurality of trenches (9) in the epitaxial semiconductor layer sequence (1) so as to create a plurality of epitaxial semiconductor layer stacks (10), wherein the trenches (9) completely penetrate the epitaxial semiconductor layer sequence (1) so that the substrate is freely accessible, - depositing an absorption layer (15) on or over the side surfaces (12) of the epitaxial semiconductor layer stack (10) in the trench (9), the absorption layer (15) being absorptive to electromagnetic radiation, - depositing a further layer (38) on or over the first main surface of the epitaxial semiconductor layer stack (10), the further layer (38) covering the trench (9), - generating a bridge element (28) connecting the epitaxial semiconductor layer stack (10) starting from the first main surface (13) to a handle wafer (25), and - at least partially removing the substrate (2).

2. The method according to the preceding claim, wherein: - the electronically functional region (6) comprises a pn junction (5) configured to detect electromagnetic radiation of a first wavelength range during operation, and - The absorption layer (15) absorbs electromagnetic radiation in the first wavelength range.

3. The method according to the preceding claim, wherein: - the absorbent layer (15) is electrically conductive, and - depositing an electrically insulating layer (11) between the epitaxial semiconductor layer stack (10) and the absorber layer (15).

4. A method according to any one of the preceding claims, wherein: The further layer (38) is a passivation layer (17) and / or a release layer (21).

5. A method according to any one of the preceding claims, wherein: The steps of generating the bridge element (28) include: - depositing the release layer (21) on or over the first main surface (13) of the epitaxial semiconductor layer stack (10), the release layer (21) covering the trench (9), - generating a recess (22) in the release layer (21), the recess (22) completely penetrating the release layer (21), - depositing a polymer layer (24) on or over the release layer (21), the material of the polymer layer (24) filling the recesses (22) in the release layer (21), - removing the release layer (21) so that the epitaxial semiconductor layer stack (10) is connected to the handle wafer (25) via the bridge element (28) formed by the material of the polymer layer (24) in the recess (22) of the release layer (21).

6. A method according to the preceding claim, wherein: An adhesive layer (23) is deposited between the polymer layer (24) and the release layer (21), and the adhesive layer (23) has enhanced adhesion to the polymer layer (24) and the release layer (21) compared to the adhesion between the polymer layer (24) and the release layer (21).

7. The method according to claim 5 or 6, wherein: The handle wafer (25) is deposited on or over the polymer layer (24) prior to removing the substrate (2).

8. The method according to any one of the preceding claims, further comprising the steps of: A filter layer (26) is deposited on or over the second main surface (29) of the epitaxial semiconductor layer stack (10), wherein the filter layer (26) covers the groove (9).

9. The method according to the preceding claim, wherein: - the electronically functional region (6) comprises a pn junction (5) configured to detect electromagnetic radiation of a first wavelength range during operation, and The filter layer (26) is an interference filter layer that filters a portion of the electromagnetic radiation in the first wavelength range.

10. An electronic semiconductor chip (27, 27'), comprising: - an epitaxial semiconductor layer stack (10) having an electronically functional region (6), comprising a pn junction (5) configured to detect electromagnetic radiation of a first wavelength range during operation, an absorption layer (15) covering a side surface (12) of the epitaxial semiconductor layer stack (10), the absorption layer (15) absorbing electromagnetic radiation in the first wavelength range, wherein the absorption layer (15) at least partially forms a side surface of the electronic semiconductor chip, at least two electrical mounting pads (30) configured for electrically conductive and mechanically stable connection of the electronic semiconductor chip (27, 27'), the electrical mounting pads (30) being arranged on a rear side surface (31) of the electronic semiconductor chip (27, 27'), A radiation entrance surface (32) configured for transmitting electromagnetic radiation to be detected, said radiation entrance surface (32) being arranged on a front side surface (33) of said electronic semiconductor chip (27, 27') opposite said rear side surface (31).

11. An electronic semiconductor chip (27, 27'), comprising: - an epitaxial semiconductor layer stack (10) having an electronic functional area (6) comprising an integrated circuit (34) configured to control a light-emitting diode chip (35), - an absorption layer (15) covering the side surfaces (12) of the epitaxial semiconductor layer stack (10), at least two electrical mounting pads (30) configured for electrically conductive and mechanically stable connection of the electronic semiconductor chip (27, 27'), the electrical mounting pads (30) being arranged on a rear side surface (31) of the electronic semiconductor chip (27, 27'), An electrical mounting surface (36) configured for mounting a light-emitting diode chip (35) to be controlled, said electrical mounting surface (36) being arranged on a front surface (33) of said electronic semiconductor chip (27, 27') opposite said rear surface (31).

12. The electronic semiconductor chip (27, 27') according to any one of claims 10 or 11, wherein The thickness (D) of the electronic semiconductor chip (27, 27') does not exceed 20 micrometers.

13. The electronic semiconductor chip (27, 27') according to any one of claims 10 to 12, wherein: The edge length (EL) of the electronic semiconductor chip (27, 27') does not exceed 100 micrometers.

14. A display comprising: - an electronic semiconductor chip (27, 27') according to any one of claims 10, 12 or 13, A light-emitting diode chip (35) which, during operation, emits electromagnetic radiation in a second wavelength range.

15. A display comprising: - An electronic semiconductor chip (27, 27')， - a light-emitting diode chip (35) emitting electromagnetic radiation in a second wavelength range, wherein The electronic semiconductor chip (27, 27') controls the light-emitting diode chip (35) during operation.

16. A display according to the preceding claim, wherein: The electronic semiconductor chip (27, 27') and the light-emitting diode chip (35) are stacked on top of one another.

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