Display substrate, display panel and display device

Abstract

A display substrate, comprising: a plurality of sub-pixels, an nth sub-pixel (PX) comprising: a transmission region (TS) and a reflection region (FS); a storage capacitor (C) and a switch transistor (T2) disposed in the reflection region (FS); the storage capacitor (C) comprising: a first plate (C11), a second plate (C12) and a third plate (C13), the first plate (C11) being electrically connected with the third plate (C13), the second plate (C12) being electrically connected with the switch transistor (T2), each of the first plate (C11) and the second plate (C12) being spaced apart from the second plate (C12) in an insulating manner; the switch transistor (T2) comprising an active part (A); wherein a normal projection of the first plate (C11) on a substrate (200) overlaps a normal projection of the second plate (C12) on the substrate (200), the normal projection of the second plate (C12) on the substrate (200) overlaps a normal projection of the third plate (C13) on the substrate (200); a normal projection of the active part (A) on the substrate (200) is spaced apart from a normal projection of the third plate (C13) on the substrate (200), and a thickness of the active part (A) is substantially the same as a thickness of the third plate (C13). A display panel and a display device are also provided.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically to a display substrate, a display panel, and a display device. Background Technology

[0002] Currently, displays mainly include Liquid Crystal Displays (LCDs) and Organic Light-Emitting Diode (OLEDs). An LCD typically consists of a display substrate, a counter substrate opposite to the display substrate, and a liquid crystal layer located between the display substrate and the counter substrate. LCDs can generate an electric field through pixel electrodes in the display substrate to change the orientation of liquid crystal molecules in the liquid crystal layer, and this, combined with a polarizer, achieves the display effect. An OLED includes an anode, a cathode, and an organic light-emitting layer disposed between the anode and cathode. OLEDs can generate current through the anode and cathode to drive the organic light-emitting layer to emit light for display. Summary of the Invention

[0003] This disclosure provides a display substrate, a display panel, and a display device.

[0004] According to a first aspect of this disclosure, a display substrate is provided, comprising: a substrate, a semiconductor layer, a first conductive layer and a second conductive layer, wherein the second conductive layer is located on the side of the first conductive layer away from the substrate.

[0005] The display substrate further includes a plurality of sub-pixels, wherein the nth sub-pixel includes: a transmissive area and a reflective area located outside the transmissive area;

[0006] The nth sub-pixel further includes: a storage capacitor and a switching transistor disposed in the reflective region;

[0007] The storage capacitor includes a first electrode plate, a second electrode plate, and a third electrode plate. The first electrode plate is located in the first conductive layer, the second electrode plate is located in the second conductive layer, and the third electrode plate is located on the side of the second conductive layer away from the substrate. The first electrode plate is electrically connected to the third electrode plate, and the second electrode plate is electrically connected to the switching transistor. Each of the first electrode plate and the second electrode plate is insulated from and spaced apart from the second electrode plate.

[0008] The switching transistor includes an active portion, which is disposed in the semiconductor layer;

[0009] Wherein, the orthographic projection of the first electrode plate on the substrate overlaps with the orthographic projection of the second electrode plate on the substrate, and the orthographic projection of the second electrode plate on the substrate overlaps with the orthographic projection of the third electrode plate on the substrate;

[0010] The orthographic projection of the active part on the substrate and the orthographic projection of the third electrode plate on the substrate are spaced apart, and the thickness of the active part and the thickness of the third electrode plate are approximately the same.

[0011] n is a positive integer.

[0012] According to an embodiment of this disclosure, the display substrate further includes a transparent conductive layer and a first insulating layer, the transparent conductive layer being located on the side of the second conductive layer facing away from the substrate, and the first insulating layer being located between the second conductive layer and the transparent conductive layer;

[0013] The third electrode plate is located in the transparent conductive layer, and the nth sub-pixel further includes a transparent conductive part, which is located in the transparent conductive layer and is insulated from the third electrode plate.

[0014] The transparent conductive portion includes a first sub-portion and a second sub-portion, and the first sub-portion and the second sub-portion are electrically connected.

[0015] The first insulating layer is provided with a first through-hole penetrating the first insulating layer, the first sub-part is located in the transmission area, the second sub-part is located in the reflection area, the orthographic projection of the second sub-part on the substrate overlaps with the orthographic projection of the second electrode plate on the substrate, and in the overlapping area, the second sub-part and the second electrode plate are electrically connected through the first through-hole;

[0016] The first electrode plate includes a third sub-part, the orthographic projection of the third sub-part on the substrate at least partially surrounds the orthographic projection of the first via on the substrate, and a portion of the orthographic projection of the third sub-part on the substrate overlaps with the orthographic projection of the second sub-part on the substrate, and another portion overlaps with the orthographic projection of the second sub-part on the substrate at a distance.

[0017] According to embodiments of this disclosure, the third sub-part includes: a first structure and a second structure;

[0018] The first sub-part, the second sub-part, and the active part are arranged along a first direction on the orthographic projection of the substrate. In a second direction, the orthographic projections of the first structure and the second structure on the substrate are located on opposite sides of the orthographic projection of the first via on the substrate.

[0019] The orthographic projection of a portion of the first structure near the second structure onto the substrate overlaps with the orthographic projection of the second sub-part onto the substrate, while the orthographic projection of a portion of the first structure away from the second structure onto the substrate is spaced apart from the orthographic projection of the second sub-part onto the substrate; and / or,

[0020] The orthographic projection of a portion of the second structure on the substrate near the first structure overlaps with the orthographic projection of the second sub-part on the substrate, while the orthographic projection of a portion of the first structure on the substrate away from the orthographic projection of the second sub-part on the substrate is spaced apart;

[0021] The second direction intersects with the first direction.

[0022] According to an embodiment of the present disclosure, in the first direction, the orthographic projection of either the first structure or the second structure on the substrate has a first distance between the orthographic projection of the first sub-part on the substrate, and the orthographic projection of the first via on the substrate has a second distance between the orthographic projection of the first sub-part on the substrate.

[0023] The first spacing is smaller than the second spacing.

[0024] According to embodiments of this disclosure, the transparent conductive portion further includes a connecting sub-portion located between the first sub-portion and the second sub-portion;

[0025] The orthographic projection of the second electrode plate on the substrate overlaps with the orthographic projection of the connecting sub-part on the substrate.

[0026] According to an embodiment of the present disclosure, the first electrode plate further includes a fourth sub-part, wherein in the first direction, the orthographic projection of the fourth sub-part on the substrate is located between the orthographic projection of the second sub-part on the substrate and the orthographic projection of the active part on the substrate, and the orthographic projection of the third sub-part on the substrate is located on the side of the orthographic projection of the fourth sub-part on the substrate that is close to the orthographic projection of the second sub-part on the substrate.

[0027] The orthographic projection of the third electrode plate on the substrate overlaps with the orthographic projection of the fourth sub-part on the substrate.

[0028] According to an embodiment of this disclosure, the display substrate further includes a plurality of data lines arranged along a second direction, wherein the xth data line is electrically connected to the nth sub-pixel;

[0029] In the nth sub-pixel, in the second direction, there is a third spacing between the orthographic projection of the third electrode plate on the substrate and the orthographic projection of the xth data line on the substrate; there is a fourth spacing between the orthographic projection of the third electrode plate on the substrate and the orthographic projection of the (x+1)th data line on the substrate; there is a fifth spacing between the orthographic projection of the second electrode plate on the substrate and the orthographic projection of the xth data line on the substrate; and there is a sixth spacing between the orthographic projection of the second electrode plate on the substrate and the orthographic projection of the (x+1)th data line on the substrate.

[0030] The third spacing is smaller than the fifth spacing, and the fourth spacing is smaller than the sixth spacing;

[0031] Both x and y are positive integers.

[0032] According to an embodiment of the present disclosure, in the nth sub-pixel, in the second direction, there is a seventh spacing between the orthographic projection of the first electrode plate on the substrate and the orthographic projection of the xth data line on the substrate, and an eighth spacing between the orthographic projection of the first electrode plate on the substrate and the orthographic projection of the (x+1)th data line on the substrate.

[0033] The fifth spacing is greater than the seventh spacing, and the sixth spacing is greater than the eighth spacing.

[0034] According to an embodiment of the present disclosure, the orthographic projection of the third electrode plate on the substrate and the orthographic projection of the active part on the substrate are arranged along a first direction, and in the first direction, there is a ninth spacing between the orthographic projection of the third electrode plate on the substrate and the orthographic projection of the active part on the substrate.

[0035] The orthographic projection of the second electrode plate on the substrate and the orthographic projection of the active part on the substrate are arranged along the first direction, and in the first direction, there is a tenth spacing between the orthographic projection of the second electrode plate on the substrate and the orthographic projection of the active part on the substrate.

[0036] The first direction intersects the second direction, and the ninth spacing is greater than the tenth spacing.

[0037] According to an embodiment of the present disclosure, the orthographic projection of the first electrode plate on the substrate and the orthographic projection of the active portion on the substrate are arranged along the first direction, and in the first direction, there is an eleventh spacing between the orthographic projection of the first electrode plate on the substrate and the orthographic projection of the active portion on the substrate, wherein the ninth spacing is smaller than the eleventh spacing.

[0038] According to an embodiment of the present disclosure, the display substrate further includes a second reflective conductive layer, the second reflective conductive layer being located on the side of the transparent conductive layer opposite to the substrate.

[0039] The nth sub-pixel further includes a reflective portion, which is located in the second reflective conductive layer and has a fourth opening.

[0040] The orthogonal projection of the reflective portion onto the substrate at least covers the orthogonal projections of the active portion and the third electrode plate onto the substrate, and the orthogonal projection of the fourth opening onto the substrate covers the orthogonal projection of the first sub-part onto the substrate.

[0041] According to an embodiment of this disclosure, the display substrate further includes a first reflective conductive layer, the first reflective conductive layer being located on the side of the second conductive layer opposite to the substrate, and the third electrode plate being located in the first reflective conductive layer;

[0042] The display substrate further includes multiple data lines and multiple gate lines, the multiple data lines are arranged along a second direction, the multiple gate lines are arranged along a first direction, and the first direction intersects the second direction;

[0043] The x-th data line is electrically connected to the n-th sub-pixel, and the y-th gate line is electrically connected to the n-th sub-pixel;

[0044] The orthographic projection of at least one of the data line x, the data line x+1, the gate line y-1, and the gate line y on the substrate overlaps with the orthographic projection of the third electrode plate in the nth sub-pixel on the substrate.

[0045] Both x and y are positive integers.

[0046] According to an embodiment of this disclosure, the display substrate further includes a transparent conductive layer and a first insulating layer, wherein the transparent conductive layer is located on the side of the first reflective conductive layer away from the substrate, and the first insulating layer is located between the second conductive layer and the transparent conductive layer;

[0047] The nth sub-pixel further includes a transparent conductive portion, which is located in the transparent conductive layer;

[0048] The transparent conductive portion includes a first sub-portion and a second sub-portion, and the first sub-portion and the second sub-portion are electrically connected.

[0049] The first insulating layer is provided with a first through-hole penetrating the first insulating layer, the first sub-part is located in the transmission area, the second sub-part is located in the reflection area, the orthographic projection of the second sub-part on the substrate overlaps with the orthographic projection of the second electrode plate on the substrate, and in the overlapping area, the second sub-part and the second electrode plate are electrically connected through the first through-hole;

[0050] The third electrode plate is provided with a first opening and a second opening. The orthographic projection of the first opening on the substrate covers the orthographic projection of the transmission area on the substrate, and the orthographic projection of the second opening on the substrate covers the orthographic projection of the first via on the substrate.

[0051] According to an embodiment of this disclosure, a third opening is further provided on the third electrode plate, and the orthographic projection of the third opening on the substrate covers the orthographic projection of the active part on the substrate.

[0052] In the second direction, the first opening has a first size, the second opening has a second size, and the third opening has a third size;

[0053] The third dimension is smaller than the first dimension and larger than the second dimension.

[0054] According to an embodiment of the present disclosure, the orthographic projection of the first electrode plate on the substrate overlaps with the orthographic projection of the second sub-part on the substrate, and the orthographic projection of the first electrode plate on the substrate is located on the side of the orthographic projection of the first via on the substrate away from the first sub-part.

[0055] According to embodiments of this disclosure, the first sub-part and the second sub-part have substantially the same dimensions in the second direction.

[0056] According to an embodiment of the present disclosure, the display substrate further includes a second reflective conductive layer, the second reflective conductive layer being located on the side of the first reflective conductive layer away from the substrate.

[0057] The nth sub-pixel further includes a reflective portion located in the second reflective conductive layer. The orthographic projection of the reflective portion on the substrate covers the orthographic projections of the second opening and the third opening on the substrate. The reflective portion is also provided with a fourth opening, and the orthographic projection of the fourth opening on the substrate covers the transmissive area.

[0058] The reflective portion is electrically connected to the first sub-portion in the edge region of the fourth opening.

[0059] According to an embodiment of this disclosure, the size of the fourth opening in the second direction is greater than or equal to the size of the fourth opening in the first direction.

[0060] According to embodiments of this disclosure, the display substrate further includes a display area and a peripheral area that at least partially surrounds the display area, wherein the plurality of sub-pixels are located in the display area;

[0061] The display substrate further includes multiple first connection lines, multiple second connection lines, and at least one common signal line. The multiple first connection lines are arranged along a first direction, and the multiple second connection lines are arranged along the first direction.

[0062] In the nth sub-pixel, the third electrode plate is electrically connected to the i-th first connection line, the first electrode plate is electrically connected to the j-th second connection line, and the i-th first connection line and the j-th second connection line are electrically connected to the common signal line in the peripheral area;

[0063] Both i and j are positive integers.

[0064] According to an embodiment of this disclosure, in the reflective region, the orthographic projection of the active portion on the substrate and the orthographic projection of the third electrode plate on the substrate form a complementary pattern.

[0065] According to a second aspect of this disclosure, a display panel is provided, comprising a display substrate and an opposing substrate, wherein the display substrate comprises the aforementioned display substrate, and the opposing substrate comprises a plurality of color resists, wherein the m-th color resist is disposed corresponding to the n-th sub-pixel;

[0066] The m-th color resist includes a first region, a second region, and a third region. The orthographic projection of the first region on the substrate covers the orthographic projection of the transmissive region of the n-th sub-pixel on the substrate. The orthographic projection of the third region on the substrate covers the orthographic projection of the active portion of the n-th sub-pixel on the substrate. In a first direction, the second region is located between the first region and the third region.

[0067] In the second direction, the size of the second region is less than or equal to the size of the third region, and the second direction intersects the first direction;

[0068] m is a positive integer.

[0069] According to an embodiment of the present disclosure, the plurality of color resists includes a first color resist, a second color resist, and a third color resist, wherein the first color resist, the second color resist, and the third color resist are different colors, and the orthographic projections of the first color resist, the second color resist, and the third color resist on the substrate are spaced apart from each other.

[0070] In the second direction, the second region of the first color resist has a fourth dimension, the second region of the second color resist has a fifth dimension, and the second region of the third color resist has a sixth dimension, wherein the fifth dimension is larger than the fourth dimension and smaller than the sixth dimension.

[0071] According to an embodiment of this disclosure, the display panel further includes a liquid crystal layer, the liquid crystal layer including a plurality of dimming regions, wherein the z-th dimming region is configured corresponding to the n-th sub-pixel;

[0072] The z-th dimming region includes a first dimming sub-region and a second dimming sub-region. The orthographic projection of the first dimming sub-region on the substrate covers the orthographic projection of the transmissive region of the n-th sub-pixel on the substrate. The orthographic projection of the second dimming sub-region on the substrate covers the orthographic projection of the reflective region of the n-th sub-pixel on the substrate. The cell thickness of the first dimming sub-region is greater than the cell thickness of the second dimming sub-region.

[0073] According to a third aspect of this disclosure, a display device is provided, which includes the display panel described above. Attached Figure Description

[0074] The foregoing contents, as well as other objects, features, and advantages of this disclosure, will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0075] Figures 1A to 1E The schematic diagram shows a plan view of the sub-pixels of the display substrate in one example;

[0076] Figure 2 A schematic plan view of the display substrate is shown in an embodiment of the present disclosure;

[0077] Figure 3 A schematic plan view of the first conductive layer is shown in some embodiments of this disclosure;

[0078] Figure 4 A schematic plan view of a semiconductor layer is shown in some embodiments of this disclosure;

[0079] Figure 5 A schematic plan view of the second conductive layer is shown in some embodiments of this disclosure;

[0080] Figure 6 A schematic plan view of the transparent conductive layer is shown in some embodiments of this disclosure;

[0081] Figure 7 A schematic plan view of the first insulating layer is shown in some embodiments of this disclosure;

[0082] Figure 8 A schematic plan view of the second reflective conductive layer is shown in some embodiments of this disclosure;

[0083] Figure 9 A schematic plan view of the first conductive layer and semiconductor layer in some embodiments of this disclosure is shown;

[0084] Figure 10 A schematic plan view of a first conductive layer, a semiconductor layer, a second conductive layer, and a first insulating layer is shown in some embodiments of this disclosure;

[0085] Figure 11 The schematic diagram illustrates a plan view of a first conductive layer, a semiconductor layer, a second conductive layer, a first insulating layer, and a transparent conductive layer in some embodiments of the present disclosure;

[0086] Figure 12 The schematic diagram illustrates a plan view of a first conductive layer, a semiconductor layer, a second conductive layer, a first insulating layer, a transparent conductive layer, and a second reflective conductive layer in some embodiments of this disclosure.

[0087] Figure 13 The illustration schematically shows cross-sectional views of sub-pixels in some embodiments of this disclosure;

[0088] Figure 14 The spacing between the first structure, the second structure, the first via, and the first sub-part is schematically shown in an embodiment of this disclosure.

[0089] Figure 15 The spacing between the first electrode plate, the second electrode plate, the third electrode plate and the data line in an embodiment of this disclosure is schematically shown.

[0090] Figure 16 The schematic diagram illustrates the spacing between the first electrode plate, the second electrode plate, the third electrode plate, and the active part in an embodiment of this disclosure;

[0091] Figure 17 A schematic plan view of the first conductive layer is shown in some other embodiments of this disclosure;

[0092] Figure 18 A schematic plan view of the semiconductor layer is shown in some other embodiments of this disclosure;

[0093] Figure 19 A schematic plan view of the second conductive layer is shown in some other embodiments of this disclosure;

[0094] Figure 20 A schematic plan view of the first insulating layer is shown in some other embodiments of this disclosure;

[0095] Figure 21 A schematic plan view of the transparent conductive layer is shown in some other embodiments of this disclosure;

[0096] Figure 22 A schematic plan view of the first reflective conductive layer is shown in some other embodiments of this disclosure;

[0097] Figure 23 A schematic plan view of the second reflective conductive layer is shown in some other embodiments of this disclosure;

[0098] Figure 24 A schematic plan view of the first conductive layer and semiconductor layer is shown in some other embodiments of this disclosure;

[0099] Figure 25 A schematic plan view of the first conductive layer, semiconductor layer, second conductive layer, and first insulating layer is shown in some other embodiments of this disclosure;

[0100] Figure 26 A schematic plan view of a first conductive layer, a semiconductor layer, a second conductive layer, a first insulating layer, and a first reflective conductive layer is shown in some other embodiments of this disclosure;

[0101] Figure 27 The schematic diagram illustrates a plan view of a first conductive layer, a semiconductor layer, a second conductive layer, a first insulating layer, a first reflective conductive layer, and a transparent conductive layer in other embodiments of this disclosure;

[0102] Figure 28 The schematic diagram illustrates a plan view of a first conductive layer, a semiconductor layer, a second conductive layer, a first insulating layer, a first reflective conductive layer, a transparent conductive layer, and a second reflective conductive layer in some other embodiments of this disclosure.

[0103] Figure 29 Cross-sectional views of sub-pixels are schematically shown in some other embodiments of this disclosure;

[0104] Figure 30 and Figure 31 A cross-sectional view of the display panel in an embodiment of this disclosure is shown schematically;

[0105] Figure 32 A schematic plan view of the color resist in an embodiment of this disclosure is shown. Detailed Implementation

[0106] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the protection scope of this disclosure.

[0107] It should be noted that, for clarity and / or descriptive purposes, the dimensions and relative dimensions of components may be enlarged in the accompanying drawings. Therefore, the dimensions and relative dimensions of the individual components are not necessarily limited to those shown in the drawings. In the specification and accompanying drawings, the same or similar reference numerals indicate the same or similar parts.

[0108] When an element is described as being "on" another element, "connected to" another element, or "attached to" another element, the element may be directly on, directly connected to, or directly attached to the other element, or there may be intermediate elements. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly attached to" another element, there are no intermediate elements. Other terms and / or expressions used to describe relationships between elements should be interpreted in a similar manner, such as "between" versus "directly between," "adjacent" versus "directly adjacent," or "on" versus "directly on," etc. Furthermore, the term "connection" can refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. Moreover, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the listed related items.

[0109] It should be noted that although the terms "first," "second," etc., may be used herein to describe various components, members, elements, regions, layers, and / or parts, these components, members, elements, regions, layers, and / or parts should not be limited by these terms. Rather, these terms are used to distinguish one component, member, element, region, layer, and / or part from another. Thus, for example, the first component, first member, first element, first region, first layer, and / or first part discussed below may be referred to as a second component, second member, second element, second region, second layer, and / or second part without departing from the teachings of this disclosure.

[0110] For ease of description, spatial relation terms, such as “above,” “below,” “left,” “right,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figure. It should be understood that spatial relation terms are intended to cover other orientations of the device in use or operation besides those described in the figure. For example, if the device in the figure were inverted, an element described as “below” or “under” other elements or features would be oriented “above” or “on top” other elements or features.

[0111] In this document, the terms “substantially,” “approximately,” “approximately,” “roughly,” and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to account for inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account factors such as process variations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), “approximately” as used herein includes stated values ​​and indicates that a particular value is within an acceptable range of deviation for one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0112] It should be noted that in this paper, "same layer" refers to a layer structure formed by using the same film deposition process to form a film layer for a specific pattern, and then using the same mask to pattern that film layer in a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. That is, multiple elements, components, structures, and / or portions located in the "same layer" are made of the same material and formed by the same single patterning process. Typically, multiple elements, components, structures, and / or portions located in the "same layer" have approximately the same thickness.

[0113] Those skilled in the art will understand that, unless otherwise stated herein, the terms “height” or “thickness” refer to the dimensions along the surface of each film layer disposed perpendicular to the display substrate, i.e., the dimensions along the light-emitting direction of the display substrate, or the dimensions along the normal direction of the display device.

[0114] Currently, LCD screens can be categorized into transmissive LCDs, reflective LCDs, and transflective LCDs. Transmissive LCDs use a backlight module as the light source; light emitted from the backlight module passes through the liquid crystal layer and polarizer to display the image. Transmissive LCDs can display images in dark environments, but their display is unclear in bright environments. Reflective LCDs use ambient light as the light source; ambient light enters the reflective LCD and is reflected to display the image. Reflective LCDs can achieve clear display in bright environments, but they cannot display images in dark environments. Transflective LCDs combine the characteristics of both transmissive and reflective LCDs, simultaneously incorporating both transmissive and reflective areas within the screen, allowing for use in both bright and dark environments.

[0115] In one example, a transflective liquid crystal display (LCD) is provided. This transflective LCD can switch between reflective and transmissive display modes. In reflective display mode, ambient light is used as the light source, while in transmissive display mode, a backlight module is used as the light source.

[0116] The transflective liquid crystal display in this example includes a display substrate and an opposing substrate. Figures 1A to 1E A schematic diagram illustrates a plan view of subpixels of a display substrate in one example, wherein, Figure 1A A schematic diagram of the first conductive layer in one example is shown. Figure 1B A schematic diagram of the second conductive layer in one example is shown. Figure 1C A schematic diagram of a reflective layer in one example is shown. Figure 1D A schematic diagram of a first conductive layer and a second conductive layer is shown in one example. Figure 1E A schematic diagram of a first conductive layer, a second conductive layer, and a reflective layer is shown in one example.

[0117] See also Figures 1A to 1EThe display substrate includes multiple sub-pixels, at least one of which includes a reflective portion 110 located in a reflective layer. The reflective portion 110 is used to reflect ambient light during reflective display and to prevent light leakage during transmissive display. In this example, at least a portion of the black matrix in the opposing substrate is removed, while the widths of the data lines 120 and gate lines 130 in the display substrate are thickened. The data lines 120 and gate lines 130 can also serve a reflective function, thereby increasing the reflective area during reflective display and thus improving the aperture ratio during reflective display. Furthermore, the data lines 120 and gate lines 130 can overlap with the reflective portion 110 in the display substrate, thereby replacing the removed black matrix to achieve a light-shielding function during transmissive display, thus preventing light leakage during transmissive display.

[0118] In this example, at least one sub-pixel includes a switching transistor T1 and a storage capacitor Cst. Due to the pixel structure of the sub-pixel, a switching voltage ΔVp inevitably exists due to the coupling capacitance and the transition of the gate voltage from a high potential to a low potential. The theoretical formula for the switching voltage ΔVp is as follows:

[0119] ΔVp=Cgs*(Vgh-Vgl) / (Cgs+Cst+Clc);

[0120] Where: ΔVp is the switching voltage, Vgh is the gate high voltage of switching transistor T1, Vgl is the gate low voltage of switching transistor T1, and Clc is the liquid crystal capacitance. Typically, Cgs is the capacitance formed by the gate, source, and gate insulating layer between the switching transistor T1, and Cst is the storage capacitance formed by the pixel electrode, common electrode, and insulating layer between them.

[0121] Due to the characteristics of liquid crystals, the maximum value Clcmax of the liquid crystal capacitance and the minimum value Clcmin of the liquid crystal capacitance are significantly different. This results in a large difference Ω between the maximum value Vpmax of the switching voltage and the minimum value ΔVpmin of the switching voltage. When the difference Ω is greater than 0.5, unacceptable flickering will occur on the screen.

[0122] To reduce the difference Ω, the capacitance of the storage capacitor Cst can be increased. However, to meet the demands of high resolution, the size of sub-pixels in the display substrate is becoming smaller, and correspondingly, the area of ​​the storage capacitor Cst within each sub-pixel is also decreasing. In the example above, the data line 120 and the gate line 130 are thickened, further restricting the area of ​​the storage capacitor Cst. Since the area of ​​the storage capacitor Cst is positively correlated with its capacitance, a decrease in the area of ​​Cst directly leads to a decrease in its capacitance. In this example, due to the significant restriction on the area of ​​the storage capacitor Cst, its capacitance is insufficient to meet the requirement of reducing the difference Ω.

[0123] In view of the above, embodiments of this disclosure provide a display substrate, comprising: a substrate, a semiconductor layer, a first conductive layer, and a second conductive layer, wherein the second conductive layer is located on the side of the first conductive layer away from the substrate. The display substrate further comprises a plurality of sub-pixels, wherein the nth sub-pixel comprises: a transmissive region and a reflective region located outside the transmissive region. n is a positive integer. The nth sub-pixel further comprises: a storage capacitor and a switching transistor disposed in the reflective region. The storage capacitor comprises: a first electrode plate, a second electrode plate, and a third electrode plate, wherein the first electrode plate is located in the first conductive layer, the second electrode plate is located in the second conductive layer, and the third electrode plate is located on the side of the second conductive layer away from the substrate. The first electrode plate and the third electrode plate are electrically connected, and the second electrode plate is electrically connected to the switching transistor. Each of the first electrode plate and the second electrode plate is insulated from and spaced apart from the second electrode plate. The switching transistor includes an active portion disposed in the semiconductor layer. The orthographic projection of the first electrode plate onto the substrate overlaps with the orthographic projection of the second electrode plate onto the substrate, and the orthographic projection of the second electrode plate onto the substrate overlaps with the orthographic projection of the third electrode plate onto the substrate. The orthographic projection of the active part on the substrate and the orthographic projection of the third electrode plate on the substrate are spaced apart, and the thickness of the active part and the thickness of the third electrode plate are approximately the same.

[0124] In this way, the capacitance of the storage capacitor can be increased, effectively reducing the aforementioned difference Ω. Simultaneously, the horizontal dimensions of the storage capacitor only require minor changes, or even no change at all, which is beneficial for small-size subpixel designs. Furthermore, the third electrode plate is spaced apart from the active part and has approximately the same thickness, thereby reducing or filling the film layer difference caused by the active part. This helps to make the reflective surface in the reflective region flatter, thus improving the reflection efficiency of the reflective region.

[0125] Figure 2 A schematic plan view of the display substrate is shown in an embodiment of the present disclosure.

[0126] See Figure 2 The display substrate in this embodiment includes a display area AA and a peripheral area NA located on at least one side of the display area AA.

[0127] The display area AA can have various shapes. For example, the display area AA can be set in various shapes such as a polygon (e.g., a rectangle) with a closed shape including straight edges, a circle or ellipse with curved edges, and a semicircle or semi-ellipse with both straight and curved edges. In the embodiments of this disclosure, the display area AA is set as an area having a quadrilateral shape including straight edges. It should be understood that this is only an exemplary embodiment of this disclosure and not a limitation thereof.

[0128] The display substrate may further include a substrate 200 and a plurality of pixel units P disposed on the substrate 200 and located in the display area AA. The plurality of pixel units P may be arranged in an array along a first direction Y and a second direction X. Each pixel unit P may include a plurality of sub-pixels PX. For example, pixel unit P may include a first sub-pixel, a second sub-pixel, and a third sub-pixel. Exemplarily, the first sub-pixel, the second sub-pixel, and the third sub-pixel may be set as a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively; however, the embodiments disclosed herein are not limited thereto.

[0129] The display substrate also includes a plurality of gate lines GL and a plurality of data lines DL disposed on the substrate 200 and located at least in the display area AA. The plurality of gate lines GL extend along a second direction X, and the plurality of data lines DL extend along a first direction Y. For example, a sub-pixel PX is connected to one data line DL and one gate line GL, sub-pixels PX in the same row are connected to the same gate line GL, sub-pixels PX in different rows are connected to different gate lines GL, sub-pixels PX in the same column are connected to the same data line DL, and sub-pixels PX in different columns are connected to different data lines DL.

[0130] The peripheral area NA can be disposed on at least one side of the display area AA. For example, the peripheral area NA can surround the outer periphery of the display area AA. In embodiments of this disclosure, the peripheral area NA may include a vertical portion extending in a first direction Y and a horizontal portion extending in a second direction X.

[0131] The display substrate may further include a gate driving circuit 21 and a driving chip 22 disposed on the substrate 200 and located in the peripheral region NA. For example, the gate driving circuit 21 may be located on at least one side of the display region AA. Figure 2 In the illustrated embodiment, the gate driving circuit 21 is located on the left and right sides of the display area AA, respectively. It should be noted that the left and right sides can refer to the left and right sides of the display substrate (screen) as viewed by the human eye during display. For example, the driving chip 22 can be located on at least one side of the display area AA. Figure 2 In the illustrated embodiment, the driver chip 22 is located below the display area AA. It should be noted that "below" can refer to the lower side of the display substrate (screen) as viewed by the human eye during display.

[0132] The driver chip 22 includes a data driver circuit, which sequentially latches the input data according to a clock signal and converts the latched data into analog signals before inputting them to the data lines DL of the display substrate. The gate driver circuit 21 is typically implemented by a shift register, which converts the clock signal into turn-on / turn-off voltages and outputs them to the gate lines GL of the display substrate, respectively.

[0133] It should be noted that, although Figure 2 The diagram shows that the gate driving circuit 21 is located on the left and right sides of the display area AA, and the driving chip 22 is located on the lower side of the display area AA. However, the embodiments of this disclosure are not limited to this, and the gate driving circuit 21 and the driving chip 22 can be located at any suitable position in the peripheral area NA.

[0134] For example, the gate driving circuit 21 can employ GOA (Gate Driver on Array) technology. In GOA technology, the gate driving circuit 21 is directly disposed on the array substrate, replacing an external chip. Each GOA unit serves as a first-stage shift register, and each stage shift register is connected to a gate line GL. By sequentially outputting scan signals through each stage shift register, line-by-line scanning of pixel units is achieved. In some embodiments, each stage shift register can also be connected to multiple gate lines GL. This adapts to the development trend of high resolution and narrow bezels in display substrates. The driving chip 22 can be folded onto the back side of the display substrate using a structure such as a flip-chip film.

[0135] The following is combined with Figures 2 to 29 The display substrate of the present disclosure will be described in detail.

[0136] Figures 3 to 12 The schematic diagram illustrates a planar view of a sub-pixel in some embodiments of this disclosure. Figure 13 Cross-sectional views of sub-pixels are schematically shown in some embodiments of this disclosure. Figure 3 A schematic plan view of the first conductive layer is shown in some embodiments of this disclosure. Figure 4 A schematic plan view of a semiconductor layer is shown in some embodiments of this disclosure. Figure 5 A schematic plan view of the second conductive layer is shown in some embodiments of this disclosure. Figure 6 A schematic plan view of the transparent conductive layer in some embodiments of this disclosure is shown. Figure 7 A schematic plan view of the first insulating layer is shown in some embodiments of this disclosure. Figure 8 A schematic plan view of the second reflective conductive layer in some embodiments of this disclosure is shown. Figure 9 A schematic plan view of the first conductive layer and semiconductor layer in some embodiments of this disclosure is shown. Figure 10 The schematic diagram illustrates a plan view of a first conductive layer, a semiconductor layer, a second conductive layer, and a first insulating layer in some embodiments of this disclosure. Figure 11 The schematic diagram illustrates a plan view of a first conductive layer, a semiconductor layer, a second conductive layer, a first insulating layer, and a transparent conductive layer in some embodiments of this disclosure. Figure 12 The schematic diagram illustrates a plan view of a first conductive layer, a semiconductor layer, a second conductive layer, a first insulating layer, a transparent conductive layer, and a second reflective conductive layer in some embodiments of the present disclosure.

[0137] See also Figures 2 to 13 The display substrate of this embodiment further includes a semiconductor layer 210, a first conductive layer 220 and a second conductive layer 230, wherein the second conductive layer 230 is located on the side of the first conductive layer 220 away from the substrate 200.

[0138] The semiconductor layer 210 may be made of materials such as amorphous silicon, polycrystalline silicon, or oxide semiconductors. The first conductive layer 220 may be made of a metallic material, for example, it may include metals such as Mo, Al, and Cu, or their alloys, or materials such as Ti / Al / Ti. Optionally, multiple gate lines GL may be located in the first conductive layer 220. The second conductive layer 230 may be made of a metallic material, for example, it may include metals such as Mo, Al, and Cu, or their alloys, or materials such as Ti / Al / Ti. Optionally, multiple data lines DL may be located in the second conductive layer 230.

[0139] The display substrate of this disclosure is applied in a transflective display screen. The nth sub-pixel PX among a plurality of sub-pixels PX includes: a transmissive region TS and a reflective region FS located outside the transmissive region TS. The nth sub-pixel PX also includes: a storage capacitor C and a switching transistor T2 disposed in the reflective region FS. n is a positive integer.

[0140] The nth sub-pixel PX can refer to any one of multiple sub-pixels PX. That is, in the embodiments of this disclosure, any one of the multiple sub-pixels PX can include a reflective area FS, a transmissive area TS, a storage capacitor C located in the reflective area FS, and a switching transistor T2. The reflective area FS is used to reflect ambient light when the display is reflective, while the transmissive area TS is used to allow light emitted by the backlight module to pass through when the display is transmissive.

[0141] The transmissive region TS and the reflective region FS can have various shapes. For example, the transmissive region TS and the reflective region FS can be arranged in various shapes such as polygons (e.g., rectangles) with closed shapes including straight sides, circles, ellipses, etc., and semicircles, semi-ellipses, etc., including both straight and curved sides. In embodiments of this disclosure, the transmissive region TS and the reflective region FS are set as a region having a quadrilateral shape including straight sides. It should be understood that this is only an exemplary embodiment of this disclosure and not a limitation thereof. For example, alternatively, the reflective region FS may at least partially surround the transmissive region TS.

[0142] Optionally, the transmissive region TS and the reflective region FS are arranged along the first direction Y. The nth sub-pixel PX is electrically connected to the yth gate line GL. In the nth sub-pixel PX, the orth projection of the transmissive region TS on the substrate 200 is located on the side of the reflective region FS opposite to the orth projection of the reflective region FS on the substrate 200. In other words, the reflective region FS is closer to the yth gate line GL than the transmissive region TS. Alternatively, the reflective region FS may also be arranged around the transmissive region TS. The specific arrangement can be determined according to actual needs, and the embodiments disclosed herein do not limit this.

[0143] For clarity, unless otherwise specified, the following explanation will use a sub-pixel PX (i.e., the nth sub-pixel PX) and the signal line electrically connected to that sub-pixel PX as examples.

[0144] In the nth sub-pixel PX, the storage capacitor C includes a first electrode C11, a second electrode C12, and a third electrode C13. The first electrode C11 is located in the first conductive layer 220, the second electrode C12 is located in the second conductive layer 230, and the third electrode C13 is located on the side of the second conductive layer 230 facing away from the substrate 200. The first electrode C11 and the third electrode C13 are electrically connected, and the second electrode C12 is electrically connected to the switching transistor T2. Each of the first electrode C11 and the second electrode C12 is insulated from the second electrode C12 by a distance. The switching transistor T2 includes an active part A, which is disposed in the semiconductor layer 210. The orthographic projection of the first electrode C11 on the substrate 200 overlaps with the orthographic projection of the second electrode C12 on the substrate 200, and the orthographic projection of the second electrode C12 on the substrate 200 overlaps with the orthographic projection of the third electrode C13 on the substrate 200.

[0145] The first electrode C11 is closer to the substrate 200 than the second electrode C12, and the second electrode C12 is closer to the substrate 200 than the third electrode C13. In other words, in the thickness direction of the display substrate, the first electrode C11 and the third electrode C13 are respectively disposed on both sides of the second electrode C12. The first electrode C11 and the third electrode C13 are electrically connected, thereby jointly forming the first terminal of the storage capacitor C. For example, both the first electrode C11 and the third electrode C13 are electrically connected to the common signal line VCOM located in the peripheral region NA through a connecting line, and thus, a constant voltage signal (e.g., a common voltage signal) is provided to the first electrode C11 and the third electrode C13 through the common signal line VCOM.

[0146] The second plate C12 forms the second terminal of the storage capacitor C. The gate G of the switching transistor T2 is electrically connected to the gate line GL. The first terminal TS of the switching transistor T2 is electrically connected to the data line DL. The second terminal TD of the switching transistor T2 is electrically connected to the second terminal of the storage capacitor C. The switching transistor T2 turns on in response to a valid level signal provided by the gate line GL. At this time, the data voltage signal on the data line DL can be written into the storage capacitor C through the switching transistor T2.

[0147] In the example shown in Figure 1, the storage capacitor C includes two plates, for example, a first plate C1 located in the first conductive layer and a second plate C2 located in the second conductive layer. The first plate C1 and the second plate C2 overlap in the thickness direction of the display substrate and are insulated from each other. Compared to the example shown in Figure 1, the storage capacitor C of the embodiment of this disclosure adds a third plate C13, which is stacked with the first plate C11 and the second plate C12. This significantly increases the capacitance of the storage capacitor C while requiring only a minor change, or even no change, in the horizontal dimension, which is beneficial for the small-size design of the sub-pixel PX.

[0148] The switching transistor T2 may include a top-gate structure or a bottom-gate structure. Exemplarily, in this embodiment of the present disclosure, the switching transistor T2 employs a bottom-gate structure. For example, the semiconductor layer 210 is located between the first conductive layer 220 and the second conductive layer 230, the gate G of the switching transistor T2 is located in the first conductive layer 220, and the orthogonal projection of the gate G of the switching transistor T2 onto the substrate 200 overlaps with the orthogonal projection of the active portion A onto the substrate 200. The active portion A includes a first electrode connection portion, a second electrode connection portion, and a channel portion located between the first electrode connection portion and the second electrode connection portion. The first electrode connection portion is electrically connected to the first electrode TS of the switching transistor T2, and the second electrode connection portion is electrically connected to the second electrode TD of the switching transistor T2.

[0149] In the reflective region FS, the active part A is only provided in the switching transistor T2. The active part A causes a film layer step difference in the reflective region FS, thereby affecting the uniformity of the film thickness in the reflective region FS. In view of this, the embodiments of the present disclosure are arranged such that the orthographic projection of the third electrode C13 on the substrate 200 is spaced apart from the orthographic projection of the active part A on the substrate 200, and the thickness of the third electrode C13 is approximately the same as the thickness of the active part A.

[0150] For example, the ratio of the thickness of the active portion A to the thickness of the third electrode C13 can be set to 8:11 to 11:8. For instance, the ratio can be set to 9:11 to 11:9. Preferably, the ratio can be set to 10:11 to 11:10. Ideally, the ratio can be set to 1:1, which better improves the film thickness gradient.

[0151] The thickness of the active portion A can be set to 0.12 μm to 0.24 μm, for example, the thickness of the active portion A can be set to 0.14 μm, 0.16 μm, 0.18 μm, 0.2 μm, or 0.22 μm. The thickness of the third electrode C13 can be set to 0.14 μm to 0.26 μm, for example, the thickness of the third electrode C13 can be set to 0.16 μm, 0.18 μm, 0.2 μm, 0.22 μm, or 0.24 μm. In the embodiments of this disclosure, the thickness of the active portion A can be set to 0.18 μm, and the thickness of the third electrode C13 can be set to 0.2 μm.

[0152] It should be noted that the ratio and specific value between the thickness of the active part A and the thickness of the third electrode C13 are not limited to the above example. They can be selected according to actual needs, as long as the difference between the thickness of the active part A and the thickness of the third electrode C13 does not exceed 30%.

[0153] In this way, the difference in film thickness caused by the active part A can be reduced or filled by the third electrode C13, which is beneficial to improving the uniformity of the film thickness in the reflective region FS.

[0154] Therefore, the third plate C13 can not only increase the capacitance of the storage capacitor C, but also reduce or fill the film layer difference caused by the active part A, thereby making the reflective surface in the reflective region FS flatter and improving the reflection efficiency of the reflective region FS.

[0155] The embodiments of this disclosure will be further described below.

[0156] In some specific embodiments, the display substrate further includes a transparent conductive layer 240 and a first insulating layer 250. The transparent conductive layer 240 is located on the side of the second conductive layer 230 away from the substrate 200, and the first insulating layer 250 is located between the second conductive layer 230 and the transparent conductive layer 240.

[0157] In embodiments of this disclosure, the material of the transparent conductive layer 240 may include a transparent conductive material, for example, the material of the transparent conductive layer 240 may include indium tin oxide (ITO). The first insulating layer 250 may include inorganic insulating materials, organic insulating materials, or any combination thereof. For example, inorganic insulating materials may include silicon oxide, silicon nitride, silicon oxynitride, etc., and organic insulating materials may include polyimide, polyamide, acrylic resin, phenolic resin, benzocyclobutene, etc.

[0158] In embodiments of this disclosure, the third electrode C13 may be located in the transparent conductive layer 240, or the third electrode C13 may also be located in the first reflective conductive layer, which will be mentioned below. Below, we will first combine... Figures 3 to 16 The following describes the embodiment of the present disclosure in which the third electrode C13 is located in the transparent conductive layer 240.

[0159] The third electrode C13 is located in the transparent conductive layer 240, and the third electrode C13 can have various shapes. For example, the third electrode C13 can be provided in various shapes such as a polygon (e.g., a rectangle) with a closed shape including straight edges, a circle or ellipse with curved edges, and a semicircle or semi-ellipse with both straight and curved edges. In the embodiments of this disclosure, the third electrode C13 is provided as a region having a quadrilateral shape including straight edges. It should be understood that this is only an exemplary embodiment of this disclosure and not a limitation thereof. For example, in other embodiments, the third electrode C13 may also include a shape that can form a complementary pattern with the active part A, which will be described in detail below, and therefore will not be repeated here.

[0160] The nth sub-pixel PX also includes a transparent conductive portion 241, which is located in the transparent conductive layer 240 and is insulated from the third electrode plate C13. The transparent conductive portion 241 includes a first sub-portion 2411 and a second sub-portion 2412, which are electrically connected. A first via V1 penetrating the first insulating layer 250 is provided. The first sub-portion 2411 is located in the transmission region TS, and the second sub-portion 2412 is located in the reflection region FS. The orthographic projection of the second sub-portion 2412 on the substrate 200 overlaps with the orthographic projection of the second electrode plate C12 on the substrate 200, and in the overlapping region, the second sub-portion 2412 and the second electrode plate C12 are electrically connected through the first via V1.

[0161] In the embodiments of this disclosure, the first sub-part 2411 can be a pixel electrode in the transmissive region TS. For example, after the display substrate and the opposing substrate 300 are aligned, the liquid crystal layer is located on the side of the first sub-part 2411 facing away from the substrate 200. Since the transparent conductive layer 240 includes a transparent conductive material, the first sub-part 2411 allows light to pass through, that is, the light emitted by the backlight module can pass through the first sub-part 2411 and enter the liquid crystal layer. One end of the second electrode C12 is electrically connected to the second electrode TD of the switching transistor T2, and the other end of the second electrode C12 is electrically connected to the second sub-part 2412 through the first via V1. Thus, when the switching transistor T2 is turned on, the data voltage signal on the data line DL can be transmitted to the first sub-part 2411 through the switching transistor T2, the second electrode C12, and the second sub-part 2412, thereby forming a first electric field between the first sub-part 2411 and the corresponding common electrode. This first electric field can drive the liquid crystal in the liquid crystal layer to change its rotation direction to achieve the display function.

[0162] In some specific embodiments, the display substrate further includes a second reflective conductive layer 260, which is located on the side of the transparent conductive layer 240 facing away from the substrate 200. The nth sub-pixel PX further includes a reflective portion 261, which is located in the second reflective conductive layer 260, and a fourth opening K4 is provided on the reflective portion 261. The orthographic projection of the reflective portion 261 on the substrate 200 at least covers the orthographic projections of the source portion A and the third electrode plate C13 on the substrate 200, and the orthographic projection of the fourth opening K4 on the substrate 200 covers the orthographic projection of the first sub-portion 2411 on the substrate 200.

[0163] The second reflective conductive layer 260 is made of a reflective conductive material, enabling the reflective portion 261 to reflect light. Thus, in reflective displays, the reflective portion 261 can reflect ambient light, and in transmissive displays, it can prevent light leakage. The fourth opening K4 exposes the reflective area FS of the sub-pixel PX, allowing light emitted from the backlight module to exit through it in transmissive displays. At the edge region of the fourth opening K4, the reflective portion 261 is electrically connected to the first sub-portion 2411, enabling the reflective portion 261 to function as a pixel electrode in the reflective area FS.

[0164] For example, after the display substrate and the opposing substrate 300 are aligned, the liquid crystal layer is located on the side of the reflective portion 261 facing away from the substrate 200. In this way, during reflective display, ambient light can be reflected back into the liquid crystal layer via the reflective portion 261. At the same time, when the switching transistor T2 is turned on, the data voltage signal on the data line DL can be transmitted to the reflective portion 261 via the switching transistor T2, the second electrode C12, the second sub-part 2412, and the first sub-part 2411. This allows a second electric field to be formed between the reflective portion 261 and the corresponding common electrode. This second electric field can drive the liquid crystal in the liquid crystal layer to change its rotation direction, thereby realizing the display function.

[0165] Reference Figure 13 The reflector 261 covers the active part A and the third electrode plate C13. Through the third electrode plate C13, the part of the reflector 261 covering the active part A and the part covering the third electrode plate C11 are roughly in the same horizontal plane, so that the reflective surface in the reflective area FS is as flat as possible.

[0166] The orthographic projection of the reflective portion 261 onto the substrate 200 covers not only the active portion A and the third electrode plate C13, but also the orthographic projection of the entire reflective area FS onto the substrate 200. Furthermore, the orthographic projection of the reflective portion 261 onto the substrate 200 can overlap with adjacent gate lines and data lines. For example, the reflective portion 261 in the nth sub-pixel PX can overlap with the xth data line DL, the (x+1)th data line DL, the (y-1)th gate line GL, and the yth gate line GL. This increases the reflective area in reflective displays and, in transmissive displays, allows the reflective portion 261, data lines GL, and gate lines DL to replace the black matrix in the color filter substrate for light blocking, thereby eliminating the need for the black matrix in the color filter substrate and increasing the amount of light received in reflective displays.

[0167] In some specific embodiments, the first electrode plate C11 includes a third sub-part 211 and a fourth sub-part 212. The orthographic projection of the fourth sub-part 212 on the substrate 200 is located on the side of the orthographic projection of the second sub-part 2412 on the substrate 200 that is away from the orthographic projection of the first sub-part 2411 on the substrate 200. The orthographic projection of the third sub-part 211 on the substrate 200 is located on the side of the orthographic projection of the fourth sub-part 212 on the substrate 200 that is close to the second sub-part 2412. The orthographic projection of the third sub-part 211 on the substrate 200 at least partially surrounds the orthographic projection of the first via V1 on the substrate 200. Furthermore, a portion of the orthographic projection of the third sub-part 211 on the substrate 200 overlaps with the orthographic projection of the second sub-part 2412 on the substrate 200, and another portion overlaps with the orthographic projection of the second sub-part 2412 on the substrate 200 at intervals. In the thickness direction of the display substrate, the third sub-part 211 overlaps with the second sub-part 2412, and extends from the overlapping position to the periphery of the second sub-part 2412.

[0168] The first via V1 is closer to the first sub-part 2411 than the fourth sub-part 212. The orthographic projection of the third sub-part 211 on the substrate 200 is approximately "U"-shaped. In the thickness direction of the display substrate, the inner side of the U-shape overlaps with the second sub-part 2412, and the outer side is spaced apart from the second sub-part 2412. This allows the third sub-part 211 to surround the periphery of the first via V1 and maintain a certain distance from it. This prevents electrostatic discharge near the location of the first via V1 from damaging adjacent devices. For example, when the first via V1 is formed by a dry etching process (e.g., plasma bombardment), charge accumulation will form on the second electrode plate C12 exposed by the first via V1. In the embodiments of this disclosure, by having the third sub-part 211 surround the periphery of the first via V1 and maintain a certain distance from it, an electrostatic discharge path can be prevented between the charge accumulation location on the second electrode plate C12 and the third sub-part 211, thereby preventing electrostatic discharge.

[0169] Furthermore, the third sub-part 211 extends to the periphery of the second sub-part 2412, specifically to the periphery of the overlapping area of ​​the second electrode C12 and the second sub-part 2412. The third sub-part 211 can reduce the film layer difference caused by the overlap of the second sub-part 2412 and the second electrode C12, thereby improving the uniformity of film thickness in the overlapping area of ​​the second electrode C12 and the second sub-part 2412 and its periphery, and thus improving the flatness of the reflective surface of the reflective region FS.

[0170] Optionally, the orthographic projection of the third sub-part 211 on the substrate 200 can overlap with the orthographic projection of the second electrode C12 on the substrate 200, thereby further increasing the capacitance value of the storage capacitor C.

[0171] In some specific embodiments, the third sub-part 211 includes: a first structure 2111 and a second structure 2112.

[0172] In embodiments of this disclosure, the first structure 2111 and the second structure 2112 may include strip-shaped structures, wherein the dimensions of the first structure 2111 and the second structure 2112 in the first direction Y are larger than their dimensions in the second direction X, for example, referring to... Figure 3 The first structure 2111 and the second structure 2112 are vertically extending strip structures.

[0173] The orthographic projections of the first sub-part 2411, the second sub-part 2412, and the active part A on the substrate 200 are arranged along the first direction Y. The orthographic projection of the first via V1 on the substrate 200 is located on the side of the orthographic projection of the first sub-part 2411 on the substrate 200 that is close to the orthographic projection of the active part A on the substrate 200. In the second direction X, the orthographic projections of the first structure 2111 and the second structure 2112 on the substrate 200 are located on opposite sides of the orthographic projection of the first via V1 on the substrate 200.

[0174] The orthographic projection of a portion of the first structure 2111 near the second structure 2112 on the substrate 200 overlaps with the orthographic projection of the second electrode C12 on the substrate 200, while the orthographic projections of the portion of the second structure 2112 away from the first structure 2111 on the substrate 200 and the second electrode C12 on the substrate 200 are spaced apart. And / or, the orthographic projection of the portion of the second structure 2112 near the first structure 2111 on the substrate 200 overlaps with the orthographic projection of the second electrode C12 on the substrate 200, while the orthographic projections of the portion of the first structure 2111 away from the first structure 2111 on the substrate 200 and the second electrode C12 on the substrate 200 are spaced apart, with the second direction X intersecting the first direction Y.

[0175] In embodiments of this disclosure, multiple gate lines GL are arranged along a first direction Y, and the nth sub-pixel PX is electrically connected to the yth gate line GL. In the direction from the (y-1)th gate line GL to the yth gate line GL, a first sub-part 2411, a second sub-part 2412, and an active part A are arranged sequentially. Multiple data lines DL are arranged along a second direction X, and the nth sub-pixel PX is electrically connected to the xth data line DL. In the direction from the xth data line DL to the (x+1)th data line DL, a first structure 2111, a first via V1, and a second structure 2112 are arranged sequentially.

[0176] In the embodiments of this disclosure, for either the first structure 2111 or the second structure 2112, its orthographic projection on the substrate 200 partially overlaps with the orthographic projection of the second sub-part 2412 on the substrate 200. For example, in the thickness direction of the display substrate, the right side of the first structure 2111 overlaps with the second sub-part 2412, and its left side is spaced apart from the second sub-part 2412. The left side of the second structure 2112 overlaps with the second sub-part 2412, and its right side is spaced apart from the second sub-part 2412. In this way, the third sub-part 211 reduces the overlap area between the second electrode C12 and the second sub-part 2412 and the film layer difference on its left and right sides.

[0177] Figure 14 The spacing between the first structure, the second structure, the first via, and the first sub-part is schematically shown in an embodiment of this disclosure.

[0178] Reference Figure 14 In some specific embodiments, in the first direction Y, the orthographic projection of either the first structure 2111 or the second structure 2112 on the substrate 200 has a first distance d1 between it and the orthographic projection of the first sub-part 2411 on the substrate 200, and the orthographic projection of the first via V1 on the substrate 200 has a second distance d2 between it and the orthographic projection of the first sub-part 2411 on the substrate 200.

[0179] In the embodiments of this disclosure, the first spacing d1 may refer to the average spacing between the orthographic projection of the first structure 2111 (second structure 2112) on the substrate 200 and the orthographic projection of the first sub-part 2411 on the substrate 200, and the second spacing d2 may refer to the average spacing between the orthographic projection of the first via V1 on the substrate 200 and the orthographic projection of the first sub-part 2411 on the substrate 200. The first spacing d1 is smaller than the second spacing d2, so that the first structure 2111 (second structure 2112) extends as far as possible toward the first sub-part 2411, thereby increasing the coverage area of ​​the first structure 2111 (second structure 2112) and further improving the film thickness uniformity.

[0180] See also Figure 6 and Figure 11 In some specific embodiments, the transparent conductive portion 241 further includes a connecting portion 2413 located between the first sub-portion 2411 and the second sub-portion 2412. The orthographic projection of the second electrode plate C12 on the substrate 200 overlaps with the orthographic projection of the connecting portion 2413 on the substrate 200.

[0181] Optionally, the connecting sub-part 2413 may be arranged around the first sub-part 2411, and the orthographic projection of either the first structure 2111 or the second structure 2112 on the substrate 200 is spaced apart from the orthographic projection of the connecting sub-part 2413 on the substrate 200. The second electrode C12 is closer to the first sub-part 2411 than the first structure 2111 (second structure 2112), and the second electrode C12 is close to the transmission region TS. This facilitates alignment based on the second electrode C12 in subsequent steps.

[0182] See also Figure 9 and Figure 11 In some specific embodiments, the orthographic projection of the third electrode plate C13 on the substrate 200 overlaps with the orthographic projection of the fourth sub-part 212 on the substrate 200. This allows the first electrode plate C11, the second electrode plate C12, and the third electrode plate C13 to overlap, thereby reducing the space occupied by the three electrode plates in the horizontal direction.

[0183] Optionally, in the first direction Y, the orthographic projection of the third electrode C13 onto the substrate 200 lies between the orthographic projection of the third sub-part 2412 onto the substrate 200 and the orthographic projection of the active part A onto the substrate 200. In this way, the third electrode C13 is further away from the second sub-part 2412 than the third sub-part 211, thereby maintaining a certain distance between the third electrode C13 and the second sub-part 2412 to prevent short circuit between them.

[0184] Figure 15 The spacing between the first electrode plate, the second electrode plate, the third electrode plate and the data line in an embodiment of this disclosure is schematically shown.

[0185] Combined with reference Figure 11 and Figure 15 In some specific embodiments, the display substrate further includes multiple data lines DL, which are arranged along a second direction X. The xth data line DL is electrically connected to the nth sub-pixel PX. In the nth sub-pixel PX, in the second direction X, there is a third distance d3 between the orth projection of the third electrode plate C13 on the substrate 200 and the orth projection of the xth data line DL on the substrate 200; a fourth distance d4 between the orth projection of the third electrode plate C13 on the substrate 200 and the orth projection of the (x+1)th data line DL on the substrate 200; a fifth distance d5 between the orth projection of the second electrode plate C12 on the substrate 200 and the orth projection of the xth data line DL on the substrate 200; and a sixth distance d6 between the orth projection of the second electrode plate C12 on the substrate 200 and the orth projection of the (x+1)th data line DL on the substrate 200.

[0186] It should be noted that the spacing mentioned above may refer to the average spacing or minimum spacing between two structures. In the embodiments disclosed herein, unless otherwise specified, the spacing is described as the average spacing between two structures.

[0187] In the embodiments of this disclosure, the third spacing d3 is smaller than the fifth spacing d5, and the fourth spacing d4 is smaller than the sixth spacing d6. This ensures that the second electrode C12 maintains a safe distance from the x-th data line DL and the (x+1)-th data line DL, preventing short circuits. In the second direction X, the left side of the third electrode C13 is closer to the x-th data line DL than the left side of the second electrode C12, and the right side of the third electrode C13 is closer to the (x+1)-th data line DL than the right side of the second electrode C12. This prevents changes in the overlap position of the second electrode C12 and the third electrode C13 due to process variations (where parts that should overlap become non-overlapping due to misalignment). This helps ensure the uniformity of the storage capacitor C.

[0188] In some specific embodiments, in the nth sub-pixel PX, in the second direction X, there is a seventh spacing d7 between the orth projection of the first electrode plate C11 on the substrate 200 and the orth projection of the xth data line DL on the substrate 200, and an eighth spacing d8 between the orth projection of the first electrode plate C11 on the substrate 200 and the orth projection of the (x+1)th data line DL on the substrate 200.

[0189] In the embodiments of this disclosure, the fifth spacing d5 is greater than the seventh spacing d7, and the sixth spacing d6 is greater than the eighth spacing d8. In the second direction X, the left side of the first electrode C11 is closer to the x-th data line DL than the left side of the second electrode C12, and the right side of the first electrode C11 is closer to the (x+1)-th data line DL than the right side of the second electrode C12. This prevents the overlapping position of the first electrode C11 and the third electrode C13 from changing due to process fluctuations (the part that should have overlapped becomes non-overlapping due to misalignment). This helps to ensure the uniformity of the storage capacitor C.

[0190] Optionally, in the embodiments of this disclosure, there are no restrictions on the size relationship between the third spacing d3 and the seventh spacing d7, and the size relationship between the fourth spacing d4 and the eighth spacing d8. For example, the third spacing d3 can be less than or equal to the seventh spacing d7, and the fourth spacing d4 can be less than or equal to the eighth spacing d8, as long as these spacings can ensure that the parasitic capacitance generated by the first electrode C11 (third electrode C13) and the data line DL is within an acceptable range.

[0191] Figure 16The spacing between the first electrode plate, the second electrode plate, the third electrode plate and the active part in an embodiment of this disclosure is schematically shown.

[0192] Combined with reference Figure 11 and Figure 16 In some specific embodiments, the orthographic projections of the third electrode C13 on the substrate 200 and the orthographic projections of the active part A on the substrate 200 are arranged along the first direction Y, and a ninth distance d9 is provided between the orthographic projections of the third electrode C13 and the active part A on the substrate 200 in the first direction Y. The orthographic projections of the second electrode C12 on the substrate 200 and the active part A on the substrate 200 are arranged along the first direction Y, and a tenth distance d10 is provided between the orthographic projections of the second electrode C12 and the active part A on the substrate 200 in the first direction Y. The first direction Y intersects the second direction X.

[0193] In the embodiments of this disclosure, the ninth spacing d9 is greater than the tenth spacing d10. In the first direction Y, the lower side of the second electrode C12 is closer to the active part A than the lower side of the third electrode C13. This prevents the area of ​​the third electrode C13 from becoming too large, thereby maintaining a safe distance between the third electrode C13 and the active part A to prevent the common voltage signal on the third electrode C13 from interfering with the characteristics of the switching transistor T2.

[0194] In some specific embodiments, the orthographic projection of the first electrode plate C11 on the substrate 200 and the orthographic projection of the active part A on the substrate 200 are arranged along the first direction Y, and there is an eleventh distance d11 between the orthographic projection of the first electrode plate C11 on the substrate 200 and the orthographic projection of the active part A on the substrate 200 in the first direction Y.

[0195] In the embodiments of this disclosure, the ninth spacing d9 is smaller than the eleventh spacing d11. In the first direction Y, the lower side of the second electrode C12 is closer to the active part A than the lower side of the first electrode. This prevents the area of ​​the first electrode C11 from being too large, which helps to maintain a sufficient distance between the first electrode C11 and the active part A, so as to prevent the first electrode C11 from interfering with the characteristics of the switching transistor T2.

[0196] Optionally, the orthographic projection of the gate G of the switching transistor T2 onto the substrate 200 covers the orthographic projection of the active portion A onto the substrate 200. The orthographic projections of the first electrode C11 onto the substrate 200 and the gate G of the switching transistor T2 onto the substrate 200 are aligned along a first direction Y, and a twelfth spacing is formed between them in the first direction Y. The orthographic projections of the second electrode C12 onto the substrate 200 and the gate G of the switching transistor T2 onto the substrate 200 are aligned along the first direction Y, and a thirteenth spacing is formed between them in the first direction Y. The thirteenth spacing is smaller than the twelfth spacing. This ensures that the first electrode C11 and the gate G of the switching transistor T2 maintain a sufficient distance to prevent the first electrode C11 from being short-circuited with the gate G of the switching transistor T2.

[0197] Reference Figure 13 In some specific embodiments, in addition to the first insulating layer 250 described above, corresponding insulating layers can be provided between adjacent conductive film layers. For example, a second insulating layer 280 is provided between the first conductive layer 220 and the semiconductor layer 210; the second insulating layer 280 can also be referred to as a gate insulating layer. A planarization layer 290 can be provided between the transparent conductive layer 240 and the second reflective conductive layer 260. The planarization layer 290 may include an organic material and is used to improve the film layer step difference so that the second reflective conductive layer 260 remains as flat as possible.

[0198] The preparation process in the embodiments of this disclosure is briefly described below.

[0199] First, a first conductive layer 220 is formed on a substrate 200. The first conductive layer 220 includes a first electrode C11, the gate of a switching transistor T2, and a gate line GL. Next, a second insulating layer 280 is formed on the first conductive layer 220, and a semiconductor layer 210 is formed on the second insulating layer 280, the semiconductor layer 210 including an active portion A. Then, a second conductive layer 230 is formed on the semiconductor layer 210, the second conductive layer 230 including a second electrode C12, the source and drain of the switching transistor T2, and a data line DL. A first insulating layer 250 is formed on the second conductive layer 230, and a first via V1 is formed therein. Subsequently, a transparent conductive layer 240 is formed on the first insulating layer 250, the transparent conductive layer 240 including a third electrode C13 and a transparent conductive portion 241, the transparent conductive portion 241 being electrically connected to the second electrode C12 through the first via V1. Finally, a planarization layer 290 and a second reflective conductive layer 260 are formed on the transparent conductive layer 240. A large hole V2 is formed in the planarization layer 290 corresponding to the position of the transmission region TS. The position of the large hole V2 in the second reflective conductive layer 260 overlaps with the transparent conductive part 241.

[0200] Through the above embodiments, by adding a third electrode plate C13 to the transparent conductive layer 240, the capacitance value of the storage capacitor C can be increased without increasing the process, and at the same time the film layer difference caused by the active part A can be improved.

[0201] Figures 17 to 28 The diagram schematically illustrates a planar view of a sub-pixel in some other embodiments of this disclosure. Figure 29 Cross-sectional views of sub-pixels are schematically shown in some other embodiments of this disclosure. Figure 17 A schematic plan view of the first conductive layer is shown in some other embodiments of this disclosure. Figure 18 A schematic plan view of the semiconductor layer is shown in some other embodiments of this disclosure. Figure 19 A schematic plan view of the second conductive layer is shown in some other embodiments of this disclosure. Figure 20 A schematic plan view of the first insulating layer is shown in some other embodiments of this disclosure. Figure 21 A schematic plan view of the transparent conductive layer in some other embodiments of this disclosure is shown. Figure 22 A schematic plan view of the first reflective conductive layer is shown in some other embodiments of this disclosure. Figure 23 A schematic plan view of the second reflective conductive layer is shown in some other embodiments of this disclosure. Figure 24 A schematic plan view of the first conductive layer and semiconductor layer is shown in some other embodiments of this disclosure. Figure 25 The schematic diagram illustrates a plan view of the first conductive layer, semiconductor layer, second conductive layer, and first insulating layer in some other embodiments of this disclosure. Figure 26The schematic diagram illustrates a plan view of a first conductive layer, a semiconductor layer, a second conductive layer, a first insulating layer, and a first reflective conductive layer in some other embodiments of the present disclosure. Figure 27 The schematic diagram illustrates a plan view of a first conductive layer, a semiconductor layer, a second conductive layer, a first insulating layer, a first reflective conductive layer, and a transparent conductive layer in other embodiments of this disclosure. Figure 28 The schematic diagram illustrates a plan view of a first conductive layer, a semiconductor layer, a second conductive layer, a first insulating layer, a first reflective conductive layer, a transparent conductive layer, and a second reflective conductive layer in some other embodiments of the present disclosure.

[0202] The following is combined with Figures 17 to 29 The scheme in which the third electrode C13 is located in the first reflective conductive layer in the embodiments of this disclosure will be described.

[0203] In some specific embodiments, the display substrate further includes a first reflective conductive layer 270, which is located on the side of the second conductive layer 230 facing away from the substrate 200, and a third electrode C13 is located in the first reflective conductive layer 270. The display substrate also includes multiple data lines DL and multiple gate lines GL. The multiple data lines DL are arranged along a second direction X, and the multiple gate lines GL are arranged along a first direction Y, which intersects the second direction X. The x-th data line DL is electrically connected to the n-th sub-pixel PX, and the y-th gate line GL is electrically connected to the n-th sub-pixel PX. The orth projection of at least one of the x-th data line DL, the (x+1)-th data line DL, the (y-1)-th gate line GL, and the y-th gate line GL onto the substrate 200 overlaps with the orth projection of the third electrode C13 in the n-th sub-pixel PX onto the substrate 200. Here, x and y are both positive integers.

[0204] In embodiments of this disclosure, the first reflective conductive layer 270 comprises a reflective metallic material, such as silver, copper, and aluminum, or an alloy of the aforementioned metals. Since the first reflective conductive layer 270 comprises a reflective metallic material, the third electrode C13 disposed in the first reflective conductive layer 270 can reflect light. Based on this, embodiments of this disclosure can allow the third electrode C13 to overlap with at least one of the x-th data line DL, the (x+1)-th data line DL, the (y-1)-th gate line GL, and the y-th gate line GL, to replace the black matrix originally disposed in the color filter substrate and achieve a light-shielding effect, thereby preventing light leakage during transmissive display. Simultaneously, by using the third electrode C13, data lines DL, and gate lines GL instead of the black matrix, the amount of light entering during reflective display can be increased, and the reflective area can also be increased, thereby improving the display effect during reflective display. For example, in the thickness direction of the display substrate, the third electrode plate C13 overlaps with each of the x-th data line DL, the x+1-th data line DL, the y-1-th gate line GL, and the y-th gate line GL, thereby covering the reflective area FS as much as possible.

[0205] Furthermore, since the third electrode C13 can reflect light, compared to the aforementioned embodiments, the linewidths of the gate line GL and data line DL in this embodiment can be reduced, thereby reducing the space occupied by the gate line GL and data line DL. This is beneficial for increasing the size of each structure in the sub-pixel PX. For example, in the embodiments of this disclosure, the linewidth of the gate line GL can be set to 3-6 μm, and the linewidth of the data line DL can be set to 2-4 μm. After reducing the linewidths of the gate line GL and data line DL, the size of the third electrode C13 in the first direction Y and the second direction X can be increased, thereby ensuring that in the thickness direction of the display substrate, the third electrode C13 in the nth sub-pixel PX can always overlap with each of the xth data line DL, the (x+1)th data line DL, the (y-1)th gate line GL, and the yth gate line GL, thus ensuring no light leakage during transmissive display.

[0206] Optionally, the third plate C13 in adjacent sub-pixels PX can be formed as a single structure.

[0207] In some specific embodiments, the display substrate further includes a transparent conductive layer 240 and a first insulating layer 250. The transparent conductive layer 240 is located on the side of the second conductive layer 230 facing away from the substrate 200, and the first insulating layer 250 is located between the second conductive layer 230 and the transparent conductive layer 240. The nth sub-pixel PX further includes a transparent conductive portion 241, which is located in the transparent conductive layer 240. The transparent conductive portion 241 includes a first sub-portion 2411 and a second sub-portion 2412, which are electrically connected. A first through-hole V1 is provided on the first insulating layer 250, the first sub-part 2411 is located in the transmission region TS, the second sub-part 2412 is located in the reflection region FS, the orthographic projection of the second sub-part 2412 on the substrate 200 overlaps with the orthographic projection of the second electrode C12 on the substrate 200, and in the overlapping area, the second sub-part 2412 and the second electrode C12 are electrically connected through the first through-hole V1.

[0208] Unlike the previous embodiments, in this embodiment, the third electrode C13 is no longer provided in the transparent conductive layer 240. However, the transparent conductive layer 240 still provides a transparent conductive portion 241, which is used as the pixel electrode in the transmission region TS. The transparent conductive portion 241 can have the same morphological design as in the previous embodiments, or it can have a different morphological design.

[0209] For example, in this embodiment, because the linewidth of the data line DL is reduced, the shape design of the transmission region TS is more flexible. For instance, the transmission region TS can be a vertically extending strip as in the previous embodiment. Alternatively, without changing the area of ​​the transmission region TS, the transmission region TS can be changed to a horizontally extending strip. Alternatively, without changing the area of ​​the transmission region TS, the transmission region TS can be changed to a square. Accordingly, in this embodiment, the first sub-part 2411 can be a vertical strip, a horizontal strip, or a square, etc.

[0210] In some specific embodiments, the second sub-part 2412 may adopt the same morphological design as the aforementioned embodiments, or it may adopt a different morphological design.

[0211] For example, the first sub-part 2411 adopts the same morphological design as the aforementioned embodiment. At the same time, the first electrode plate C11 adopts the design of the aforementioned embodiment, that is, the first electrode plate C11 includes the aforementioned third sub-part 211. The third sub-part 211 extends beyond the periphery of the overlapping area of ​​the second electrode plate C12 and the transparent conductive part 241, so as to improve the film thickness difference between the overlapping area and its periphery.

[0212] Alternatively, the dimensions of the first sub-part 2411 and the second sub-part 2412 in the second direction X can be made approximately the same. In this case, the design of the third sub-part 211 on the first electrode plate C11 can be eliminated, and the second sub-part 2412 can extend beyond the periphery of the overlapping area between the second electrode plate C12 and the transparent conductive part 241, thereby improving the film thickness difference between the overlapping area and its periphery. Optionally, the third electrode plate C13 can cover the portion of the second sub-part 2412 that extends to the periphery of the aforementioned overlapping area, thereby preventing parasitic capacitance between the second sub-part 2412 and the data line DL.

[0213] The third electrode plate C13 has a first opening K1 and a second opening K2. The orthographic projection of the first opening K1 onto the substrate 200 covers the orthographic projection of the transmission area TS onto the substrate 200, and the orthographic projection of the second opening K2 onto the substrate 200 covers the orthographic projection of the first via V1 onto the substrate 200. Thus, the first opening K1 allows the third electrode plate C13 to avoid the transmission area TS of the sub-pixel PX. The second opening K2 exposes the first via V1, allowing the subsequently formed transparent conductive portion 241 to be electrically connected to the second electrode plate C12 through the second opening K2 and the first via V1.

[0214] Optionally, the first opening K1 and the second opening K2 are formed as an integral structure. In addition to exposing the first via V1, the second opening K2 can also expose the second electrode plate C12 around the first via V1, thereby maintaining a certain safe distance between the third electrode plate C13 and the first via V1 to avoid accidentally damaging the third electrode plate C13 when etching the first via V1.

[0215] Optionally, the corners of the first opening K1 and the second opening K2 can be non-right-angle corners, such as arc-shaped corner areas, to reduce stress concentration at the corners.

[0216] Optionally, the orthographic projection of the second electrode plate C12 on the substrate 200 covers the orthographic projection of the second opening K2 on the substrate 200. For example, the left side of the second opening K2 is located from the left side to the right of the second electrode plate C12, and the right side of the second opening K2 is located to the left of the right side of the second electrode plate C12.

[0217] In some specific embodiments, a third opening K3 is further provided on the third electrode plate C13, and the orthographic projection of the third opening K3 on the substrate 200 covers the orthographic projection of the source portion A on the substrate 200. In the second direction X, the first opening K1 has a first dimension d21, the second opening K2 has a second dimension d22, and the third opening K3 has a third dimension d23. The third dimension d23 is smaller than the first dimension d21 and larger than the second dimension d22.

[0218] In embodiments of this disclosure, the pattern of the third opening K3 may be substantially the same as the pattern of the active part A.

[0219] Optionally, the orthographic projection of the gate of the switching transistor T2 onto the substrate 200 covers the orthographic projection of the third opening K3 onto the substrate 200. This allows the third electrode C13 to bypass the active part A through the third opening K3, preventing the third electrode C13 from affecting the characteristics of the switching transistor T2. At the same time, the area of ​​the third opening K3 is not too large, so that the third electrode C13 covers as much of the reflection area FS as possible, thereby maximizing the improvement of the film layer step difference caused by the active part A.

[0220] In some specific embodiments, the orthographic projection of the first electrode plate C11 on the substrate 200 overlaps with the orthographic projection of the second sub-part 2412 on the substrate 200, and the orthographic projection of the first electrode plate C11 on the substrate 200 is located on the side of the orthographic projection of the first via V1 on the substrate 200 away from the first sub-part 2411.

[0221] In the embodiments disclosed herein, the first electrode plate C11 is closer to the active portion A than the first via V1, and the first electrode plate C11 is located below the first via V1. Unlike the previous embodiments, this embodiment omits the design of the third sub-part 211 on the first electrode plate C11, and improves the aforementioned film thickness step difference through the second sub-part 2412. The first electrode plate C11 is entirely located on the side of the first via V1 closer to the active portion A.

[0222] In some specific embodiments, the display substrate further includes a second reflective conductive layer 260, which is located on the side of the first reflective conductive layer 270 facing away from the substrate 200. The nth sub-pixel PX further includes a reflective portion 261, which is located in the second reflective conductive layer 260. The orthographic projection of the reflective portion 261 on the substrate 200 covers the orthographic projections of the second opening K2 and the third opening K3 on the substrate 200. A fourth opening K4 is also provided on the reflective portion 261, and the orthographic projection of the fourth opening K4 on the substrate 200 covers the transmissive region TS. At the edge region of the fourth opening K4, the reflective portion 261 is electrically connected to the first sub-portion 2411.

[0223] In embodiments of this disclosure, the second reflective conductive layer 260 includes a reflective metallic material. The reflective portion 261 and the third electrode C13 can form a complementary pattern, that is, in the reflective area FS, the portion exposed by the third electrode C13 can be covered by the reflective portion 261, and the portion exposed by the third electrode C13 is covered by the reflective portion 261, thereby increasing the reflective area.

[0224] In the embodiments of this disclosure, the orthographic projection of the first opening K1 on the substrate 200 covers the orthographic projection of the fourth opening K4 on the substrate 200, so that the range of the transmission region TS can be defined by the fourth opening K4.

[0225] In some specific embodiments, the dimension of the fourth opening K4 in the second direction X is greater than or equal to the dimension of the fourth opening K4 in the first direction Y. The fourth opening K4 is a horizontal strip structure. Alternatively, the fourth opening K4 is a square; compared to a strip structure, a square structure of the fourth opening K4 can better improve the light leakage problem in transmissive displays.

[0226] Reference Figure 29 In some specific embodiments, in addition to the first insulating layer 250 described above, corresponding insulating layers can be provided between adjacent conductive film layers. For example, a second insulating layer 280 is provided between the first conductive layer 220 and the semiconductor layer 210; the second insulating layer 280 can also be referred to as a gate insulating layer. A planarization layer 290 can be provided between the transparent conductive layer 240 and the second reflective conductive layer 260. The planarization layer 290 may include an organic material and is used to improve the film layer step difference so that the second reflective conductive layer 260 remains as flat as possible.

[0227] The first insulating layer 250 may include a composite structure of two insulating film layers. For example, the first insulating layer 250 includes a first spacer layer 251 and a second spacer layer 252. The first spacer layer 251 is located between the first reflective conductive layer 270 and the second conductive layer 230, and the second spacer layer 252 is located between the first reflective conductive layer 270 and the transparent conductive layer 240. The first via V1 penetrates the first spacer layer 251 and the second spacer layer 252.

[0228] The preparation process in the embodiments of this disclosure is briefly described below.

[0229] First, a first conductive layer 220 is formed on a substrate 200. The first conductive layer 220 includes a first electrode C11, the gate of a switching transistor T2, and a gate line GL. Compared to the previous embodiment, the linewidth of the gate line GL is reduced. Next, a second insulating layer 280 is formed on the first conductive layer 220, and a semiconductor layer 210 is formed on the second insulating layer 280. The semiconductor layer 210 includes an active portion A. Then, a second conductive layer 230 is formed on the semiconductor layer 210. The second conductive layer 230 includes a second electrode C12, the source and drain of the switching transistor T2, and a data line DL. Compared to the previous embodiment, the linewidth of the data line DL is reduced. A first spacer layer 251 is formed on the second conductive layer 230. Subsequently, a first reflective conductive layer 270 is formed on the first spacer layer 251. The first reflective conductive layer 270 includes a third electrode C13. Next, a second spacer layer 252 is formed on the first reflective conductive layer 270, and a first via V1 is formed penetrating the first spacer layer 251 and the second spacer layer 252. Then, a transparent conductive layer 240 is formed on the second spacer layer 252, the transparent conductive layer 240 including a transparent conductive portion 241, the transparent conductive portion 241 being electrically connected to the second electrode plate C12 through the first via V1. Finally, a planarization layer 290 and a second reflective conductive layer 260 are formed on the transparent conductive layer 240, the planarization layer 290 having a large hole V2 formed corresponding to the position of the transmission region TS, and the second reflective conductive layer 260 overlapping the transparent conductive portion 241 at the position of the large hole V2.

[0230] In the embodiments of this disclosure, the third electrode plate C13 is disposed in the first reflective conductive layer 270. Compared with the solution disposed in the transparent conductive layer 240, the size of the third electrode plate C13 is not limited by the transparent conductive part 241. Therefore, the design is more flexible and the coverage area can be larger. In addition to increasing the capacitance value of the storage capacitor C and improving the film thickness difference, it can also increase the reflective area and improve the reflection effect.

[0231] The general design that can be applied to each of the above embodiments is described below in the embodiments of this disclosure.

[0232] Combined with reference Figure 2 and Figure 11In some specific embodiments, the display substrate further includes a display area and a peripheral area NA that at least partially surrounds the display area, with multiple sub-pixels PX located in the display area. The display substrate also includes multiple first connection lines L1, multiple second connection lines L2, and at least one common signal line VCOM. The multiple first connection lines L1 are arranged along a first direction Y, and the multiple second connection lines L2 are arranged along the first direction Y. In the nth sub-pixel PX, the third electrode plate C13 is electrically connected to the i-th first connection line L1, the first electrode plate C11 is electrically connected to the j-th second connection line L2, and the i-th first connection line L1 and the j-th second connection line L2 are electrically connected to the common signal line VCOM in the peripheral area NA. Here, i and j are both positive integers.

[0233] In embodiments of this disclosure, the common signal line VCOM is located in the peripheral area NA; for example, the common signal line VCOM is disposed at least partially surrounding the display area AA. Optionally, the common signal line VCOM is located in the first conductive layer 220.

[0234] Optionally, a gate driving circuit 21 is provided in the peripheral area NA, and the orthographic projection of the common signal line VCOM on the substrate 200 is located between the orthographic projection of the display area AA on the substrate 200 and the orthographic projection of the gate driving circuit 21 on the substrate 200.

[0235] The first connecting line L1 and the second connecting line L2 extend along the second direction X. The common signal line VCOM crosses the first connecting line L1 (or the second connecting line L2) in the peripheral area NA. At the crossing position, the common signal line VCOM and the first connecting line L1 (or the second connecting line L2) can be connected through the connecting hole.

[0236] Optionally, when the third electrode plate C13 is located in the first reflective conductive layer 270, the third electrode plate C13 in the multiple sub-pixels PX can be formed as an integral structure. In addition to being electrically connected to the common signal line VCOM through the first connecting line L1 extending along the second direction X, the third electrode plate C13 can also be electrically connected to the common signal line VCOM through the third connecting line extending along the first direction Y.

[0237] In some specific embodiments, in the reflective region FS, the orthographic projection of the active part A on the substrate 200 and the orthographic projection of the third electrode C13 on the substrate 200 form a complementary pattern.

[0238] In the embodiments of this disclosure, the orthographic projections of the active part A and the third electrode C13 on the substrate 200 forming a complementary pattern in the reflective area FS can mean that, except for the area of ​​the reflective area FS that must be exposed (e.g., the first via V1 and its surrounding area and the surrounding area of ​​the active part A), the orthographic projections of the active part A and the third electrode C13 on the substrate 200 can fill the entire reflective area FS, thereby maximizing the coverage area of ​​the third electrode C13 to better improve the film thickness step problem caused by the active part A.

[0239] At least some embodiments of this disclosure also provide a display panel, which includes the display substrate as described above, having a display area AA and a peripheral area NA, and related structures therein. For example, the display panel may be a liquid crystal display panel.

[0240] Figure 30 and Figure 31 A schematic cross-sectional view of the display panel in an embodiment of this disclosure is shown, wherein, Figure 30 This shows the display panel with the third electrode plate located in the transparent conductive layer. Figure 31 The third electrode is shown in the display panel located in the first reflective conductive layer. Figure 32 A schematic plan view of the color resist in an embodiment of this disclosure is shown.

[0241] See also Figures 30 to 32 The display panel in this embodiment includes a display substrate 400 and a counter substrate 300. The display substrate 400 is the same as the one described in the previous embodiment. The counter substrate 300 includes a plurality of color resists SRs, with the m-th color resist SR corresponding to the n-th sub-pixel PX. The m-th color resist SR includes a first region Q1, a second region Q2, and a third region Q3. The orthographic projection of the first region Q1 onto the substrate 200 covers the orthographic projection of the transmissive region TS of the n-th sub-pixel PX onto the substrate 200. The orthographic projection of the third region Q3 onto the substrate 200 covers the orthographic projection of the active portion A of the n-th sub-pixel PX onto the substrate 200. In the first direction Y, the second region Q2 is located between the first region Q1 and the third region Q3. In the second direction X, the size of the second region Q2 is less than or equal to the size of the third region Q3. The second direction X intersects the first direction Y.

[0242] Optionally, the first direction Y may include the extension direction of the data line DL on the display substrate, and the second direction X includes the extension direction of the gate line GL on the display substrate, for example, referring to... Figure 2 The first direction Y can be Figure 2 The vertical direction in the middle, the second direction X can be Figure 2 The horizontal direction in the middle, that is, the intersection of the first direction and the second direction.

[0243] In the embodiments of this disclosure, each color resist SR allows light of one color to pass through, and different color resist SRs allow different colors of light to pass through. For example, multiple color resist SRs may allow red light, green light, and blue light to pass through, respectively. Multiple color resist SRs can be configured in a one-to-one correspondence with multiple sub-pixels PX; that is, each color resist SR corresponds to one sub-pixel PX, and different sub-pixels PX correspond to different color resist SRs. The nth sub-pixel PX can refer to any one of the multiple sub-pixels PX, and the mth color resist SR is the color resist SR configured to correspond to that sub-pixel PX.

[0244] Reference Figure 32 The first region Q1 covers the transmission area TS, the third region Q3 covers the switching transistor T2, and the second region Q2 is located between the first region Q1 and the third region Q3. The second region Q2 is narrower than the third region Q3, which can increase the amount of ambient light entering during reflective display, thereby improving the reflective display effect.

[0245] In some specific embodiments, the plurality of color resists SR include a first color resist SR1, a second color resist SR2, and a third color resist SR3. The first color resist SR1, the second color resist SR2, and the third color resist SR3 are of different colors, and the orthographic projections of the first color resist SR1, the second color resist SR2, and the third color resist SR3 on the substrate 200 are spaced apart from each other to prevent optical crosstalk between the plurality of color resists SR. For example, the first color resist SR1 is a red color resist, the second color resist SR2 is a green color resist, and the third color resist SR3 is a blue color resist.

[0246] In the second direction X, the second region Q2 of the first color resist SR1 has a fourth dimension d31, the second region Q2 of the second color resist has a fifth dimension d32, and the second region Q2 of the third color resist has a sixth dimension d33. The fifth dimension d32 is larger than the fourth dimension d31 and smaller than the sixth dimension d33. For example, the second region Q2 of the first color resist SR1 is narrower than the second region Q2 of the second color resist SR2, and the second region Q2 of the second color resist is narrower than the second region Q2 of the third color resist SR3.

[0247] In the embodiments of this disclosure, the second region Q2 of different color resists SRs has different sizes, thereby meeting the needs of different color light intake.

[0248] It should be noted that the dimensional relationship of the second region Q2 between multiple color resists SR in the embodiments of this disclosure is not limited to the above example, and can be determined according to actual needs, and will not be listed one by one here.

[0249] In some specific embodiments, the display panel further includes a liquid crystal layer LC, which includes multiple dimming regions TG, with the z-th dimming region TG corresponding to the n-th sub-pixel PX.

[0250] The z-th dimming region TG includes a first dimming region TG1 and a second dimming region TG2. The orthographic projection of the first dimming region TG1 on the substrate 200 covers the orthographic projection of the transmissive region TS of the nth sub-pixel PX on the substrate 200. The orthographic projection of the second dimming region TG2 on the substrate 200 covers the orthographic projection of the reflective region FS of the nth sub-pixel PX on the substrate 200. The cell thickness h1 of the first dimming region TG1 is greater than the cell thickness h2 of the second dimming region TG2.

[0251] In the embodiments of this disclosure, the ratio of the cell thickness h1 of the first photonic region TG1 to the cell thickness h2 of the second photonic region TG2 can be set to 2:1. Thus, in reflective display, the optical path of ambient light in the second photonic region TG2 is the first optical path, and in transmissive display, the optical path of light emitted from the backlight module in the first photonic region TG1 is the second optical path. Since the first and second optical paths are equal, optimal transmissive and reflective display effects are achieved.

[0252] In the embodiments disclosed herein, the color filter substrate no longer has a black matrix. Instead, the light-shielding function is achieved by using structures such as the reflective portion 261, the third electrode plate C13, the data line DL, and the gate line GL in the display substrate 400. For details, please refer to the foregoing embodiments, which will not be repeated here.

[0253] At least some embodiments of this disclosure also provide a display device, which may include any device or product with display functionality. For example, the display device may be a smartphone, mobile phone, e-book reader, desktop computer (PC), laptop PC, netbook PC, personal digital assistant (PDA), portable multimedia player (PMP), digital audio player, mobile medical device, camera, wearable device (e.g., head-mounted device, electronic clothing, electronic bracelet, electronic necklace, electronic accessory, electronic tattoo, or smartwatch), television set, etc.

[0254] It should be understood that the display device according to the embodiments of this disclosure has all the features and advantages of the above-described display substrate and display panel, which can be referred to in detail above and will not be repeated here.

Claims

1. A display substrate, wherein, include: The substrate comprises a semiconductor layer, a first conductive layer, a second conductive layer, a transparent conductive layer, and a first insulating layer, wherein the second conductive layer is located on the side of the first conductive layer away from the substrate, the transparent conductive layer is located on the side of the second conductive layer opposite to the substrate, and the first insulating layer is located between the second conductive layer and the transparent conductive layer. The display substrate further includes a plurality of sub-pixels, wherein the nth sub-pixel includes: a transmissive area and a reflective area located outside the transmissive area; The nth sub-pixel further includes: a storage capacitor, a switching transistor, and a transparent conductive portion disposed in the reflective area, wherein the transparent conductive portion is located in the transparent conductive layer; The storage capacitor includes a first electrode plate, a second electrode plate, and a third electrode plate. The first electrode plate is located in the first conductive layer, the second electrode plate is located in the second conductive layer, and the third electrode plate is located on the side of the second conductive layer away from the substrate and in the transparent conductive layer. The first electrode plate and the third electrode plate are electrically connected, and the second electrode plate is electrically connected to the switching transistor. Each of the first electrode plate and the third electrode plate is insulated from the second electrode plate. The transparent conductive portion is insulated from the third electrode plate. The transparent conductive portion includes a first sub-portion and a second sub-portion, and the first sub-portion and the second sub-portion are electrically connected. The switching transistor includes an active portion, which is disposed in the semiconductor layer; Wherein, the orthographic projection of the first electrode plate on the substrate overlaps with the orthographic projection of the second electrode plate on the substrate, and the orthographic projection of the second electrode plate on the substrate overlaps with the orthographic projection of the third electrode plate on the substrate; The orthographic projection of the active part on the substrate and the orthographic projection of the third electrode plate on the substrate are spaced apart, and the thickness of the active part and the thickness of the third electrode plate are approximately the same. n is a positive integer.

2. The display substrate according to claim 1, wherein a first through-hole is provided on the first insulating layer, the first sub-part is located in the transmission region, the second sub-part is located in the reflection region, the orthographic projection of the second sub-part on the substrate overlaps with the orthographic projection of the second electrode plate on the substrate, and in the overlapping region, the second sub-part and the second electrode plate are electrically connected through the first through-hole; The first electrode plate includes a third sub-part, the orthographic projection of the third sub-part on the substrate at least partially surrounds the orthographic projection of the first via on the substrate, and a portion of the orthographic projection of the third sub-part on the substrate overlaps with the orthographic projection of the second sub-part on the substrate, and another portion overlaps with the orthographic projection of the second sub-part on the substrate at a distance.

3. The display substrate according to claim 2, wherein, The third sub-part includes: a first structure and a second structure; The first sub-part, the second sub-part, and the active part are arranged along a first direction on the orthographic projection of the substrate. In a second direction, the orthographic projections of the first structure and the second structure on the substrate are located on opposite sides of the orthographic projection of the first via on the substrate. The orthographic projection of a portion of the first structure near the second structure onto the substrate overlaps with the orthographic projection of the second sub-part onto the substrate, while the orthographic projection of a portion of the first structure away from the second structure onto the substrate is spaced apart from the orthographic projection of the second sub-part onto the substrate; and / or, The orthographic projection of a portion of the second structure on the substrate near the first structure overlaps with the orthographic projection of the second sub-part on the substrate, while the orthographic projection of a portion of the first structure on the substrate away from the orthographic projection of the second sub-part on the substrate is spaced apart. The second direction intersects with the first direction.

4. The display substrate according to claim 3, wherein, In the first direction, the orthographic projection of either the first structure or the second structure on the substrate has a first distance between the orthographic projection of the first sub-part on the substrate, and the orthographic projection of the first via on the substrate has a second distance between the orthographic projection of the first sub-part on the substrate. The first spacing is smaller than the second spacing.

5. The display substrate according to claim 1, wherein, The transparent conductive portion further includes a connecting sub-port located between the first sub-port and the second sub-port; The orthographic projection of the second electrode plate on the substrate overlaps with the orthographic projection of the connecting part on the substrate.

6. The display substrate according to claim 3, wherein, The first electrode plate further includes a fourth sub-part. In the first direction, the orthographic projection of the fourth sub-part on the substrate is located between the orthographic projection of the second sub-part on the substrate and the orthographic projection of the active part on the substrate. The orthographic projection of the third sub-part on the substrate is located on the side of the orthographic projection of the fourth sub-part on the substrate that is close to the orthographic projection of the second sub-part on the substrate. The orthographic projection of the third electrode plate on the substrate overlaps with the orthographic projection of the fourth sub-part on the substrate.

7. The display substrate according to claim 1, wherein, The display substrate also includes multiple data lines arranged along a second direction, wherein the xth data line is electrically connected to the nth sub-pixel; In the nth sub-pixel, in the second direction, there is a third spacing between the orthographic projection of the third electrode plate on the substrate and the orthographic projection of the xth data line on the substrate; there is a fourth spacing between the orthographic projection of the third electrode plate on the substrate and the orthographic projection of the (x+1)th data line on the substrate; there is a fifth spacing between the orthographic projection of the second electrode plate on the substrate and the orthographic projection of the xth data line on the substrate; and there is a sixth spacing between the orthographic projection of the second electrode plate on the substrate and the orthographic projection of the (x+1)th data line on the substrate. The third spacing is smaller than the fifth spacing, and the fourth spacing is smaller than the sixth spacing; x is a positive integer.

8. The display substrate according to claim 7, wherein, In the nth sub-pixel, in the second direction, there is a seventh spacing between the orthographic projection of the first electrode plate on the substrate and the orthographic projection of the xth data line on the substrate, and an eighth spacing between the orthographic projection of the first electrode plate on the substrate and the orthographic projection of the (x+1)th data line on the substrate. The fifth spacing is greater than the seventh spacing, and the sixth spacing is greater than the eighth spacing.

9. The display substrate according to claim 8, wherein, The orthographic projection of the third electrode plate on the substrate and the orthographic projection of the active part on the substrate are arranged along a first direction, and in the first direction, there is a ninth spacing between the orthographic projection of the third electrode plate on the substrate and the orthographic projection of the active part on the substrate. The orthographic projection of the second electrode plate on the substrate and the orthographic projection of the active part on the substrate are arranged along the first direction, and in the first direction, there is a tenth spacing between the orthographic projection of the second electrode plate on the substrate and the orthographic projection of the active part on the substrate. The first direction intersects the second direction, and the ninth spacing is greater than the tenth spacing.

10. The display substrate according to claim 9, wherein, The orthographic projection of the first electrode plate on the substrate and the orthographic projection of the active part on the substrate are arranged along the first direction, and in the first direction, there is an eleventh spacing between the orthographic projection of the first electrode plate on the substrate and the orthographic projection of the active part on the substrate, wherein the ninth spacing is smaller than the eleventh spacing.

11. The display substrate according to claim 1, wherein, The display substrate further includes a second reflective conductive layer, which is located on the side of the transparent conductive layer that is away from the substrate. The nth sub-pixel further includes a reflective portion, which is located in the second reflective conductive layer and has a fourth opening. The orthogonal projection of the reflective portion onto the substrate at least covers the orthogonal projections of the active portion and the third electrode plate onto the substrate, and the orthogonal projection of the fourth opening onto the substrate covers the orthogonal projection of the first sub-part onto the substrate.

12. The display substrate according to claim 1, wherein, The display substrate further includes a first reflective conductive layer, which is located on the side of the second conductive layer away from the substrate, and the third electrode plate is located in the first reflective conductive layer; The display substrate further includes multiple data lines and multiple gate lines, the multiple data lines are arranged along a second direction, the multiple gate lines are arranged along a first direction, and the first direction intersects the second direction; The x-th data line is electrically connected to the n-th sub-pixel, and the y-th gate line is electrically connected to the n-th sub-pixel; The orthographic projection of at least one of the data line x, the data line x+1, the gate line y-1, and the gate line y on the substrate overlaps with the orthographic projection of the third electrode plate in the nth sub-pixel on the substrate. Both x and y are positive integers.

13. The display substrate according to claim 12, wherein, The display substrate further includes a transparent conductive layer and a first insulating layer. The transparent conductive layer is located on the side of the first reflective conductive layer away from the substrate, and the first insulating layer is located between the second conductive layer and the transparent conductive layer. The nth sub-pixel further includes a transparent conductive portion, which is located in the transparent conductive layer; The transparent conductive portion includes a first sub-portion and a second sub-portion, and the first sub-portion and the second sub-portion are electrically connected. The first insulating layer is provided with a first through-hole penetrating the first insulating layer, the first sub-part is located in the transmission area, the second sub-part is located in the reflection area, the orthographic projection of the second sub-part on the substrate overlaps with the orthographic projection of the second electrode plate on the substrate, and in the overlapping area, the second sub-part and the second electrode plate are electrically connected through the first through-hole; The third electrode plate is provided with a first opening and a second opening. The orthographic projection of the first opening on the substrate covers the orthographic projection of the transmission area on the substrate, and the orthographic projection of the second opening on the substrate covers the orthographic projection of the first via on the substrate.

14. The display substrate according to claim 13, wherein, The third electrode plate is also provided with a third opening, and the orthogonal projection of the third opening on the substrate covers the orthogonal projection of the active part on the substrate. In the second direction, the first opening has a first size, the second opening has a second size, and the third opening has a third size; The third dimension is smaller than the first dimension and larger than the second dimension.

15. The display substrate according to claim 13, wherein, The orthographic projection of the first electrode plate on the substrate overlaps with the orthographic projection of the second sub-part on the substrate, and the orthographic projection of the first electrode plate on the substrate is located on the side of the orthographic projection of the first via on the substrate away from the first sub-part.

16. The display substrate according to claim 13, wherein, The first sub-part and the second sub-part have approximately the same dimensions in the second direction.

17. The display substrate according to claim 14, wherein, The display substrate further includes a second reflective conductive layer, which is located on the side of the first reflective conductive layer that is away from the substrate. The nth sub-pixel further includes a reflective portion located in the second reflective conductive layer. The orthographic projection of the reflective portion on the substrate covers the orthographic projections of the second opening and the third opening on the substrate. The reflective portion is also provided with a fourth opening, and the orthographic projection of the fourth opening on the substrate covers the transmissive area. The reflective portion is electrically connected to the first sub-portion in the edge region of the fourth opening.

18. The display substrate according to claim 17, wherein, The size of the fourth opening in the second direction is greater than or equal to the size of the fourth opening in the first direction.

19. The display substrate according to any one of claims 1 to 18, wherein, The display substrate further includes a display area and a peripheral area that at least partially surrounds the display area, wherein the plurality of sub-pixels are located in the display area; The display substrate further includes multiple first connection lines, multiple second connection lines, and at least one common signal line. The multiple first connection lines are arranged along a first direction, and the multiple second connection lines are arranged along the first direction. In the nth sub-pixel, the third electrode plate is electrically connected to the i-th first connection line, the first electrode plate is electrically connected to the j-th second connection line, and the i-th first connection line and the j-th second connection line are electrically connected to the common signal line in the peripheral area; Both i and j are positive integers.

20. The display substrate according to any one of claims 1 to 18, wherein, In the reflection region, the orthographic projection of the active part on the substrate and the orthographic projection of the third electrode plate on the substrate form a complementary pattern.

21. A display panel, wherein, It includes a display substrate and an opposing substrate, the display substrate including the display substrate as described in any one of claims 1 to 20, and the opposing substrate including a plurality of color resists, wherein the m-th color resist is disposed corresponding to the n-th sub-pixel; The m-th color resist includes a first region, a second region, and a third region. The orthographic projection of the first region on the substrate covers the orthographic projection of the transmissive region of the n-th sub-pixel on the substrate. The orthographic projection of the third region on the substrate covers the orthographic projection of the active portion of the n-th sub-pixel on the substrate. In a first direction, the second region is located between the first region and the third region. In the second direction, the size of the second region is less than or equal to the size of the third region, and the second direction intersects the first direction; m is a positive integer.

22. The display panel according to claim 21, wherein, The plurality of color resists includes a first color resist, a second color resist, and a third color resist. The first color resist, the second color resist, and the third color resist are different colors. Furthermore, the orthographic projections of the first color resist, the second color resist, and the third color resist on the substrate are spaced apart from each other. In the second direction, the second region of the first color resist has a fourth dimension, the second region of the second color resist has a fifth dimension, and the second region of the third color resist has a sixth dimension, wherein the fifth dimension is larger than the fourth dimension and smaller than the sixth dimension.

23. The display panel according to claim 21, wherein, The display panel further includes a liquid crystal layer, which includes multiple dimming areas, wherein the z-th dimming area is configured to correspond to the n-th sub-pixel; The z-th dimming region includes a first dimming sub-region and a second dimming sub-region. The orthographic projection of the first dimming sub-region on the substrate covers the orthographic projection of the transmissive region of the n-th sub-pixel on the substrate. The orthographic projection of the second dimming sub-region on the substrate covers the orthographic projection of the reflective region of the n-th sub-pixel on the substrate. The cell thickness of the first dimming sub-region is greater than the cell thickness of the second dimming sub-region.

24. A display device, wherein, Includes the display panel as described in any one of claims 21 to 23.

Images