Display substrate, display panel and display device

Abstract

The invention provides a display substrate, which comprises a plurality of sub-pixels, a partition structure is arranged between two adjacent sub-pixels, the partition structure comprises a partition part and a first groove, and the orthographic projection of the partition part on a substrate is partially overlapped with the orthographic projection of the first groove on the substrate; the sub-pixel comprises an organic light-emitting device, and the organic light-emitting device comprises a light-emitting part and a charge generation part; for two adjacent sub-pixels and a partition structure between the two sub-pixels, the charge generation part of one sub-pixel comprises a first extension sub-part extending to the position between the two sub-pixels, and the charge generation part of the other sub-pixel comprises a second extension sub-part extending to the position between the two sub-pixels. One of the first extension sub-part and the second extension sub-part is located on the side, away from the substrate, of the partition part, the other one of the first extension sub-part and the second extension sub-part is located on the bottom wall of the first groove, and the first extension sub-part and the second extension sub-part are arranged in an insulated and spaced mode. The invention further provides a display panel and a display device.

Description

Display substrate, display panel, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate, a display panel, and a display device. Background Art

[0002] Currently, display screens mainly include liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays. A liquid crystal display typically includes a display substrate, an opposing substrate disposed opposite the display substrate, and a liquid crystal layer located between the display substrate and the opposing substrate. A liquid crystal display can generate an electric field through pixel electrodes in the display substrate to change the rotational orientation of liquid crystal molecules in the liquid crystal layer, and can be used in conjunction with polarizers to achieve display. An organic light-emitting diode display includes an anode, a cathode, and a light-emitting portion disposed between the anode and cathode. An organic light-emitting diode can generate current through the anode and cathode to drive the light-emitting portion for light-emitting display.

[0003] With the development of display technology, there is a higher demand for the brightness of sub-pixels. Higher brightness corresponds to a larger current, which may cause crosstalk between the currents of two adjacent sub-pixels.

[0004] Summary of the Invention

[0005] In view of the above problems, the present disclosure provides a display substrate, a display panel, and a display device.

[0006] According to a first aspect of the present disclosure, there is provided a display substrate, comprising:

[0007] substrate;

[0008] a first planar layer disposed on the base substrate;

[0009] A first passivation layer is provided on a side of the first planar layer facing away from the substrate;

[0010] an organic light-emitting layer and an organic common layer provided on a side of the first passivation layer facing away from the base substrate;

[0011] The display substrate further includes a plurality of sub-pixels, wherein a partition structure is provided between two adjacent sub-pixels, the partition structure including a partition portion and a first groove, the partition portion being located in the first passivation layer, the first groove being located in the first planar layer, and an orthographic projection of the partition portion on the base substrate partially overlapping with an orthographic projection of the first groove on the base substrate;

[0012] At least one of the sub-pixels includes an organic light-emitting device, the organic light-emitting device includes a light-emitting portion and a charge-generating portion, the light-emitting portion is located in the organic light-emitting layer, and the charge-generating portion is located in the organic common layer;

[0013] For two adjacent sub-pixels and a partition structure located between the two sub-pixels, the charge generating portion of one sub-pixel includes a first extending sub-portion extending between the two sub-pixels, and the charge generating portion of the other sub-pixel includes a second extending sub-portion extending between the two sub-pixels; and

[0014] One of the first extension sub-portion and the second extension sub-portion is located on a side of the partition portion away from the base substrate, and the other is located on the bottom wall of the first groove. The first extension sub-portion and the second extension sub-portion are insulated and spaced apart.

[0015] According to an embodiment of the present disclosure, the display substrate further includes a first electrode layer, a second electrode layer, and a pixel circuit layer. The first electrode layer is located on a side of the organic light-emitting layer close to the base substrate, the second electrode layer is located on a side of the organic light-emitting layer away from the base substrate, and the pixel circuit layer is located on a side of the first planar layer close to the base substrate.

[0016] At least one of the sub-pixels further includes a pixel circuit, and the organic light-emitting device further includes a first electrode and a second electrode, the first electrode is located in the first electrode layer, the second electrode is located in the second electrode layer, the first electrode is electrically connected to the pixel circuit, and the second electrode is electrically connected to the first voltage terminal;

[0017] For two adjacent sub-pixels and a partition structure located between the two sub-pixels, the second electrode of one of the sub-pixels includes a third extending sub-portion extending between the two sub-pixels, and the second electrode of the other sub-pixel includes a fourth extending sub-portion extending between the two sub-pixels; and

[0018] The third extension sub-portion is located on a side of the first extension sub-portion away from the base substrate, the fourth extension sub-portion is located on a side of the second extension sub-portion away from the base substrate, and the third extension sub-portion and the fourth extension sub-portion are insulated and spaced apart.

[0019] According to an embodiment of the present disclosure, at least one sub-pixel further includes a first connection portion, and in the same sub-pixel, the first electrode is electrically connected to the pixel circuit via the first connection portion;

[0020] An orthographic projection of the first groove on the base substrate does not overlap with an orthographic projection of the first connecting portion on the base substrate.

[0021] According to an embodiment of the present disclosure, the partition portion includes a first partition sub-portion and a second partition sub-portion;

[0022] The first partition sub-portion covers the surface of the first flat layer facing away from the base substrate, the orthographic projection of the first groove on the base substrate covers the orthographic projection of the second partition sub-portion on the base substrate, and the orthographic projection of the first partition sub-portion on the base substrate at least partially surrounds the orthographic projection of the second partition sub-portion on the base substrate.

[0023] According to an embodiment of the present disclosure, for two adjacent sub-pixels and a partition structure located between the two sub-pixels,

[0024] In a direction from one of the sub-pixels to another of the sub-pixels, a distance between the first groove and one of the sub-pixels is smaller than a distance between the first groove and another of the sub-pixels;

[0025] The first extension portion of the sub-pixel having a smaller distance from the first groove is located on the side of the partition portion away from the base substrate, and the second extension portion of the sub-pixel having a larger distance from the first groove is located on the bottom wall of the first groove.

[0026] According to an embodiment of the present disclosure, at least one of the sub-pixels further includes a first passivation portion, the first passivation portion is located in the first passivation layer, and in the same sub-pixel, an orthographic projection of the first passivation portion on the base substrate covers an orthographic projection of the first electrode on the base substrate;

[0027] For two adjacent sub-pixels and a partition structure located between the two sub-pixels, the first passivation portion and the partition portion of one of the sub-pixels form an integrated structure.

[0028] According to an embodiment of the present disclosure, the display substrate further includes a first pixel defining layer and a second pixel defining layer, the first pixel defining layer being located on a side of the first electrode layer facing away from the base substrate, the second pixel defining layer being located between the first pixel defining layer and the first passivation layer, the first pixel defining layer being made of a black pixel defining material, and the second pixel defining layer being made of a transparent pixel defining material;

[0029] At least one of the sub-pixels further includes a pixel defining portion and an auxiliary bonding portion, wherein the pixel defining portion is located in the first pixel defining layer, and the auxiliary bonding portion is located in the second pixel defining layer;

[0030] In the same sub-pixel, the pixel defining portion is configured to define the effective light-emitting area of ​​the organic light-emitting device, and the pixel defining portion is adhered to the first passivation portion through the auxiliary bonding portion, and the maximum thickness of the auxiliary bonding portion is less than or equal to the maximum thickness of the pixel defining portion.

[0031] According to an embodiment of the present disclosure, in the same sub-pixel, the orthographic projection of the pixel defining portion on the base substrate overlaps with the orthographic projection of the first passivation portion on the base substrate, and the overlapping portion defines a first pattern;

[0032] The first pattern includes a middle area and an edge area outside the middle area. The orthographic projection of the first electrode on the base substrate covers the middle area. The orthographic projection of the auxiliary laminating portion on the base substrate covers the edge area.

[0033] According to an embodiment of the present disclosure, in the same sub-pixel, the orthographic projection of the auxiliary bonding portion on the base substrate surrounds the orthographic projection of the first electrode on the base substrate.

[0034] According to an embodiment of the present disclosure, for two adjacent sub-pixels and a partition structure located between the two sub-pixels, the orthographic projection of the first electrode of at least one of the sub-pixels on the base substrate does not overlap with the orthographic projection of the partition portion on the base substrate.

[0035] According to an embodiment of the present disclosure, a plurality of partition structures are provided between two adjacent sub-pixels, wherein at least two of the partition structures have different areas.

[0036] According to an embodiment of the present disclosure, the display substrate further includes a second planar layer, wherein the second planar layer is located between the first passivation layer and the first electrode layer;

[0037] At least one of the sub-pixels further includes a first spacer, wherein the first spacer is located in the second planar layer;

[0038] In the same sub-pixel, the orthographic projection of the first electrode on the base substrate overlaps with the orthographic projection of the first passivation portion on the base substrate, and the overlapping portion defines a second pattern, and the orthographic projection of the first spacer on the base substrate covers the second pattern.

[0039] According to an embodiment of the present disclosure, in the same sub-pixel, the orthographic projection of the pixel defining portion on the base substrate overlaps with the orthographic projection of the first passivation portion on the base substrate, and the overlapping portion defines a first pattern, and the orthographic projection of the first spacer portion on the base substrate covers the first pattern.

[0040] According to an embodiment of the present disclosure, at least one of the sub-pixels further includes a first flat portion, and the first flat portion is located in the first flat layer;

[0041] In the same sub-pixel, the thickness of the first spacer is less than or equal to the thickness of the first passivation portion, and the thickness of the first passivation portion is less than the thickness of the first flat portion.

[0042] According to an embodiment of the present disclosure, the plurality of sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel, the first sub-pixel and the second sub-pixel have the same color, and the second sub-pixel and the third sub-pixel have the same color;

[0043] For the first sub-pixel and the second sub-pixel that are adjacent to each other and the partition structure located between the first sub-pixel and the second sub-pixel, in a direction from the first sub-pixel to the second sub-pixel, a distance between the first groove and the first sub-pixel is smaller than a distance between the first groove and the second sub-pixel;

[0044] For the first sub-pixel and the third sub-pixel that are adjacently arranged and the partition structure located between the first sub-pixel and the third sub-pixel, in the direction from the first sub-pixel to the third sub-pixel, the distance between the first groove and the first sub-pixel is smaller than the distance between the first groove and the third sub-pixel.

[0045] According to an embodiment of the present disclosure, the partition structure arranged adjacent to the first sub-pixel defines a third pattern as an orthographic projection on the base substrate, and the third pattern at least partially surrounds the pixel opening of the first sub-pixel as an orthographic projection on the base substrate.

[0046] According to an embodiment of the present disclosure, the plurality of sub-pixels further include a fourth sub-pixel, and the colors of the first sub-pixel, the second sub-pixel, and the fourth sub-pixel are different from each other;

[0047] For the adjacent third sub-pixel and the fourth sub-pixel and the partition structure located between the third sub-pixel and the fourth sub-pixel, in a direction from the third sub-pixel to the fourth sub-pixel, a distance between the first groove and the third sub-pixel is smaller than a distance between the first groove and the fourth sub-pixel;

[0048] For the adjacently arranged second sub-pixel and the fourth sub-pixel and the partition structure located between the second sub-pixel and the fourth sub-pixel, in the direction from the second sub-pixel to the fourth sub-pixel, the distance between the first groove and the second sub-pixel is smaller than the distance between the first groove and the fourth sub-pixel.

[0049] According to an embodiment of the present disclosure, the area of ​​the effective light-emitting area of ​​the first sub-pixel is larger than the area of ​​the effective light-emitting area of ​​the second sub-pixel, and smaller than the area of ​​the effective light-emitting area of ​​the fourth sub-pixel, and the area of ​​the effective light-emitting area of ​​the second sub-pixel is approximately the same as the area of ​​the effective light-emitting area of ​​the third sub-pixel.

[0050] According to an embodiment of the present disclosure, the display substrate further includes a plurality of gate lines and a plurality of data lines, the plurality of gate lines extending along a first direction, and the plurality of data lines extending along a second direction;

[0051] The first sub-pixels and the second sub-pixels are alternately arranged along a third direction, the first sub-pixels and the third sub-pixels are alternately arranged along a fourth direction, the third sub-pixels and the fourth sub-pixels are alternately arranged along the third direction, and the second sub-pixels and the fourth sub-pixels are alternately arranged along the fourth direction;

[0052] The first direction, the second direction, the third direction and the fourth direction intersect with each other.

[0053] According to an embodiment of the present disclosure, an orthographic projection of the partition structure disposed adjacent to the third sub-pixel in the third direction on the base substrate defines a fourth pattern, and the fourth pattern at least partially surrounds the orthographic projection of the pixel opening of the third sub-pixel on the base substrate; and / or,

[0054] The orthographic projection of the partition structure arranged adjacent to the second sub-pixel in the fourth direction on the base substrate defines a fifth pattern, and the fifth pattern at least partially surrounds the orthographic projection of the pixel opening of the second sub-pixel on the base substrate.

[0055] According to a second aspect of the present disclosure, a display panel is provided, wherein the display panel includes the display substrate described above.

[0056] According to a third aspect of the present disclosure, a display device is provided, wherein the display device includes the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The above contents and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0058] FIG1 schematically shows a plan view of a display substrate according to an embodiment of the present disclosure;

[0059] FIG2 schematically shows a plan view of a sub-pixel according to an embodiment of the present disclosure;

[0060] FIG3 schematically shows a plan view of a sub-pixel and a partition structure according to an embodiment of the present disclosure;

[0061] FIG4 schematically shows a cross-sectional view of a sub-pixel and a partition structure according to an embodiment of the present disclosure;

[0062] FIG5 schematically shows one of the cross-sectional views of two adjacent sub-pixels according to an embodiment of the present disclosure;

[0063] FIG6 schematically shows a cross-sectional view of a light emitting device according to an embodiment of the present disclosure;

[0064] FIG7 schematically shows a second cross-sectional view of two adjacent sub-pixels according to an embodiment of the present disclosure;

[0065] FIG8A schematically shows one of the plan views of the first passivation layer according to an embodiment of the present disclosure;

[0066] FIG8B schematically shows a plan view of a first electrode layer according to an embodiment of the present disclosure;

[0067] FIG8C schematically shows a plan view of a first pixel defining layer according to an embodiment of the present disclosure;

[0068] FIG8D schematically illustrates a plan view of a first groove according to an embodiment of the present disclosure;

[0069] FIG9 schematically shows one of the plan views of the first passivation layer, the first electrode layer, the first pixel defining layer, and the first groove according to an embodiment of the present disclosure;

[0070] 10A and 10B schematically illustrate a schematic diagram of a distance between a first groove and a sub-pixel according to an embodiment of the present disclosure;

[0071] FIG11 schematically shows a second plan view of the first passivation layer according to an embodiment of the present disclosure;

[0072] FIG12 schematically shows a second plan view of the first passivation layer, the first electrode layer, the first pixel defining layer, and the first groove according to an embodiment of the present disclosure;

[0073] FIG13 schematically shows a third cross-sectional view of two adjacent sub-pixels according to an embodiment of the present disclosure;

[0074] FIG14 schematically shows a plan view of a second pixel defining layer according to an embodiment of the present disclosure;

[0075] FIG15 schematically shows a plan view of a first passivation layer, a first electrode layer, a first pixel defining layer, a second pixel defining layer, and a first groove according to an embodiment of the present disclosure;

[0076] FIG16 schematically shows a fourth cross-sectional view of two adjacent sub-pixels according to an embodiment of the present disclosure;

[0077] FIG17 schematically shows a third plan view of the first passivation layer according to an embodiment of the present disclosure;

[0078] FIG18 schematically shows a third plan view of the first passivation layer, the first electrode layer, the first pixel defining layer, and the first groove according to an embodiment of the present disclosure;

[0079] FIG19 schematically shows a fifth cross-sectional view of two adjacent sub-pixels according to an embodiment of the present disclosure;

[0080] FIG20 schematically shows a plan view of a second planar layer according to an embodiment of the present disclosure;

[0081] FIG21 schematically shows a plan view of a first passivation layer, a first electrode layer, a first pixel defining layer, a second planarization layer, and a first groove according to an embodiment of the present disclosure;

[0082] FIG22 schematically shows a sixth cross-sectional view of two adjacent sub-pixels according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0083] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0084] It should be noted that in the drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0085] When an element is described as being "on" another element, "connected to" another element, or "bound to" another element, the element may be directly on the other element, directly connected to the other element, or directly bound to the other element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly bound to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between" versus "directly between", "adjacent" versus "directly adjacent", or "on" versus "directly on", etc. In addition, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0086] It should be noted that although the terms "first," "second," etc. may be used herein to describe various parts, components, elements, regions, layers, and / or portions, these parts, components, elements, regions, layers, and / or portions should not be limited by these terms. Rather, these terms are used to distinguish one part, component, element, region, layer, and / or portion from another. Thus, for example, the first part, first member, first element, first region, first layer, and / or first portion discussed below may be referred to as a second part, second member, second element, second region, second layer, and / or second portion without departing from the teachings of the present disclosure.

[0087] For ease of description, spatially relative terms, such as "upper," "lower," "left," "right," etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features.

[0088] As used herein, the terms "substantially," "about," "approximately," "roughly," and other similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. To account for factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximately" as used herein are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0089] It should be noted that, in this article, the term "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer used to form a specific pattern, and then patterning the film layer using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous. In other words, multiple elements, components, structures, and / or parts located in the "same layer" are composed of the same material and are formed through the same patterning process. Typically, multiple elements, components, structures, and / or parts located in the "same layer" have approximately the same thickness.

[0090] Those skilled in the art should understand that, in this article, unless otherwise specified, the expression "height" or "thickness" refers to the dimension of the surface of each film layer arranged perpendicular to the display substrate, that is, the dimension along the light emitting direction of the display substrate, or the dimension along the normal direction of the display device.

[0091] In one example, a display substrate is provided, comprising a base substrate and a plurality of sub-pixels disposed on the base substrate. The sub-pixels include organic light-emitting diodes (OLEDs), each comprising a light-emitting portion and a first electrode and a second electrode located on either side of the light-emitting portion. For example, the first electrode is located on a side of the light-emitting portion close to the base substrate, and the second electrode is located on a side of the light-emitting portion facing away from the base substrate. One of the first electrode and the second electrode is an anode, and the other is a cathode.

[0092] The organic light-emitting device also includes a charge generation unit. For example, the charge generation unit includes at least one of a hole transport layer, a hole injection layer, an electron transport layer, and an electron injection layer. The hole injection layer is located on the side of the light-emitting unit closest to the substrate, the hole transport layer is located between the light-emitting unit and the hole injection layer, the electron injection layer is located on the side of the light-emitting unit facing away from the substrate, and the electron transport layer is located between the light-emitting unit and the electron injection layer. In multiple adjacent sub-pixels, the layer containing the charge generation unit can be a single, interconnected layer (this layer may also be referred to as a common layer) formed in a single process, thereby reducing process costs.

[0093] With the development of display technology, the demand for sub-pixel brightness has become higher. Higher brightness corresponds to greater current. As a result, the current between two adjacent sub-pixels may be conducted through the charge generation unit between them, resulting in crosstalk. For example, when lighting a green sub-pixel, due to the lower lighting voltage of the red sub-pixel, the adjacent red sub-pixel will be abnormally illuminated. This will cause a more obvious color cast on the screen, for example, the green screen will appear reddish.

[0094] In view of this, an embodiment of the present disclosure provides a display substrate, which includes: a base substrate, a first flat layer arranged on the base substrate, a first passivation layer arranged on the side of the first flat layer away from the base substrate, an organic light-emitting layer and an organic common layer arranged on the side of the first passivation layer away from the base substrate.

[0095] The display substrate also includes a plurality of sub-pixels. A partition structure is disposed between two adjacent sub-pixels along a predetermined direction. The partition structure includes a partition portion and a first groove. The partition portion is located in the first passivation layer, and the first groove is located in the first planar layer. The orthographic projection of the partition portion on the substrate partially overlaps the orthographic projection of the first groove on the substrate. At least one sub-pixel includes an organic light-emitting device, which includes a light-emitting portion and a charge-generating portion. The light-emitting portion is located in the organic light-emitting layer, and the charge-generating portion is located in the organic common layer. For two adjacent sub-pixels and the partition structure disposed between the two sub-pixels, the charge-generating portion of one sub-pixel includes a first extension sub-portion extending between the two sub-pixels, and the charge-generating portion of the other sub-pixel includes a second extension sub-portion extending between the two sub-pixels. Furthermore, one of the first extension sub-portion and the second extension sub-portion is located on a side of the partition portion facing away from the substrate, and the other is located on the bottom wall of the first groove. The first extension sub-portion and the second extension sub-portion are insulated and spaced apart.

[0096] The partition structure can insulate and separate the charge generation sections of two adjacent sub-pixels without changing the charge generation section manufacturing process, preventing current from flowing through the charge generation sections between the two sub-pixels and thereby alleviating issues such as crosstalk and color shift. Furthermore, in the disclosed embodiments, the partition section partially covers the first groove to form an undercut structure. The first planar layer is relatively thick, and trenching therein to form the undercut structure does not affect the existing structure. Furthermore, its thickness helps maintain a sufficient height difference between the first extension sub-section and the second extension sub-section, ensuring that they can be misaligned, thereby preventing adhesion due to process fluctuations.

[0097] FIG1 schematically shows a plan view of a display substrate according to an embodiment of the present disclosure, and FIG2 schematically shows a plan view of a sub-pixel according to an embodiment of the present disclosure.

[0098] 1 and 2 , the display substrate in the embodiment of the present disclosure includes a display area AA and a peripheral area NA located on at least one side of the display area AA.

[0099] The display area AA can have various shapes. For example, the display area AA can be provided in various shapes, such as a polygon (e.g., a rectangle) with straight edges, a circle or an ellipse with curved edges, or a semicircle or a semiellipse with both straight and curved edges. In the embodiment of the present disclosure, the display area AA is provided as a region having a quadrilateral shape with straight edges. It should be understood that this is merely an exemplary embodiment of the present disclosure and is not intended to limit the present disclosure.

[0100] The display substrate may further include a base substrate 200 and a plurality of repeating units P disposed on the base substrate 200 and located in the display area AA. Each repeating unit P may include a plurality of sub-pixels PX. In the same repeating unit P, at least two sub-pixels PX have different colors.

[0101] For example, the repeating unit P may include a first subpixel PX1, a second subpixel PX2, a third subpixel PX3, and a fourth subpixel PX4. For example, the first subpixel PX1 may be set as a red subpixel, the second subpixel PX2 and the third subpixel PX3 may be set as green subpixels, and the fourth subpixel PX4 may be set as a blue subpixel. However, the embodiments of the present disclosure are not limited thereto. For example, the first subpixel PX1, the second subpixel PX2, the third subpixel PX3, and the fourth subpixel PX4 may also be set as a red subpixel, a green subpixel, a blue subpixel, and a white subpixel, respectively.

[0102] The display substrate further includes a plurality of gate lines GL and a plurality of data lines DL disposed on the base substrate 200 and located at least in the display area AA. The plurality of gate lines GL extend along a first direction X, and the plurality of data lines DL extend along a second direction Y, where the first direction X and the second direction Y intersect. For example, the first direction X may include the horizontal direction in FIG. 1 , and the second direction Y may include the vertical direction in FIG. 1 , that is, the first direction X and the second direction Y are perpendicular to each other.

[0103] For example, one subpixel PX is connected to one data line DL and one gate line GL. For example, multiple subpixels PX on a display substrate can be divided into multiple subpixel groups, where a subpixel group includes multiple subpixels PX arranged along a first direction X, and multiple subpixel groups are arranged along a second direction Y.

[0104] A gate line GL connects to a subpixel group, thereby simultaneously providing a turn-on voltage to the subpixel group. Multiple subpixels PX in a subpixel group are connected to different data lines DL. When a turn-on voltage is provided to the subpixel group, the required data voltages can be provided to each of the subpixels PX according to display requirements.

[0105] The peripheral area NA may be disposed on at least one side of the display area AA. For example, the peripheral area NA may surround the periphery of the display area AA. In an embodiment of the present disclosure, the peripheral area NA may include a horizontal portion extending in a first direction X and a vertical portion extending in a second direction Y.

[0106] The display substrate may further include a gate drive circuit 21 and a drive chip 22 arranged on the base substrate 200 and located in the peripheral area NA. For example, the gate drive circuit 21 may be located on at least one side of the display area AA. In the embodiment shown in Figure 1, the gate drive circuit 21 is respectively located on the left and right sides of the display area AA. It should be noted that the left and right sides may be the left and right sides of the display substrate (screen) viewed by the human eye during display. For example, the drive chip 22 may be located on at least one side of the display area AA. In the embodiment shown in Figure 1, the drive chip 22 is located on the lower side of the display area AA. It should be noted that the lower side may be the lower side of the display substrate (screen) viewed by the human eye during display.

[0107] The driver chip 22 includes a data driver circuit that sequentially latches input data according to a clock signal, converts the latched data into analog signals, and then inputs them to the data lines DL of the display substrate. The gate driver circuit 21 is typically implemented by a shift register, which converts the clock signal into on / off voltages and outputs them to the gate lines GL of the display substrate.

[0108] It should be noted that although Figure 1 shows that the gate drive circuit 21 is located on the left and right sides of the display area AA and the drive chip 22 is located on the lower side of the display area AA, the embodiments of the present disclosure are not limited to this. The gate drive circuit 21 and the drive chip 22 can be located at any suitable position in the peripheral area NA.

[0109] For example, the gate driver circuit 21 can adopt GOA technology, i.e., Gate Driver on Array. In GOA technology, the gate driver circuit 21 is directly set on the array substrate to replace the external chip. Each GOA unit serves as a first-level shift register, and each level of shift register is connected to a gate line GL. The scanning signal is output in sequence through the shift registers at each level to achieve row-by-row scanning of the pixel unit. In some embodiments, each level of shift register can also be connected to multiple gate lines GL. In this way, it can adapt to the development trend of high resolution and narrow frame of display substrates. The driver chip 22 can be folded to the back side of the display substrate through structures such as flip chip film, which is conducive to narrowing the lower frame.

[0110] FIG3 schematically shows a plan view of a sub-pixel and a partition structure according to an embodiment of the present disclosure, and FIG4 schematically shows a cross-sectional view of a sub-pixel and a partition structure according to an embodiment of the present disclosure.

[0111] 3 and 4 , the display substrate of the embodiment of the present disclosure includes a first planar layer 210 disposed on a base substrate 200. The display substrate also includes a pixel circuit layer disposed on the base substrate 200. The first planar layer 210 is disposed on a side of the pixel circuit layer facing away from the base substrate 200. The first planar layer 210 may be a single, interconnected layer. The first planar layer 210 is used to reduce step differences, thereby providing a relatively flat base for subsequent components (e.g., light-emitting devices).

[0112] A partition structure GD is provided between two adjacent sub-pixels PX. Specifically, the two adjacent sub-pixels PX may refer to two sub-pixels PX that are adjacent to each other in a preset direction, with no other sub-pixels PX between the two sub-pixels PX. Optionally, the preset direction may be determined according to actual needs and is not limited here. In the embodiment of the present disclosure, it is sufficient as long as a partition structure GD is provided between two adjacent sub-pixels PX in a certain direction. For example, the preset direction may include one of the first direction X and the second direction Y, or the preset direction may include both the first direction X and the second direction Y. For another example, the preset direction may include a direction that intersects both the first direction X and the second direction Y. The partition structure GD may isolate the charge generating portion 241 between two adjacent sub-pixels PX, thereby preventing the current between the two sub-pixels PX from being conducted through the charge generating portion 241.

[0113] Optionally, the preset direction can be adaptively set according to the current pixel structure. For example, referring to FIG3 , the display substrate in the embodiment of the present disclosure adopts an RGGB pixel structure, the first sub-pixel PX1 can be set as a red sub-pixel PX, the second sub-pixel PX2 and the third sub-pixel PX3 can be set as a green sub-pixel PX, and the fourth sub-pixel PX4 can be set as a blue sub-pixel PX. In this pixel structure, the first sub-pixel PX1 and the second sub-pixel PX2 are alternately arranged along the third direction Z1, the first sub-pixel PX1 and the third sub-pixel PX3 are alternately arranged along the fourth direction Z2, the second sub-pixel PX2 and the fourth sub-pixel PX4 are alternately arranged along the fourth direction Z2, and the third sub-pixel PX3 and the fourth sub-pixel PX4 are alternately arranged along the third direction Z1. In which, the first direction X, the second direction Y, the third direction Z1 and the fourth direction Z2 intersect with each other, and the preset direction may include the third direction Z1 and the fourth direction Z2. The spacing between two adjacent sub-pixels PX in the third direction Z1 (fourth direction Z2) is closer than the spacing between two adjacent sub-pixels PX in the first direction X (second direction Y), resulting in a greater risk of current crosstalk. Therefore, referring to FIG3 , providing a partition structure GD between two adjacent sub-pixels PX in the third direction Z1 (fourth direction Z2) can effectively improve the current crosstalk problem between adjacent sub-pixels PX. Furthermore, providing a partition structure GD between two adjacent sub-pixels PX in the third direction Z1 (fourth direction Z2) can help reduce interference with existing structures. For example, referring to FIG9 , in the same sub-pixel PX, the first electrode 251 needs to be electrically connected to the pixel circuit via a first connecting portion 252, and the first connecting portion 252 extends along the first direction X or the second direction Y. Providing a partition structure GD between two adjacent sub-pixels PX in the third direction Z1 (fourth direction Z2) can prevent the partition structure GD from isolating the first connecting portion 252.

[0114] 3 and 4 , the display substrate further includes a first passivation layer 220 disposed on a side of the first planar layer 210 facing away from the base substrate 200. The partition structure GD includes a partition portion 221 and a first groove 211. The partition portion 221 is located in the first passivation layer 220, and the first groove 211 is located in the first planar layer 210. The orthographic projection of the partition portion 221 on the base substrate 200 partially overlaps with the orthographic projection of the first groove 211 on the base substrate 200.

[0115] For clarity, unless otherwise specified, the following description will be made by taking the adjacently arranged first sub-pixel PX1 and the second sub-pixel PX2 as an example.

[0116] FIG5 schematically shows one of the cross-sectional views of two adjacent sub-pixels according to an embodiment of the present disclosure.

[0117] 5 , the sub-pixel PX on the left is the first sub-pixel PX1, and the sub-pixel PX on the right is the second sub-pixel PX2. A partition 211 is provided between the first sub-pixel PX1 and the second sub-pixel PX2. The partition 221 covers the left half of the first groove 211 and exposes the right half of the first groove 211. The left sidewall of the first groove 211 is retracted to the left relative to the partition 211. Thus, the partition 221 and the left half of the first groove 211 form an undercut structure.

[0118] In an embodiment of the present disclosure, the first groove 211 can be formed after the partition portion 211. For example, a first flat material layer is first prepared on the base substrate 200. The material of the first flat material layer includes a photoresist material. The first flat material layer can be denatured after being exposed to light, and the denatured portion can be removed after development. Afterwards, the partition portion 211 is formed on the area of ​​the first flat material layer where the first groove 211 is to be formed. The partition portion 211 may include a transparent material, that is, the partition portion 211 allows light to pass through. Then, the area of ​​the first flat material layer where the first groove 211 is to be formed is exposed through a mask pattern to denature the part. Finally, by wet etching or selective dry etching, the area where the first groove 211 is to be formed is etched while retaining the partition portion 211, so that the first groove 211 partially covered by the partition portion 211 can be obtained.

[0119] FIG6 schematically shows a cross-sectional view of a light emitting device according to an embodiment of the present disclosure.

[0120] 5 and 6 , the display substrate further includes an organic light emitting layer 230 and an organic common layer 240 disposed on a side of the first passivation layer 220 facing away from the base substrate 200 .

[0121] At least one sub-pixel PX includes an organic light emitting device OL, which includes a light emitting portion 231 and a charge generating portion 241 . The light emitting portion 231 is located in the organic light emitting layer 230 , and the charge generating portion 241 is located in the organic common layer 240 .

[0122] The charge generation portion 241 may include at least one of a hole transport layer, a hole injection layer, an electron transport layer, and an electron injection layer. The hole injection layer is located on the side of the light-emitting portion 231 that is closer to the base substrate 200, the hole transport layer is located between the light-emitting portion 231 and the hole injection layer, the electron injection layer is located on the side of the light-emitting portion that is away from the base substrate 200, and the electron transport layer is located between the light-emitting portion 231 and the electron injection layer.

[0123] For two adjacent sub-pixels PX and the partition structure GD located between the two sub-pixels PX, the charge generating portion 241 of one sub-pixel PX includes a first extending sub-portion 2411 extending between the two sub-pixels PX, and the charge generating portion 241 of the other sub-pixel PX includes a second extending sub-portion 2412 extending between the two sub-pixels PX.

[0124] Exemplarily, the charge generating portion 241 can be formed by an evaporation process, and the charge generating portion 241 is not only located in the effective light-emitting area of ​​the sub-pixel PX, but also extends toward the sub-pixel PX adjacent thereto, where the effective light-emitting area can refer to the area defined by the pixel opening V1 of the sub-pixel PX.

[0125] 6 , in the first subpixel PX1, a portion of the charge generating portion 241 extends toward the second subpixel PX2 on the right side, and this portion is the first extending sub-portion 2411 of the first subpixel PX1. Correspondingly, in the second subpixel PX2, a portion of the charge generating portion 241 extends toward the first subpixel PX1 on the left side, and this portion is the second extending sub-portion 2412 of the second subpixel PX2.

[0126] It should be noted that each sub-pixel PX may have a first extending sub-portion 2411 and a second extending sub-portion 2412. For example, referring to FIG6 , in the first sub-pixel PX1, the portion of the charge generating portion 241 extending toward the right is the first extending sub-portion 2411, and the portion of the charge generating portion 241 extending toward the left is the second extending sub-portion 2412. Correspondingly, in the second sub-pixel PX2, the portion of the charge generating portion 241 extending toward the left is the second extending sub-portion 2412, and the portion of the charge generating portion 241 extending toward the right is the first extending sub-portion 2411.

[0127] One of the first extension portion 2411 and the second extension portion 2412 is located on a side of the partition portion 221 facing away from the base substrate 200, and the other is located on the bottom wall of the first groove 211. The first extension portion 2411 and the second extension portion 2412 are insulated and spaced apart from each other. For example, referring to FIG6 , the first extension portion 2411 in the first sub-pixel PX1 is located above the partition portion 221, and the second extension portion 2412 in the second sub-pixel PX2 is located on the bottom wall of the first groove 211. Thus, in the vertical direction, there is a height difference between the first extension portion 2411 and the second extension portion 2412, thereby isolating and spaced apart from each other.

[0128] In other words, the partition structure GD can separate the charge generation sections 241 between two adjacent sub-pixels PX without changing the charge generation section 241 fabrication process, thereby preventing current from flowing between the two adjacent sub-pixels PX through the charge generation section 241 between them, thereby alleviating issues such as crosstalk and color shift. Furthermore, in the disclosed embodiment, the partition section 221 partially covers the first groove 211 to form an undercut structure. The first planar layer 210 is relatively thick, and the undercut structure formed by trenching therein does not affect the existing structure. Furthermore, its thickness helps maintain a sufficient height difference between the first extension section 2411 and the second extension section 2412, ensuring that they can be misaligned, thereby preventing adhesion due to process fluctuations.

[0129] The embodiments of the present disclosure are further described below with reference to FIG. 1 to FIG. 22 .

[0130] FIG7 schematically shows a second cross-sectional view of two adjacent sub-pixels according to an embodiment of the present disclosure.

[0131] 6 and 7 , in some specific embodiments, the display substrate further includes a first electrode layer 250, a second electrode layer 260 and a pixel circuit layer 270, the first electrode layer 250 is located on the side of the organic light-emitting layer 230 close to the base substrate 200, the second electrode layer 260 is located on the side of the organic light-emitting layer 230 away from the base substrate 200, and the pixel circuit layer 270 is located on the side of the first flat layer 210 close to the base substrate 200.

[0132] At least one sub-pixel PX further includes a pixel circuit, and the organic light-emitting device OL further includes a first electrode 251 and a second electrode 261. The first electrode 251 is located in the first electrode layer 250, and the second electrode 261 is located in the second electrode layer 260. One of the first electrode 251 and the second electrode 261 is an anode, and the other is a cathode. For example, the first electrode 251 is an anode, and the second electrode 261 is a cathode. The first electrode 251 is electrically connected to the pixel circuit, and the second electrode 261 is electrically connected to a first voltage terminal capable of providing a constant low-level voltage.

[0133] One of the first electrode 251 and the second electrode 261 is a reflective electrode, and the other is a semi-transparent electrode. Regardless of whether the first electrode 251 is a transparent electrode or a semi-transparent electrode, or the second electrode 261 is a transparent electrode or a semi-transparent electrode, light is emitted from the transparent electrode or the semi-transparent electrode.

[0134] For two adjacent sub-pixels PX and the partition structure GD located between the two sub-pixels PX, the second electrode 261 of one sub-pixel PX includes a third extension sub-portion 2611 extending between the two sub-pixels PX, and the second electrode 261 of the other sub-pixel PX includes a fourth extension sub-portion 2612 extending between the two sub-pixels PX. The third extension sub-portion 2611 is located on the side of the first extension sub-portion 2411 facing away from the base substrate 200, and the fourth extension sub-portion 2612 is located on the side of the second extension sub-portion 2412 facing away from the base substrate 200. The third extension sub-portion 2611 and the fourth extension sub-portion 2612 are insulated and spaced apart.

[0135] For example, referring to Figure 7, the second electrode 261 of the first subpixel PX1 includes a third extending sub-portion 2611 extending toward the right side to between the first subpixel PX1 and the second subpixel PX2, and the second electrode 261 of the second subpixel PX2 includes a fourth extending sub-portion 2612 extending toward the left side to between the second subpixel PX2 and the first subpixel PX1.

[0136] The second electrode 261 can be formed by an evaporation process. The second electrode 261 is not only located in the effective light-emitting area of ​​the subpixel PX, but also extends toward the adjacent subpixel PX. Referring to Figure 7 , in the first subpixel PX1, a portion of the second electrode 261 extends toward the second subpixel PX2 on the right. This portion is the third extension sub-portion 2611 of the first subpixel PX1. Correspondingly, in the second subpixel PX2, a portion of the second electrode 261 extends toward the first subpixel PX1 on the left. This portion is the fourth extension sub-portion 2612 of the second subpixel PX2.

[0137] It should be noted that, in the embodiments of the present disclosure, each sub-pixel PX may have a third extending sub-portion 2611 and a fourth extending sub-portion 2612. For example, referring to FIG7 , in the first sub-pixel PX1, the portion of the second electrode 261 extending toward the right is the third extending sub-portion 2611, and the portion of the second electrode 261 extending toward the left is the fourth extending sub-portion 2612. Correspondingly, in the second sub-pixel PX2, the portion of the second electrode 261 extending toward the left is the fourth extending sub-portion 2612, and the portion of the second electrode 261 extending toward the right is the third extending sub-portion 2611.

[0138] 7 , the third extension sub-portion 2611 in the first sub-pixel PX1 is further away from the base substrate 200 than the first extension sub-portion 2411 thereof, and the fourth extension sub-portion 2612 in the second sub-pixel PX2 is further away from the base substrate 200 than the second extension sub-portion 2412 thereof. In the vertical direction, there is also a height difference between the third extension sub-portion 2611 and the fourth extension sub-portion 2612, thereby isolating the two from each other.

[0139] In the above manner, the second electrodes 261 of two adjacent sub-pixels PX can be separated by the partition structure GD without changing the preparation process of the second electrode 261, thereby further cutting off the current path between the two adjacent sub-pixels PX, which is conducive to better improving problems such as crosstalk and color deviation.

[0140] Figures 8A to 9 schematically show one of the plan views of the sub-pixels in a repeating unit according to an embodiment of the present disclosure, wherein Figure 8A schematically shows one of the plan views of the first passivation layer according to an embodiment of the present disclosure, Figure 8B schematically shows a plan view of the first electrode layer according to an embodiment of the present disclosure, Figure 8C schematically shows a plan view of the first pixel defining layer according to an embodiment of the present disclosure, Figure 8D schematically shows a plan view of the first groove according to an embodiment of the present disclosure, and Figure 9 schematically shows one of the plan views of the first passivation layer, the first electrode layer, the first pixel defining layer and the first groove according to an embodiment of the present disclosure.

[0141] With reference to Figures 7 to 9, in some specific embodiments, at least one subpixel PX further includes a first connection portion 252. In the same subpixel PX, the first electrode 251 is electrically connected to the pixel circuit via the first connection portion 252. Optionally, the first connection portion 252 may extend along the first direction X or the second direction Y. For example, at least a portion of the first connection portion 252 of the first subpixel PX1 and the fourth subpixel PX4 may extend along the first direction X, while the first connection portion 252 of the second subpixel PX2 and the third subpixel PX3 may extend along the second direction Y. The orthographic projection of the first groove 211 on the base substrate 200 does not overlap with the orthographic projection of the first connection portion 252 on the base substrate 200. In this way, the first groove 211 can avoid the connection path between the first electrode 251 and the pixel circuit.

[0142] In some specific embodiments, the partition portion 221 includes a first partition sub-portion 2211 and a second partition sub-portion 2212. The first partition sub-portion 2211 covers the surface of the first planar layer 210 facing away from the base substrate 200, the orthographic projection of the first groove 211 on the base substrate 200 covers the orthographic projection of the second partition sub-portion 2212 on the base substrate 200, and the orthographic projection of the first partition sub-portion 2211 on the base substrate 200 at least partially surrounds the orthographic projection of the second partition sub-portion 2212 on the base substrate 200.

[0143] Optionally, the partition portion 2211 may be disposed adjacent to at least one sub-pixel PX. For example, the orthographic projection of the partition portion 2211 on the base substrate 200 is close to or even overlaps with the orthographic projection of the first electrode 251 of at least one sub-pixel PX on the base substrate 200 .

[0144] The sub-pixel PX includes a pixel opening V1, the orthographic projection of the pixel opening V1 on the base substrate 200 is roughly circular, and the orthographic projection of the partition portion 221 on the base substrate 200 may include an arc-shaped pattern, which at least partially surrounds the periphery of the orthographic projection of the pixel opening V1 on the base substrate 200.

[0145] For example, the orthographic projection of the first electrode 251 on the base substrate 200 and the orthographic projection of the pixel opening V1 on the base substrate 200 are concentric circles, wherein the diameter of the orthographic projection of the first electrode 251 on the base substrate 200 is larger than the diameter of the orthographic projection of the pixel opening V1 on the base substrate 200. The arc-shaped pattern matches the edge morphology of the orthographic projection of the first electrode 251 on the base substrate 200.

[0146] It should be noted that the embodiments of the present disclosure are not limited to the above-mentioned shapes. For example, the orthographic projection of the pixel opening V1 on the base substrate 200 may also include a positive direction, a rectangle, a hexagon, or an irregular shape. Accordingly, the shape of the partition portion 221 may be appropriately modified so that its orthographic projection on the base substrate 200 can at least partially surround the periphery of the above-mentioned shape.

[0147] Optionally, when the orthographic projection of the partition portion 221 on the base substrate 200 is in the shape of an arc, the two ends of the first partition sub-portion 2211 in the circumferential direction extend to the two sides of the second partition sub-portion 2212 in the circumferential direction, so that the first partition sub-portion 2211 at least partially surrounds the second partition sub-portion 2212. This helps to increase the area of ​​the first partition sub-portion 2211, for example, making the area of ​​the first partition sub-portion 2211 greater than or equal to the area of ​​the second partition sub-portion 2212. In other words, the area of ​​the portion of the partition portion 221 that is in contact with the first planar layer 210 is greater than the area of ​​the suspended portion of the partition portion 221. This helps to ensure a more stable contact between the partition portion 221 and the first planar layer 210 during the subsequent etching process, preventing the partition portion 221 from warping or even peeling off from the first planar layer 210.

[0148] In some specific embodiments, the first groove 211 includes a first sub-groove and a second sub-groove, and the orthographic projection of the first sub-groove on the base substrate 200 overlaps with the second partitioning sub-portion 2212. For two adjacent sub-pixels PX and the partitioning structure GD located between the two sub-pixels PX, in a direction from one sub-pixel PX to the other sub-pixel PX, the second partitioning sub-portion 2212 has a first size, and the second sub-groove has a second size, and the first size is less than or equal to the second size.

[0149] In some specific embodiments, in the direction from the first sub-pixel PX1 to the second sub-pixel PX2, the second partition sub-portion 2212 has a first size, the second sub-groove has a second size, and the first size is less than or equal to the second size. This is beneficial for making the area covered by the first groove 211 times the partition portion 221 less than or equal to the exposed area of ​​the first groove 211, thereby facilitating the formation of an empty groove below the second partition sub-portion 2212 during the etching process, and preventing the empty groove from being indented too deeply in the horizontal direction.

[0150] In an embodiment of the present disclosure, the direction from one sub-pixel PX to another sub-pixel PX may refer to: taking the center of the pixel opening V1 of one sub-pixel PX as the starting point and the center of the pixel opening V1 of the other sub-pixel PX as the end point, and the direction of the line connecting the starting point and the end point.

[0151] In some specific embodiments, for two adjacent sub-pixels PX and the partition structure GD located between the two sub-pixels PX, the dimension of the second sub-groove in the direction from one sub-pixel PX to the other sub-pixel PX is greater than or equal to the depth of the second sub-groove. The dimension of the first sub-groove in the direction from one sub-pixel PX to the other sub-pixel PX is less than or equal to the depth of the second sub-groove. The first sub-groove and the second sub-groove have the same depth.

[0152] Figures 10A and 10B schematically illustrate schematic diagrams of the spacing between the first groove and sub-pixels according to an embodiment of the present disclosure, wherein Figure 10A schematically illustrates the spacing between the first sub-pixel and the second sub-pixel (third sub-pixel) and the first groove located therebetween, and Figure 10B schematically illustrates the spacing between the fourth sub-pixel and the second sub-pixel (third sub-pixel) and the first groove located therebetween.

[0153] 10A and 10B , in some specific embodiments, for two adjacent sub-pixels PX and the partition structure GD located between the two sub-pixels PX, in a direction from one sub-pixel PX to the other sub-pixel PX, a distance d1 (d3) between the first groove 211 and one of the sub-pixels PX is smaller than a distance d2 (d4) between the first groove 211 and the other sub-pixel PX. Specifically, the first extension portion 2411 of the sub-pixel PX having a smaller distance from the first groove 211 is located on a side of the partition portion 221 facing away from the base substrate 200, and the second extension portion 2412 of the sub-pixel PX having a larger distance from the first groove 211 is located on the bottom wall of the first groove 211.

[0154] In this document, unless otherwise specified, "the distance between the first groove 211 and one of the sub-pixels PX" and similar expressions refer to: the distance between the edge of the first groove 211 closest to the pixel opening V1 of the sub-pixel PX and the edge of the pixel opening V1 closest to the first groove 211.

[0155] For example, with reference to Figures 10A and 10B, in the direction from the first sub-pixel PX1 to the second sub-pixel PX2 (third sub-pixel PX3), the distance d1 between the first sub-pixel PX1 and the first groove 211 is smaller than the distance d2 between the second sub-pixel PX2 (third sub-pixel PX3) and the first groove 211, that is, the first groove 211 is closer to the first sub-pixel PX1, the first extension sub-portion 2411 in the first sub-pixel PX1 is located above the partition portion 221, and the second extension sub-portion 2412 in the second sub-pixel PX2 is located on the bottom wall of the first groove 211.

[0156] In the direction from the second subpixel PX2 (third subpixel PX3) to the fourth subpixel PX4, the distance d3 between the second subpixel PX2 (third subpixel PX3) and the first groove 211 is smaller than the distance d4 between the fourth subpixel PX4 and the first groove 211. In other words, the first groove 211 is closer to the second subpixel PX2 (third subpixel PX3). The first extension sub-portion 2411 in the second subpixel PX2 (third subpixel PX3) is located above the partition portion 221, and the second extension sub-portion 2412 in the fourth subpixel PX4 is located on the bottom wall of the first groove 211. In this way, the multiple first grooves 211 can be staggered, which helps to free up more space for the first grooves 211 while having little or no impact on the existing structure.

[0157] It should be noted that the above is explained using the first sub-pixel PX1 and the second sub-pixel PX2 and the partition structure GD therebetween as an example, but this does not constitute a limitation to the embodiments of the present disclosure. A partition structure GD can be provided between the first sub-pixel PX1 and the second sub-pixel PX2, between the second sub-pixel PX2 and the fourth sub-pixel PX4, and between the third sub-pixel PX3 and the fourth sub-pixel PX4. Each partition structure GD and the longitudinal cross-sectional structure of the two adjacent sub-pixels PX can be provided with reference to the above example. Therefore, the embodiments of the present disclosure are no longer listed one by one.

[0158] 7 to 9 , in some specific embodiments, for two adjacent sub-pixels PX and the partition structure GD located between the two sub-pixels PX, the orthographic projection of the first electrode 251 of at least one sub-pixel PX on the base substrate 200 does not overlap with the orthographic projection of the partition portion 221 on the base substrate 200.

[0159] In an embodiment of the present disclosure, when forming the first passivation layer 220 , only the portion necessary for forming the partition structure GD is retained, and other portions are removed, thereby obtaining a partition portion 221 located outside the first electrode 251 to minimize the space occupied by the partition portion 221 .

[0160] For example, referring to FIG9 , for a first subpixel PX1 and its four adjacent partitions 221 (two of which may be connected together to form an integral structure), each partition 221 partially surrounds the periphery of the first electrode 251 of the first subpixel PX1. Optionally, the first electrode 251 of the first subpixel PX1 is substantially circular, and accordingly, the partitions 221 surrounding the periphery of the first electrode 251 of the first subpixel PX1 are substantially arc-shaped. A second subpixel PX2 (or third subpixel PX3) is adjacent to two partitions 221 on opposite sides thereof, and each partition 221 partially surrounds the periphery of the first electrode 251 of the second subpixel PX2 (or third subpixel PX3). Optionally, the first electrode 251 of the second subpixel PX2 (or third subpixel PX3) is substantially circular, and accordingly, the partitions 221 surrounding the periphery of the first electrode 251 of the second subpixel PX2 (or third subpixel PX3) are substantially arc-shaped.

[0161] Figures 11 and 12 schematically show two plan views of sub-pixels in a repeating unit according to an embodiment of the present disclosure, wherein Figure 11 schematically shows two plan views of the first passivation layer according to an embodiment of the present disclosure, Figure 12 schematically shows two plan views of the first passivation layer, the first electrode layer, the first pixel defining layer and the first groove according to an embodiment of the present disclosure, and Figure 13 schematically shows three cross-sectional views of two adjacent sub-pixels according to an embodiment of the present disclosure.

[0162] With reference to Figures 11 to 13, in some specific embodiments, at least one sub-pixel PX further includes a first passivation portion 222. The first passivation portion 222 is located in the first passivation layer 220. In the same sub-pixel PX, the orthographic projection of the first passivation portion 222 on the base substrate 200 covers the orthographic projection of the first electrode 251 on the base substrate 200. For two adjacent sub-pixels PX and the partition structure GD located between the two sub-pixels PX, the first passivation portion 222 and the partition portion 221 of one of the sub-pixels PX form an integrated structure.

[0163] In the embodiment of the present disclosure, each partition 221 is positioned adjacent to at least one sub-pixel PX. For example, the orthographic projection of the partition 221 on the substrate 200 abuts or even overlaps the orthographic projection of the first electrode 251 of at least one sub-pixel PX on the substrate 200. The first passivation layer 222 is provided on the same layer and made of the same material as the partition 221, and both can be formed in a single process. When forming the partition 221, the partition 221 is close to the adjacent sub-pixel PX. Therefore, a portion may remain beneath the first electrode 251, affecting the flatness of the first electrode 251. Therefore, in the embodiment of the present disclosure, when forming the first passivation layer 220, in addition to retaining the partition 221, a portion beneath the first electrode 251 is also retained, thereby simultaneously forming the first passivation layer 222. By placing the first passivation layer 222 beneath the first electrode 251, the flatness of the first electrode 251 is ensured.

[0164] Optionally, with reference to Figures 8B and 12, the orthographic projection of the first passivation portion 222 on the base substrate 200 may cover not only the orthographic projection of the first electrode 251 on the base substrate 200, but also the orthographic projection of the first connecting portion 252 on the base substrate 200, thereby ensuring the overall flatness of the entire first electrode 251 and the first connecting portion 252.

[0165] Optionally, the first passivation portions 222 of at least two sub-pixels PX are formed into an integrated structure through the second connecting portion 223. For example, referring to Figures 2 and 11, in a repeating unit P, the first passivation portions 222 of multiple sub-pixels PX are connected to each other through the second connecting portion 223, thereby forming an integrated structure.

[0166] Figures 14 and 15 schematically show a third plan view of a sub-pixel in a repeating unit according to an embodiment of the present disclosure, wherein Figure 14 schematically shows a plan view of the second pixel defining layer according to an embodiment of the present disclosure, Figure 15 schematically shows a plan view of the first passivation layer, the first electrode layer, the first pixel defining layer, the second pixel defining layer and the first groove according to an embodiment of the present disclosure, and Figure 16 schematically shows a fourth cross-sectional view of two adjacent sub-pixels according to an embodiment of the present disclosure.

[0167] With reference to Figures 14 to 16 , in some specific embodiments, the display substrate further includes a first pixel defining layer (PDL1) and a second pixel defining layer (PDL2). The first pixel defining layer (PDL1) is located on the side of the first electrode 251 layer facing away from the base substrate 200. The second pixel defining layer (PDL2) is located between the first pixel defining layer (PDL1) and the first passivation layer 220. The first pixel defining layer (PDL1) includes a black pixel defining material, while the second pixel defining layer (PDL2) includes a transparent pixel defining material. At least one sub-pixel (PX) further includes a pixel defining portion (XD) and an auxiliary bonding portion (TH). The pixel defining portion (XD) is located in the first pixel defining layer (PDL1), while the auxiliary bonding portion (TH) is located in the second pixel defining layer (PDL2). In the same sub-pixel (PX), the pixel defining portion (XD) is configured to define an effective light-emitting area of ​​the organic light-emitting device (OL). The pixel defining portion (XD) is bonded to the first passivation portion (222) via the auxiliary bonding portion (TH). The maximum thickness of the auxiliary bonding portion (TH) is less than or equal to the maximum thickness of the pixel defining portion (XD).

[0168] In the embodiment of the present disclosure, a pixel opening V1 is defined in the pixel defining portion XD. The area defined by the pixel opening V1 is the effective light-emitting area of ​​the organic light-emitting device OL. Referring to FIG. 15 , the pixel opening V1 in the pixel defining portion XD defines a substantially circular area, which is also the effective light-emitting area of ​​the organic light-emitting device OL. It should be noted that this does not constitute a limitation of the embodiment of the present disclosure; the pixel opening V1 in the embodiment of the present disclosure may have any shape.

[0169] The pixel opening V1 can expose the first electrode 251 of the light-emitting device, so that the hole injection layer can contact and electrically connect with the exposed first electrode 251. Correspondingly, the second electrode 261 can cover the pixel opening V1, so that the electron injection layer can contact and electrically connect with the second electrode 261.

[0170] Compared to the black pixel defining material, the transparent pixel defining material has better adhesion to the first passivation portion 222. Therefore, an auxiliary bonding portion TH comprising the transparent pixel defining material is formed between the pixel defining portion XD and the first passivation portion 222. This ensures a more secure bonding between the pixel defining portion XD and the first passivation portion 222, preventing the pixel defining portion XD from warping or peeling off from the first passivation portion 222 when etching the first groove 211. Furthermore, the thickness of the auxiliary bonding portion TH is smaller than that of the pixel defining portion XD, making the auxiliary bonding portion TH thinner and minimizing its impact on film thickness and flatness.

[0171] With reference to Figures 14 to 16 , in some specific embodiments, within a single sub-pixel PX, the orthographic projection of the pixel defining portion XD on the substrate 200 overlaps with the orthographic projection of the first passivation portion 222 on the substrate 200, and the overlapping portion defines a first pattern. The first pattern includes a central region A1 and an edge region A2 outside the central region A1. The orthographic projection of the first electrode 251 on the substrate 200 covers the central region A1, and the orthographic projection of the auxiliary lamination portion TH on the substrate 200 covers the edge region A2.

[0172] In the same sub-pixel PX, the first electrode 251 and the auxiliary bonding portion TH cooperate to cover the first pattern as much as possible. The inner side of the first pattern is covered by the first electrode 251, and the outer side is covered by the auxiliary bonding portion TH. In this way, the contact area between the pixel defining portion XD and the first passivation portion 222 can be minimized or even made to have no contact with the first passivation portion 222.

[0173] In some specific embodiments, in the same sub-pixel PX, the orthographic projection of the auxiliary lamination portion TH on the base substrate 200 surrounds the orthographic projection of the first electrode 251 on the base substrate 200 .

[0174] In the same sub-pixel PX (for example, in the first sub-pixel PX1), the orthographic projection of the first electrode 251 on the base substrate 200 includes a circular pattern, and accordingly, the orthographic projection of the auxiliary laminating portion TH on the base substrate 200 includes a circular ring pattern. Optionally, the orthographic projection of the auxiliary laminating portion TH on the base substrate 200 may overlap with the orthographic projection of the first electrode 251 on the base substrate 200 to a certain extent, thereby preventing the two from overlapping in some areas and not overlapping in other areas due to process fluctuations, which is conducive to improving uniformity.

[0175] Optionally, the orthographic projection of the auxiliary bonding portion TH on the base substrate 200 may also cover the orthographic projection of the second connection portion 223 on the base substrate 200 , so that the first pixel defining layer PDL1 there can be better bonded to the second connection portion 223 .

[0176] Optionally, the auxiliary bonding portions TH of at least two sub-pixels PX form an integrated structure. For example, the auxiliary bonding portions TH of the sub-pixels PX in the same repeating unit P are connected to each other through the third connecting portion LJ to form an integrated structure.

[0177] Figures 17 and 18 schematically show four plan views of sub-pixels in a repeating unit according to an embodiment of the present disclosure, wherein Figure 17 schematically shows three plan views of the first passivation layer according to an embodiment of the present disclosure, Figure 18 schematically shows three plan views of the first passivation layer, the first electrode layer, the first pixel defining layer and the first groove according to an embodiment of the present disclosure, and Figure 19 schematically shows five cross-sectional views of two adjacent sub-pixels according to an embodiment of the present disclosure.

[0178] 17 to 19 , in some specific embodiments, a plurality of partition structures GD are disposed between two adjacent sub-pixels PX, wherein at least two partition structures GD have different areas.

[0179] In an embodiment of the present disclosure, between two adjacent subpixels PX, the plurality of partition structures GD may each comprise arc-shaped structures arranged in sequence. In a first subpixel PX1 and the plurality of partition structures GD adjacent thereto, the area of ​​the partition structure GD decreases as the distance from the first subpixel PX1 increases. In a second subpixel PX2 and the plurality of partition structures GD adjacent thereto in the fourth direction Z2, the area of ​​the partition structure GD decreases as the distance from the second subpixel PX2 increases. In a third subpixel PX3 and the plurality of partition structures GD adjacent thereto in the third direction Z1, the area of ​​the partition structure GD decreases as the distance from the third subpixel PX3 increases.

[0180] In this way, on the one hand, the partition effect can be further enhanced by using multiple partition structures GD, and at the same time, the area occupied by the partition structure GD can be minimized.

[0181] Figures 20 and 21 schematically show a fifth plan view of a sub-pixel in a repeating unit according to an embodiment of the present disclosure, wherein Figure 20 schematically shows a plan view of the second flat layer according to an embodiment of the present disclosure, Figure 21 schematically shows a plan view of the first passivation layer, the first electrode layer, the first pixel defining layer, the second flat layer and the first groove according to an embodiment of the present disclosure, and Figure 22 schematically shows a sixth cross-sectional view of two adjacent sub-pixels according to an embodiment of the present disclosure.

[0182] With reference to Figures 20 to 22 , in some specific embodiments, the display substrate further includes a second planar layer 280, which is located between the first passivation layer 220 and the first electrode 251. At least one sub-pixel PX further includes a first spacer 281, which is located in the second planar layer 280. In the same sub-pixel PX, the orthographic projection of the first electrode 251 on the base substrate 200 overlaps with the orthographic projection of the first passivation portion 222 on the base substrate 200, and the overlapping portion defines a second pattern B. The orthographic projection of the first spacer 281 on the base substrate 200 covers the second pattern B.

[0183] In the embodiment of the present disclosure, the shape of the first spacer 281 is substantially the same as that of the first electrode 251. The first spacer 281 is slightly larger than the first electrode 251, thereby filling the gap between the first electrode 251 and the first passivation portion 222. The material of the first planarization layer 210 and the second planarization layer 280 can be the same. Compared to the first passivation portion 222, the first spacer 281 located in the second planarization layer 280 has greater flexibility. Filling the gap between the first electrode 251 and the first passivation portion 222 further improves the flatness of the first electrode 251.

[0184] In some specific embodiments, in the same sub-pixel PX, the orthographic projection of the pixel defining portion XD on the base substrate 200 overlaps with the orthographic projection of the first passivation portion 222 on the base substrate 200, and the overlapping portion defines a first pattern, and the orthographic projection of the first spacer 281 on the base substrate 200 covers the first pattern.

[0185] In the embodiment of the present disclosure, in addition to filling between the first electrode 251 and the first passivation portion 222, the first spacer 281 further extends outward to fill between the pixel defining portion XD and the first passivation portion 222, so as to improve the adhesion between the pixel defining portion XD and the first passivation portion 222 and prevent the two from warping and peeling off.

[0186] In some specific embodiments, at least one sub-pixel PX further includes a first planar portion 212, which is located in the first planar layer 210. In the same sub-pixel PX, the thickness of the first spacer 281 is less than or equal to the thickness of the first passivation portion 222, and the thickness of the first passivation portion 222 is less than the thickness of the first planar portion 212.

[0187] In the embodiment of the present disclosure, the thickness of the first spacer 281 is relatively thin, thereby minimizing the impact of the first spacer 281 on the overall thickness of the display substrate. Alternatively, the thickness of the first flat portion 212 can be reduced, so that the overall thickness of the display substrate can be roughly the same or even remain unchanged before and after the addition of the first spacer 281.

[0188] 9 to 10B , in some specific embodiments, the plurality of sub-pixels PX include a first sub-pixel PX1, a second sub-pixel PX2, and a third sub-pixel PX3. The first sub-pixel PX1 and the second sub-pixel PX2 have the same color, and the second sub-pixel PX2 and the third sub-pixel PX3 have the same color. For the adjacent first sub-pixel PX1 and the second sub-pixel PX2, and the partition structure GD located between the first sub-pixel PX1 and the second sub-pixel PX2, in a direction from the first sub-pixel PX1 to the second sub-pixel PX2, a distance d1 between the first groove 211 and the first sub-pixel PX1 is smaller than a distance d2 between the first groove 211 and the second sub-pixel PX2. For the adjacent first sub-pixel PX1 and the third sub-pixel PX3 and the partition structure GD located between the first sub-pixel PX1 and the third sub-pixel PX3, in the direction from the first sub-pixel PX1 to the third sub-pixel PX3, the distance d1 between the first groove 211 and the first sub-pixel PX1 is smaller than the distance d2 between the first groove 211 and the third sub-pixel PX3.

[0189] For example, the first subpixel PX1 can be set as a red pixel, the second subpixel PX2 and the third subpixel PX3 can be set as green subpixels PX, and the plurality of subpixels PX further includes a fourth subpixel PX4, which can be set as a blue subpixel PX. That is, embodiments of the present disclosure can adopt the aforementioned RGGB pixel structure.

[0190] In some specific embodiments, the display substrate further includes a plurality of gate lines GL and a plurality of data lines DL, wherein the plurality of gate lines GL extend along a first direction X, and the plurality of data lines DL extend along a second direction Y. The first subpixels PX1 and the second subpixels PX2 are alternately arranged along a third direction Z1, the first subpixels PX1 and the third subpixels PX3 are alternately arranged along a fourth direction Z2, the third subpixels PX3 and the fourth subpixels PX4 are alternately arranged along the third direction Z1, and the second subpixels PX2 and the fourth subpixels PX4 are alternately arranged along the fourth direction Z2. The first direction X, the second direction Y, the third direction Z1, and the fourth direction Z2 intersect with each other.

[0191] Optionally, the third direction Z1 and the fourth direction Z2 are perpendicular to each other, and the angle between either the third direction Z1 or the fourth direction Z2 and the first direction X may be set to 45°.

[0192] In the embodiment of the present disclosure, the partition structures GD between two adjacent sub-pixels PX are arranged at unequal intervals. For example, for the first sub-pixel PX1, the partition structures GD between the first sub-pixel PX1 and the other sub-pixels PX are all arranged close to the first sub-pixel PX1. For example, the partition structure GD between the first sub-pixel PX1 and the second sub-pixel PX2 is arranged close to the first sub-pixel PX1, and the partition structure GD between the first sub-pixel PX1 and the third sub-pixel PX3 is also arranged close to the first sub-pixel PX1.

[0193] 9 , in some specific embodiments, the orthographic projection of the partition structure GD disposed adjacent to the first sub-pixel PX1 on the base substrate 200 defines a third pattern. The orthographic projection of the third pattern at least partially surrounds the pixel opening V1 of the first sub-pixel PX1 on the base substrate 200. This allows the partition structure GD around the first sub-pixel PX1 to align with the pixel opening V1 of the first sub-pixel PX1, thereby improving space utilization.

[0194] In some specific embodiments, for the adjacent third and fourth subpixels PX3 and PX4, and the partition structure GD located between the third and fourth subpixels PX3 and PX4, in a direction from the third subpixel PX3 to the fourth subpixel PX4, a distance d3 between the first groove 211 and the third subpixel PX3 is smaller than a distance d4 between the first groove 211 and the fourth subpixel PX4. For the adjacent second and fourth subpixels PX2 and PX4, and the partition structure GD located between the second and fourth subpixels PX2 and PX4, in a direction from the second subpixel PX2 to the fourth subpixel PX4, a distance d3 between the first groove 211 and the second subpixel PX2 is smaller than a distance d4 between the first groove 211 and the fourth subpixel PX4.

[0195] In the embodiments of the present disclosure, for the fourth subpixel PX4, the partition structure GD between the fourth subpixel PX4 and the other subpixels PX is positioned away from the fourth subpixel PX4. This allows sufficient space for the fourth subpixel PX4, ensuring that the effective light-emitting area of ​​the fourth subpixel PX4 is sufficient. For example, the third subpixel PX3 and the fourth subpixel PX4 are alternately positioned along the third direction Z1, and the partition structure GD between the third subpixel PX3 and the fourth subpixel PX4 is positioned close to the third subpixel PX3. The second subpixel PX4 and the fourth subpixel PX4 are alternately positioned along the fourth direction Z2, and the partition structure GD between the second subpixel PX2 and the fourth subpixel PX4 is positioned close to the second subpixel PX2.

[0196] 9 , in some specific embodiments, the orthographic projection of the partition structure GD disposed adjacent to the third sub-pixel PX3 in the third direction Z1 on the base substrate 200 defines a fourth pattern. The fourth pattern at least partially surrounds the orthographic projection of the pixel opening V1 of the third sub-pixel PX3 on the base substrate 200. This allows the partition structures GD on both sides of the third pixel to align with the pixel opening V1 of the third sub-pixel PX3, thereby improving space utilization.

[0197] In some specific embodiments, the orthographic projection of the partition structure GD disposed adjacent to the second sub-pixel PX2 in the fourth direction Z2 on the base substrate 200 defines a fifth pattern, and the fifth pattern at least partially surrounds the orthographic projection of the pixel opening V1 of the second sub-pixel PX2 on the base substrate 200. This allows the partition structures GD on both sides of the second pixel to align with the pixel opening V1 of the third sub-pixel PX3, thereby improving space utilization.

[0198] In some specific embodiments, the area of ​​the effective light-emitting area of ​​the first sub-pixel PX1 is larger than the area of ​​the effective light-emitting area of ​​the second sub-pixel PX2, and smaller than the area of ​​the effective light-emitting area of ​​the fourth sub-pixel PX4, and the area of ​​the effective light-emitting area of ​​the second sub-pixel PX2 is approximately the same as the area of ​​the effective light-emitting area of ​​the third sub-pixel PX3.

[0199] In the embodiments of the present disclosure, the effective light-emitting area of ​​a sub-pixel PX may refer to the effective light-emitting area of ​​the light-emitting device OL in the sub-pixel PX. The effective light-emitting area of ​​the light-emitting device OL has been described in detail above and will not be repeated here. For example, the first sub-pixel PX1 may be set as a red sub-pixel, the second sub-pixel PX2 and the third sub-pixel PX3 may be set as green sub-pixels, and the fourth sub-pixel PX4 may be set as a blue sub-pixel. The blue sub-pixel PX has the largest effective light-emitting area, the red sub-pixel PX has the second largest effective light-emitting area, and the green sub-pixel PX has the smallest effective light-emitting area.

[0200] At least some embodiments of the present disclosure further provide a display panel, comprising the display substrate described above, having a display area AA and a peripheral area NA and related structures therein. For example, the display panel may be a liquid crystal display panel.

[0201] At least some embodiments of the present disclosure further provide a display device, which may include any device or product having a display function. For example, the display device may be a smartphone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0202] It should be understood that the display device according to the embodiment of the present disclosure has all the characteristics and advantages of the above-mentioned display substrate and display panel. For details, please refer to the above description and will not be repeated here.

[0203] It should be noted that the above description only illustrates the technical solutions of the embodiments of the present disclosure by way of example, and does not mean that the embodiments of the present disclosure are limited to the above steps and structures. Where possible, the steps and structures can be adjusted and selected as needed. Therefore, some steps and units are not essential elements for implementing the overall inventive concept of the embodiments of the present disclosure.

[0204] The present disclosure has been described so far in conjunction with preferred embodiments. It should be understood that those skilled in the art may make various other changes, substitutions, and additions without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of the embodiments of the present disclosure is not limited to the specific embodiments described above, but is defined by the appended claims.

Claims

1. A display substrate, wherein: include: substrate substrate; A first planar layer disposed on the substrate; A first passivation layer disposed on a side of the first planar layer away from the substrate; An organic light emitting layer and an organic common layer are arranged on a side of the first passivation layer away from the base substrate; The display substrate further comprises a plurality of sub-pixels, a partition structure is arranged between two adjacent sub-pixels, the partition structure comprises a partition portion and a first groove, the partition portion is located in the first passivation layer, the first groove is located in the first flat layer, and an orthographic projection of the partition portion on the base substrate partially overlaps with an orthographic projection of the first groove on the base substrate; At least one of the sub-pixels includes an organic light-emitting device, the organic light-emitting device includes a light-emitting portion and a charge generating portion, the light-emitting portion is located in the organic light-emitting layer, and the charge generating portion is located in the organic common layer; For two adjacent sub-pixels and a partition structure between the two sub-pixels, the charge generating portion of one sub-pixel includes a first extending sub-portion extending between the two sub-pixels, and the charge generating portion of the other sub-pixel includes a second extending sub-portion extending between the two sub-pixels; and One of the first extension sub-portion and the second extension sub-portion is located on a side of the partition portion away from the base substrate, and the other is located on the bottom wall of the first groove. The first extension sub-portion and the second extension sub-portion are arranged with insulation intervals.

2. The display substrate according to claim 1, wherein: The display substrate further comprises a first electrode layer, a second electrode layer and a pixel circuit layer, wherein the first electrode layer is located on a side of the organic light-emitting layer close to the base substrate, the second electrode layer is located on a side of the organic light-emitting layer away from the base substrate, and the pixel circuit layer is located on a side of the first planar layer close to the base substrate; At least one of the sub-pixels further includes a pixel circuit, and the organic light-emitting device further includes a first electrode and a second electrode, the first electrode is located in the first electrode layer, the second electrode is located in the second electrode layer, the first electrode is electrically connected to the pixel circuit, and the second electrode is electrically connected to the first voltage terminal; For the two adjacent sub-pixels and the partition structure between the two sub-pixels, wherein The second electrode of one of the sub-pixels includes a third extending sub-portion extending between the two sub-pixels, and the second electrode of another sub-pixel includes a fourth extending sub-portion extending between the two sub-pixels; and, The third extension sub-portion is located on a side of the first extension sub-portion away from the substrate, the fourth extension sub-portion is located on a side of the second extension sub-portion away from the substrate, and the third extension sub-portion and the fourth extension sub-portion are arranged with insulation intervals.

3. The display substrate according to claim 2, wherein: At least one sub-pixel further includes a first connection portion, and in the same sub-pixel, the first electrode is electrically connected to the pixel circuit through the first connection portion; An orthographic projection of the first groove on the base substrate does not overlap with an orthographic projection of the first connecting portion on the base substrate.

4. The display substrate according to claim 1, wherein: The partition portion includes a first partition sub-portion and a second partition sub-portion; The first partition sub-portion covers the surface of the first flat layer on the side facing away from the base substrate, the orthographic projection of the first groove on the base substrate covers the orthographic projection of the second partition sub-portion on the base substrate, and the orthographic projection of the first partition sub-portion on the base substrate at least partially surrounds the orthographic projection of the second partition sub-portion on the base substrate.

5. The display substrate according to claim 1, wherein: For two adjacent sub-pixels and a partition structure between the two sub-pixels, In a direction from one of the sub-pixels to another of the sub-pixels, a distance between the first groove and one of the sub-pixels is smaller than a distance between the first groove and another of the sub-pixels; The first extension portion of the sub-pixel having a smaller distance from the first groove is located on a side of the partition portion away from the base substrate, and the second extension portion of the sub-pixel having a larger distance from the first groove is located on the bottom wall of the first groove.

6. The display substrate according to any one of claims 2 to 5, wherein: At least one of the sub-pixels further comprises a first passivation portion, the first passivation portion is located in the first passivation layer, and in the same sub-pixel, an orthographic projection of the first passivation portion on the base substrate covers an orthographic projection of the first electrode on the base substrate; For two adjacent sub-pixels and a partition structure between the two sub-pixels, the first passivation portion and the partition portion of one of the sub-pixels form an integrated structure.

7. The display substrate according to claim 6, wherein: The display substrate further comprises a first pixel defining layer and a second pixel defining layer, wherein the first pixel defining layer is located on a side of the first electrode layer away from the base substrate, and the second pixel defining layer is located between the first pixel defining layer and the first passivation layer, wherein a material of the first pixel defining layer comprises a black pixel defining material, and a material of the second pixel defining layer comprises a transparent pixel defining material; At least one of the sub-pixels further comprises a pixel defining portion and an auxiliary bonding portion, wherein the pixel defining portion is located in the first pixel defining layer, and the auxiliary bonding portion is located in the second pixel defining layer; In the same sub-pixel, the pixel defining portion is configured to define the effective light-emitting area of ​​the organic light-emitting device, the pixel defining portion is bonded to the first passivation portion through the auxiliary bonding portion, and the maximum thickness of the auxiliary bonding portion is less than or equal to the maximum thickness of the pixel defining portion.

8. The display substrate according to claim 7, wherein: In the same sub-pixel, an orthographic projection of the pixel defining portion on the base substrate overlaps with an orthographic projection of the first passivation portion on the base substrate, and the overlapping portion defines a first pattern; The first pattern includes a middle area and an edge area outside the middle area, the orthographic projection of the first electrode on the base substrate covers the middle area, and the orthographic projection of the auxiliary laminating portion on the base substrate covers the edge area.

9. The display substrate according to claim 7, wherein: In the same sub-pixel, the orthographic projection of the auxiliary bonding portion on the base substrate surrounds the orthographic projection of the first electrode on the base substrate.

10. The display substrate according to any one of claims 2 to 5, wherein: For two adjacent sub-pixels and a partition structure between the two sub-pixels, an orthographic projection of the first electrode of at least one of the sub-pixels on the base substrate does not overlap with an orthographic projection of the partition portion on the base substrate.

11. The display substrate according to any one of claims 1 to 5, wherein: A plurality of the partition structures are arranged between two adjacent sub-pixels, wherein at least two of the partition structures have different areas.

12. The display substrate according to claim 6, wherein: The display substrate further includes a second flat layer, wherein the second flat layer is located between the first passivation layer and the first electrode layer; At least one of the sub-pixels further comprises a first spacer, wherein the first spacer is located in the second planar layer; In the same sub-pixel, the orthographic projection of the first electrode on the base substrate overlaps with the orthographic projection of the first passivation portion on the base substrate, and the overlapping portion defines a second pattern, and the orthographic projection of the first spacer on the base substrate covers the second pattern.

13. The display substrate according to claim 12, wherein: In the same sub-pixel, the orthographic projection of the pixel defining portion on the base substrate overlaps with the orthographic projection of the first passivation portion on the base substrate, and the overlapping portion defines a first pattern, and the orthographic projection of the first spacer on the base substrate covers the first pattern.

14. The display substrate according to claim 13, wherein: At least one of the sub-pixels further comprises a first planar portion, wherein the first planar portion is located in the first planar layer; In the same sub-pixel, the thickness of the first spacer portion is less than or equal to the thickness of the first passivation portion, and the thickness of the first passivation portion is less than the thickness of the first flat portion.

15. The display substrate according to any one of claims 1 to 14, wherein: The plurality of sub-pixels include a first sub-pixel, a second sub-pixel and a third sub-pixel, the first sub-pixel and the second sub-pixel have the same color, and the second sub-pixel and the third sub-pixel have the same color; For the first sub-pixel and the second sub-pixel that are adjacent to each other and the partition structure between the first sub-pixel and the second sub-pixel, in the direction from the first sub-pixel to the second sub-pixel, the spacing between the first groove and the first sub-pixel is smaller than the spacing between the first groove and the second sub-pixel. a spacing between the second sub-pixels; For the first sub-pixel and the third sub-pixel that are adjacently arranged and the partition structure located between the first sub-pixel and the third sub-pixel, in the direction from the first sub-pixel to the third sub-pixel, the spacing between the first groove and the first sub-pixel is smaller than the spacing between the first groove and the third sub-pixel.

16. The display substrate according to claim 15, wherein: The orthographic projection of the partition structure disposed adjacent to the first sub-pixel on the base substrate defines a third pattern, and the orthographic projection of the third pattern on the base substrate at least partially surrounds the pixel opening of the first sub-pixel.

17. The display substrate according to claim 15, wherein: The plurality of sub-pixels further include a fourth sub-pixel, and the colors of the first sub-pixel, the second sub-pixel and the fourth sub-pixel are different from each other; For the third sub-pixel and the fourth sub-pixel that are adjacently arranged and the partition structure between the third sub-pixel and the fourth sub-pixel, in a direction from the third sub-pixel to the fourth sub-pixel, a distance between the first groove and the third sub-pixel is smaller than a distance between the first groove and the fourth sub-pixel; For the second sub-pixel and the fourth sub-pixel that are adjacently arranged and the partition structure located between the second sub-pixel and the fourth sub-pixel, in the direction from the second sub-pixel to the fourth sub-pixel, the distance between the first groove and the second sub-pixel is smaller than the distance between the first groove and the fourth sub-pixel.

18. The display substrate according to claim 16, wherein: The area of ​​the effective light-emitting area of ​​the first sub-pixel is larger than the area of ​​the effective light-emitting area of ​​the second sub-pixel and smaller than the area of ​​the effective light-emitting area of ​​the fourth sub-pixel. The area of ​​the effective light-emitting area of ​​the second sub-pixel is approximately the same as the area of ​​the effective light-emitting area of ​​the third sub-pixel.

19. The display substrate according to claim 16, wherein: The display substrate further includes a plurality of gate lines and a plurality of data lines, wherein the plurality of gate lines extend along a first direction, and the plurality of data lines extend along a second direction; The first sub-pixels and the second sub-pixels are alternately arranged along a third direction. The third sub-pixels are alternately arranged along a fourth direction, the third sub-pixels and the fourth sub-pixels are alternately arranged along the third direction, and the second sub-pixels and the fourth sub-pixels are alternately arranged along the fourth direction; The first direction, the second direction, the third direction and the fourth direction intersect with each other.

20. The display substrate according to claim 15, wherein: The orthographic projection of the partition structure disposed adjacent to the third sub-pixel in the third direction on the base substrate defines a fourth pattern, and the fourth pattern at least partially surrounds the orthographic projection of the pixel opening of the third sub-pixel on the base substrate; and / or, The orthographic projection of the partition structure disposed adjacent to the second sub-pixel in the fourth direction on the base substrate defines a fifth pattern, and the fifth pattern at least partially surrounds the orthographic projection of the pixel opening of the second sub-pixel on the base substrate.

21. A display panel, wherein: The display panel includes the display substrate according to any one of claims 1 to 20.

22. A display device, wherein: The display device comprises the display panel as claimed in claim 21.

Images