A display aging test device and system

Abstract

This invention discloses a display aging test apparatus and system, including an aging base plate, an FPGA signal board and / or MCU control board, a video adapter board, a power supply board, and a module adapter board mounted on the aging base plate; the module adapter board is electrically connected to the power supply board, the FPGA signal board and / or MCU control board, and the video adapter board; the module adapter board connects to the display to be aged, and transmits received signals and power to the display to be aged; the power supply board is configured with a top power interface, a bottom power interface, and an adjustable power supply; the top power interface is electrically connected to the bottom power interface, and the bottom power interface is electrically connected to the adjustable power supply; the number of power supply boards is n, and the n power supply boards can generate multiple power supplies to the module adapter board through a stacked structure, where n is a positive integer. The stacked structure of the power supply boards allows for flexible increases or decreases in the number of power supply boards according to the needs of the display to be aged, reducing the cost of the apparatus.

Description

Technical Field

[0001] This invention belongs to the field of aging test technology, and in particular relates to a display aging test device and system. Background Technology

[0002] With the rise of electronic devices, the demand for displays is constantly increasing. Improving display production capacity and aging-in capabilities has become a crucial step. However, in existing aging-in testing equipment, each display requires its own power supply, and different displays require different power supplies. When testing multiple displays, corresponding power supplies must be configured according to different models, resulting in power supply redundancy in existing aging-in testing equipment and increasing equipment costs. Furthermore, displays use numerous data transmission protocol standards, sometimes even non-standard protocols, forcing aging-in testing equipment to frequently rewrite programs, increasing time costs and impacting product launch schedules.

[0003] Although existing equipment can test multiple displays at once, the number that can be tested simultaneously is limited. To meet the demand for aging tests on large volumes of displays, a large number of testing devices are still needed, which not only increases the difficulty of control but also drives up aging and maintenance costs. Summary of the Invention

[0004] Based on this, the present invention provides a display aging test device and system, which aims to solve the problems of complex power supply configuration and difficulty in controlling a large number of aging test devices in the prior art.

[0005] A first aspect of the present invention provides a display aging test apparatus, comprising:

[0006] Aging baseboard, FPGA signal board and / or MCU control board, video adapter board, power board and module adapter board mounted on the aging baseboard;

[0007] The module adapter board is electrically connected to the power board, FPGA signal board and / or MCU control board, and video adapter board; the module adapter board is connected to the display to be tested for aging, and the module adapter board transmits the received signals and power to the display to be tested for aging.

[0008] The power board is equipped with a top power interface, a bottom power interface, and at least one adjustable power supply.

[0009] The top power connector is either a male or female connector, and the bottom power connector is either a female or male connector that snaps into the top power connector; both the top and bottom power connectors have z power supply pins, where z is a positive integer.

[0010] The number of voltage-adjustable power supplies is m. The m voltage-adjustable power supplies are electrically connected to the bottom power interface to form a power supply pin group containing m power supply pins, and there are zm unused power supply pins of the bottom power interface, where m is a positive integer and m≤z.

[0011] The power supply pins of the zm unused bottom power interface are electrically connected to the zm power supply pins of the top power interface on the same power board.

[0012] The number of power boards is n. The n power boards can form an electrically connected stacked structure through a snap-fit ​​method to generate multiple power supplies to the module adapter board. n is a positive integer and n≤z / m.

[0013] Optionally, in the stacked structure of n power boards forming an electrical connection, the power supply pin group of each power board that is not the bottom layer can be electrically connected to the top power interface of the power board below through a snap-fit, thereby achieving an electrical connection to the bottom power interface of the power board below, and finally to the bottom power interface of the bottom layer power board.

[0014] Optionally, the FPGA signal board is equipped with a high-speed interface, through which the FPGA signal board communicates with an external host computer to receive video signals and control signals; the aging base plate is equipped with an aging power interface, through which the aging base plate is electrically connected to an external power supply.

[0015] Optionally, the display aging test device includes an FPGA signal board and an MCU control board. The FPGA signal board transmits the received control signals to the MCU control board, and the MCU control board converts the received control signals into module control signals and transmits them to the module adapter board. The FPGA signal board converts the received video signals into module video protocol signals and transmits them to the video adapter board, and the video adapter board then transmits the module video protocol signals to the module adapter board.

[0016] Optionally, the video adapter board may also be configured with a switch chip and / or a bridge chip, which converts the module video protocol signal into a video protocol signal that the module adapter board can receive before transmitting it to the module adapter board.

[0017] Optionally, the aging base plate is configured with the same top power interface as the power board, and the video adapter board is configured with the same bottom power interface as the power board.

[0018] A second aspect of the present invention provides a display aging test system, including the display aging test apparatus described above.

[0019] Optionally, multiple display aging test devices can be connected via high-speed cables and power cables to form a chain-structured display aging test system.

[0020] Optionally, the FPGA signal board is configured with at least two high-speed interfaces. Each FPGA signal board is connected to the FPGA signal board of another display aging test device in the system through at least one high-speed interface to transmit video signals and control signals. One of the FPGA signal boards communicates with an external host computer through the high-speed interface to receive video signals and control signals.

[0021] Optionally, the aging substrate is equipped with at least two aging power interfaces, and each aging substrate is electrically connected to the aging substrate of another display aging test device in the system through at least one aging power interface; at least one aging substrate is electrically connected to an external power supply through the aging power interface.

[0022] The beneficial effects of this invention are as follows:

[0023] 1. The power board is designed with a stacked structure, which can provide a flexible and variable number of power supplies to adapt to the power requirements of different displays. The electrical connection between the top and bottom power interfaces of the power board allows for quick, reusable, and low-cost increases and decreases in the number of power supplies without the need for modification or redesign of the power board during stacking.

[0024] 2. In the aging test device, the MCU control board is used to convert and transmit control signals, and the FPGA signal board is used to convert and transmit video signals. The MCU control board can be used alone to control the display to be aged to enter the built-in test mode for aging, thereby accelerating the aging process and improving production efficiency.

[0025] 3. By configuring at least two high-speed interfaces in the FPGA signal board, the FPGA signal boards of each aging test device in the system can be cascaded together through the high-speed interfaces. Only the transmission of control signals and video signals of one FPGA signal board is required to realize the transmission of control signals and video signals of all FPGA signal boards, simplifying the entire control process.

[0026] 4. By configuring at least two aging power interfaces on the aging base plate, the aging base plates of each aging test device in the system can be cascaded together through the aging power interfaces. This allows one external power supply to be connected to the aging power interface of one aging base plate, thereby enabling the power supply to all aging base plates, reducing the use of external power supplies and lowering the system cost. Attached Figure Description

[0027] The accompanying drawings, which are provided to further illustrate the invention and constitute a part of this invention, are illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention.

[0028] Figure 1 This is a first-view three-dimensional structural diagram of the display aging test device in Embodiment 1 of the present invention.

[0029] Figure 2 This is a second-view three-dimensional structural diagram of the display aging test device in Embodiment 1 of the present invention.

[0030] Figure 3 This is an overall structural block diagram of the aging test device in Embodiment 1 of the present invention.

[0031] Figure 4 This is a schematic diagram of the aging base plate structure in Embodiment 1 of the present invention.

[0032] Figure 5 This is a schematic diagram of the FPGA signal board in Embodiment 1 of the present invention.

[0033] Figure 6 This is a schematic diagram of the video adapter board in Embodiment 1 of the present invention.

[0034] Figure 7 This is a schematic diagram of the power board structure in Embodiment 1 of the present invention.

[0035] Figure 8 This is a three-dimensional structural diagram showing the distribution of the top and bottom power interfaces of the power board in Embodiment 1 of the present invention.

[0036] Figure 9 This is a schematic diagram of a stacked three-dimensional structure of power board-power board-video adapter board-FPGA signal board in Embodiment 1 of the present invention.

[0037] Figure 10 This is a schematic diagram of the pin definitions of the top power interface and the bottom power interface of the power board in Embodiment 1 of the present invention.

[0038] Figure 11 This is a schematic diagram of the electrical connection between the top power interface and the bottom power interface power supply pins of the power board in Embodiment 1 of the present invention.

[0039] Figure 12 This is a schematic diagram of the pin distribution of the top power interface and bottom power interface of the power board in Embodiment 1 of the present invention.

[0040] Figure 13 This is a schematic diagram of the MCU control board structure in Embodiment 1 of the present invention.

[0041] Figure 14 This is a schematic diagram of the module adapter board structure in Embodiment 1 of the present invention.

[0042] Figure 15 This is a schematic diagram of the overall structure of the aging test system in Embodiment 2 of the present invention.

[0043] Figure 16 This is a schematic diagram of the connection of multiple FPGA signal boards in Embodiment 2 of the present invention.

[0044] Figure 17 This is a schematic diagram of the topological structure of multiple aging base plates connected in Embodiment 2 of the present invention. Detailed Implementation

[0045] To more clearly illustrate the overall concept of the present invention, a detailed description will be provided below with reference to the accompanying drawings and examples.

[0046] In the description of this invention, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0047] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0048] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0049] In this invention, unless otherwise expressly specified and limited, the first feature "on" or "below" the second feature may be in direct contact with the first and second features, or indirect contact through an intermediate medium. In the description of this specification, references to terms such as "an embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0050] like Figures 1 to 14 As shown, a first aspect of the present invention provides a display aging test apparatus, comprising:

[0051] Aging baseboard, FPGA signal board and / or MCU control board, video adapter board, power board and module adapter board mounted on the aging baseboard;

[0052] The module adapter board is electrically connected to the power board, FPGA signal board and / or MCU control board, and video adapter board; the module adapter board is connected to the display to be tested for aging, and the module adapter board transmits the received signals and power to the display to be tested for aging.

[0053] The power board is equipped with a top power interface, a bottom power interface, and at least one adjustable power supply.

[0054] The top power connector is either a male or female connector, and the bottom power connector is either a female or male connector that snaps into the top power connector; both the top and bottom power connectors have z power supply pins, where z is a positive integer.

[0055] The number of voltage-adjustable power supplies is m. The m voltage-adjustable power supplies are electrically connected to the bottom power interface to form a power supply pin group containing m power supply pins, and there are zm unused power supply pins of the bottom power interface, where m is a positive integer and m≤z.

[0056] The power supply pins of the zm unused bottom power interface are electrically connected to the zm power supply pins of the top power interface on the same power board.

[0057] The number of power boards is n. The n power boards can form an electrically connected stacked structure through a snap-fit ​​method to generate multiple power supplies to the module adapter board. n is a positive integer and n≤z / m.

[0058] It should be noted that the power supply board can generate multiple power sources to power the module adapter board through a stacked structure. The number of power supply boards can be flexibly increased or decreased according to the needs of the display to be aged. The electrical connection between the top and bottom power interfaces on the power supply board allows for quick, reusable, and low-cost increases and decreases in the number of power supplies without requiring modification or redesign of the power supply board during stacking. Furthermore, the stacked structure, which forms electrical connections through a snap-fit ​​method, not only allows for flexible power supply configuration but also saves lateral space required by the power supply board.

[0059] In some embodiments of the present invention, in a stacked structure of n power boards forming an electrical connection, the power supply pin group of each power board (excluding the bottommost one) can be electrically connected to the top power interface of the power board below it via a snap-fit ​​connection, and then to the bottom power interface of the power board below it, ultimately connecting to the bottom power interface of the bottommost power board. Specifically, except for the bottommost one, the power supply pin group of each power board can be electrically connected to the top power interface of the power board below it via a snap-fit ​​connection. Since there is an electrical connection between the top and bottom power interfaces of the lower power board, the electrical signal of the power supply pin group can be mapped to the power supply pin of the bottom power interface. Similarly, the signal mapped to the bottom power supply pin of the lower power board can be transmitted to the top power interface of the next lower power board via a snap-fit ​​connection, and then again mapped to the power supply pin of its bottom power interface through the internal connections of that layer of power board. This transmission continues layer by layer until the electrical signal of the power supply pin group is mapped to the bottom power interface pin of the bottommost power board.

[0060] In some embodiments of the present invention, the power supply pins of the top power interface and the bottom power interface are symmetrically distributed in the power board with the center of the power board as the origin. This eliminates the need to determine the connection direction during stacking, simplifying the installation process.

[0061] In some embodiments of the present invention, the power board is also equipped with multiple protection circuits. The voltage adjustable power supply is electrically connected to the protection circuit, and the protection circuit is then electrically connected to the bottom power interface to protect the voltage adjustable power supply and improve the stability of the power board.

[0062] In some embodiments of the present invention, the FPGA signal board is configured with a high-speed interface, through which the FPGA signal board communicates with an external host computer to receive video signals and control signals; the aging baseboard is configured with an aging power interface, through which the aging baseboard is electrically connected to an external power supply.

[0063] In some embodiments of the present invention, the display aging test device includes an FPGA signal board and an MCU control board. The FPGA signal board transmits the received control signals to the MCU control board, and the MCU control board converts the received control signals into module control signals and transmits them to the module adapter board. The FPGA signal board converts the received video signals into module video protocol signals and transmits them to the video adapter board, and the video adapter board then transmits the module video protocol signals to the module adapter board.

[0064] It should be noted that in the aging test equipment, the MCU control board converts and transmits control signals, and the FPGA signal board converts and transmits video signals. Generally speaking, the program modification complexity of the FPGA is higher than that of the MCU. The MCU control board can be used alone to control the display to be aged into the built-in test mode for aging, thereby speeding up the aging process and improving production efficiency.

[0065] In some embodiments of the present invention, the video adapter board is further configured with a switch chip and / or a bridge chip, which converts the module video protocol signal into a video protocol signal that the display can receive and then transmits it to the module adapter board.

[0066] In some embodiments of the present invention, in scenarios where aging requirements are not high, the display aging test device does not include an FPGA signal board. The MCU control board communicates with the host computer to receive control signals and switches the display to the built-in test mode, realizing the built-in test image switching aging of the display. This greatly saves aging costs.

[0067] In some embodiments of the present invention, the MCU control board is also equipped with a flash chip for storing offline control instructions, which can realize the switching and aging of built-in test images on the display without a host computer.

[0068] In some embodiments of the present invention, the aging base plate is configured with the same top power interface as the power board, and the video adapter board is configured with the same bottom power interface as the power board.

[0069] It should be noted that the power interface design allows the aging base plate to be stacked with the video adapter board or power board, or vice versa, further saving the horizontal space of the monitor aging test device.

[0070] like Figures 15-17 As shown, a second aspect of the present invention provides a display aging test system, including the display aging test apparatus described above.

[0071] In some embodiments of the present invention, multiple display aging test devices are connected by high-speed cables and power cables to form a chain-structured display aging test system.

[0072] In some embodiments of the present invention, the FPGA signal board is configured with at least two high-speed interfaces. Each FPGA signal board is connected to the high-speed interface of the FPGA signal board of another display aging test device in the system through at least one high-speed interface to transmit video signals and control signals. One of the FPGA signal boards communicates with an external host computer through the high-speed interface to receive video signals and control signals.

[0073] It should be noted that by configuring at least two high-speed interfaces in the FPGA signal board, the FPGA signal boards of each aging test device in the system can be cascaded together through the high-speed interfaces. Only the transmission of control signals and video signals of one FPGA signal board is required to realize the transmission of control signals and video signals of all FPGA signal boards, which simplifies the entire control process.

[0074] In some embodiments of the present invention, the aging substrate is configured with at least two aging power interfaces, and the aging substrate is electrically connected to the aging substrate of another display aging test device in the system through at least one aging power interface. At least one aging substrate is electrically connected to an external power supply through an aging power interface.

[0075] It should be noted that by configuring at least two aging power interfaces on the aging substrate, the aging substrates of each aging test device in the system can be cascaded together through the aging power interfaces. This allows an external power supply to be connected to the aging power interface of one aging substrate, thereby enabling power supply to all aging substrates, reducing the use of external power supplies and lowering the system cost. Example 1

[0076] like Figure 1-3 As shown, this embodiment provides a display aging test device, including an aging base plate, an FPGA signal board, a video adapter board, five power boards, ten module adapter boards mounted on one side of the aging base plate, and an MCU control board mounted on the other side of the aging base plate.

[0077] The FPGA signal board connects to the MCU control board and the video adapter board. The MCU control board and the video adapter board are connected to ten module adapter boards. Each module adapter board is connected to a display to be tested for aging. Each power board is connected to two module adapter boards.

[0078] like Figure 4As shown, the aging baseboard is configured with two MCU low-speed interfaces connected to the MCU control board, ten top power interfaces connected to the power board or video adapter board, ten module low-speed interfaces connected to the module adapter board, ten module power interfaces connected to the module adapter board, and four aging power interfaces. The MCU low-speed interfaces of the aging baseboard are electrically connected to the ten module low-speed interfaces of the aging baseboard; the top power interfaces of the aging baseboard are electrically connected to the module power interfaces of adjacent aging baseboards. The four aging power interfaces are electrically connected to each other. The aging baseboard is electrically connected to an external power source through one of the aging power interfaces to supply power to the FPGA signal board, video adapter board, five power boards, and MCU control board in the device.

[0079] The structure of the FPGA signal board is as follows: Figure 5 As shown, two high-speed interfaces, a general-purpose interface, and the FPGA module are placed on top of the FPGA signal board, while two high-speed board-to-board interfaces are placed at the bottom. The FPGA signal board communicates with the host computer via a high-speed interface, such as an optical port, receiving video and control signals from the host computer. The FPGA signal board communicates with the MCU control board via a general-purpose interface, such as a Type-C port, transmitting the received control signals to the MCU control board. The FPGA signal board and the video adapter board establish an electrical connection via the high-speed board-to-board interface; the FPGA signal board converts the received video signals into module video protocol signals via the FPGA module and transmits them to the video adapter board.

[0080] The structure of the video adapter board is as follows Figure 6 As shown, two high-speed board-to-board interfaces and ten high-speed interfaces are placed on the top of the video adapter board, and two bottom power interfaces are placed on the bottom of the video adapter board.

[0081] The two high-speed board-to-board interfaces of the video adapter board are male or female ports that can be matched with the high-speed board-to-board interfaces on the FPGA signal board. The video adapter board receives the module video protocol signals sent by the FPGA signal board through the two high-speed board-to-board interfaces that match the FPGA signal board.

[0082] Ten high-speed interfaces are FFC / FPC connectors, located at the edge of the video adapter board, and connected to the module high-speed interfaces on the module adapter board via a flexible printed circuit board (FPC). The video adapter board receives module video protocol signals sent from the FPGA signal board through two high-speed board-to-board interfaces that interlock with the FPGA signal board. It then distributes the received module video protocol signals to the ten high-speed interfaces on the video adapter board. The high-speed interfaces on the video adapter board connect to the module high-speed interfaces on the module adapter board via the FPC, sending module video protocol signals to the module adapter board.

[0083] like Figure 7-12As shown, each power board is equipped with two top power interfaces, two bottom power interfaces, four adjustable power supplies, and eight protection circuits. Each adjustable power supply is electrically connected to one of the two protection circuits, creating two protected power supply circuits that are then electrically connected to the two bottom power interfaces. The bottom power interfaces are located at the bottom of the power board, and the top power interfaces are located at the top. Both the top and bottom power interfaces have 20 pins for power supply. The four adjustable power supplies are electrically connected to the bottom power interfaces via the protection circuits, forming a four-pin power supply group with the four adjustable power supplies and the four pins of the bottom power interfaces. The remaining 16 pins of the bottom power interfaces are electrically connected to the power supply pins of the top power interfaces on the same power board.

[0084] The top power interface of the power board is a male or female connector that interlocks with the bottom power interface of the power board, and the two bottom power interfaces are male or female connectors that interlock with the top power interface. n power boards can be stacked in a stacked structure by interlocking. In this embodiment, n≤5, that is, in this embodiment, each power board can be stacked with a maximum of 4 more power boards according to actual needs, forming an electrically connected stacked structure by interlocking.

[0085] In this embodiment, the power supply pins of the bottom power interface and the top power interface of the power board are defined as follows: Figure 10 As shown, the 20 power supply pins of both the bottom and top power interfaces are divided into 5 groups, with each group containing 4 power supply pins that are closely adjacent to each other.

[0086] Taking a power supply board as an example, the top power supply pin group and the bottom power supply pin group are electrically connected in a shifted manner, as shown in the specific connection method. Figure 11 As shown. The top power interface has 5 power supply pin groups: Top Power Pin Group 1, Top Power Pin Group 2, Top Power Pin Group 3, Top Power Pin Group 4, and Top Power Pin Group 5. The bottom power interface also has 20 power supply pins divided into 5 power supply pin groups: Bottom Power Pin Group 1, Bottom Power Pin Group 2, Bottom Power Pin Group 3, Bottom Power Pin Group 4, and Bottom Power Pin Group 5. Bottom Power Pin Group 1 consists of 4 power supply pins from the bottom power interface and 4 adjustable voltage power supplies. Top Power Pin Group 1 is connected to Bottom Power Pin Group 2, Top Power Pin Group 2 is connected to Bottom Power Pin Group 3, Top Power Pin Group 3 is connected to Bottom Power Pin Group 4, and Top Power Pin Group 4 is connected to Bottom Power Pin Group 5.

[0087] When adding a power board on top of an existing power board, the top power interface of the new power board is interlocked with the bottom power interface of the added upper-level power board, and the top power supply pin group 1 of the new power board is connected to the bottom power supply pin group 1 of the upper-level power board, thus achieving electrical connection between the two power boards. When adding a power board below an existing power board, the bottom power interface of the new power board is interlocked with the top power interface of the added lower-level power board, and the bottom power supply pin group 1 of the new power board is connected to the top power supply pin group 1 of the lower-level power board, thus achieving electrical connection between the two power boards. In this embodiment, this connection is repeated to achieve electrical connection of five power boards.

[0088] The connection method allows multiple identical power boards to be stacked, and multiple power supply pin groups can be generated in the bottom power interface of the bottom power board. This allows for the stacking of power boards of different numbers according to the actual power supply requirements of the display, providing a variable and flexible multi-channel power supply circuit.

[0089] In this embodiment, the power supply pins of the two top power interfaces are distributed in the power board as follows: Figure 12 As shown, the power supply pins are arranged symmetrically with the center of the power board as the symmetry point in the two top power interfaces. Power supply pins 1-nm and 2-nm are symmetrical with the center of the power board as the symmetry point, where m and n are positive integers and m≤4 and n≤5. The distribution of the power supply pins in the two bottom power interfaces on the power board is the same as that in the two top power interfaces. Figure 12 As shown, the arrangement is symmetrical with the center of the power board as the origin. This eliminates the need to determine the connection direction during stacking, simplifying the installation process.

[0090] In this embodiment, the two bottom power interfaces of the video adapter board are the same as the bottom power interfaces of the power board. The video adapter board is connected to the two top power interfaces of the power board through the two bottom power interfaces, forming a stacked structure of power board-video adapter board, as shown below. Figure 9 As shown. The top power interface of the aging base plate is the same as the top power interface of the power board. The power board can be clipped onto the aging base plate to form a stacked structure of aging base plate-power board-video adapter board.

[0091] The structure of the MCU control board is as follows Figure 13 As shown, the MCU module, two low-speed MCU interfaces, and a general-purpose interface are all placed on the top of the MCU control board, and the two low-speed MCU interfaces and the general-purpose interface are all connected to the MCU module.

[0092] The two MCU low-speed interfaces on the MCU control board are male or female connectors that interlock with the two MCU low-speed interfaces on the aging substrate. The MCU control board achieves electrical connection with the aging substrate through the MCU low-speed interfaces.

[0093] The MCU control board's general interface connects to the FPGA signal board's general interface, receiving control signals transmitted from the FPGA signal board. The MCU module converts the control signals into module control signals, which are then transmitted to ten module adapter boards via the aging baseboard connected to the MCU control board.

[0094] Module adapter board configuration as follows Figure 14 As shown, it includes a module interface, a low-speed module interface, a high-speed module interface, and a power module interface.

[0095] The low-speed module interface on the module adapter board is interlocked with the low-speed module interface on the aging substrate, enabling the module adapter board to receive module control signals transmitted from the MCU control board and transmit them to the module interface on the module adapter board. The module power interface on the module adapter board is interlocked with the module power interface on the aging substrate, enabling the module adapter board to receive power supply output from the power board and transmit it to the module interface on the module adapter board. The high-speed module interface on the module adapter board is connected to the video adapter board via a flexible printed circuit board, receiving module video protocol signals from the video adapter board and transmitting them to the module interface on the module adapter board. The module interface on the module adapter board is matched with the module interface of the display to be aged. The module adapter board connects to the display to be aged through its module interface and transmits the received module control signals, module video protocol signals, and power supply to the display to be aged. By using a module adapter board, when the display module interface is different or different displays are used, only the module adapter board needs to be designed, instead of redesigning the entire aging test device, which can save a lot of costs. Example 2

[0096] like Figure 15-17 As shown, this embodiment provides a display aging test system, which includes multiple display aging test devices as described in Embodiment 1. Adjacent display aging test devices in the system are electrically connected together via high-speed cables and power cables, forming a chain structure. One end of the chain structure is connected to a host computer via a high-speed cable and to an external power source via a power cable.

[0097] Specifically, the host computer communicates with the display aging test device 1 in the chain structure via high-speed cable 1, sending video and control signals. The display aging test device 1 transmits the received video and control signals to the display aging test device 2 via high-speed cable 2; similarly, the display aging test device 2 transmits the received video and control signals to the display aging test device 3 via high-speed cable 3, and so on, until the last display aging test device is reached.

[0098] The FPGA signal board of the display aging test device in the system is configured with two high-speed interfaces, such as... Figure 16 As shown, one FPGA signal board communicates with the host computer via a high-speed interface to receive video and control signals. It then connects to the FPGA signal board of another display aging test device via another high-speed interface to transmit video and control signals. The FPGA signal boards of adjacent display aging test devices are connected via high-speed interfaces, creating a cascaded structure of multiple FPGA signal boards. Communication between the host computer and one display aging test device enables communication with all display aging test devices, simplifying the control process and reducing the overall system complexity.

[0099] The aging test plates of the display aging test device in the system are electrically connected to each other through the aging power interface. For example... Figure 17 As shown, the aging power interfaces on multiple aging substrates are connected by power cables to form a topology. Only one power supply needs to be connected to one of the aging substrates to power all the aging substrates, eliminating the need for an external power supply for each device, thus reducing the use of external power supplies and lowering the overall system cost.

[0100] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0101] The above description is merely an embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of the claims of the present invention.

Claims

1. A display aging test apparatus, characterized in that, include: Aging baseboard, FPGA signal board and / or MCU control board, video adapter board, power board and module adapter board mounted on the aging baseboard; The module adapter board is electrically connected to the power board, FPGA signal board and / or MCU control board, and video adapter board; the module adapter board is connected to the display to be tested for aging, and the module adapter board transmits the received signals and power to the display to be tested for aging. The power board is equipped with a top power interface, a bottom power interface, and at least one voltage-adjustable power supply. The top power interface is a male or female connector, and the bottom power interface is a female or male connector that snaps into the top power interface; both the top and bottom power interfaces have z power supply pins, where z is a positive integer. The number of adjustable voltage power supplies is m. The m adjustable voltage power supplies are electrically connected to the bottom power interface to form a power supply pin group containing m power supply pins, and there are zm unused power supply pins of the bottom power interface, where m is a positive integer and m≤z. The power supply pins of the zm unused bottom power interfaces are electrically connected to the zm power supply pins of the top power interface on the same power board. The number of power boards is n. The n power boards can form an electrically connected stacked structure through interlocking to generate multiple power supplies to the module adapter board. n is a positive integer and n≤z / m. In the electrically connected stacked structure of the n power boards, the power supply pin group of each power board other than the bottom layer can be electrically connected to the top power interface of the power board below through interlocking, thereby achieving an electrical connection with the bottom power interface of the power board below, and finally an electrical connection with the bottom power interface of the bottom layer power board.

2. The display aging test apparatus according to claim 1, characterized in that: The FPGA signal board is equipped with a high-speed interface, through which it communicates with an external host computer to receive video and control signals; the aging base plate is equipped with an aging power interface, through which it is electrically connected to an external power supply.

3. The display aging test apparatus according to claim 2, characterized in that: The display aging test device includes an FPGA signal board and an MCU control board. The FPGA signal board transmits the received control signals to the MCU control board, and the MCU control board converts the received control signals into module control signals and transmits them to the module adapter board. The FPGA signal board converts the received video signals into module video protocol signals and transmits them to the video adapter board, and the video adapter board then transmits the module video protocol signals to the module adapter board.

4. The display aging test apparatus according to claim 3, characterized in that: The video adapter board is also equipped with a switch chip and / or a bridge chip, which converts the module video protocol signal into a video protocol signal that the module adapter board can receive before transmitting it to the module adapter board.

5. The display aging test apparatus according to claim 1, characterized in that: The aging base plate is equipped with the same top power interface as the power board, and the video adapter board is equipped with the same bottom power interface as the power board.

6. A display aging test system, characterized in that... This includes the display aging test apparatus according to any one of claims 1-5.

7. The display aging test system according to claim 6, characterized in that: Multiple display aging test devices are connected by high-speed cables and power cables to form a chain-structured display aging test system.

8. The display aging test system according to claim 7, characterized in that: The FPGA signal board is equipped with at least two high-speed interfaces. Each FPGA signal board is connected to the FPGA signal board of another display aging test device in the system through at least one high-speed interface to transmit video signals and control signals. One of the FPGA signal boards communicates with an external host computer through a high-speed interface to receive video signals and control signals.

9. The display aging test system according to claim 7, characterized in that: The aging substrate is equipped with at least two aging power interfaces. Each aging substrate is electrically connected to the aging substrate of another display aging test device in the system through at least one aging power interface; at least one aging substrate is electrically connected to an external power source through the aging power interface.

Images