Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and electronic equipment, and the manufacturing method comprises the steps: sequentially and alternately forming first insulating layers and conductive layers on a substrate, and obtaining a stacked structure; patterning etching is carried out on the stacked structure to form a plurality of grooves, the conductive layer forms a plurality of bit reading lines, second insulating layers and first insulating layers are sequentially formed in the grooves, and the first insulating layers in the grooves form insulating parts; removing at least part of the second insulating layer between the adjacent conductive layers; a writing bit line is formed on the conductive layer between the adjacent reading bit lines; a plurality of writing word line holes are formed in the two sides, distributed in the first direction, of the writing bit line, and semiconductor layers, gate insulation layers and writing word lines are sequentially formed in the writing word line holes; etching the first insulating layer in the groove to form a first through hole, and removing at least part of the semiconductor layer between the conductive layers through the first through hole; and forming a semiconductor layer, a storage node and a read word line of the read transistor. According to the manufacturing method provided by the embodiment of the invention, the parasitic MOS is removed by adopting a relatively simple process.

Description

Technical Field

[0001] The embodiments of the present application relate to but are not limited to the field of design and manufacturing of semiconductor devices, and in particular to a semiconductor device and a manufacturing method thereof and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products. Summary of the invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0005] The embodiments of the present application provide a semiconductor device and a manufacturing method thereof, and an electronic device. The manufacturing method can remove parasitic MOS by using a relatively simple process.

[0006] An embodiment of the present application provides a method for manufacturing a semiconductor device, the method comprising:

[0007] A first insulating layer and a conductive layer are alternately formed on a substrate in sequence to obtain a stacked structure; the stacked structure is patterned and etched to form a plurality of grooves extending in a direction perpendicular to the substrate, a plurality of read bit lines are formed on the conductive layer that are spaced apart in a first direction and extend in a second direction, a second insulating layer and a first insulating layer are sequentially formed in the grooves, and the first insulating layer in the grooves constitutes an insulating portion;

[0008] removing at least a portion of the second insulating layer located between adjacent conductive layers;

[0009] Forming a write bit line extending along the second direction in a conductive layer between the read bit lines adjacent to each other in the first direction;

[0010] A plurality of write word line holes are formed on both sides of the write bit line distributed along a first direction, and a semiconductor layer, a gate insulating layer and a write word line are sequentially formed in the write word line holes;

[0011] The first insulating layer in the trench is etched to form a first through hole, and at least a portion of the semiconductor layer between the conductive layers is removed through the first through hole; a semiconductor layer, a storage node and a read word line of a read transistor are formed.

[0012] Exemplarily, forming a plurality of grooves extending in a direction perpendicular to the substrate includes:

[0013] Two trenches spaced apart from each other are formed in a first direction between two adjacent read bit lines.

[0014] Exemplarily, the patterning and etching the stacked structure includes:

[0015] Performing a first patterning etching on the stacked structure along a direction toward the substrate to form a plurality of grooves penetrating each of the conductive layers in the stacked structure, wherein the plurality of grooves extend along the first direction and are spaced apart in the first direction and the second direction, and the first patterned conductive layer includes the write bit line and the read bit line;

[0016] Laterally etching the exposed first-patterned first insulating layer in the groove so that the groove in the first-patterned first insulating layer extends toward the first insulating layer;

[0017] A second insulating layer is deposited on the sidewall of the trench, and the trench is filled with the first insulating layer. The first insulating layer in the trench constitutes the insulating portion.

[0018] Exemplarily, the step of laterally etching the exposed first patterned first insulating layer in the trench comprises:

[0019] The orthographic projection of the trench in the first-patterned conductive layer on the substrate is made to fall within the range of the orthographic projection of the trench in the first-patterned first insulating layer on the substrate.

[0020] Exemplarily, the manufacturing method further includes: after the first patterning, performing the following process:

[0021] Performing a second patterning etching on the first patterned stack structure along a direction toward the substrate, and etching the conductive layer on both sides of the write bit line to form a row of write word line holes spaced apart along the second direction;

[0022] The first patterned conductive layer is laterally etched in the write word line hole to retain only the read bit line.

[0023] Exemplarily, etching the conductive layer on both sides of the write bit line to form a row of write word line holes spaced apart along the second direction comprises:

[0024] The write line hole disconnects the second insulating layer between different conductive layers, so that the sidewalls of the insulating portion between different conductive layers are exposed.

[0025] Exemplarily, forming a plurality of write word line holes on both sides of the write bit line distributed along the first direction, and sequentially forming a semiconductor layer, a gate insulating layer and a write word line in the write word line holes comprises:

[0026] Etching the conductive layer on both sides of the write bit line along a direction toward the substrate to form a write bit line hole extending into the substrate, so that the write bit line hole exposes the semiconductor layer on the side wall of the insulating portion;

[0027] Depositing a semiconductor layer and a gate insulating layer on the inner wall of the word line hole in sequence, so that the semiconductor layer on the inner wall of the word line hole is connected with the semiconductor layer on the side wall of the insulating portion;

[0028] The write word line extending in a direction perpendicular to the substrate is formed in the write word line hole.

[0029] Exemplarily, etching the first insulating layer in the trench to form a first through hole, and removing at least part of the semiconductor layer between the conductive layers through the first through hole comprises:

[0030] Etching on each of the insulating parts to form a first through hole penetrating the insulating part, wherein the first through hole exposes the semiconductor layer on the side wall of the insulating part;

[0031] At least a portion of the semiconductor layer between the conductive layers is removed through the first through hole.

[0032] Exemplarily, forming the read word line includes:

[0033] The read word line is formed between a first insulating layer of the insulating portion and the semiconductor layer.

[0034] Exemplarily, forming the read word line between the first insulating layer of the insulating portion and the semiconductor layer includes:

[0035] Filling the first insulating layer in the first through hole;

[0036] Etching the insulating portion and the second insulating layer along a direction toward the substrate to form an initial read word line hole, wherein the initial read word line hole exposes the first insulating layer between two adjacent conductive layers;

[0037] Transversely etching the first insulating layer located between two adjacent conductive layers in the initial read word line hole, so that the initial read word line hole is laterally extended toward the first insulating layer located between two adjacent conductive layers to form a second through hole;

[0038] A conductive layer is filled in the second through hole; a portion of the conductive layer located in the initial read word line hole is etched away to form a third through hole located in the initial read word line hole, wherein the side walls of the third through hole in the second direction all expose the conductive layer, and the conductive layer is used to form the read word line.

[0039] Exemplarily, the forming the read word line by using the conductive layer includes:

[0040] A certain thickness of the conductive layer is retained on the sidewall of the initial read word line hole, and the remaining conductive layer in the second through hole connects the conductive layers between two adjacent first insulating layers to form a read word line extending toward the substrate.

[0041] An embodiment of the present application provides a semiconductor device, the semiconductor device comprising: a substrate and a plurality of memory cells;

[0042] The memory cell comprises: a read transistor and a write transistor connected to each other, and a write word line perpendicular to the substrate; the write transistor comprises a first gate electrode, a first electrode, and a second electrode, the read transistor comprises a second gate electrode, a third electrode, and a fourth electrode, and the first gate electrode of the write transistor serves as a part of the write word line; the write word line comprises a bottom surface close to the substrate, a top surface away from the substrate, and a side surface between the top surface and the bottom surface; on the side surface of the write word line, a first gate insulating layer and a first semiconductor layer are sequentially provided in a direction away from the write word line, and the first semiconductor layer is disconnected in a direction perpendicular to the substrate; a second insulating layer is provided on a side of the first semiconductor layer away from the write line, and the second insulating layer is also disconnected in a direction perpendicular to the substrate.

[0043] Exemplarily, the first semiconductor layer covers a side surface of a first gate electrode of a corresponding write transistor, and the second insulating layer covers a side surface of a corresponding first semiconductor layer.

[0044] Exemplarily, the side surfaces of the first semiconductor layer are covered by a second insulating layer in the second direction, and the side surfaces of the first semiconductor layer are respectively connected to the write bit line and the storage node in the first direction; the first direction and the second direction are parallel to and intersect with the substrate, and the write bit line is parallel to the substrate and extends along the second direction.

[0045] Exemplarily, the first semiconductor layer has a top surface away from the substrate and a bottom surface close to the substrate, and the second insulating layer covers the top surface and the bottom surface of the first semiconductor layer.

[0046] Exemplarily, the top surface of the write bit line away from the substrate and the bottom surface close to the substrate are both covered by the third insulating layer and the third semiconductor layer, and the third insulating layer is disconnected from the first gate insulating layer, and the third semiconductor layer is disconnected from the first semiconductor layer.

[0047] Exemplarily, the storage node is parallel to the substrate and extends along the first direction, a side of the storage node away from the write word line is covered by a second gate insulating layer and a second semiconductor layer, and in a plane perpendicular to the substrate and parallel to the first direction, the storage node is surrounded and covered by the second gate insulating layer and the second semiconductor layer.

[0048] Exemplarily, the semiconductor device also includes a read bit line and a read word line, the read bit line extends along the second direction, and the read word line is perpendicular to the substrate; the second semiconductor layer is connected to the read bit line on a side away from the write word line; in a plane perpendicular to the substrate and parallel to the first direction, the circumference of the second semiconductor layer is connected to the read word line.

[0049] Exemplarily, a size of the read word line in the first direction is smaller than a size of the storage node in the first direction.

[0050] Exemplarily, in the second direction, there is a first insulating layer between two adjacent storage cells, the first insulating layer is in contact with the second insulating layer in the circumferential direction, and the first insulating layer and the second insulating layer are made of different materials.

[0051] Exemplarily, in the first direction, the second insulating layer is disconnected by the read word line; the first insulating layer contacts both of the two adjacent read word lines in the second direction, and the size of the portion of the first insulating layer contacting the read word line in the second direction is smaller than the size of the other portion in the second direction. The embodiment of the present application also provides an electronic device, comprising the semiconductor device provided in the embodiment of the present application.

[0052] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or understood by practicing the present application. The objects and advantages of the present application can be realized and obtained by the structures particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0054] Figure 1 A process flow chart of a method for manufacturing a semiconductor device provided for an exemplary embodiment of the present application;

[0055] Figure 2 A logic circuit diagram of a semiconductor device provided for an exemplary embodiment of the present application;

[0056] Figure 3AA schematic cross-sectional view parallel to the substrate of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application after a first insulating material is filled in a trench;

[0057] Figure 3B for Figure 3A A schematic cross-sectional view of the semiconductor device shown is perpendicular to the substrate in the a-a' direction;

[0058] Figure 3C for Figure 3A A schematic cross-sectional view of the device structure shown is perpendicular to the substrate in the bb' direction;

[0059] Figure 3D for Figure 3A A schematic cross-sectional view of the device structure shown is perpendicular to the substrate in the c-c' direction;

[0060] Figure 4A A schematic cross-sectional view parallel to a substrate of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application after forming a write line hole;

[0061] Figure 4B for Figure 4A A schematic cross-sectional view of the device structure shown is perpendicular to the substrate in the bb' direction;

[0062] Figure 4C for Figure 4A A schematic cross-sectional view of the device structure shown is perpendicular to the substrate in the c-c' direction;

[0063] Figure 5A A schematic cross-sectional view parallel to the substrate after a conductive layer is laterally etched in a write line hole in a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application;

[0064] Figure 5B for Figure 5A The device structure shown is a schematic cross-sectional view perpendicular to the substrate in the a-a' direction;

[0065] Figure 5C for Figure 5A A schematic cross-sectional view of the device structure shown is perpendicular to the substrate in the bb' direction;

[0066] Fig. 6A A schematic cross-sectional view parallel to the substrate of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application after a gate insulating layer is first deposited;

[0067] Figure 6B for Fig. 6A A schematic cross-sectional view of the semiconductor device shown is perpendicular to the substrate in the a-a' direction;

[0068] Figure 6C for Fig. 6A A schematic cross-sectional view of the device structure shown is perpendicular to the substrate in the bb' direction;

[0069] Fig.6D for Fig. 6A A schematic cross-sectional view of the device structure shown is perpendicular to the substrate in the c-c' direction;

[0070] Fig. 7A A schematic cross-sectional view parallel to the substrate after a conductive layer is filled in a gap between first insulating layers in a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application;

[0071] Figure 7B for Fig. 7A A schematic cross-sectional view of the semiconductor device shown is perpendicular to the substrate in the a-a' direction;

[0072] Figure 7C for Fig. 7A A schematic cross-sectional view of the device structure shown is perpendicular to the substrate in the bb' direction;

[0073] Fig.7D for Fig. 7A A schematic cross-sectional view of the device structure shown is perpendicular to the substrate in the c-c' direction;

[0074] Fig. 8A A schematic cross-sectional view parallel to a substrate of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application after forming a write word line;

[0075] Figure 8B for Fig. 8A A schematic cross-sectional view of the device structure shown is perpendicular to the substrate in the bb' direction;

[0076] Figure 8C for Fig. 8A A schematic cross-sectional view of the device structure shown is perpendicular to the substrate in the c-c' direction;

[0077] Fig.9A A schematic cross-sectional view parallel to the substrate of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application after removing a parasitic MOS;

[0078] Fig. 9B for Fig.9A A schematic cross-sectional view of the semiconductor device shown is perpendicular to the substrate in the a-a' direction;

[0079] Fig. 9C for Fig.9A A schematic cross-sectional view of the device structure shown is perpendicular to the substrate in the bb' direction;

[0080] Fig.9D for Fig.9A A schematic cross-sectional view of the device structure shown is perpendicular to the substrate in the c-c' direction;

[0081] Fig. 10A A schematic cross-sectional view parallel to the substrate of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application after a first insulating layer is filled in a through hole;

[0082] Fig. 10B for Fig. 10A A schematic cross-sectional view of the semiconductor device shown is perpendicular to the substrate in the a-a' direction;

[0083] Fig. 10C for Fig. 10A A schematic cross-sectional view of the device structure shown is perpendicular to the substrate in the bb' direction;

[0084] Fig. 10D for Fig. 10A A schematic cross-sectional view of the device structure shown is perpendicular to the substrate in the c-c' direction;

[0085] Fig.11A A schematic cross-sectional view parallel to a substrate of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application after forming a write line hole;

[0086] Fig. 11B for Fig.11A A schematic cross-sectional view of the semiconductor device shown is perpendicular to the substrate in the a-a' direction;

[0087] Fig. 11C for Fig.11A A schematic cross-sectional view of the device structure shown is perpendicular to the substrate in the bb' direction;

[0088] Fig. 12A A schematic cross-sectional view parallel to the substrate of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application after a conductive layer is filled in a second through hole;

[0089] Fig. 12B for Fig. 12A A schematic cross-sectional view of the semiconductor device shown is perpendicular to the substrate in the a-a' direction;

[0090] Fig. 12C for Fig. 12A A schematic cross-sectional view of the semiconductor device shown is perpendicular to the substrate in the bb' direction;

[0091] Fig.13A A schematic cross-sectional view parallel to a substrate of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application after forming a read word line;

[0092] Fig. 13B for Fig.13A A schematic cross-sectional view of the semiconductor device shown is perpendicular to the substrate in the a-a' direction;

[0093] Fig. 13C for Fig.13A A schematic cross-sectional view of the semiconductor device shown is perpendicular to the substrate in the bb' direction;

[0094] Fig.13D for Fig.13A The semiconductor device shown is a schematic cross-sectional view perpendicular to the substrate in the c-c' direction. DETAILED DESCRIPTION

[0095] In order to make the purpose, technical solution and advantages of the present application more clear, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other arbitrarily without conflict.

[0096] The embodiments of the present application are not necessarily limited to the dimensions shown in the drawings. The shapes and sizes of the components in the drawings belong to the preferred embodiments and may also be other shapes and sizes. In addition, the drawings schematically show ideal examples, and the embodiments of the present application are not limited to the shapes or values ​​shown in the drawings.

[0097] The ordinal numbers such as "first" and "second" in this application are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0098] In this application, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation on this application. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the disclosure and can be appropriately replaced according to the circumstances.

[0099] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0100] In this application, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this application, a channel region refers to a region where current mainly flows.

[0101] In the present application, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or a change in the direction of current during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present application, unless otherwise specified, the "source electrode" and the "drain electrode" may be interchanged.

[0102] In the present application, "electrical connection" or "connection" includes the situation where the components are connected together through an element with some electrical function, such as electrical signal connection (coupled connection, such as coupled to), or physical direct connection. There is no particular limitation on "element with some electrical function" as long as it can transfer electrical signals between the connected components. Examples of "element with some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0103] In this application, "parallel" means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.

[0104] In some embodiments of the present application, "film" and "layer" can be interchanged. For example, "conductive layer" can sometimes be replaced with "conductive film". Similarly, "insulating film" can sometimes be replaced with "insulating layer".

[0105] The term "A and B are arranged in the same layer" in this application means that A and B are distributed on the same horizontal plane, or although not on the same horizontal plane, they are in different areas of the same support surface. In one embodiment, A and B are formed simultaneously by subjecting the same film layer to the same patterning process.

[0106] In the embodiments of the present application, "A and B are an integrated structure" may mean that there is no obvious boundary interface such as a fault or gap in the microstructure. Generally, a film layer patterned on a film layer to form a connection is an integrated structure. For example, A and B use the same material to form a film layer and form a structure with a connection relationship at the same time through the same patterning process, or B is directly grown on A by epitaxy, and the materials of the two may not be exactly the same.

[0107] In this application, "pore size" refers to the average pore size measured at multiple locations.

[0108] In the present application, the spacing distribution can be understood as a separate, independent distribution, which can be achieved by a physical structural disconnection or an electrical characteristic disconnection. For example, the semiconductor layer between the effective channels corresponding to the two transistors is modified to achieve insulation to achieve electrical spacing between the two channels.

[0109] In order to overcome the problems of small capacitance and large leakage current in 3D DRAM, people have developed 3D DRAM with a 2T structure and a channel formed by metal oxide semiconductor materials such as indium gallium zinc oxide (IGZO). The 2T structure 3D DRAM based on metal oxide semiconductor materials is expected to achieve high-density storage and is a possible direction for the next generation of DRAM chips. However, this solution still faces some difficulties, such as the removal of parasitic metal oxide semiconductors (MOS). The presence of parasitic MOS makes it impossible to store information because different storage units are interconnected through the metal oxide semiconductor layer.

[0110] An embodiment of the present application provides a method for manufacturing a semiconductor device.

[0111] Figure 1 A process flow chart of a method for manufacturing a semiconductor device provided for an exemplary embodiment of the present application.

[0112] like Figure 1 As shown, the manufacturing method comprises:

[0113] A first insulating layer and a conductive layer are alternately formed on a substrate in sequence to obtain a stacked structure; the stacked structure is patterned and etched to form a plurality of grooves extending in a direction perpendicular to the substrate, a plurality of read bit lines are formed on the conductive layer that are spaced apart in a first direction and extend in a second direction, a second insulating layer and a first insulating layer are sequentially formed in the grooves, and the first insulating layer in the grooves constitutes an insulating portion;

[0114] removing at least a portion of the second insulating layer located between adjacent conductive layers;

[0115] Forming a write bit line extending along the second direction in a conductive layer between the read bit lines adjacent to each other in the first direction;

[0116] A plurality of write word line holes are formed on both sides of the write bit line distributed along a first direction, and a semiconductor layer, a gate insulating layer and a write word line are sequentially formed in the write word line holes;

[0117] The first insulating layer in the trench is etched to form a first through hole, and at least a portion of the semiconductor layer between the conductive layers is removed through the first through hole; a semiconductor layer, a storage node and a read word line of a read transistor are formed.

[0118] Exemplarily, forming a plurality of grooves extending in a direction perpendicular to the substrate includes:

[0119] Two trenches spaced apart from each other are formed in a first direction between two adjacent read bit lines.

[0120] Exemplarily, the patterning and etching the stacked structure includes:

[0121] Performing a first patterning etching on the stacked structure along a direction toward the substrate to form a plurality of grooves penetrating each of the conductive layers in the stacked structure, wherein the plurality of grooves extend along the first direction and are spaced apart in the first direction and the second direction, and the first patterned conductive layer includes the write bit line and the read bit line;

[0122] Laterally etching the exposed first-patterned first insulating layer in the groove so that the groove in the first-patterned first insulating layer extends toward the first insulating layer;

[0123] A second insulating layer is deposited on the sidewall of the trench, and the trench is filled with the first insulating layer. The first insulating layer in the trench constitutes the insulating portion.

[0124] Exemplarily, the step of laterally etching the exposed first patterned first insulating layer in the trench comprises:

[0125] The orthographic projection of the trench in the first-patterned conductive layer on the substrate is made to fall within the range of the orthographic projection of the trench in the first-patterned first insulating layer on the substrate.

[0126] Exemplarily, the manufacturing method further includes: after the first patterning, performing the following process:

[0127] Performing a second patterning etching on the first patterned stack structure along a direction toward the substrate, and etching the conductive layer on both sides of the write bit line to form a row of write word line holes spaced apart along the second direction;

[0128] The first patterned conductive layer is laterally etched in the write word line hole to retain only the read bit line.

[0129] Exemplarily, etching the conductive layer on both sides of the write bit line to form a row of write word line holes spaced apart along the second direction comprises:

[0130] The write line hole disconnects the second insulating layer between different conductive layers, so that the sidewalls of the insulating portion between different conductive layers are exposed.

[0131] Exemplarily, forming a plurality of write word line holes on both sides of the write bit line distributed along the first direction, and sequentially forming a semiconductor layer, a gate insulating layer and a write word line in the write word line holes comprises:

[0132] Etching the conductive layer on both sides of the write bit line along a direction toward the substrate to form a write bit line hole extending into the substrate, so that the write bit line hole exposes the semiconductor layer on the side wall of the insulating portion;

[0133] Depositing a semiconductor layer and a gate insulating layer on the inner wall of the word line hole in sequence, so that the semiconductor layer on the inner wall of the word line hole is connected with the semiconductor layer on the side wall of the insulating portion;

[0134] The write word line extending in a direction perpendicular to the substrate is formed in the write word line hole.

[0135] Exemplarily, etching the first insulating layer in the trench to form a first through hole, and removing at least part of the semiconductor layer between the conductive layers through the first through hole comprises:

[0136] Etching on each of the insulating parts to form a first through hole penetrating the insulating part, wherein the first through hole exposes the semiconductor layer on the side wall of the insulating part;

[0137] At least a portion of the semiconductor layer between the conductive layers is removed through the first through hole.

[0138] Exemplarily, forming the read word line includes:

[0139] The read word line is formed between a first insulating layer of the insulating portion and the semiconductor layer.

[0140] Exemplarily, forming the read word line between the first insulating layer of the insulating portion and the semiconductor layer includes:

[0141] Filling the first insulating layer in the first through hole;

[0142] Etching the insulating portion and the second insulating layer along a direction toward the substrate to form an initial read word line hole, wherein the initial read word line hole exposes the first insulating layer between two adjacent conductive layers;

[0143] Transversely etching the first insulating layer located between two adjacent conductive layers in the initial read word line hole, so that the initial read word line hole is laterally extended toward the first insulating layer located between two adjacent conductive layers to form a second through hole;

[0144] A conductive layer is filled in the second through hole; a portion of the conductive layer located in the initial read word line hole is etched away to form a third through hole located in the initial read word line hole, wherein the side walls of the third through hole in the second direction all expose the conductive layer, and the conductive layer is used to form the read word line.

[0145] Exemplarily, the forming the read word line by using the conductive layer includes:

[0146] A certain thickness of the conductive layer is retained on the sidewall of the initial read word line hole, and the remaining conductive layer in the second through hole connects the conductive layers between two adjacent first insulating layers to form a read word line extending toward the substrate.

[0147] The technical solution of the embodiment of the present application is further explained below through the manufacturing process of the semiconductor device of the exemplary embodiment. The "patterned etching" mentioned in this embodiment includes deposition of film layers, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which is a mature preparation process in the relevant technology. The "photolithography" process mentioned in this embodiment includes coating of film layers, mask exposure and development, which is a mature preparation process in the relevant technology. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, etc., coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here.

[0148] Figure 2 A logic circuit diagram of a semiconductor device provided for an exemplary embodiment of the present application; FIG. 3A to FIG. 13D Schematic cross-sectional views of a device structure parallel to a substrate and schematic cross-sectional views perpendicular to the substrate in different directions obtained in various steps of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application.

[0149] like Figures 2 to 13D As shown, in an exemplary embodiment, the method for manufacturing the semiconductor device may include the following processes.

[0150] S10: forming a stack structure consisting of alternately stacked first insulating layers 11 and conductive layers 13 on a substrate 10, and performing patterning etching on the stack structure, wherein the patterned conductive layer 13 includes a write bit line W_BL and a read bit line R_BL, such as FIG. 3A to FIG. 3D shown.

[0151] Exemplarily, step S10 may include:

[0152] S11: providing a substrate 10, and alternately depositing a first insulating layer 11 and a conductive layer 13 on the substrate 10 in sequence to obtain a stacked structure consisting of alternately stacked first insulating layers 11 and conductive layers 13;

[0153] S12: performing patterned etching on the stacked structure along a direction toward the substrate 10, forming a plurality of grooves penetrating each conductive layer 13 in the stacked structure, wherein the plurality of grooves extend along a first direction and are spaced apart in the first direction and a second direction, wherein the first direction intersects the second direction; and sidewalls of the grooves expose the patterned first insulating layer 11 and the patterned conductive layer 13;

[0154] The patterned conductive layer 13 includes a write bit line W_BL and a read bit line R_BL, the write bit line W_BL and the read bit line R_BL are spaced apart in the first direction, and both the write bit line W_BL and the read bit line R_BL extend along the second direction, and a row of grooves spaced apart in the second direction are provided between adjacent write bit lines W_BL and read bit lines R_BL;

[0155] S13: performing transverse etching on the exposed patterned first insulating layer 11 in the groove, so that the groove in the patterned first insulating layer 11 expands toward the patterned first insulating layer 11, that is, the orthographic projection of the groove in the patterned conductive layer 13 on the substrate 10 falls within the range of the orthographic projection of the groove in the patterned first insulating layer 11 on the substrate 10;

[0156] S14: depositing a second insulating layer 12 on the substrate 10 to cover the sidewalls of the expanded trench and the top surface of the patterned stack structure;

[0157] S15: Fill the expanded groove with the first insulating layer 11, which will simultaneously cover the top surface of the patterned stacking structure; use a chemical mechanical polishing (CMP) process to flatten the first insulating layer 11 on the top surface of the patterned stacking structure until the second insulating layer 12 on the top surface of the patterned stacking structure is exposed, and the first insulating layer 11 located in the groove forms an insulating portion 14.

[0158] For example, the first direction may be parallel to the substrate, the second direction may be parallel to the substrate, and the first direction and the second direction may be perpendicular to each other. For example, the first direction may be Figure 3A The a-a' direction or the b-b' direction shown in FIG. 1 , the second direction may be as follows Figure 3A c-c' direction shown.

[0159] Exemplarily, the groove obtained in step S13 may extend in a direction perpendicular to the substrate 10 , and the substrate 10 may be exposed.

[0160] In an exemplary embodiment of the present disclosure, the material of the first insulating layer may be a low-K dielectric material, that is, a dielectric material with a dielectric constant K<3.9, including but not limited to silicon oxides, such as silicon dioxide (SiO2) or other silicon-containing film layers.

[0161] Exemplarily, the material of the second insulating layer may be any one or more of silicon oxide (e.g., SiO2), silicon oxynitride (SiON), silicon nitride (SiN), and silicon carbonitride (SiCN), and the material of the second insulating layer is different from that of the first insulating layer, so that when one of the first insulating layer and the second insulating layer is subsequently etched and removed, the first insulating layer and the second insulating layer may have different etching rates, thereby removing the insulating layer that is desired to be removed. For example, in this embodiment, the material of the first insulating layer may be silicon oxide, and the material of the second insulating layer may be silicon nitride.

[0162] Exemplarily, the material of the conductive layer can be formed of conductive materials such as conductive metals, metal nitrides, metal oxides and polysilicon (Poly); the conductive materials include but are not limited to tungsten (W), cobalt (Co), titanium (Ti), titanium nitride (TiN), indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0163] Figure 3B The stacked structure shown includes four first insulating layers 11 and three conductive layers 13 , which is only an example. In other embodiments, the stacked structure may include more or fewer first insulating layers 11 and conductive layers 13 that are alternately arranged.

[0164] The substrate in the embodiment of the present application may be a supporting structure, such as a silicon substrate, or a supporting structure on which other film layers or functions or circuits are already distributed. The device involved in the inventive structure of the embodiment of the present application is arranged on the main surface of the supporting structure.

[0165] S20: etching the patterned stacked structure to form a write line hole K1 penetrating each patterned conductive layer 13, such as FIG. 4A to FIG. 4C As shown, Figure 4A The schematic cross-sectional view of the device structure shown in the a-a' direction perpendicular to the substrate is Figure 3B same.

[0166] Exemplarily, step S20 may include: etching the patterned stacked structure along the direction toward the substrate 10, forming a write line hole K1 between each two of the grooves on both sides of the write bit line W_BL, the write line hole K1 penetrates each patterned conductive layer 13 in a direction perpendicular to the substrate 10, and exposes the second insulating layer 12 located on the inner wall of the groove of the conductive layer 13, that is, the conductive layer 13 between two adjacent grooves is penetrated by the write line hole K1 in the second direction.

[0167] Exemplarily, the write line hole K1 may extend in a direction perpendicular to the substrate 10 and may expose the substrate 10 .

[0168] S30: The conductive layer 13 is laterally etched in the write word line hole K1, and only the conductive layer 13 used as the read bit line R_BL is retained. FIG. 5A to FIG. 5C As shown, Figure 5A The schematic cross-sectional view of the device structure shown in the c-c' direction perpendicular to the substrate is Figure 4C same.

[0169] like Figure 5A , Figure 5B and Figure 4C As shown, the insulating portion 14 extends toward the substrate 10 and extends along the first direction, a second insulating layer 12 is provided between an insulating portion 14 and a column of read bit lines R_BL located in a different layer, and there are only two insulating portions 14 spaced apart in the first direction between two adjacent columns of read bit lines R_BL in the first direction.

[0170] S40: sequentially depositing a semiconductor layer 20 and a gate insulating layer 30 on the exposed side walls of the first insulating layer 11, the second insulating layer 12 and the conductive layer 13, such as FIG. 6A to FIG. 6D shown.

[0171] S50: fill the gaps between the gate insulating layers 30 with the conductive layer 13, and re-form the write bit line W_BL at the position of the write bit line W_BL in step S10, such as 7A to 7D shown.

[0172] S60: The conductive layer 13, the gate insulating layer and the semiconductor layer in the write word line hole K1 are removed by etching, and the semiconductor layer 20 and the gate insulating layer 30 are sequentially deposited on the inner wall (including the side wall and the bottom wall) of the write word line hole K1 to form a write word line W_WL in the write word line hole K1. FIG. 8A to FIG. 8C As shown, Fig. 8AThe schematic cross-sectional view of the device structure shown in the a-a' direction perpendicular to the substrate is Figure 7B same.

[0173] Exemplarily, step S60 may include:

[0174] S61: etching and removing the conductive layer 13 in the word line hole K1, and vacating the word line hole K1; depositing the semiconductor layer 20 and the gate insulating layer 30 in sequence on the inner wall (including the side wall and the bottom wall) of the word line hole K1; since the word line hole K1 formed in step S20 penetrates the conductive layer 13 between two adjacent grooves in the second direction, that is, the word line hole K1 directly contacts the side wall of the groove, the semiconductor layer 20 deposited in step S60 will be connected with the semiconductor layer 20 located on the side wall of the groove;

[0175] S62: Fill the write word line hole K1 with a conductive material to obtain a write word line W_WL located in the write word line hole K1.

[0176] like Figure 8B and Figure 8C As shown, since the semiconductor layer 20 deposited in step S60 is continuously distributed on the side wall of the write word line hole K1 in the extension direction of the write word line hole K1, that is, the semiconductor layer 20 in the channel region 200 located between two adjacent first insulating layers 11 is connected to the semiconductor layer 20 in the parasitic MOS region 300 located between two adjacent conductive layers 13, a parasitic MOS tube (parasitic MOS for short) is formed.

[0177] S70: Remove parasitic MOS.

[0178] Exemplarily, step S70 may include: etching the first insulating layer 11 on the outer wall of the write word line hole K1 along the direction toward the substrate 10 to form a first through hole K2 that penetrates the first insulating layer 11 between two adjacent write word line holes K1 along the second direction and extends to the first insulating layer 11 between two adjacent conductive layers, and allowing the first through hole K2 to penetrate the first insulating layer 11 between two adjacent write word line holes K1 in the second direction, so that the side wall of the first through hole K2 exposes the semiconductor layer 20 on the side wall of the write word line hole K1 in the first insulating layer 11, that is, the semiconductor layer 20 located in the parasitic MOS region 300; etching and removing the semiconductor layer 20 in the parasitic MOS region 300, such as 9A to 9D shown.

[0179] For example, Fig.9A and Fig. 9B As shown, the first through hole K2 may expose the second insulating layer on the side wall of the write bit line W_BL.

[0180] S80 : using the conductive layer 13 to connect the conductive layers 13 between the write bit line W_BL and the read bit line R_BL to form a read word line R_WL extending in a direction perpendicular to the substrate 10 .

[0181] Exemplarily, step S80 may include:

[0182] S81: Fill the first through hole K2 with the first insulating layer 11. FIG. 10A to FIG. 10D As shown;

[0183] S82: etching the first insulating layer 11 and the second insulating layer 12 between two write word lines W_WL adjacent to each other along the second direction along the direction toward the substrate 10 to form an initial read word line hole, wherein the initial read word line hole exposes the first insulating layer 11 between two adjacent conductive layers 13;

[0184] S83: Laterally etching the first insulating layer 11 between two adjacent conductive layers 13 in the initial read word line hole, so that the initial read word line hole extends laterally toward the first insulating layer 11 between two adjacent conductive layers 13, forming a second through hole K3, such as FIG. 11A to FIG. 11C As shown;

[0185] like Fig. 11B As shown, the second through hole K3 at aa' penetrates the entire first insulating layer 11; Fig. 11C As shown, the second through hole K3 located between two adjacent conductive layers 13 only penetrates the first insulating layer 11 between the two adjacent conductive layers 13 , but is disconnected at the conductive layer 13 .

[0186] S84: Fill the second through hole K3 with the conductive layer 13. Fig. 12A and Fig. 12C As shown;

[0187] S85: etching and removing a part of the conductive layer 13 in the initial read word line hole to form a second through hole in the initial read word line hole, the side walls of the second through hole in the second direction all expose the conductive layer 13, that is, the length of the second through hole in the second direction is less than the length of the initial read word line hole in the second direction, so that a certain thickness of the conductive layer 13 is retained on the side walls of the initial read word line hole, and the remaining conductive layer 13 in the second through hole K3 connects the conductive layers 13 between the write bit line W_BL and the read bit line R_BL to form a read word line R_WL extending in a direction perpendicular to the substrate 10; the area between two adjacent first insulating layers 11 in the read word line R_WL is used as a storage node SN (Storagegate);

[0188] S86: Fill the second through hole with insulating material, such as FIG. 13A to FIG. 13DIn the present application, the semiconductor layer can be understood as a semiconductor material, and its shape and structure are not emphasized here, but only its function is emphasized.

[0189] Exemplarily, the material of the semiconductor layer may be a material such as silicon or polysilicon with a band gap smaller than 1.65 eV, or may be a wide band gap material, such as a metal oxide material with a band gap larger than 1.65 eV.

[0190] For example, the material of the metal oxide semiconductor layer or channel may include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may contain compounds of other elements, such as N, Si, etc., and may contain other small amounts of doping elements.

[0191] In some embodiments, the material of the metal oxide semiconductor layer or the channel may include any one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InW O, IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO) and other materials. As long as the leakage current of the transistor can meet the requirements, the specific adjustment can be made according to the actual situation.

[0192] These materials have a wide band gap and a low leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A, thereby improving the working performance of dynamic memory.

[0193] The material of the metal oxide semiconductor layer or channel only emphasizes the element type of the material, and does not emphasize the atomic proportion in the material and the film quality of the material.

[0194] Exemplarily, the materials of the read bit line and the write bit line can be selected from any one or more of other metal materials with similar properties such as tungsten, molybdenum, cobalt, etc. The bit line can be a single-layer or multi-layer structure, for example, a multi-layer structure formed of titanium (Ti), titanium nitride (TiN) and tungsten (W).

[0195] In an exemplary embodiment of the present application, the conductive material of the read word line and the write word line may be any one or more of the following different types of materials:

[0196] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;

[0197] It can also be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as metal oxide materials with high conductivity such as indium tin oxide ITO, indium zinc oxide IZO, indium oxide InO, etc.; for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), etc.;

[0198] Of course, it can also be polysilicon material; it can also be conductive material doped semiconductor material, such as conductively doped silicon, conductively doped germanium, conductively doped silicon germanium, etc.; other materials that embody conductivity, etc.

[0199] Exemplarily, the material of the gate insulating layer may include one or more layers of Low-K and / or High-K dielectric materials, or include two or more regions with different dielectric constants K. The characteristics of the gate insulating layer of the present application will be exemplarily described below.

[0200] Low-K materials, such as silicon oxide.

[0201] The present application also provides a semiconductor device, such as Figure 2 and FIG. 13A to FIG. 13D As shown, the semiconductor device comprises: a substrate 10 and a plurality of memory cells;

[0202] The storage unit includes: a read transistor Tr_r and a write transistor Tr_w connected to each other, and a write word line W_WL perpendicular to the substrate 10; the write transistor Tr_w includes a first gate electrode G1, a first electrode 41 and a second electrode 42, the read transistor Tr_r includes a second gate electrode G2, a third electrode 43 and a fourth electrode 44, and the first gate electrode G1 of the write transistor Tr_w serves as a part of the write word line W_WL; the write word line W_WL includes a bottom surface close to the substrate 10 and a top surface away from the substrate 10, and a side surface between the top surface and the bottom surface; on the side surface of the write word line W_WL, a first gate insulating layer 31 and a first semiconductor layer 21 are sequentially provided in a direction away from the write word line W_WL, and the first semiconductor layer 21 is disconnected in a direction perpendicular to the substrate 10; a second insulating layer 12 is provided on a side of the first semiconductor layer 21 away from the write word line W_WL, and the second insulating layer 12 is also disconnected in a direction perpendicular to the substrate 10.

[0203] Exemplarily, the first semiconductor layer 21 covers the side of the first gate electrode G1 of the corresponding write transistor Tr_w, and the second insulating layer 12 covers the side of the corresponding first semiconductor layer 21. The second insulating layer 12 is provided in a direction perpendicular to the substrate 10, and the channel of the write transistor Tr_w can be protected when the parasitic MOS between the write transistors Tr_w of different layers is etched and removed.

[0204] Exemplarily, the first gate insulating layer 31 and the first semiconductor layer 21 may completely surround the write word line W_WL or may partially surround the write word line W_WL.

[0205] Exemplarily, the side surface of the first semiconductor layer 21 is covered by the second insulating layer 12 in the second direction, and the side surface of the first semiconductor layer 21 is respectively connected to the write bit line W_BL and the storage node SN in the first direction; the first direction and the second direction are parallel to the substrate 10 and intersect, and the write bit line W_BL is parallel to the substrate 10 and extends along the second direction. When the parasitic MOS between the write transistors Tr_w of different layers is etched and removed, the side surface of the first semiconductor layer 21 is protected by the second insulating layer 12 in the second direction, and is respectively protected by the write bit line W_BL and the storage node SN in the first direction.

[0206] Exemplarily, the first semiconductor layer 21 has a top surface away from the substrate 10 and a bottom surface close to the substrate 10, and the second insulating layer 12 covers the top and bottom surfaces of the first semiconductor layer 21. Covering the top and bottom surfaces of the first semiconductor layer 21 with the second insulating layer 12 can enhance the protection of the top and bottom surfaces of the first semiconductor layer 21.

[0207] Exemplarily, the storage node SN is parallel to the substrate 10 and extends along the first direction, the side of the storage node SN away from the write word line W_WL is covered by the second gate insulation layer 32 and the second semiconductor layer 22, and in a plane perpendicular to the substrate 10 and parallel to the first direction, the storage node SN is surrounded and covered by the second gate insulation layer 32 and the second semiconductor layer 22.

[0208] like Fig.13A As shown, the first semiconductor layer 21 and the second semiconductor layer 22 can be connected together. At this time, the write word line W_WL can be used as a switch. When current enters the storage unit from the write bit line W_BL, if the write word line W_WL switch is turned on, the first semiconductor layer 21 and the second semiconductor layer 22 are turned on, and the current enters the storage node SN through the first semiconductor layer 21 and the second semiconductor layer 22; if the word line W_WL switch is turned off, the first semiconductor layer 21 and the second semiconductor layer 22 are not turned on, and the charge is stored in the storage node SN.

[0209] Exemplarily, the semiconductor device further includes a read bit line R_BL and a read word line R_WL, the read bit line R_BL extends along the second direction, and the read word line R_WL is perpendicular to the substrate 10; the side of the second semiconductor layer 22 away from the write word line W_WL is connected to the read bit line R_BL; in a plane perpendicular to the substrate 10 and parallel to the first direction, the circumference of the second semiconductor layer 22 is connected to the read word line R_WL. The second semiconductor layer 22 is connected to the read word line R_WL in the circumference, which can increase the contact area with the read word line R_WL and reduce the contact resistance.

[0210] The storage node SN is arranged parallel to the substrate 10 and is respectively connected to the write word line W_WL and the read bit line R_BL in a first direction, so as to remove the parasitic MOS in the direction parallel to the substrate 10 .

[0211] Exemplarily, the size of the read word line R_WL in the first direction is smaller than the size of the storage node SN in the first direction. If the size of the read word line R_WL in the first direction is larger than the size of the storage node SN in the first direction, the read word line R_WL and the read bit line R_BL will be short-circuited.

[0212] Exemplarily, the top surface of the write bit line W_BL away from the substrate 10 and the bottom surface close to the substrate 10 are covered by the third insulating layer 15 and the third semiconductor layer 23, and the third insulating layer 15 is disconnected from the first gate insulating layer 31, and the third semiconductor layer 23 is disconnected from the first semiconductor layer 21. The disconnection of the third semiconductor layer 23 from the first semiconductor layer 21 can avoid the short circuit of the adjacent write transistor Tr_w.

[0213] Exemplarily, in the second direction, there is a first insulating layer 11 between two adjacent storage cells, the first insulating layer 11 is in contact with the second insulating layer 12 in the circumferential direction, and the materials of the first insulating layer 11 and the second insulating layer 12 are different. By arranging the first insulating layer 11 and the second insulating layer 12 between adjacent write word lines W_WL, the etching selectivity of the two is different, so that when the parasitic MOS between the write transistors Tr_w of different layers is etched and removed, the channel of the write transistor Tr_w can be protected by the second insulating layer 12.

[0214] Exemplarily, in the first direction, the second insulating layer 12 is disconnected by the read word line R_WL; the first insulating layer 11 contacts both of the two read word lines R_WL adjacent to each other in the second direction, and the size of the portion of the first insulating layer 11 contacting the read word line R_WL in the second direction is smaller than the size of the other portion in the second direction. The portion of the first insulating layer contacting the read word line R_WL is retracted to provide space for the read word line R_WL, so that the read word line R_WL can also contact the second semiconductor layer 22 in the circumferential direction, thereby reducing the contact resistance.

[0215] The semiconductor device can be obtained by the manufacturing method provided in the above embodiment of the present application.

[0216] The semiconductor layer spacing arrangement of transistors in at least some adjacent layers of the semiconductor device provided in the embodiment of the present application can reduce or eliminate parasitic MOS between at least some layers and improve the stability of the device.

[0217] In an exemplary embodiment of the present application, the semiconductor layers of the transistors in different layers are spaced apart in a direction perpendicular to the substrate, that is, the semiconductor layers of the transistors in all adjacent layers are spaced apart in a direction perpendicular to the substrate, thereby eliminating parasitic MOS capacitance between all adjacent layers and improving device stability.

[0218] Exemplarily, the semiconductor device may be a 3D memory, such as a 3D DRAM or other memory. The 3D memory may be a 2TOC structure.

[0219] An embodiment of the present application further provides an electronic device, which includes the semiconductor device provided in the above embodiment of the present application.

[0220] In an exemplary embodiment of the present application, the electronic device may be: a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply, etc. The storage device may include a memory in a computer, etc., which is not limited here.

[0221] Although the embodiments disclosed in this application are as above, the contents described are only embodiments adopted to facilitate understanding of this application and are not intended to limit this application. Any technician in the field to which this application belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in this application, but the scope of protection of this application shall still be based on the scope defined in the attached claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Alternatingly forming a first insulating layer and a conductive layer on a substrate in sequence to obtain a stacked structure; Performing pattern etching on the stacked structure to form a plurality of grooves extending in a direction perpendicular to the substrate, forming a plurality of read bit lines spaced apart in a first direction and extending in a second direction on the conductive layer, and sequentially forming a second insulating layer and a first insulating layer in the grooves, wherein the first insulating layer in the grooves constitutes an insulating portion; removing at least a portion of the second insulating layer located between adjacent conductive layers; Forming a write bit line extending along the second direction in a conductive layer between the read bit lines adjacent to each other in the first direction; A plurality of write word line holes are formed on both sides of the write bit line distributed along a first direction, and a semiconductor layer, a gate insulating layer and a write word line are sequentially formed in the write word line holes; The first insulating layer in the trench is etched to form a first through hole, and at least a portion of the semiconductor layer between the conductive layers is removed through the first through hole; a semiconductor layer, a storage node and a read word line of a read transistor are formed.

2. The manufacturing method according to claim 1, characterized in that: The forming of a plurality of grooves extending in a direction perpendicular to the substrate comprises: Two trenches spaced apart from each other are formed in a first direction between two adjacent read bit lines.

3. The manufacturing method according to claim 1, characterized in that: The patterning and etching of the stacked structure comprises: Performing a first patterning etching on the stacked structure along a direction toward the substrate to form a plurality of grooves penetrating each of the conductive layers in the stacked structure, wherein the plurality of grooves extend along the first direction and are spaced apart in the first direction and the second direction, and the first patterned conductive layer includes the write bit line and the read bit line; Laterally etching the exposed first-patterned first insulating layer in the groove so that the groove in the first-patterned first insulating layer extends toward the first insulating layer; A second insulating layer is deposited on the sidewall of the trench, and the trench is filled with the first insulating layer. The first insulating layer in the trench constitutes the insulating portion.

4. The manufacturing method according to claim 3, characterized in that: The step of laterally etching the exposed first patterned first insulating layer in the groove comprises: The orthographic projection of the trench in the first-patterned conductive layer on the substrate is made to fall within the range of the orthographic projection of the trench in the first-patterned first insulating layer on the substrate.

5. The manufacturing method according to claim 3, characterized in that: Also includes: After the first patterning, the following process is performed: Performing a second patterning etching on the first patterned stack structure along a direction toward the substrate, and etching the conductive layer on both sides of the write bit line to form a row of write word line holes spaced apart along the second direction; The first patterned conductive layer is laterally etched in the write word line hole to retain only the read bit line.

6. The manufacturing method according to claim 5, characterized in that: The etching of the conductive layer on both sides of the write bit line to form a row of write word line holes spaced apart along the second direction comprises: The write line hole disconnects the second insulating layer between different conductive layers, so that the sidewalls of the insulating portion between different conductive layers are exposed.

7. The manufacturing method according to any one of claims 1 to 6, characterized in that: The step of forming a plurality of write word line holes on both sides of the write bit line distributed along the first direction, and sequentially forming a semiconductor layer, a gate insulating layer and a write word line in the write word line holes comprises: Etching the conductive layer on both sides of the write bit line along a direction toward the substrate to form a write bit line hole extending into the substrate, so that the write bit line hole exposes the semiconductor layer on the side wall of the insulating portion; Depositing a semiconductor layer and a gate insulating layer on the inner wall of the word line hole in sequence, so that the semiconductor layer on the inner wall of the word line hole is connected with the semiconductor layer on the side wall of the insulating portion; The write word line extending in a direction perpendicular to the substrate is formed in the write word line hole.

8. The manufacturing method according to any one of claims 1 to 6, characterized in that: The etching of the first insulating layer in the trench to form a first through hole, and removing at least a portion of the semiconductor layer between the conductive layers through the first through hole comprises: Etching on each of the insulating parts to form a first through hole penetrating the insulating part, wherein the first through hole exposes the semiconductor layer on the side wall of the insulating part; At least a portion of the semiconductor layer between the conductive layers is removed through the first through hole.

9. The manufacturing method according to any one of claims 1 to 6, characterized in that: Forming the read word line includes: The read word line is formed between a first insulating layer of the insulating portion and the semiconductor layer.

10. The manufacturing method according to claim 9, characterized in that: The forming of the read word line between the first insulating layer of the insulating portion and the semiconductor layer comprises: Filling the first insulating layer in the first through hole; Etching the insulating portion and the second insulating layer along a direction toward the substrate to form an initial read word line hole, wherein the initial read word line hole exposes the first insulating layer between two adjacent conductive layers; Transversely etching the first insulating layer located between two adjacent conductive layers in the initial read word line hole, so that the initial read word line hole is laterally extended toward the first insulating layer located between two adjacent conductive layers to form a second through hole; A conductive layer is filled in the second through hole; a portion of the conductive layer located in the initial read word line hole is etched away to form a third through hole located in the initial read word line hole, wherein the side walls of the third through hole in the second direction all expose the conductive layer, and the conductive layer is used to form the read word line.

11. The manufacturing method according to claim 10, characterized in that: The forming the read word line by using the conductive layer comprises: A certain thickness of the conductive layer is retained on the sidewall of the initial read word line hole, and the remaining conductive layer in the second through hole connects the conductive layers between two adjacent first insulating layers to form a read word line extending toward the substrate.

12. A semiconductor device, characterized in that: include: a substrate and a plurality of memory cells; The memory cell comprises: a read transistor and a write transistor connected to each other, and a write word line perpendicular to the substrate; the write transistor comprises a first gate electrode, a first electrode, and a second electrode, the read transistor comprises a second gate electrode, a third electrode, and a fourth electrode, and the first gate electrode of the write transistor serves as a part of the write word line; the write word line comprises a bottom surface close to the substrate, a top surface away from the substrate, and a side surface between the top surface and the bottom surface; on the side surface of the write word line, a first gate insulating layer and a first semiconductor layer are sequentially provided in a direction away from the write word line, and the first semiconductor layer is disconnected in a direction perpendicular to the substrate; a second insulating layer is provided on a side of the first semiconductor layer away from the write line, and the second insulating layer is also disconnected in a direction perpendicular to the substrate.

13. The semiconductor device according to claim 12, characterized in that The first semiconductor layer covers a side surface of a first gate electrode of a corresponding write transistor, and the second insulating layer covers a side surface of a corresponding first semiconductor layer.

14. The semiconductor device according to claim 12, wherein: The side surfaces of the first semiconductor layer are covered by the second insulating layer in the second direction, and the side surfaces of the first semiconductor layer are respectively connected to the write bit line and the storage node in the first direction; the first direction and the second direction are parallel to and intersect with the substrate, and the write bit line is parallel to the substrate and extends along the second direction.

15. The semiconductor device according to claim 14, characterized in that The first semiconductor layer has a top surface far away from the substrate and a bottom surface close to the substrate, and the second insulating layer covers the top surface and the bottom surface of the first semiconductor layer.

16. The semiconductor device according to claim 14, characterized in that The storage node is parallel to the substrate and extends along the first direction, and the side of the storage node away from the write word line is covered by the second gate insulation layer and the second semiconductor layer. In a plane perpendicular to the substrate and parallel to the first direction, the storage node is surrounded and covered by the second gate insulation layer and the second semiconductor layer.

17. The semiconductor device according to claim 16, characterized in that It also includes a read bit line and a read word line, wherein the read bit line extends along the second direction and the read word line is perpendicular to the substrate; and a side of the second semiconductor layer away from the write word line is connected to the read bit line; In a plane perpendicular to the substrate and parallel to the first direction, a circumference of the second semiconductor layer is connected to the read word line.

18. The semiconductor device according to claim 17, characterized in that The size of the read word line in the first direction is smaller than the size of the storage node in the first direction.

19. The semiconductor device according to claim 14, characterized in that The top surface of the write bit line away from the substrate and the bottom surface close to the substrate are both covered by the third insulating layer and the third semiconductor layer, and the third insulating layer is disconnected from the first gate insulating layer, and the third semiconductor layer is disconnected from the first semiconductor layer.

20. The semiconductor device according to claim 18, wherein: In the second direction, there is a first insulating layer between two adjacent storage units, the first insulating layer is in contact with the second insulating layer in the circumferential direction, and the first insulating layer and the second insulating layer are made of different materials.

21. The semiconductor device according to claim 20, characterized in that In the first direction, the second insulating layer is disconnected by the read word line; the first insulating layer contacts both of the two adjacent read word lines in the second direction, and the size of the portion of the first insulating layer contacting the read word line in the second direction is smaller than the size of the other portion in the second direction.

22. An electronic device, characterized in that: Comprising the semiconductor device according to any one of claims 12 to 21.

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