Semiconductor device and method of manufacturing the same, electronic device

Abstract

A semiconductor device and a manufacturing method thereof, and an electronic device, the manufacturing method comprising: sequentially and alternately forming a first insulating layer and a conductive layer on a substrate to obtain a stack structure; performing patterned etching on the stack structure to form a plurality of trenches, the conductive layer forming a plurality of read bit lines, sequentially forming a second insulating layer and a first insulating layer in the trenches, the first insulating layer in the trenches constituting an insulating portion; removing at least part of the second insulating layer between adjacent conductive layers; forming a write bit line in the conductive layer between adjacent read bit lines; forming a plurality of write word line holes on both sides of the write bit line along a first direction, sequentially forming a semiconductor layer, a gate insulating layer and a write word line in the write word line hole; etching the first insulating layer in the trench to form a first via hole, removing at least part of the semiconductor layer between the conductive layers through the first via hole; and forming a semiconductor layer of a read transistor, a storage node and a read word line. The manufacturing method of the embodiment of the application removes a parasitic MOS by using a simpler process.

Description

Technical Field

[0001] The embodiments of this application relate to, but are not limited to, the design and manufacture of semiconductor devices, and particularly to a semiconductor device, a method for manufacturing the same, and an electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0005] This application provides a semiconductor device and its manufacturing method, as well as an electronic device. The manufacturing method can use a relatively simple process to remove parasitic MOS.

[0006] This application provides a method for manufacturing a semiconductor device, the method comprising:

[0007] A first insulating layer and a conductive layer are alternately formed on a substrate to obtain a stacked structure; the stacked structure is patterned and etched to form multiple trenches extending in a direction perpendicular to the substrate; multiple read lines are formed on the conductive layer at intervals in a first direction and extending in a second direction; a second insulating layer and a first insulating layer are formed in sequence in the trenches; the first insulating layer in the trenches constitutes an insulating portion.

[0008] Remove at least a portion of the second insulating layer located between adjacent conductive layers;

[0009] A write bit line extending along the second direction is formed in a conductive layer between the adjacent read bit lines in the first direction;

[0010] Multiple write word line holes are formed on both sides of the write bit line distributed along the first direction, and a semiconductor layer, a gate insulating layer and a write word line are sequentially formed in the write word line holes;

[0011] The first insulating layer in the trench is etched to form a first via, and at least a portion of the semiconductor layer between the conductive layers is removed through the first via; a semiconductor layer, a memory node, and a read word line are formed for the read transistor.

[0012] For example, forming a plurality of trenches extending in a direction perpendicular to the substrate includes:

[0013] Two grooves are formed at intervals in a first direction between two adjacent read lines.

[0014] For example, the patterning etching of the stacked structure includes:

[0015] The stacked structure is first patterned by etching along the direction toward the substrate, forming a plurality of trenches through each of the conductive layers in the stacked structure. The plurality of trenches extend along the first direction and are spaced apart in the first and second directions. The first patterned conductive layer includes the write bit line and the read bit line.

[0016] Laterally etch the exposed first patterned first insulating layer in the trench, so that the trench in the first patterned first insulating layer extends toward the first insulating layer.

[0017] A second insulating layer is deposited on the sidewall of the trench, and the first insulating layer is filled into the trench, wherein the first insulating layer located in the trench constitutes the insulating portion.

[0018] Exemplarily, the lateral etching of the exposed first patterned insulating layer within the trench includes:

[0019] The orthographic projection of the trench in the first patterned conductive layer onto the substrate falls within the range of the orthographic projection of the trench in the first patterned insulating layer onto the substrate.

[0020] Exemplarily, the manufacturing method further includes, after the first patterning, performing the following process,

[0021] Along the direction toward the substrate, the first patterned stacked structure is patterned a second time, and a row of write line holes spaced apart along the second direction are etched on the conductive layers on both sides of the write bit line.

[0022] The conductive layer, which was first patterned, is etched laterally inside the writing line hole, leaving only the reading line.

[0023] For example, etching a row of write line holes spaced apart along the second direction on the conductive layers on both sides of the write bit line includes:

[0024] The writing line hole breaks the second insulating layer between different conductive layers, exposing the sidewall of the insulating portion located between the different conductive layers.

[0025] For example, forming a plurality of write word line holes on both sides of the write bit line distributed along the first direction, and sequentially forming a semiconductor layer, a gate insulating layer, and a write word line within the write word line holes includes:

[0026] The conductive layers on both sides of the write bit line are etched along the direction toward the substrate to form write bit hole extending into the substrate, so that the write bit hole exposes the semiconductor layer on the sidewall of the insulating portion;

[0027] A semiconductor layer and a gate insulating layer are sequentially deposited on the inner wall of the writing line hole, so that the semiconductor layer on the inner wall of the writing line hole is connected to the semiconductor layer on the side wall of the insulating portion;

[0028] The writing line is formed within the writing line hole, extending in a direction perpendicular to the substrate.

[0029] For example, etching the first insulating layer within the trench to form a first via, and removing at least a portion of the semiconductor layer between the conductive layers through the first via, includes:

[0030] A first through-hole is etched into each of the insulating portions, and the first through-hole exposes the semiconductor layer on the sidewall of the insulating portion;

[0031] At least a portion of the semiconductor layer between the conductive layers is removed through the first via.

[0032] For example, forming the reading line includes:

[0033] The reading line is formed between the first insulating layer of the insulating portion and the semiconductor layer.

[0034] For example, forming the read line between the first insulating layer and the semiconductor layer of the insulating portion includes:

[0035] The first insulating layer is filled into the first through hole;

[0036] The insulating portion and the second insulating layer are etched along the direction toward the substrate to form an initial readout hole, which exposes the first insulating layer located between two adjacent conductive layers.

[0037] The first insulating layer located between two adjacent conductive layers is laterally etched within the initial readout line hole, causing the initial readout line hole to extend laterally toward the first insulating layer located between two adjacent conductive layers, forming a second through hole;

[0038] A conductive layer is filled into the second through hole; a portion of the conductive layer located in the initial read line hole is etched away to form a third through hole located in the initial read line hole, wherein the sidewalls of the third through hole in the second direction expose the conductive layer, and the read line is formed using the conductive layer.

[0039] For example, forming the readout line using the conductive layer includes:

[0040] A conductive layer of a certain thickness is retained on the sidewall of the initial reading line hole, and the remaining conductive layer in the second through hole connects the conductive layers between two adjacent first insulating layers to form a reading line extending toward the substrate.

[0041] This application provides a semiconductor device, which includes a substrate and a plurality of memory cells;

[0042] The memory cell includes: a read transistor and a write transistor interconnected, and a write word line perpendicular to the substrate; the write transistor includes a first gate electrode, a first electrode, and a second electrode, the read transistor includes a second gate electrode, a third electrode, and a fourth electrode, and the first gate electrode of the write transistor is part of the write word line; the write word line includes a bottom surface near the substrate and a top surface away from the substrate, and a side surface between the top surface and the bottom surface; on the side surface of the write word line, a first gate insulating layer and a first semiconductor layer are sequentially provided in a direction away from the write word line, the first semiconductor layer being broken in a direction perpendicular to the substrate; a second insulating layer is provided on the side of the first semiconductor layer away from the write word line, the second insulating layer also being broken in a direction perpendicular to the substrate.

[0043] For example, the first semiconductor layer covers the side of the first gate electrode of the corresponding write transistor, and the second insulating layer covers the side of the corresponding first semiconductor layer.

[0044] For example, the side of the first semiconductor layer is covered by a second insulating layer in the second direction, and the side of the first semiconductor layer is connected to the write bit line and the memory node in the first direction, respectively; the first direction and the second direction are parallel to the substrate and intersect, and the write bit line is parallel to the substrate and extends along the second direction.

[0045] For example, the first semiconductor layer has a top surface away from the substrate and a bottom surface near the substrate, and the second insulating layer covers the top and bottom surfaces of the first semiconductor layer.

[0046] For example, the top surface of the write bit line away from the substrate and the bottom surface near the substrate are both covered by a third insulating layer and a third semiconductor layer, and the third insulating layer is disconnected from the first gate insulating layer, and the third semiconductor layer is disconnected from the first semiconductor layer.

[0047] For example, the memory node is parallel to the substrate and extends along the first direction, and the side of the memory node away from the write line is covered by a second gate insulating layer and a second semiconductor layer. In a plane perpendicular to the substrate and parallel to the first direction, the memory node is surrounded and covered by the second gate insulating layer and the second semiconductor layer.

[0048] For example, the semiconductor device further includes read bit lines and read word lines, the read bit lines extending along a second direction and the read word lines perpendicular to the substrate; the side of the second semiconductor layer away from the read word lines is connected to the read bit lines; in a plane perpendicular to the substrate and parallel to the first direction, the circumferential direction of the second semiconductor layer is connected to the read word lines.

[0049] For example, the size of the reading line in the first direction is smaller than the size of the storage node in the first direction.

[0050] For example, in the second direction, there is a first insulating layer between two adjacent storage cells, the first insulating layer is in contact with a second insulating layer in the circumferential direction, and the materials of the first insulating layer and the second insulating layer are different.

[0051] Exemplarily, in a first direction, the second insulating layer is interrupted by the readout lines; the first insulating layer is in contact with both adjacent readout lines in a second direction, and the portion of the first insulating layer in contact with the readout lines has a smaller dimension in the second direction than the other portions. This application also provides an electronic device comprising the semiconductor device provided in the above embodiments.

[0052] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. The objectives and advantages of this application may be realized and obtained by means of the structures particularly pointed out in the description and the accompanying drawings. Attached Figure Description

[0053] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0054] Figure 1 A process flow diagram of a method for manufacturing a semiconductor device provided as an exemplary embodiment of this application;

[0055] Figure 2 A logic circuit diagram of a semiconductor device provided for an exemplary embodiment of this application;

[0056] Figure 3AA schematic cross-sectional view parallel to the substrate after the trench is filled with a first insulating material, provided as an exemplary embodiment of this application, of a method for manufacturing a semiconductor device;

[0057] Figure 3B for Figure 3A A schematic diagram of a cross-section of the semiconductor device perpendicular to the substrate in the a-a' direction;

[0058] Figure 3C for Figure 3A The diagram shows a cross-sectional view of the device structure perpendicular to the substrate in the b-b' direction;

[0059] Figure 3D for Figure 3A The diagram shows a cross-sectional view of the device structure perpendicular to the substrate in the c-c' direction;

[0060] Figure 4A A schematic cross-sectional view of a semiconductor device manufacturing method provided for an exemplary embodiment of this application, after forming a writing line hole, parallel to the substrate;

[0061] Figure 4B for Figure 4A The diagram shows a cross-sectional view of the device structure perpendicular to the substrate in the b-b' direction;

[0062] Figure 4C for Figure 4A The diagram shows a cross-sectional view of the device structure perpendicular to the substrate in the c-c' direction;

[0063] Figure 5A A schematic cross-sectional view of the substrate after lateral etching of the conductive layer in the writing line hole, provided as an exemplary embodiment of this application, in a method for manufacturing a semiconductor device.

[0064] Figure 5B for Figure 5A The diagram shows a cross-sectional view of the device structure perpendicular to the substrate along the a-a' direction;

[0065] Figure 5C for Figure 5A The diagram shows a cross-sectional view of the device structure perpendicular to the substrate in the b-b' direction;

[0066] Figure 6A A schematic cross-sectional view of a semiconductor device manufacturing method provided for an exemplary embodiment of this application, after the first deposition of a gate insulating layer, parallel to the substrate;

[0067] Figure 6B for Figure 6A A schematic diagram of a cross-section of the semiconductor device perpendicular to the substrate in the a-a' direction;

[0068] Figure 6C for Figure 6A The diagram shows a cross-sectional view of the device structure perpendicular to the substrate in the b-b' direction;

[0069] Figure 6D for Figure 6A The diagram shows a cross-sectional view of the device structure perpendicular to the substrate in the c-c' direction;

[0070] Figure 7A A schematic cross-sectional view parallel to the substrate of a method for manufacturing a semiconductor device provided in an exemplary embodiment of this application, after the gaps between the first insulating layers are filled with a conductive layer;

[0071] Figure 7B for Figure 7A A schematic diagram of a cross-section of the semiconductor device perpendicular to the substrate in the a-a' direction;

[0072] Figure 7C for Figure 7A The diagram shows a cross-sectional view of the device structure perpendicular to the substrate in the b-b' direction;

[0073] Figure 7D for Figure 7A The diagram shows a cross-sectional view of the device structure perpendicular to the substrate in the c-c' direction;

[0074] Figure 8A A schematic cross-sectional view of a semiconductor device manufacturing method provided for an exemplary embodiment of this application, after forming a writing line, parallel to the substrate;

[0075] Figure 8B for Figure 8A The diagram shows a cross-sectional view of the device structure perpendicular to the substrate in the b-b' direction;

[0076] Figure 8C for Figure 8A The diagram shows a cross-sectional view of the device structure perpendicular to the substrate in the c-c' direction;

[0077] Figure 9A A schematic cross-sectional view of a semiconductor device manufacturing method provided in an exemplary embodiment of this application after removing parasitic MOS, parallel to the substrate;

[0078] Figure 9B for Figure 9A A schematic diagram of a cross-section of the semiconductor device perpendicular to the substrate in the a-a' direction;

[0079] Figure 9C for Figure 9A The diagram shows a cross-sectional view of the device structure perpendicular to the substrate in the b-b' direction;

[0080] Figure 9D for Figure 9A The diagram shows a cross-sectional view of the device structure perpendicular to the substrate in the c-c' direction;

[0081] Figure 10A A schematic cross-sectional view parallel to the substrate after a first insulating layer is filled into a via in a method for manufacturing a semiconductor device according to an exemplary embodiment of this application;

[0082] Figure 10B for Figure 10A A schematic diagram of a cross-section of the semiconductor device perpendicular to the substrate in the a-a' direction;

[0083] Figure 10C for Figure 10A The diagram shows a cross-sectional view of the device structure perpendicular to the substrate in the b-b' direction;

[0084] Figure 10D for Figure 10A The diagram shows a cross-sectional view of the device structure perpendicular to the substrate in the c-c' direction;

[0085] Figure 11A A schematic cross-sectional view of a semiconductor device manufacturing method provided for an exemplary embodiment of this application, after forming a writing line hole, parallel to the substrate;

[0086] Figure 11B for Figure 11A A schematic diagram of a cross-section of the semiconductor device perpendicular to the substrate in the a-a' direction;

[0087] Figure 11C for Figure 11A The diagram shows a cross-sectional view of the device structure perpendicular to the substrate in the b-b' direction;

[0088] Figure 12A A schematic cross-sectional view of a semiconductor device manufacturing method provided in an exemplary embodiment of this application, after a conductive layer is filled into a second via;

[0089] Figure 12B for Figure 12A A schematic diagram of a cross-section of the semiconductor device perpendicular to the substrate in the a-a' direction;

[0090] Figure 12C for Figure 12A The diagram shows a cross-section of the semiconductor device perpendicular to the substrate in the b-b' direction;

[0091] Figure 13A A schematic cross-sectional view of a semiconductor device manufacturing method provided for an exemplary embodiment of this application, after forming read lines, parallel to the substrate;

[0092] Figure 13B for Figure 13A A schematic diagram of a cross-section of the semiconductor device perpendicular to the substrate in the a-a' direction;

[0093] Figure 13C for Figure 13A The diagram shows a cross-section of the semiconductor device perpendicular to the substrate in the b-b' direction;

[0094] Figure 13D for Figure 13A The diagram shows a cross-section of the semiconductor device perpendicular to the substrate in the c-c' direction. Detailed Implementation

[0095] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0096] The embodiments of this application are not necessarily limited to the dimensions shown in the drawings. The shapes and sizes of the components in the drawings are preferred embodiments, but other shapes and sizes are also possible. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this application are not limited to the shapes or values ​​shown in the drawings.

[0097] The ordinal numbers such as "first" and "second" in this application are used to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0098] In this application, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of this specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this application. The positional relationships of the constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the application is not limited to the terms described in the disclosure and may be appropriately replaced as appropriate.

[0099] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0100] In this application, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this application, the channel region refers to the region through which current primarily flows.

[0101] In this application, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, unless otherwise specified, in this application, the "source electrode" and "drain electrode" can be interchanged.

[0102] In this application, "electrical connection" or "connection" includes situations where constituent elements are connected together by a component having some electrical function, such as an electrical signal connection (coupled connection, e.g., coupled to), or a physical direct connection. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0103] In this application, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0104] In some embodiments of this application, the terms "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".

[0105] The phrase "A and B are arranged in the same layer" in this application refers to A and B being distributed on the same horizontal plane, or although not on the same horizontal plane, both being in different areas of the same supporting surface. One embodiment involves A and B being formed simultaneously on the same film layer using the same patterning process.

[0106] In this application's embodiments, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected layers on a single film layer. For example, A and B may be formed using the same material to create a single film layer and simultaneously formed with interconnected structures through the same patterning process, or B may be directly grown on A via epitaxy, and the materials of the two may not be exactly the same.

[0107] In this application, "aperture" refers to the average aperture obtained after measurements at multiple locations.

[0108] In this application, the spacing distribution can be understood as a separate distribution, which can be achieved through physical structural breaks or electrical characteristic breaks. For example, the semiconductor layer between the effective channels of two transistors is modified to achieve insulation, thereby realizing the electrical spacing between the two channels.

[0109] To overcome the problems of small capacitance and large leakage current in 3D DRAM, researchers have developed 3D DRAM with a 2T structure, using metal-oxide-semiconductor (MIS) materials such as indium gallium zinc oxide (IGZO) to form the channel. 3D DRAM with a 2T structure based on MIS materials holds promise for high-density storage and is a possible direction for next-generation DRAM chips. However, this approach still faces some challenges, such as the removal of parasitic metal-oxide-semiconductor (MOS) layers. The presence of parasitic MOS layers prevents different memory cells from being interconnected through MIS layers, hindering information storage.

[0110] This application provides a method for manufacturing a semiconductor device.

[0111] Figure 1 A process flow diagram of a method for manufacturing a semiconductor device provided as an exemplary embodiment of this application.

[0112] like Figure 1 As shown, the manufacturing method includes:

[0113] A first insulating layer and a conductive layer are alternately formed on a substrate to obtain a stacked structure; the stacked structure is patterned and etched to form multiple trenches extending in a direction perpendicular to the substrate; multiple read lines are formed on the conductive layer at intervals in a first direction and extending in a second direction; a second insulating layer and a first insulating layer are formed in sequence in the trenches; the first insulating layer in the trenches constitutes an insulating portion.

[0114] Remove at least a portion of the second insulating layer located between adjacent conductive layers;

[0115] A write bit line extending along the second direction is formed in a conductive layer between the adjacent read bit lines in the first direction;

[0116] Multiple write word line holes are formed on both sides of the write bit line distributed along the first direction, and a semiconductor layer, a gate insulating layer and a write word line are sequentially formed in the write word line holes;

[0117] The first insulating layer in the trench is etched to form a first via, and at least a portion of the semiconductor layer between the conductive layers is removed through the first via; a semiconductor layer, a memory node, and a read word line are formed for the read transistor.

[0118] For example, forming a plurality of trenches extending in a direction perpendicular to the substrate includes:

[0119] Two grooves are formed at intervals in a first direction between two adjacent read lines.

[0120] For example, the patterning etching of the stacked structure includes:

[0121] The stacked structure is first patterned by etching along the direction toward the substrate, forming a plurality of trenches through each of the conductive layers in the stacked structure. The plurality of trenches extend along the first direction and are spaced apart in the first and second directions. The first patterned conductive layer includes the write bit line and the read bit line.

[0122] Laterally etch the exposed first patterned first insulating layer in the trench, so that the trench in the first patterned first insulating layer extends toward the first insulating layer.

[0123] A second insulating layer is deposited on the sidewall of the trench, and the first insulating layer is filled into the trench, wherein the first insulating layer located in the trench constitutes the insulating portion.

[0124] Exemplarily, the lateral etching of the exposed first patterned insulating layer within the trench includes:

[0125] The orthographic projection of the trench in the first patterned conductive layer onto the substrate falls within the range of the orthographic projection of the trench in the first patterned insulating layer onto the substrate.

[0126] Exemplarily, the manufacturing method further includes, after the first patterning, performing the following process,

[0127] Along the direction toward the substrate, the first patterned stacked structure is patterned a second time, and a row of write line holes spaced apart along the second direction are etched on the conductive layers on both sides of the write bit line.

[0128] The conductive layer, which was first patterned, is etched laterally inside the writing line hole, leaving only the reading line.

[0129] For example, etching a row of write line holes spaced apart along the second direction on the conductive layers on both sides of the write bit line includes:

[0130] The writing line hole breaks the second insulating layer between different conductive layers, exposing the sidewall of the insulating portion located between the different conductive layers.

[0131] For example, forming a plurality of write word line holes on both sides of the write bit line distributed along the first direction, and sequentially forming a semiconductor layer, a gate insulating layer, and a write word line within the write word line holes includes:

[0132] The conductive layers on both sides of the write bit line are etched along the direction toward the substrate to form write bit hole extending into the substrate, so that the write bit hole exposes the semiconductor layer on the sidewall of the insulating portion;

[0133] A semiconductor layer and a gate insulating layer are sequentially deposited on the inner wall of the writing line hole, so that the semiconductor layer on the inner wall of the writing line hole is connected to the semiconductor layer on the side wall of the insulating portion;

[0134] The writing line is formed within the writing line hole, extending in a direction perpendicular to the substrate.

[0135] For example, etching the first insulating layer within the trench to form a first via, and removing at least a portion of the semiconductor layer between the conductive layers through the first via, includes:

[0136] A first through-hole is etched into each of the insulating portions, and the first through-hole exposes the semiconductor layer on the sidewall of the insulating portion;

[0137] At least a portion of the semiconductor layer between the conductive layers is removed through the first via.

[0138] For example, forming the reading line includes:

[0139] The reading line is formed between the first insulating layer of the insulating portion and the semiconductor layer.

[0140] For example, forming the read line between the first insulating layer and the semiconductor layer of the insulating portion includes:

[0141] The first insulating layer is filled into the first through hole;

[0142] The insulating portion and the second insulating layer are etched along the direction toward the substrate to form an initial readout hole, which exposes the first insulating layer located between two adjacent conductive layers.

[0143] The first insulating layer located between two adjacent conductive layers is laterally etched within the initial readout line hole, causing the initial readout line hole to extend laterally toward the first insulating layer located between two adjacent conductive layers, forming a second through hole;

[0144] A conductive layer is filled into the second through hole; a portion of the conductive layer located in the initial read line hole is etched away to form a third through hole located in the initial read line hole, wherein the sidewalls of the third through hole in the second direction expose the conductive layer, and the read line is formed using the conductive layer.

[0145] For example, forming the readout line using the conductive layer includes:

[0146] A conductive layer of a certain thickness is retained on the sidewall of the initial reading line hole, and the remaining conductive layer in the second through hole connects the conductive layers between two adjacent first insulating layers to form a reading line extending toward the substrate.

[0147] The technical solutions of the embodiments of this application are further illustrated below through exemplary embodiments of the semiconductor device manufacturing process. The "patterning etching" mentioned in this embodiment includes processes such as film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in related technologies. The "photolithography" process mentioned in this embodiment includes film coating, mask exposure, and development, which are mature fabrication processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations here.

[0148] Figure 2 A logic circuit diagram of a semiconductor device provided for an exemplary embodiment of this application; Figures 3A to 13D These are schematic cross-sectional views of the device structure obtained from each step of a semiconductor device manufacturing method, which is an exemplary embodiment of this application, parallel to the substrate and perpendicular to the substrate in different directions.

[0149] like Figures 2 to 13D As shown, in one exemplary embodiment, the method for manufacturing the semiconductor device may include the following processes.

[0150] S10: A stacked structure consisting of alternating stacked first insulating layers 11 and conductive layers 13 is formed on the substrate 10. The stacked structure is patterned by etching. The patterned conductive layer 13 includes write bit lines W_BL and read bit lines R_BL, such as... Figures 3A to 3D As shown.

[0151] For example, step S10 may include:

[0152] S11: Provide a substrate 10, and sequentially deposit a first insulating layer 11 and a conductive layer 13 on the substrate 10 to obtain a stacked structure composed of alternately stacked first insulating layers 11 and conductive layers 13;

[0153] S12: The stacked structure is patterned and etched along the direction toward the substrate 10 to form a plurality of trenches penetrating each conductive layer 13 in the stacked structure. The plurality of trenches extend along a first direction and are spaced apart in the first direction and a second direction, the first direction intersecting the second direction. The sidewalls of the trenches expose the patterned first insulating layer 11 and the patterned conductive layer 13.

[0154] The patterned conductive layer 13 includes write bit lines W_BL and read bit lines R_BL, which are spaced apart in the first direction and both extend along the second direction. A row of trenches spaced apart in the second direction is provided between adjacent write bit lines W_BL and read bit lines R_BL.

[0155] S13: Laterally etch the exposed patterned first insulating layer 11 in the trench, so that the trench in the patterned first insulating layer 11 expands toward the patterned first insulating layer 11, that is, the orthogonal projection of the trench in the patterned conductive layer 13 on the substrate 10 falls into the range of the orthogonal projection of the trench in the patterned first insulating layer 11 on the substrate 10.

[0156] S14: Deposit a second insulating layer 12 on the substrate 10 to cover the sidewalls of the expanded trench and the top surface of the patterned stacked structure;

[0157] S15: The first insulating layer 11 is filled into the expanded trench, and the first insulating layer 11 will simultaneously cover the top surface of the patterned stacked structure; the first insulating layer 11 on the top surface of the patterned stacked structure is planarized by chemical mechanical polishing (CMP) until the second insulating layer 12 on the top surface of the patterned stacked structure is exposed, and the first insulating layer 11 located in the trench forms the insulating part 14.

[0158] For example, the first direction may be parallel to the substrate, the second direction may be parallel to the substrate, and the first direction and the second direction may be perpendicular to each other. For instance, the first direction may be as follows: Figure 3A The direction shown is either a-a' or b-b', and the second direction can be as follows: Figure 3A The c-c' direction is shown.

[0159] For example, the trench obtained in step S13 can extend in a direction perpendicular to the substrate 10 and can expose the substrate 10.

[0160] In an exemplary embodiment of this disclosure, the material of the first insulating layer may be a low-K dielectric material, that is, a dielectric material with a dielectric constant K < 3.9, including but not limited to silicon oxides, such as silicon dioxide (SiO2) or other silicon-containing films.

[0161] For example, the material of the second insulating layer can be any one or more of silicon oxide (e.g., SiO2), silicon oxynitride (SiON), silicon nitride (SiN), and silicon carbonitride (SiCN), and the material of the second insulating layer is different from that of the first insulating layer, so that when one of the first and second insulating layers is subsequently etched away, the first and second insulating layers can have different etching rates, thereby removing the desired insulating layer. For example, in this embodiment, the material of the first insulating layer can be silicon oxide, and the material of the second insulating layer can be silicon nitride.

[0162] For example, the conductive layer can be formed from conductive metals, metal nitrides, metal oxides, and polycrystalline silicon, etc.; the conductive materials include, but are not limited to, tungsten (W), cobalt (Co), titanium (Ti), titanium nitride (TiN), indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0163] Figure 3B The stacked structure shown includes four first insulating layers 11 and three conductive layers 13. This is merely an example; in other embodiments, the stacked structure may include more or fewer alternating layers of first insulating layers 11 and conductive layers 13.

[0164] The substrate in the embodiments of this application can be a support structure, such as a silicon substrate, or a support structure on which other films or functions or circuits are already distributed. The device involved in the inventive construction of the embodiments of this application is disposed on the main surface of the support structure.

[0165] S20: The patterned stacked structure is etched to form writing line holes K1 penetrating each patterned conductive layer 13, such as... Figures 4A to 4C As shown, Figure 4A The schematic diagram of the device structure shown is a cross-section perpendicular to the substrate in the a-a' direction. Figure 3B same.

[0166] For example, step S20 may include: etching the patterned stacked structure along the direction toward the substrate 10, forming a write line hole K1 between every two trenches on both sides of the write bit line W_BL, the write line hole K1 penetrating each patterned conductive layer 13 in a direction perpendicular to the substrate 10, and exposing the second insulating layer 12 located on the inner wall of the trench of the conductive layer 13, that is, the conductive layer 13 between two adjacent trenches is penetrated by the write line hole K1 in the second direction.

[0167] For example, the writing line hole K1 can extend in a direction perpendicular to the substrate 10, and can expose the substrate 10.

[0168] S30: Laterally etch the conductive layer 13 inside the write line hole K1, retaining only the conductive layer 13 used as the read bit line R_BL, such as Figures 5A to 5C As shown, Figure 5A The schematic diagram of the device structure shown is a cross-section perpendicular to the substrate in the c-c' direction. Figure 4C same.

[0169] like Figure 5A , Figure 5B and Figure 4C As shown, the insulating portion 14 extends toward the substrate 10 and along the first direction. A second insulating layer 12 is provided between an insulating portion 14 and a column of read bit lines R_BL located on a different layer. There are only two insulating portions 14 spaced apart between two adjacent columns of read bit lines R_BL in the first direction.

[0170] S40: A semiconductor layer 20 and a gate insulating layer 30 are sequentially deposited on the exposed sidewalls of the first insulating layer 11, the second insulating layer 12, and the conductive layer 13, such as... Figures 6A to 6D As shown.

[0171] S50: The gaps between the gate insulating layers 30 are filled with conductive layer 13, and the write bit line W_BL is re-formed at the position of write bit line W_BL in step S10, such as... Figures 7A to 7D As shown.

[0172] S60: Etch away the conductive layer 13, gate insulating layer, and semiconductor layer inside the write line hole K1. Sequentially deposit the semiconductor layer 20 and gate insulating layer 30 on the inner wall (including sidewall and bottom wall) of the write line hole K1 to form the write line W_WL inside the write line hole K1. Figures 8A to 8C As shown, Figure 8AThe schematic diagram of the device structure shown is a cross-section perpendicular to the substrate in the a-a' direction. Figure 7B same.

[0173] For example, step S60 may include:

[0174] S61: Etch away the conductive layer 13 inside the write line hole K1 to vacate the write line hole K1; deposit a semiconductor layer 20 and a gate insulating layer 30 sequentially on the inner wall (including the side wall and bottom wall) of the write line hole K1; since the write line hole K1 formed in step S20 penetrates the conductive layer 13 between two adjacent trenches in the second direction, that is, the write line hole K1 is in direct contact with the side wall of the trench, the semiconductor layer 20 deposited in step S60 will be connected with the semiconductor layer 20 located on the side wall of the trench;

[0175] S62: Fill the writing line hole K1 with conductive material to obtain the writing line W_WL located in the writing line hole K1.

[0176] like Figure 8B and Figure 8C As shown, since the semiconductor layer 20 deposited in step S60 is continuously distributed on the sidewall of the writing line hole K1 in the extension direction of the writing line hole K1, that is, the semiconductor layer 20 located in the channel region 200 between two adjacent first insulating layers 11 is connected to the semiconductor layer 20 located in the parasitic MOS region 300 between two adjacent conductive layers 13, thus forming a parasitic MOS transistor (referred to as parasitic MOS).

[0177] S70: Remove parasitic MOS.

[0178] For example, step S70 may include: etching the first insulating layer 11 on the outer wall of the write line hole K1 along the direction toward the substrate 10 to form a first through hole K2 that penetrates the first insulating layer 11 between two adjacent write line holes K1 along the second direction and extends into the first insulating layer 11 between two adjacent conductive layers, and making the first through hole K2 penetrate the first insulating layer 11 between two adjacent write line holes K1 in the second direction, thereby exposing the semiconductor layer 20 on the sidewall of the write line hole K1 located in the first insulating layer 11, that is, the semiconductor layer 20 located in the parasitic MOS region 300; etching away the semiconductor layer 20 of the parasitic MOS region 300, such as... Figures 9A to 9D As shown.

[0179] For example, such as Figure 9A and Figure 9B As shown, the first through-hole K2 can expose the second insulating layer on the sidewall of the write bit line W_BL.

[0180] S80: The conductive layers 13 between the write bit line W_BL and the read bit line R_BL are connected by the conductive layer 13 to form the read word line R_WL extending in a direction perpendicular to the substrate 10.

[0181] For example, step S80 may include:

[0182] S81: Fill the first through hole K2 with the first insulating layer 11, such as Figures 10A to 10D As shown;

[0183] S82: Etch the first insulating layer 11 and the second insulating layer 12 between two adjacent word lines W_WL along the direction toward the substrate 10 to form an initial word line hole, the initial word line hole exposing the first insulating layer 11 located between two adjacent conductive layers 13;

[0184] S83: Laterally etch the first insulating layer 11 located between two adjacent conductive layers 13 within the initial read-line hole, causing the initial read-line hole to extend laterally towards the first insulating layer 11 located between two adjacent conductive layers 13, forming a second through-hole K3. Figures 11A to 11C As shown;

[0185] like Figure 11B As shown, the second through-hole K3 at aa' penetrates the entire first insulating layer 11; as Figure 11C As shown, the second through-hole K3 located between two adjacent conductive layers 13 only penetrates the first insulating layer 11 between the two adjacent conductive layers 13, but is disconnected at the conductive layer 13.

[0186] S84: The second through hole K3 is filled with a conductive layer 13, such as Figure 12A and Figure 12C As shown;

[0187] S85: Etching removes a portion of the conductive layer 13 located within the initial read word line hole, forming a second via within the initial read word line hole. The sidewalls of the second via in the second direction expose the conductive layer 13, meaning the length of the second via in the second direction is less than the length of the initial read word line hole in the second direction, thus retaining a conductive layer 13 of a certain thickness on the sidewalls of the initial read word line hole. The remaining conductive layer 13 within the second via K3 connects the conductive layers 13 between the write bit line W_BL and the read bit line R_BL to form a read word line R_WL extending in a direction perpendicular to the substrate 10. The region between two adjacent first insulating layers 11 in the read word line R_WL is used as a storage node SN (Storagegate).

[0188] S86: Fill the second through hole with insulating material, such as... Figures 13A to 13DAs shown. In this application, the semiconductor layer can be understood as a semiconductor material; its shape and structure are not emphasized here, only its function.

[0189] For example, the material of the semiconductor layer can be silicon or polycrystalline silicon with a band gap of less than 1.65 eV, or it can be a wide band gap material, such as a metal oxide material with a band gap of greater than 1.65 eV.

[0190] For example, the material of the metal oxide semiconductor layer or channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen (N) and silicon (Si); it may also contain trace amounts of other doping elements.

[0191] In some embodiments, the material of the metal oxide semiconductor layer or channel may comprise any one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InW). Materials such as O, IWO, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) are all acceptable, as long as the leakage current of the transistor meets the requirements. Specific adjustments can be made based on the actual situation.

[0192] These materials have wide band gaps and low leakage current. For example, when the metal oxide material is IGZO, the transistor leakage current is less than or equal to 10. -15 A. This can improve the performance of dynamic memory.

[0193] The above-mentioned materials for metal oxide semiconductor layers or channels only emphasize the element type of the material, without emphasizing the atomic ratio or the film quality of the material.

[0194] For example, the materials of the read bit line and the write bit line can be selected from any one or more other metallic materials with similar properties, such as tungsten, molybdenum, and cobalt. The bit line can be a single-layer or multi-layer structure, for example, it can be a multi-layer structure formed of titanium (Ti), titanium nitride (TiN), and tungsten (W).

[0195] In an exemplary embodiment of this application, the conductive material of the read line and the write line can be any one or more of the following different types of materials:

[0196] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can be a metal alloy containing these metals.

[0197] It can also be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), and other metal oxide materials with high conductivity; such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), and other metal nitride materials.

[0198] Of course, it can also be polycrystalline silicon; it can also be a conductive material doped with a semiconductor material, such as conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium, etc.; and other materials that exhibit conductivity, etc.

[0199] Exemplarily, the gate insulating layer may comprise one or more Low-K and / or High-K dielectric materials, or comprise two or more regions with different dielectric constants K. The characteristics of the gate insulating layer of this application will be illustrated below by way of example.

[0200] Low-K materials, such as silicon oxide.

[0201] This application also provides a semiconductor device, such as... Figure 2 and Figures 13A to 13D As shown, the semiconductor device includes: a substrate 10 and a plurality of memory cells;

[0202] The memory cell includes: a read transistor Tr_r and a write transistor Tr_w connected to each other, and a write word line W_WL perpendicular to the substrate 10; the write transistor Tr_w includes a first gate electrode G1, a first electrode 41 and a second electrode 42, the read transistor Tr_r includes a second gate electrode G2, a third electrode 43 and a fourth electrode 44, and the first gate electrode G1 of the write transistor Tr_w is part of the write word line W_WL; the write word line W_WL includes a bottom surface near the substrate 10 and a top surface away from the substrate 10, and a side surface between the top surface and the bottom surface; on the side surface of the write word line W_WL, a first gate insulating layer 31 and a first semiconductor layer 21 are sequentially provided in a direction away from the write word line W_WL, and the first semiconductor layer 21 is broken in a direction perpendicular to the substrate 10; a second insulating layer 12 is provided on the side of the first semiconductor layer 21 away from the write word line W_WL, and the second insulating layer 12 is also broken in a direction perpendicular to the substrate 10.

[0203] For example, the first semiconductor layer 21 covers the side of the first gate electrode G1 of the corresponding write transistor Tr_w, and the second insulating layer 12 covers the side of the corresponding first semiconductor layer 21. The second insulating layer 12 is provided in a direction perpendicular to the substrate 10, which can protect the channel of the write transistor Tr_w when the parasitic MOS between the different layers of write transistor Tr_w is etched away.

[0204] For example, the first gate insulating layer 31 and the first semiconductor layer 21 may fully surround the write line W_WL or partially surround it.

[0205] Exemplarily, the side surface of the first semiconductor layer 21 is covered by the second insulating layer 12 in the second direction, and the side surface of the first semiconductor layer 21 is connected to the write bit line W_BL and the memory node SN in the first direction, respectively; the first direction and the second direction are parallel to the substrate 10 and intersect, and the write bit line W_BL is parallel to the substrate 10 and extends along the second direction. When etching away the parasitic MOS between the write transistors Tr_w of different layers, the side surface of the first semiconductor layer 21 is protected by the second insulating layer 12 in the second direction, and is protected by the write bit line W_BL and the memory node SN in the first direction, respectively.

[0206] For example, the first semiconductor layer 21 has a top surface away from the substrate 10 and a bottom surface close to the substrate 10, and the second insulating layer 12 covers the top and bottom surfaces of the first semiconductor layer 21. Covering the top and bottom surfaces of the first semiconductor layer 21 with the second insulating layer 12 can enhance the protection of the top and bottom surfaces of the first semiconductor layer 21.

[0207] For example, the memory node SN extends parallel to the substrate 10 and along the first direction, and the side of the memory node SN away from the write word line W_WL is covered by the second gate insulating layer 32 and the second semiconductor layer 22. In a plane perpendicular to the substrate 10 and parallel to the first direction, the memory node SN is surrounded and covered by the second gate insulating layer 32 and the second semiconductor layer 22.

[0208] like Figure 13A As shown, the first semiconductor layer 21 and the second semiconductor layer 22 can be connected together. In this case, the write word line W_WL can be used as a switch. When current enters the memory cell from the write bit line W_BL, if the switch of the write word line W_WL is turned on, the first semiconductor layer 21 and the second semiconductor layer 22 are turned on, and the current enters the memory node SN through the first semiconductor layer 21 and the second semiconductor layer 22. If the switch of the word line W_WL is turned off, the first semiconductor layer 21 and the second semiconductor layer 22 are not turned on, and the charge is stored in the memory node SN.

[0209] Exemplarily, the semiconductor device further includes a read bit line R_BL and a read word line R_WL. The read bit line R_BL extends along a second direction, and the read word line R_WL is perpendicular to the substrate 10. The side of the second semiconductor layer 22 away from the write word line R_WL is connected to the read bit line R_BL. In a plane perpendicular to the substrate 10 and parallel to the first direction, the circumferential direction of the second semiconductor layer 22 is connected to the read word line R_WL. The circumferential connection of the second semiconductor layer 22 to the read word line R_WL can increase the contact area with the read word line R_WL and reduce the contact resistance.

[0210] The storage node SN is arranged parallel to the substrate 10 and is connected to the write word line W_WL and the read bit line R_BL in the first direction, which facilitates the removal of parasitic MOS in the direction parallel to the substrate 10.

[0211] For example, the size of the read word line R_WL in the first direction is smaller than the size of the storage node SN in the first direction. If the size of the read word line R_WL in the first direction is larger than the size of the storage node SN in the first direction, it will cause a short circuit between the read word line R_WL and the read bit line R_BL.

[0212] For example, the top surface of the write bit line W_BL away from the substrate 10 and the bottom surface near the substrate 10 are both covered by the third insulating layer 15 and the third semiconductor layer 23, and the third insulating layer 15 is disconnected from the first gate insulating layer 31, and the third semiconductor layer 23 is disconnected from the first semiconductor layer 21. The disconnection of the third semiconductor layer 23 from the first semiconductor layer 21 can prevent the adjacent write transistor Tr_w from short-circuiting.

[0213] Exemplarily, in the second direction, a first insulating layer 11 is provided between two adjacent memory cells, the first insulating layer 11 being in contact with a second insulating layer 12 in the circumferential direction, and the first insulating layer 11 and the second insulating layer 12 being made of different materials. By providing the first insulating layer 11 and the second insulating layer 12 between adjacent write word lines W_WL, and having different etching selectivity ratios for the two, the channel of the write transistor Tr_w can be protected by the second insulating layer 12 when etching away the parasitic MOS between different layers of write transistor Tr_w.

[0214] For example, in the first direction, the second insulating layer 12 is disconnected by the read line R_WL; the first insulating layer 11 is in contact with both adjacent read lines R_WL in the second direction, and the portion of the first insulating layer 11 in contact with the read lines R_WL has a smaller dimension in the second direction than the other portions. The portion of the first insulating layer in contact with the read lines R_WL is recessed, providing space for the read lines R_WL so that the read lines R_WL can also contact the second semiconductor layer 22 in the circumferential direction, reducing the contact resistance.

[0215] The semiconductor device can be obtained by the manufacturing method provided in the embodiments of this application above.

[0216] The semiconductor layer spacing of transistors in at least some adjacent layers of the semiconductor device provided in this application embodiment can reduce or eliminate parasitic MOS between at least some layers and improve device stability.

[0217] In an exemplary embodiment of this application, the semiconductor layers of the transistors in different layers are spaced apart in a direction perpendicular to the substrate, that is, the semiconductor layers of the transistors in all adjacent layers are spaced apart in a direction perpendicular to the substrate, thereby eliminating parasitic MOS capacitance between all adjacent layers and improving device stability.

[0218] For example, the semiconductor device can be a 3D memory, such as a 3D DRAM or similar memory. The 3D memory can be a 2TOC structure.

[0219] This application also provides an electronic device, which includes the semiconductor device described in the above embodiments of this application.

[0220] In exemplary embodiments of this application, the electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0221] While the embodiments disclosed in this application are as described above, the content is merely for the purpose of facilitating understanding of this application and is not intended to limit this application. Any person skilled in the art to which this application pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application; however, the scope of protection of this application shall still be determined by the scope defined in the appended claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A stacked structure is obtained by sequentially and alternately forming a first insulating layer and a conductive layer on a substrate. The stacked structure is first patterned by etching along the direction toward the substrate, forming a plurality of trenches through each of the conductive layers in the stacked structure. The plurality of trenches extend along a first direction and are spaced apart in a first direction and a second direction. The first patterned conductive layer includes write bit lines and read bit lines. Laterally etch the exposed first patterned first insulating layer in the trench, so that the trench in the first patterned first insulating layer extends toward the first insulating layer. A second insulating layer is deposited on the sidewall of the trench, and the first insulating layer is filled in the trench, wherein the first insulating layer located in the trench constitutes an insulating portion; Remove at least a portion of the second insulating layer located between adjacent conductive layers; A write bit line extending along the second direction is formed in a conductive layer between the adjacent read bit lines in the first direction; Multiple write word line holes are formed on both sides of the write bit line distributed along the first direction, and a semiconductor layer, a gate insulating layer and a write word line are sequentially formed in the write word line holes; The first insulating layer in the trench is etched to form a first via, and at least a portion of the semiconductor layer between the conductive layers is removed through the first via; a semiconductor layer, a memory node, and a read word line are formed for the read transistor.

2. The manufacturing method according to claim 1, characterized in that, The formation of multiple trenches extending in a direction perpendicular to the substrate includes: Two grooves are formed at intervals in a first direction between two adjacent read lines.

3. The manufacturing method according to claim 1, characterized in that, The lateral etching of the exposed, first patterned insulating layer within the trench includes: The orthographic projection of the trench in the first patterned conductive layer onto the substrate falls within the range of the orthographic projection of the trench in the first patterned insulating layer onto the substrate.

4. The manufacturing method according to claim 1, characterized in that, Also includes: After the first patterning, the following process is performed. Along the direction toward the substrate, the first patterned stacked structure is patterned a second time, and a row of write line holes spaced apart along the second direction are etched on the conductive layers on both sides of the write bit line. The conductive layer, which was first patterned, is etched laterally inside the writing line hole, leaving only the reading line.

5. The manufacturing method according to claim 4, characterized in that, The step of etching a row of write line holes spaced apart along the second direction on the conductive layers on both sides of the write bit line includes: The writing line hole breaks the second insulating layer between different conductive layers, exposing the sidewall of the insulating portion located between the different conductive layers.

6. The manufacturing method according to any one of claims 1 to 5, characterized in that, The method of forming a plurality of write word line holes on both sides of the write bit line distributed along the first direction, and sequentially forming a semiconductor layer, a gate insulating layer and a write word line within the write word line holes, includes: The conductive layers on both sides of the write bit line are etched along the direction toward the substrate to form write bit hole extending into the substrate, so that the write bit hole exposes the semiconductor layer on the sidewall of the insulating portion; A semiconductor layer and a gate insulating layer are sequentially deposited on the inner wall of the writing line hole, so that the semiconductor layer on the inner wall of the writing line hole is connected to the semiconductor layer on the side wall of the insulating portion; The writing line is formed within the writing line hole, extending in a direction perpendicular to the substrate.

7. The manufacturing method according to any one of claims 1 to 5, characterized in that, The step of etching the first insulating layer within the trench to form a first via, and removing at least a portion of the semiconductor layer between the conductive layers through the first via, includes: A first through-hole is etched into each of the insulating portions, and the first through-hole exposes the semiconductor layer on the sidewall of the insulating portion; At least a portion of the semiconductor layer between the conductive layers is removed through the first via.

8. The manufacturing method according to any one of claims 1 to 5, characterized in that, The formation of the reading line includes: The reading line is formed between the first insulating layer of the insulating portion and the semiconductor layer.

9. The manufacturing method according to claim 8, characterized in that, The formation of the read line between the first insulating layer and the semiconductor layer in the insulating portion includes: The first insulating layer is filled into the first through hole; The insulating portion and the second insulating layer are etched along the direction toward the substrate to form an initial readout hole, which exposes the first insulating layer located between two adjacent conductive layers. The first insulating layer located between two adjacent conductive layers is laterally etched within the initial readout line hole, causing the initial readout line hole to extend laterally toward the first insulating layer located between two adjacent conductive layers, forming a second through hole; A conductive layer is filled into the second through hole; a portion of the conductive layer located in the initial read line hole is etched away to form a third through hole located in the initial read line hole, wherein the sidewalls of the third through hole in the second direction expose the conductive layer, and the read line is formed using the conductive layer.

10. The manufacturing method according to claim 9, characterized in that, The step of forming the readout line using the conductive layer includes: A conductive layer of a certain thickness is retained on the sidewall of the initial reading line hole, and the remaining conductive layer in the second through hole connects the conductive layers between two adjacent first insulating layers to form a reading line extending toward the substrate.

11. A semiconductor device, characterized in that, Obtained by the manufacturing method according to any one of claims 1 to 10; The semiconductor device includes: a substrate and multiple memory cells; The memory cell includes: a read transistor and a write transistor interconnected, and a write word line perpendicular to the substrate; the write transistor includes a first gate electrode, a first electrode, and a second electrode, the read transistor includes a second gate electrode, a third electrode, and a fourth electrode, and the first gate electrode of the write transistor is part of the write word line; the write word line includes a bottom surface near the substrate and a top surface away from the substrate, and a side surface between the top surface and the bottom surface; on the side surface of the write word line, a first gate insulating layer and a first semiconductor layer are sequentially provided in a direction away from the write word line, the first semiconductor layer being broken in a direction perpendicular to the substrate; a second insulating layer is provided on the side of the first semiconductor layer away from the write word line, the second insulating layer also being broken in a direction perpendicular to the substrate.

12. The semiconductor device according to claim 11, characterized in that, The first semiconductor layer covers the side of the first gate electrode of the corresponding write transistor, and the second insulating layer covers the side of the corresponding first semiconductor layer.

13. The semiconductor device according to claim 11, characterized in that, The side of the first semiconductor layer is covered by a second insulating layer in the second direction. The side of the first semiconductor layer is connected to the write bit line and the memory node in the first direction, respectively. The first direction and the second direction are parallel to the substrate and intersect each other. The write bit line is parallel to the substrate and extends along the second direction.

14. The semiconductor device according to claim 13, characterized in that, The first semiconductor layer has a top surface away from the substrate and a bottom surface close to the substrate, and the second insulating layer covers the top and bottom surfaces of the first semiconductor layer.

15. The semiconductor device according to claim 13, characterized in that, The memory node is parallel to the substrate and extends along the first direction. The side of the memory node away from the write line is covered by a second gate insulating layer and a second semiconductor layer. In a plane perpendicular to the substrate and parallel to the first direction, the memory node is surrounded and covered by the second gate insulating layer and the second semiconductor layer.

16. The semiconductor device according to claim 15, characterized in that, It also includes read bit lines and read word lines, the read bit lines extending along a second direction and the read word lines perpendicular to the substrate; the side of the second semiconductor layer away from the write word lines is connected to the read bit lines; In a plane perpendicular to the substrate and parallel to the first direction, the second semiconductor layer is circumferentially connected to the word line.

17. The semiconductor device according to claim 16, characterized in that, The dimension of the reading line in the first direction is smaller than the dimension of the storage node in the first direction.

18. The semiconductor device according to claim 13, characterized in that, The top surface of the write bit line away from the substrate and the bottom surface near the substrate are both covered by a third insulating layer and a third semiconductor layer, and the third insulating layer is disconnected from the first gate insulating layer, and the third semiconductor layer is disconnected from the first semiconductor layer.

19. The semiconductor device according to claim 17, characterized in that, In the second direction, there is a first insulating layer between two adjacent storage cells, the first insulating layer is in contact with a second insulating layer in the circumferential direction, and the first insulating layer and the second insulating layer are made of different materials.

20. The semiconductor device according to claim 19, characterized in that, In the first direction, the second insulating layer is interrupted by the reading lines; the first insulating layer is in contact with both adjacent reading lines in the second direction, and the portion of the first insulating layer in contact with the reading lines is smaller in the second direction than the other portions.

21. An electronic device, characterized in that, Includes the semiconductor device according to any one of claims 11 to 20.

Images