Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the structure comprises a substrate which comprises a storage unit region; the laminated gate structure is located on the substrate of the storage unit area, the laminated gate structure comprises a floating gate structure and a control gate structure located on the floating gate structure, one side of the floating gate structure protrudes outwards relative to the side wall of the control gate structure, and an acute angle is formed by the top surface and the side wall of the floating gate structure at the protruding part of the floating gate structure; and the erase gate structure is located on the substrate on one side, protruding outwards, of the floating gate structure in the storage unit region, and the erase gate structure covers the top surface and the side wall, exposed by the control gate structure, of the floating gate structure. According to the invention, the influence on the erasing efficiency is reduced, so that the performance of the semiconductor structure is guaranteed.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In the current semiconductor industry, integrated circuit products can be divided into three main types: analog circuits, digital circuits, and mixed analog / digital circuits. Among them, memory devices are an important type of digital circuits. In recent years, among memory devices, flash memory has developed particularly rapidly. The main feature of flash memory is that it can retain stored information for a long time without power; it also has the advantages of high integration, fast access speed, easy erasure and rewriting, etc., so it has been widely used in many fields such as microcomputers and automation control.

[0003] Flash memory mainly includes stacked gate flash memory and split gate flash memory, among which split gate flash memory has the advantages of low programming voltage and high programming efficiency and is widely used. Summary of the invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which are helpful to ensure the performance of the semiconductor structure.

[0005] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, including a storage cell region; a stacked gate structure, located on the substrate in the storage cell region, the stacked gate structure including a floating gate structure, and a control gate structure located on the floating gate structure, one side of the floating gate structure protrudes outward relative to the side wall of the control gate structure, and at the protruding portion of the floating gate structure, the top surface of the floating gate structure and the side wall form an acute angle; an erase gate structure, located on the substrate on the side of the floating gate structure protruding outward in the storage cell region, the erase gate structure covering the top surface and side wall of the floating gate structure exposed by the control gate structure.

[0006] Optionally, the storage cell region includes two stacked gate structures, the acute angles of the floating gate structures of the two stacked gate structures are arranged opposite to each other, and the side walls of the floating gate structures facing away from the acute angles are perpendicular to the substrate; and two adjacent stacked gate structures share the same erase gate structure.

[0007] Optionally, the distance from the acute top angle of the floating gate structure to the side wall of the control gate structure is one third to two thirds of the total width of the erase gate structure.

[0008] Optionally, the semiconductor structure further includes: a first dielectric layer located between the floating gate structure and the control gate structure; and a second dielectric layer located between the floating gate structure and the erase gate structure, and between the control gate structure and the erase gate structure.

[0009] Optionally, the semiconductor structure further includes: a protective sidewall covering a sidewall of the control gate structure.

[0010] Optionally, in the protruding portion of the floating gate structure, an acute angle formed by a top surface and a side wall of the floating gate structure is greater than or equal to 30°.

[0011] Optionally, the material of the floating gate structure includes polysilicon; the material of the control gate structure includes polysilicon; and the material of the erase gate structure includes polysilicon.

[0012] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, including a storage cell region; forming a stacked gate structure on the substrate in the storage cell region, the stacked gate structure including a floating gate structure and a control gate structure located on the floating gate structure, one side of the floating gate structure protrudes outward relative to the side wall of the control gate structure, and in the protruding portion of the floating gate structure, the top surface of the floating gate structure and the side wall form an acute angle; forming an erase gate structure on the substrate on the side of the floating gate structure protruding outward in the storage cell region, the erase gate structure covering the top surface and side wall of the floating gate structure exposed by the control gate structure.

[0013] Optionally, in the step of forming a stacked gate structure, two stacked gate structures are formed in the storage cell area, the acute angles of the floating gate structures of the two stacked gate structures are arranged opposite to each other, and the side walls of the floating gate structures facing away from the acute angles are perpendicular to the substrate; in the step of forming an erase gate structure, two adjacent stacked gate structures share the same erase gate structure.

[0014] Optionally, the step of forming a stacked gate structure includes: forming a first gate material layer covering the substrate, and a second gate material layer located on the first gate material layer; patterning the second gate material layer, retaining the remaining second gate material layer protruding from the first gate material layer in the storage cell area as a control gate structure; and patterning the first gate material layer exposed by the control gate structure to form a floating gate structure.

[0015] Optionally, in the step of providing a substrate, the storage cell area includes a preset area for forming an erase gate structure; the first gate material layer exposed by the patterning control gate structure, and the step of forming a floating gate structure includes: forming a mask side wall on the side wall of the control gate structure facing the preset area; using the mask side wall as a mask, patterning the first gate material layer in the preset area and exposed by the mask side wall to form a floating gate structure.

[0016] Optionally, the step of forming a mask side wall on the side wall of the control gate structure facing the preset area includes: forming a side wall material layer covering the side wall of the control gate structure; removing the side wall material layer of the side wall of the control gate structure facing away from the preset area, and retaining the side wall material layer of the side wall of the control gate structure facing the preset area as the mask side wall.

[0017] Optionally, in the step of forming the mask sidewalls, the thickness of the mask sidewalls is one third to two thirds of the preset total width of the erase gate structure.

[0018] Optionally, before the first gate material layer exposed by the patterned control gate structure is exposed, the method further includes: forming a protective sidewall on the sidewall of the control gate structure; in the step of forming a mask sidewall on the sidewall of the control gate structure facing a preset area, the mask sidewall covers the protective sidewall.

[0019] Optionally, the step of using the mask sidewall as a mask to pattern the first gate material layer exposed by the mask sidewall in a preset area includes: using the mask sidewall and the control gate structure as a mask to pattern the first gate material layer to form an initial gate structure whose sidewalls are perpendicular to the substrate; and laterally processing the sidewalls of the initial gate structure toward the preset area so that the top surface of the initial gate structure forms an acute angle with the sidewalls and serves as a floating gate structure.

[0020] Optionally, an anisotropic dry etching process is used to pattern the first gate material layer.

[0021] Optionally, the step of laterally processing the side walls of the initial gate structure toward the preset area includes: forming a protective layer covering the top of the stacked gate structure and the side walls facing away from the mask side walls, the protective layer having an opening exposing the mask side walls and the side walls of the floating gate structure toward the preset area; and laterally processing the side walls of the floating gate structure along the opening.

[0022] Optionally, an isotropic wet etching process is used to laterally process the sidewalls of the floating gate structure.

[0023] Optionally, the etching solution used in the wet etching process includes a NaOH solution or a KOH solution.

[0024] Optionally, in the step of forming a stacked gate structure on the substrate of the memory cell region, a first dielectric layer is formed between the floating gate structure and the control gate structure; before forming the erase gate structure, the sidewall of the control gate structure and the portion of the floating gate structure exposed by the control gate structure are covered with a second dielectric layer.

[0025] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0026] In the semiconductor structure provided by the embodiment of the present invention, one side of the floating gate structure protrudes outward relative to the side wall of the control gate structure, and in the protruding portion of the floating gate structure, the top surface of the floating gate structure and the side wall form an acute angle, the erase gate structure is located on the substrate on the side of the floating gate structure protruding outward in the storage cell area, and the erase gate structure covers the top surface and side wall of the floating gate structure exposed by the control gate structure, that is, the erase gate structure covers the acute angle portion of the floating gate structure, and the portion of the floating gate structure extending into the erase gate structure is an acute angle. The electric field at the acute angle is large, which is conducive to reducing the energy band barrier from the floating gate structure to the erase gate structure, and electrons are more likely to reach the erase gate structure from the floating gate structure, which is conducive to improving the writing and erasing efficiency of the semiconductor structure. Moreover, the portion of the floating gate structure extending into the erase gate structure is an acute angle, which is conducive to reducing the degree to which the portion of the floating gate structure extending into the erase gate structure becomes rounded due to oxidation in the subsequent process, thereby helping to reduce the impact on the erase efficiency, and further to help ensure the performance of the semiconductor structure.

[0027] In the formation method provided by the embodiment of the present invention, one side of the floating gate structure protrudes outward relative to the side wall of the control gate structure, and at the protruding portion of the floating gate structure, the top surface of the floating gate structure and the side wall form an acute angle, and an erase gate structure is formed on the substrate on the side of the floating gate structure protruding outward in the storage cell area, and the erase gate structure covers the top surface and side wall of the floating gate structure exposed by the control gate structure, that is, the erase gate structure covers the acute angle portion of the floating gate structure, and the portion of the floating gate structure extending into the erase gate structure is an acute angle. The electric field at the acute angle is large, which is conducive to reducing the energy band barrier from the floating gate structure to the erase gate structure, and electrons are more likely to reach the erase gate structure from the floating gate structure, which is conducive to improving the writing and erasing efficiency of the semiconductor structure. Moreover, the portion of the floating gate structure extending into the erase gate structure is an acute angle, which is conducive to reducing the degree to which the portion of the floating gate structure extending into the erase gate structure becomes rounded due to oxidation in the subsequent process, thereby helping to reduce the impact on the erase efficiency, and further to help ensure the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic diagram of the structure of a semiconductor structure;

[0029] Figure 2 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0030] Figures 3 to 12 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0031] At present, the working performance of semiconductor structures is difficult to guarantee. Now, the reasons why the working performance is difficult to guarantee are analyzed in combination with a method for forming a semiconductor structure.

[0032] Figure 1It is a structural diagram of a semiconductor structure.

[0033] refer to Figure 1 The semiconductor structure includes: a substrate 10, including a storage cell region 10S; a floating gate structure 24, and a control gate structure 22 located on the floating gate structure 24, located on the substrate 10 in the storage cell region 10S, the floating gate structure 24 protrudes outward relative to the sidewall of the control gate structure 22, and in the protruding portion of the floating gate structure 24, the top surface of the floating gate structure 24 is perpendicular to the sidewall structure; an erase gate structure 25, located on the substrate 10 on the side of the floating gate structure 24 protruding outward in the storage cell region 10S, the erase gate structure 25 covers the top surface and sidewall of the floating gate structure 24 exposed by the control gate structure 22.

[0034] The semiconductor structure is a Flash memory, specifically, a split-gate memory. The split-gate memory completes the erase operation through the tunneling effect principle from the floating gate (FG) structure 24 to the erase gate (EG) structure 25. In order to improve the erase efficiency and increase the tunneling area, in the existing process, a right-angle floating gate (FG) tip (such as Figure 1 The dotted circle in the middle shows the shape of the FG tip, which is used to improve the electric field distribution and increase the area of ​​the EG-coupled FG, so that the electrons in the floating gate structure 24 can be easily pulled out. However, in the subsequent thermal process, the FG tip is easily oxidized and becomes rounded, especially after the bipolar-complementary-bipolar-metal oxide semi-field effect transistor (Bipolar-CMOS-DMOS, BCD) device is embedded, the gate oxidation process of the BCD device is added, and the annealing (thermal) process is added during the process, which further aggravates the rounding of the FG tip during the process, thereby reducing the electric field at the FG tip and shortening the width of the floating gate structure 24 extending into the erase gate structure 25, thereby reducing the erase efficiency of the split-gate memory and affecting the performance of the semiconductor structure.

[0035] In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate, including a storage cell region; a stacked gate structure, located on the substrate in the storage cell region, the stacked gate structure including a floating gate structure, and a control gate structure located on the floating gate structure, one side of the floating gate structure protrudes outward relative to the side wall of the control gate structure, and in the protruding portion of the floating gate structure, the top surface of the floating gate structure and the side wall form an acute angle; an erase gate structure, located on the substrate on the side of the floating gate structure protruding outward in the storage cell region, the erase gate structure covering the top surface and side wall of the floating gate structure exposed by the control gate structure.

[0036] In the semiconductor structure provided by the embodiment of the present invention, one side of the floating gate structure protrudes outward relative to the side wall of the control gate structure, and in the protruding portion of the floating gate structure, the top surface of the floating gate structure and the side wall form an acute angle, the erase gate structure is located on the substrate on the side of the floating gate structure protruding outward in the storage cell area, and the erase gate structure covers the top surface and side wall of the floating gate structure exposed by the control gate structure, that is, the erase gate structure covers the acute angle portion of the floating gate structure, and the portion of the floating gate structure extending into the erase gate structure is an acute angle. The electric field at the acute angle is large, which is conducive to reducing the energy band barrier from the floating gate structure to the erase gate structure, and electrons are more likely to reach the erase gate structure from the floating gate structure, which is conducive to improving the writing and erasing efficiency of the semiconductor structure. Moreover, the portion of the floating gate structure extending into the erase gate structure is an acute angle, which is conducive to reducing the degree to which the portion of the floating gate structure extending into the erase gate structure becomes rounded due to oxidation in the subsequent process, thereby helping to reduce the impact on the erase efficiency, and further to help ensure the performance of the semiconductor structure.

[0037] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0038] Figure 2 It is a structural schematic diagram of an embodiment of a semiconductor structure of the present invention.

[0039] The semiconductor structure includes: a substrate 100, including a memory cell region 100S; a stacked gate structure 500, located on the substrate 100 in the memory cell region 100S, the stacked gate structure 500 including a floating gate structure 240, and a control gate structure 220 located on the floating gate structure 240, the floating gate structure 240 protrudes outward relative to the side wall of the control gate structure 220, and at the protruding portion of the floating gate structure 240, the top surface of the floating gate structure 240 forms an acute angle with the side wall; an erase gate structure 250, located on the substrate 100 on the side of the floating gate structure 240 protruding outward in the memory cell region 100S, the erase gate structure 250 covers the top surface and side wall of the floating gate structure 240 exposed by the control gate structure 220.

[0040] In this embodiment, the semiconductor structure is a Flash memory, specifically, a Nor Flash memory, and the Flash memory is a non-volatile storage device.

[0041] Specifically, in this embodiment, the semiconductor structure is a split-gate memory.

[0042] The substrate 100 provides a process operation basis for the formation process of the semiconductor structure.

[0043] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may be one or more of germanium, silicon germanium, silicon carbide, gallium arsenide and indium gallium. The substrate may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0044] The memory cell region 100S is used to form a split-gate memory structure composed of a floating gate structure 240 , a coupling gate (CG) structure 220 , and an erase gate (EG) structure.

[0045] In this embodiment, a word line (WL) region is located between adjacent memory cell regions 100S, and a gate structure for controlling channel electrons is formed in the WL region.

[0046] In this embodiment, an isolation layer 110 is further formed between the substrate 100 and the stacked gate structure 500 , for isolating the stacked gate structure 500 from the substrate 100 , and isolating the erase gate structure 250 from the substrate 100 .

[0047] The stacked gate structure 500 is used to implement signal writing of the memory. Specifically, the floating gate structure 240 is used as a unit structure for storing data in the memory, and the control gate structure 220 is used to electrically connect to the outside to control the longitudinal electric field of the floating gate structure 240 .

[0048] Specifically, a high voltage is applied to the gate structure of the WL region to open the channel, and a high voltage is applied to the control gate 220 to create a strong vertical electric field between the floating gate structure 240 and the control gate structure 220. The strong vertical electric field accelerates the channel electrons in the vertical direction, and a portion of the electrons pass through the isolation layer 110 and are injected into the floating gate structure 240, thereby realizing electron injection and signal writing.

[0049] The erase gate structure 250 is used to implement signal erasure of the memory.

[0050] Specifically, by applying a high voltage to the erase gate structure 250, a potential difference is formed on the first dielectric layer between the erase gate structure 250 and the floating gate structure 240 due to the coupling capacitance, and the electrons in the floating gate structure 240 can be pulled to the erase gate structure 250 through tunneling. As the electrons in the floating gate structure 240 are pulled out, the potential of the floating gate structure 240 increases, and the difference between its potential and the erase gate structure 250 will decrease, weakening the potential difference between the first dielectric layer, and finally the electrons in the floating gate structure 240 are completely pulled out, realizing the signal erasure of the memory.

[0051] In this embodiment, one side of the floating gate structure 240 protrudes outward relative to the side wall of the control gate structure 220, and at the protruding portion of the floating gate structure 240, the top surface of the floating gate structure 240 forms an acute angle with the side wall, and the erase gate structure 250 is located on the substrate 100 on the side of the floating gate structure 240 protruding outward in the memory cell region 100S, and the erase gate structure 250 covers the top surface and side wall of the floating gate structure 240 exposed by the control gate structure 220, that is, the erase gate structure 250 covers the acute angle portion of the floating gate structure 240, and the floating gate structure 240 extends into the erase gate structure 250. The portion of the floating gate structure 240 extending into the erase gate structure 250 is an acute angle, and the electric field at the acute angle is larger, which is beneficial to reducing the energy band barrier from the floating gate structure 240 to the erase gate structure 250, and electrons can more easily reach the erase gate structure 250 from the floating gate structure 240, which is beneficial to improving the writing and erasing efficiency of the semiconductor structure. Moreover, the portion of the floating gate structure 240 extending into the erase gate structure 250 is an acute angle, which is beneficial to reducing the degree to which the portion of the floating gate structure 240 extending into the erase gate structure 250 becomes rounded due to oxidation in subsequent processes, thereby helping to reduce the impact on the erasure efficiency, and further helping to ensure the performance of the semiconductor structure.

[0052] Moreover, in the present embodiment, one side of the floating gate structure 240 protrudes outward relative to the side wall of the control gate structure 220, which is beneficial to the formation of the acute angle portion of the floating gate structure 240, and is also beneficial to making the floating gate structure 240 extend further into the erase gate structure, thereby increasing the active area of ​​the floating gate structure 240 and the erase gate structure and improving the erase efficiency.

[0053] In this embodiment, the memory cell region 100S includes two stacked gate structures 500 . The acute angles of the floating gate structures 240 of the two stacked gate structures 500 are arranged opposite to each other, and the sidewalls of the floating gate structures 240 facing away from the acute angles are perpendicular to the substrate 100 .

[0054] The storage cell area 100S includes two stacked gate structures 500, and the acute angles of the floating gate structures 240 of the two stacked gate structures 500 are relatively set, so that in the storage cell area 100S, two floating gate structures 240 are used simultaneously to write signals, which is beneficial to improving the efficiency of signal writing. Moreover, the side wall of the floating gate structure 240 facing away from the acute angle is perpendicular to the substrate 100, so the contact structure between the floating gate structure 240 and the gate structure of the WL area is not changed, thereby reducing the changes to the current semiconductor structure.

[0055] In this embodiment, two adjacent stacked gate structures 500 share the same erase gate structure 250 .

[0056] Two adjacent stacked gate structures 500 share the same erase gate structure 250 , and two floating gate structures 240 are used simultaneously to perform signal erasure, which is beneficial to improving the efficiency of signal erasure.

[0057] It should be noted that, in the present embodiment, the ratio of the distance t from the acute angle of the floating gate structure 240 to the side wall of the control gate structure 220 to the total width of the erase gate structure 250 should not be too large or too small. If the ratio of the distance t from the acute angle of the floating gate structure 240 to the side wall of the control gate structure 220 to the total width of the erase gate structure 250 is too large, it is easy to cause the floating gate structure 240 to extend too much into the position where the erase gate structure 250 is formed, and it is easy to cause the formation space of the erase gate structure 250 to be too small, affecting the formation of the erase gate structure 250; if the ratio of the distance t from the acute angle of the floating gate structure 240 to the side wall of the control gate structure 220 to the total width of the erase gate structure 250 is too small, it is easy to cause the floating gate structure 240 to extend too little into the erase gate structure 250, affecting the signal erasing work between the floating gate structure 240 and the erase gate structure 250. To this end, in this embodiment, the distance t from the acute top angle of the floating gate structure 240 to the sidewall of the control gate structure 220 is one third to two thirds of the total width of the erase gate structure 250 .

[0058] It should also be noted that, in the present embodiment, in the protruding portion of the floating gate structure 240, the acute angle α formed by the top surface of the floating gate structure 240 and the side wall should not be too small. If the acute angle α formed by the top surface of the floating gate structure 240 and the side wall in the protruding portion of the floating gate structure 240 is too small, it is easy to cause the acute angle portion of the floating gate structure 240 to break, affecting the performance of the semiconductor structure, and it is also easy to cause difficulties in the subsequent formation of the film layer covering the acute angle portion of the floating gate structure 240, affecting the formation of the semiconductor structure. For this reason, in the present embodiment, in the protruding portion of the floating gate structure 240, the acute angle α formed by the top surface of the floating gate structure 240 and the side wall is greater than or equal to 30°.

[0059] In this embodiment, the material of the floating gate structure 240 includes polysilicon; the material of the control gate structure 220 includes polysilicon; and the material of the erase gate structure 250 includes polysilicon.

[0060] In this embodiment, the semiconductor structure further includes: a first dielectric layer 120 located between the floating gate structure 240 and the control gate structure 220 .

[0061] The first dielectric layer 120 is used to isolate the floating gate structure 240 from the control gate structure 220 .

[0062] In this embodiment, the first dielectric layer 120 is an Oxide-Nitride-Oxide (ONO) structure of a silicon oxide layer, a silicon nitride layer on the silicon oxide layer, and a silicon oxide layer on the silicon nitride layer.

[0063] In this embodiment, the semiconductor structure further includes: a second dielectric layer 140 located between the floating gate structure 240 and the erase gate structure 250 , and between the control gate structure 220 and the erase gate structure 250 .

[0064] The second dielectric layer 140 is used to isolate the floating gate structure 240 from the erase gate structure 250 , and to isolate the control gate structure 220 from the erase gate structure 250 .

[0065] In this embodiment, the material of the second dielectric layer 240 includes silicon oxide.

[0066] In this embodiment, the semiconductor structure further includes: a protection spacer 310 covering the sidewall of the control gate structure 220 .

[0067] The protection spacer 310 is used to protect the sidewall of the control gate structure 220 .

[0068] In this embodiment, the protective spacer 310 is a silicon oxide layer and a silicon nitride layer covering the silicon oxide layer.

[0069] In this embodiment, the semiconductor structure further includes: a hard mask layer 130 located on the top of the control gate structure 220 .

[0070] The hard mask layer 130 is used as an etching mask for forming the control gate structure 220 .

[0071] In the present embodiment, the hard mask layer 130 is a silicon nitride layer, a silicon oxide layer on the silicon nitride layer, and a silicon nitride layer on the silicon oxide layer. The structure is a nitride-oxide-nitride (NON) structure.

[0072] Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure.

[0073] Figures 3 to 12 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0074] refer to Figure 3 , providing a substrate including a memory cell region 100S.

[0075] In this embodiment, the semiconductor structure is a Flash memory, specifically, a Nor Flash memory, and the Flash memory is a non-volatile storage device.

[0076] Specifically, in this embodiment, the semiconductor structure is a split-gate memory.

[0077] The substrate 100 provides a process operation basis for the formation process of the semiconductor structure.

[0078] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may be one or more of germanium, silicon germanium, silicon carbide, gallium arsenide and indium gallium. The substrate may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0079] The memory cell region 100S is used to form a split-gate memory structure consisting of a floating gate structure, a coupling gate (CG) structure, and an erase gate (EG) structure.

[0080] In this embodiment, a word line (WL) region is located between adjacent memory cell regions 100S, and a gate structure for controlling channel electrons is formed in the WL region.

[0081] In the present embodiment, in the step of providing the substrate 100 , the memory cell region 100S includes a preset region for subsequently forming an erase gate structure.

[0082] In this embodiment, an isolation layer 110 is further formed on the substrate 100 to isolate the subsequently formed stacked gate structure from the substrate 100 , and the subsequently formed isolated erase gate structure from the substrate 100 .

[0083] Combined with reference Figures 3 to 10 A stacked gate structure 500 is formed on the substrate 100 of the storage cell region 100S. The stacked gate structure 500 includes a floating gate structure 240 and a control gate structure 220 located on the floating gate structure 240. One side of the floating gate structure 240 protrudes outward relative to the side wall of the control gate structure 220, and at the protruding portion of the floating gate structure 240, the top surface of the floating gate structure 240 forms an acute angle with the side wall.

[0084] The stacked gate structure 500 is used to implement signal writing of the memory. Specifically, the floating gate structure 240 is used as a unit structure for storing data in the memory, and the control gate structure 220 is used to electrically connect to the outside to control the longitudinal electric field of the floating gate structure 240 .

[0085] Specifically, a high voltage is applied to the gate structure of the WL region to open the channel, and a high voltage is applied to the control gate 220 to create a strong vertical electric field between the floating gate structure 240 and the control gate structure 220. The strong vertical electric field accelerates the channel electrons in the vertical direction, and a portion of the electrons pass through the isolation layer 110 and are injected into the floating gate structure 240, thereby realizing electron injection and signal writing.

[0086] In the present embodiment, one side of the floating gate structure 240 protrudes outward relative to the side wall of the control gate structure 220, and at the protruding portion of the floating gate structure 240, the top surface of the floating gate structure 240 forms an acute angle with the side wall, and the subsequently formed erase gate structure covers the top surface and side wall of the floating gate structure 240 exposed by the control gate structure 220, that is, the erase gate structure covers the acute angle portion of the floating gate structure 240, and the portion of the floating gate structure 240 extending into the erase gate structure is an acute angle, and the electric field at the acute angle is large, which is beneficial to reducing the energy band barrier from the floating gate structure 240 to the erase gate structure, and electrons can more easily reach the erase gate structure from the floating gate structure 240, which is beneficial to improving the writing and erasing efficiency of the semiconductor structure. Moreover, the portion of the floating gate structure 240 extending into the erase gate structure is an acute angle, which is beneficial to reducing the degree to which the portion of the floating gate structure 240 extending into the erase gate structure becomes rounded due to oxidation in the subsequent process, thereby helping to reduce the impact on the erase efficiency, and further to help ensure the performance of the semiconductor structure.

[0087] Moreover, in the present embodiment, one side of the floating gate structure 240 protrudes outward relative to the side wall of the control gate structure 220, which is beneficial to the formation of the acute angle portion of the floating gate structure 240, and is also beneficial to making the floating gate structure 240 extend further into the erase gate structure, thereby increasing the active area of ​​the floating gate structure 240 and the erase gate structure and improving the erase efficiency.

[0088] It should be noted that, in the present embodiment, in the protruding portion of the floating gate structure 240, the acute angle α formed by the top surface of the floating gate structure 240 and the side wall should not be too small. If the acute angle α formed by the top surface of the floating gate structure 240 and the side wall in the protruding portion of the floating gate structure 240 is too small, it is easy to cause the acute angle portion of the floating gate structure 240 to break, affecting the performance of the semiconductor structure, and it is also easy to cause difficulties in the subsequent formation of the film layer covering the acute angle portion of the floating gate structure 240, affecting the formation of the semiconductor structure. For this reason, in the present embodiment, in the protruding portion of the floating gate structure 240, the acute angle α formed by the top surface of the floating gate structure 240 and the side wall is greater than or equal to 30°.

[0089] In this embodiment, the material of the floating gate structure 240 includes polysilicon; the material of the control gate structure 220 includes polysilicon.

[0090] In this embodiment, in the step of forming the stacked gate structure 500 , the memory cell region 100S includes two stacked gate structures 500 , the acute angles of the floating gate structures 240 of the two stacked gate structures 500 are arranged opposite to each other, and the sidewalls of the floating gate structures 240 facing away from the acute angles are perpendicular to the substrate 100 .

[0091] The storage cell area 100S includes two stacked gate structures 500, and the acute angles of the floating gate structures 240 of the two stacked gate structures 500 are relatively set, so that in the storage cell area 100S, two floating gate structures 240 are used simultaneously to write signals, which is beneficial to improving the efficiency of signal writing. Moreover, the side wall of the floating gate structure 240 facing away from the acute angle is perpendicular to the substrate 100, so the contact structure between the floating gate structure 240 and the gate structure of the WL area is not changed, thereby reducing the changes to the current semiconductor structure.

[0092] In this embodiment, in the step of forming the stacked gate structure 500 on the substrate 100 of the memory cell region 100S, a first dielectric layer 120 is formed between the floating gate structure 240 and the control gate structure 220 .

[0093] The first dielectric layer 120 is used to isolate the floating gate structure 240 from the control gate structure 220 .

[0094] In this embodiment, the first dielectric layer 120 is an Oxide-Nitride-Oxide (ONO) structure of a silicon oxide layer, a silicon nitride layer on the silicon oxide layer, and a silicon oxide layer on the silicon nitride layer.

[0095] Combined with reference Figure 3 and Figure 4 The steps of forming the stacked gate structure 500 include: forming a first gate material layer 200 (eg, Figure 3 ), and a second gate material layer 210 (as shown) located on the first gate material layer 200 Figure 4 shown).

[0096] The first gate material layer 200 is used to form a floating gate structure 240 , and the second gate material layer 210 is used to form a control gate structure 220 .

[0097] Specifically, in this embodiment, the first gate material layer 200 covers the isolation layer 110 .

[0098] Correspondingly, in this embodiment, the material of the first gate material layer 200 includes polysilicon; the material of the second gate material layer 210 includes polysilicon.

[0099] Specifically, in this embodiment, after forming the first gate material layer 200 and before forming the second gate material layer 210 , the method further includes: forming a first dielectric layer 120 covering the first gate material layer 200 .

[0100] In this embodiment, after forming the second gate material layer 210 , the method further includes: forming a hard mask layer 130 covering the second gate material layer 210 .

[0101] The hard mask layer 130 is used as an etching mask for forming the control gate structure 220 .

[0102] In the present embodiment, the hard mask layer 130 is a silicon nitride layer, a silicon oxide layer on the silicon nitride layer, and a silicon nitride layer on the silicon oxide layer. The structure is a nitride-oxide-nitride (NON) structure.

[0103] refer to Figure 5 , patterning the second gate material layer 210 , retaining the remaining second gate material layer 210 protruding from the first gate material layer 200 in the memory cell region 100S as a control gate structure 220 .

[0104] Specifically, in this embodiment, the step of patterning the second gate material layer 210 includes: patterning the hard mask layer 130 so that the remaining hard mask layer 130 is separated on the second gate material layer 210; patterning the second gate material layer 210 using the remaining hard mask layer 130 as a mask to form a control gate structure 220.

[0105] Accordingly, in this embodiment, in the step of patterning the second gate material layer 210 , the first dielectric layer 120 is also patterned, and the first dielectric layer 120 located at the bottom of the control gate structure 220 is retained.

[0106] refer to Figure 6 Before patterning the first gate material layer 200 that exposes the control gate structure 220 , the method further includes: forming a protective spacer 310 on the sidewall of the control gate structure 220 .

[0107] The protective spacer 310 is used to protect the sidewall of the control gate structure 220 , and is also used as an etching mask for subsequent patterning of the first gate material layer 200 .

[0108] Specifically, in this embodiment, the protection spacer 310 extends to cover the sidewalls of the hard mask layer 130 and the first dielectric layer 120 .

[0109] In this embodiment, the protective spacer 310 is a silicon oxide layer and a silicon nitride layer covering the silicon oxide layer.

[0110] Combined with reference Figures 6 to 10 , the first gate material layer 200 exposed by the control gate structure 220 is patterned to form a floating gate structure 240 .

[0111] Specifically, in conjunction with reference Figure 6 and Figure 7 The step of patterning the first gate material layer 200 exposed by the control gate structure 220 to form the floating gate structure 240 includes: forming a mask sidewall 320 on the sidewall of the control gate structure 220 facing the preset area.

[0112] The mask sidewall 320 is used as an etching mask for patterning the first gate material layer 200, and is also used to occupy a portion of the top surface of the first gate material layer 200 to provide a process window for obtaining a floating gate structure 240 that protrudes outward relative to the side wall of the control gate structure 220. At the same time, the acute angle portion of the floating gate structure 240 will be obtained at the position of the first gate material layer 320 below the mask sidewall 320, and it is also used to reserve space for converting the right-angle top angle into an acute angle.

[0113] The preset region is subsequently used to form an erase gate structure, and a mask spacer 320 is formed on the sidewall of the control gate structure 220 facing the preset region, so that the acute angle portion of the obtained floating gate structure 240 points to the erase gate structure.

[0114] Accordingly, in this embodiment, in the step of forming the mask spacer 320 on the sidewall of the control gate structure 220 facing the preset area, the mask spacer 320 covers the protection spacer 310 .

[0115] In this embodiment, the material of the mask spacer 320 includes silicon oxide.

[0116] Accordingly, in this embodiment, the protection spacer 310 and the mask spacer 320 form an Oxide-Nitride-Oxide (ONO) structure.

[0117] It should be noted that, in this embodiment, in the step of forming the mask sidewall 320 on the sidewall of the control gate structure 220 facing the preset area, the ratio of the thickness t of the mask sidewall 320 to the preset total width of the erase gate structure should not be too large or too small. If the thickness t of the mask sidewall 320 accounts for too large a proportion of the preset total width of the erase gate structure, the distance from the acute angle of the gate structure 240 to the side wall of the control gate structure 220 accounts for too large a proportion of the preset total width of the erase gate structure, which may easily cause the floating gate structure 240 to extend too far into the position where the erase gate structure is formed, which may easily cause the formation space of the erase gate structure to be too small, affecting the formation of the erase gate structure 250; if the thickness t of the mask sidewall 320 accounts for too small a proportion of the preset total width of the erase gate structure, it may easily cause the process window for obtaining the floating gate structure 240 protruding outward relative to the side wall of the control gate structure 220 to be too small, affecting the acquisition of the acute angle portion of the floating gate structure 240, and also causing the distance from the acute angle of the floating gate structure 240 to the side wall of the control gate structure 220 to account for too small a proportion of the preset total width of the erase gate structure, which may easily cause the portion of the floating gate structure 240 that subsequently extends into the erase gate structure to be too small, affecting the signal erasure work between the floating gate structure 240 and the erase gate structure. To this end, in this embodiment, in the step of forming the mask spacer 320 on the sidewall of the control gate structure 220 facing the preset area, the thickness t of the mask spacer 320 is one third to two thirds of the preset total width of the erase gate structure.

[0118] refer to Figure 6 In this embodiment, the step of forming a mask spacer 300 on the sidewall of the control gate structure 220 facing the preset area includes: forming a spacer material layer 300 covering the sidewall of the control gate structure 220 .

[0119] The spacer material layer 300 is used to form a mask spacer 320 .

[0120] refer to Figure 7 , remove the sidewall material layer 300 of the control gate structure 220 facing away from the preset area, and retain the sidewall material layer 300 of the control gate structure 220 facing the preset area as the mask sidewall 320.

[0121] Specifically, in this embodiment, a blocking layer of the sidewall material layer 300 is formed to block the sidewall of the control gate structure 220 facing the preset area; using the blocking layer as a mask, the sidewall material layer 300 of the sidewall of the control gate structure 220 facing away from the preset area is removed; the blocking layer is removed, and the sidewall material layer 300 of the sidewall of the control gate structure 220 facing the preset area is retained as a mask sidewall 320.

[0122] Combined with reference Figures 8 to 10 , using the mask sidewall 320 as a mask, the first gate material layer 200 exposed by the mask sidewall 320 in the preset area is patterned to form a floating gate structure 240 .

[0123] Specifically, refer to Figure 8 The step of patterning the first gate material layer 200 exposed by the mask sidewall 320 in the preset area using the mask sidewall 320 as a mask includes: patterning the first gate material layer 200 using the mask sidewall 320 and the control gate structure 220 as masks to form an initial gate structure 230 whose sidewalls are perpendicular to the substrate 100.

[0124] The initial gate structure 230 is used to form the floating gate structure 240. Specifically, the sidewalls of the initial gate structure 230 are perpendicular to the substrate 100. That is, the initial gate structure 230 exposes the sidewalls and has a right angle, which is used to subsequently convert the right angle into an acute angle.

[0125] Specifically, in this embodiment, the first gate material layer 200 is patterned using the mask sidewall 320 and the protection sidewall 310 of the control gate structure 220 facing away from the mask sidewall 320 as masks to form an initial gate structure 230 with sidewalls perpendicular to the substrate 100 .

[0126] In this embodiment, an anisotropic dry etching process is used to pattern the first gate material layer 200 to form an initial gate structure 230 whose sidewalls are perpendicular to the substrate 100 .

[0127] The anisotropic dry etching process is more directional, and the etching rate in the longitudinal direction is much greater than the etching rate in the lateral direction, which is conducive to obtaining an initial gate structure 230 with higher surface quality and higher dimensional accuracy, so that the sidewall verticality of the initial gate structure 230 is better.

[0128] Combined with reference Fig. 9 and Fig.10 , the sidewall of the initial gate structure 230 facing the preset area is laterally processed so that the top surface of the initial gate structure 230 forms an acute angle with the sidewall and serves as the floating gate structure 240.

[0129] Specifically, refer to Fig. 9 The step of laterally processing the sidewalls of the initial gate structure 230 facing the preset area includes: forming a protective layer 400 covering the control gate structure 220 and the sidewalls of the initial gate structure 230 facing away from the mask sidewalls, the protective layer 400 having an opening 410 exposing the mask sidewalls 320 and the sidewalls of the initial gate structure 230 facing the preset area.

[0130] The protection layer 400 is used to protect the control gate structure 220 and the sidewalls of the initial gate structure 230 facing away from the mask sidewalls from being damaged during the lateral processing of the initial gate structure 230 . The opening 410 is used as a mask opening for the lateral processing of the initial gate structure 230 .

[0131] refer to Fig.10 , the sidewalls of the initial gate structure 230 are laterally processed along the opening 410 .

[0132] Specifically, in this embodiment, an isotropic wet etching process is used to perform lateral processing on the sidewalls of the initial gate structure 230 .

[0133] The isotropic wet etching process has a relatively close etching rate in the longitudinal direction and the etching rate in the lateral direction. Therefore, the isotropic wet etching process can simultaneously perform longitudinal etching and lateral etching along the side wall of the initial gate structure 230. At the same time, in the etching solution, due to factors such as gravity deposition, the etching solution concentration at the bottom is greater than the etching solution concentration at the top. Therefore, in the process of performing lateral processing on the side wall of the initial gate structure 230 using the isotropic wet etching process, the etching rate at the bottom of the initial gate structure 230 is faster than the etching rate at the top, and lateral undercutting occurs at the bottom of the initial gate structure 230, thereby obtaining a morphology of an inclined side wall in which the top size of the initial gate structure 230 is larger than the bottom size, that is, obtaining a floating gate structure 240 in which the top surface and the side wall form an acute angle.

[0134] In this embodiment, the etching solution used in the wet etching process includes a NaOH solution or a KOH solution.

[0135] In this embodiment, the material of the initial gate structure 230 is polysilicon. Therefore, using NaOH solution or KOH solution as the etching solution of the wet etching process is conducive to etching the polysilicon material and it is easy to obtain the floating gate structure 240 with a top surface and sidewalls forming an acute angle.

[0136] refer to Fig.11 After forming the stacked gate structure 500 , the method further includes: removing the mask sidewall 320 .

[0137] The mask sidewall 320 is removed to expose the acute angle of the floating gate structure 230 , so that the erase gate structure formed subsequently can cover the acute angle of the floating gate structure 230 , increase the interaction area of ​​the floating gate structure 240 and the erase gate structure, and improve the erase efficiency.

[0138] refer to Fig.12 Before the erase gate structure is subsequently formed, the method further includes: covering the sidewall of the control gate structure 220 and the portion of the floating gate structure 240 exposed by the control gate structure 220 with a second dielectric layer 140 .

[0139] The second dielectric layer 140 is used to isolate the floating gate structure 240 from an erase gate structure formed subsequently, and to isolate the control gate structure 220 from an erase gate structure formed subsequently.

[0140] In this embodiment, the material of the second dielectric layer 240 includes silicon oxide.

[0141] Continue to refer Fig.12 An erase gate structure 250 is formed on the substrate 100 on the side of the floating gate structure 240 protruding outward in the memory cell region 100S, and the erase gate structure 250 covers the top surface and sidewalls of the floating gate structure 240 exposed by the control gate structure 220 .

[0142] The erase gate structure 250 is used to implement signal erasure of the memory.

[0143] Specifically, by applying a high voltage to the erase gate structure 250, a potential difference is formed on the first dielectric layer between the erase gate structure 250 and the floating gate structure 240 due to the coupling capacitance, and the electrons in the floating gate structure 240 can be pulled to the erase gate structure 250 through tunneling. As the electrons in the floating gate structure 240 are pulled out, the potential of the floating gate structure 240 increases, and the difference between its potential and the erase gate structure 250 will decrease, weakening the potential difference between the first dielectric layer, and finally the electrons in the floating gate structure 240 are completely pulled out, realizing the signal erasure of the memory.

[0144] In this embodiment, in the step of forming the erase gate structure 250 , two adjacent stacked gate structures 500 share the same erase gate structure 250 .

[0145] Two adjacent stacked gate structures 500 share the same erase gate structure 250 , and two floating gate structures 240 are used simultaneously to perform signal erasure, which is beneficial to improving the efficiency of signal erasure.

[0146] In this embodiment, the material of the erase gate structure 250 includes polysilicon.

[0147] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: a substrate including a storage unit region; A stacked gate structure, located on the substrate of the memory cell region, the stacked gate structure comprising a floating gate structure and a control gate structure located on the floating gate structure, one side of the floating gate structure protrudes outward relative to the side wall of the control gate structure, and at the protruding portion of the floating gate structure, the top surface of the floating gate structure forms an acute angle with the side wall; The erase gate structure is located on the substrate on the side of the floating gate structure protruding outward in the memory cell area, and the erase gate structure covers the top surface and sidewalls of the floating gate structure exposed by the control gate structure.

2. The semiconductor structure according to claim 1, wherein: The memory cell region comprises two stacked gate structures, the acute angles of the floating gate structures of the two stacked gate structures are arranged opposite to each other, and the sidewalls of the floating gate structures facing away from the acute angles are perpendicular to the substrate; Two adjacent stacked gate structures share the same erase gate structure.

3. The semiconductor structure according to claim 1 or 2, characterized in that: The distance from the acute top angle of the floating gate structure to the side wall of the control gate structure is one third to two thirds of the total width of the erase gate structure.

4. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes: a first dielectric layer located between the floating gate structure and the control gate structure; The second dielectric layer is located between the floating gate structure and the erase gate structure, and between the control gate structure and the erase gate structure.

5. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes: a protective sidewall covering the sidewall of the control gate structure.

6. The semiconductor structure according to claim 1, wherein: In the protruding portion of the floating gate structure, an acute angle formed by a top surface and a side wall of the floating gate structure is greater than or equal to 30°.

7. The semiconductor structure according to claim 1, wherein: The material of the floating gate structure includes polysilicon; the material of the control gate structure includes polysilicon; and the material of the erase gate structure includes polysilicon.

8. A method for forming a semiconductor structure, characterized in that: include: providing a substrate including a memory cell region; A stacked gate structure is formed on the substrate of the memory cell region, wherein the stacked gate structure includes a floating gate structure and a control gate structure located on the floating gate structure, wherein one side of the floating gate structure protrudes outward relative to the side wall of the control gate structure, and at the protruding portion of the floating gate structure, the top surface of the floating gate structure forms an acute angle with the side wall; An erase gate structure is formed on the substrate at a side of the floating gate structure protruding outward in the memory cell region, and the erase gate structure covers the top surface and sidewalls of the floating gate structure exposed by the control gate structure.

9. The method for forming a semiconductor structure according to claim 8, wherein: In the step of forming the stacked gate structure, two stacked gate structures are formed in the memory cell region, the acute angles of the floating gate structures of the two stacked gate structures are arranged opposite to each other, and the sidewalls of the floating gate structures facing away from the acute angles are perpendicular to the substrate; In the step of forming the erase gate structure, two adjacent stacked gate structures share the same erase gate structure.

10. The method for forming a semiconductor structure according to claim 8 or 9, characterized in that: The step of forming the stacked gate structure includes: forming a first gate material layer covering the substrate, and a second gate material layer located on the first gate material layer; Patterning the second gate material layer, and retaining the remaining second gate material layer protruding from the first gate material layer in the memory cell area as the control gate structure; The first gate material layer exposed by the control gate structure is patterned to form the floating gate structure.

11. The method for forming a semiconductor structure according to claim 10, wherein: In the step of providing the substrate, the memory cell region includes a preset area for forming an erase gate structure; The step of patterning the first gate material layer exposed by the control gate structure to form the floating gate structure includes: forming a mask sidewall on the sidewall of the control gate structure facing the preset area; The mask sidewall is used as a mask to perform patterning on the first gate material layer in the preset area exposed by the mask sidewall to form the floating gate structure.

12. The method for forming a semiconductor structure according to claim 11, wherein: The step of forming a mask sidewall on the sidewall of the control gate structure facing the preset area includes: forming a sidewall material layer covering the sidewall of the control gate structure; The sidewall material layer of the control gate structure facing away from the preset area is removed, and the sidewall material layer of the control gate structure facing the preset area is retained as the mask sidewall.

13. The method for forming a semiconductor structure according to claim 11, wherein: In the step of forming the mask sidewalls, the thickness of the mask sidewalls is one third to two thirds of the preset total width of the erase gate structure.

14. The method for forming a semiconductor structure according to claim 11, wherein: Before patterning the first gate material layer exposed by the control gate structure, the method further includes: forming a protective sidewall on the sidewall of the control gate structure; In the step of forming a mask sidewall on the sidewall of the control gate structure facing the preset area, the mask sidewall covers the protection sidewall.

15. The method for forming a semiconductor structure according to claim 11, wherein: The step of patterning the first gate material layer exposed by the mask sidewall in the preset area using the mask sidewall as a mask comprises: patterning the first gate material layer using the mask sidewall and the control gate structure as a mask to form an initial gate structure with a sidewall perpendicular to the substrate; The sidewall of the initial gate structure facing the preset region is laterally processed so that the top surface of the initial gate structure forms an acute angle with the sidewall and serves as the floating gate structure.

16. The method for forming a semiconductor structure according to claim 15, wherein: The first gate material layer is patterned by an anisotropic dry etching process.

17. The method for forming a semiconductor structure according to claim 15, wherein: The step of laterally processing the sidewall of the initial gate structure facing the preset area includes: forming a protection layer covering the control gate structure and the sidewall of the initial gate structure facing away from the mask sidewall, the protection layer having an opening exposing the mask sidewall and the sidewall of the initial gate structure facing the preset area; The lateral processing is performed on the sidewall of the initial gate structure along the opening.

18. The method for forming a semiconductor structure according to claim 17, wherein: The sidewalls of the initial gate structure are lateral-processed by an isotropic wet etching process.

19. The method for forming a semiconductor structure according to claim 18, wherein: The etching solution used in the wet etching process includes NaOH solution or KOH solution.

20. The method for forming a semiconductor structure according to claim 8, wherein: In the step of forming a stacked gate structure on the substrate of the memory cell region, a first dielectric layer is formed between the floating gate structure and the control gate structure; Before forming the erase gate structure, the method further includes: covering the sidewalls of the control gate structure and the portion of the floating gate structure exposed by the control gate structure with a second dielectric layer.

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