Fabricating slot structures in three-dimensional semiconductor devices

Abstract

Systems, devices, and methods for fabricating slot structures in three-dimensional (3D) semiconductor devices are provided. In one aspect, a method includes providing a semiconductor structure including a first region including a first trench structure and a second region including a second trench structure, the semiconductor structure includes a first sacrificial film covering the first trench structure, and a second sacrificial film formed on a surface of the second trench structure from an opening of the second trench structure to a bottom of the second trench structure in a first direction. At least one portion of the second sacrificial film is etched while at least one portion of the first sacrificial film remains to cover the first trench structure.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices and manufacturing processes for semiconductor devices. Background Art

[0002] Semiconductor devices (e.g., memory devices) can have various structures to increase the density of memory cells and lines on a chip. For example, three-dimensional (3D) memory devices have attracted attention due to their ability to increase array density by stacking more layers within a similar footprint. 3D memory devices typically include a memory array of memory cells and peripheral circuits for facilitating the operation of the memory array. The memory cells may include a vertical structure. Summary of the invention

[0003] The present disclosure describes methods, devices, systems, and techniques for managing vertical structures in three-dimensional (3D) semiconductor devices.

[0004] One aspect of the present disclosure is characterized by a method, comprising: providing a semiconductor structure including a first region and a second region, the first region including a first trench structure, the second region including a second trench structure, wherein the semiconductor structure includes: a first sacrificial film covering the first trench structure, and a second sacrificial film formed on a surface of the second trench structure from an opening of the second trench structure to a bottom of the second trench structure along a first direction. At least a portion of the second sacrificial film is etched, while at least a portion of the first sacrificial film remains to cover the first trench structure.

[0005] In some embodiments, the first trench structure is coupled to the second trench structure, and wherein the first sacrificial film is coupled to the second sacrificial film.

[0006] In some embodiments, along a second direction perpendicular to the first direction, the first trench structure has a smaller width than the second trench structure.

[0007] In some embodiments, the method includes depositing a sacrificial material over the first trench structure and the second trench structure to fill the sacrificial material in the first trench structure and form a first sacrificial film covering the filled sacrificial material in the first trench structure, and forming a second sacrificial film having a first portion located on the top surface of the second region and a second portion located on the inner surface of the second trench structure.

[0008] In some embodiments, the second sacrificial film includes a first portion located on the top surface of the second region and a second portion located on the inner surface of the second trench structure, and wherein etching at least a portion of the second sacrificial film includes etching the second portion of the second sacrificial film from the inner surface of the second trench structure.

[0009] In some embodiments, the method includes changing at least one property of a region of sacrificial material, wherein the region of the sacrificial material includes at least one of the first portion of the second sacrificial film or the first sacrificial film.

[0010] In some embodiments, changing the at least one property of the region of the sacrificial material includes implanting ions into the region of the sacrificial material to change an etch rate of the region of the sacrificial material.

[0011] In some embodiments, implanting the ions into the region of the sacrificial material includes: controlling at least one of ion implantation power, ion implantation angle, or ion implantation density to implant the ions into the region of the sacrificial material.

[0012] In some embodiments, the sacrificial material includes at least one of polysilicon or aluminum oxide, and wherein the ions include at least one of nitrogen, argon, carbon, or boron.

[0013] In some embodiments, the sacrificial material includes polysilicon, and the method further includes injecting ions into a region of the sacrificial material to convert the polysilicon in the region of the sacrificial material into non-polysilicon, thereby changing the etching rate of the region of the sacrificial material, wherein the region of the sacrificial material includes a first portion of a second sacrificial film located on a top surface of the second region.

[0014] In some embodiments, the second region includes a plurality of alternating sacrificial layers and insulating layers, and wherein the method further includes removing the sacrificial layers in the second region through the opening of the second trench structure after etching the at least one portion of the second sacrificial film.

[0015] Another aspect of the present disclosure is characterized by a semiconductor device, comprising: an array region, the array region comprising a first gap structure extending along a first direction; and a connection region, the connection region being adjacent to the array region along a second direction perpendicular to the first direction, wherein the connection region comprises a second gap structure, the second gap structure extending along the first direction through an insulating layer extending along the second direction, and wherein the insulating layer comprises an insulating material and ions distributed among the insulating material in the insulating layer.

[0016] In some embodiments, the semiconductor device includes a stack of conductive layers and isolation layers alternating with each other along the first direction, wherein each of the first gap structure and the second gap structure extends through the stack of conductive layers and isolation layers, and wherein the insulating layer is closer to an end of the second gap structure than the stack of conductive layers and isolation layers along the first direction.

[0017] In some embodiments, the connection region includes a plurality of contact structures extending through the stack of the conductive layers and the isolation layers, and at least one of the conductive layers is coupled to a corresponding contact structure of the plurality of contact structures.

[0018] In some embodiments, the connection region includes a first end and a second end opposite to each other along the first direction, and each of the plurality of contact structures is externally coupled to a conductive contact at the first end or the second end.

[0019] In some embodiments, the array region includes a plurality of channel structures extending through the stack of the conductive layer and the isolation layer.

[0020] In some embodiments, the first gap structure connects the second gap structure along the second direction, and along a third direction perpendicular to the first direction and the second direction, a width of the first gap structure is smaller than a width of the second gap structure.

[0021] In some embodiments, the insulating layer includes a first surface and a second surface along the first direction, the first surface is closer to an end of the second gap structure along the first direction than the second surface, and wherein a first concentration of the ions adjacent to the first surface is higher than a second concentration of the ions adjacent to the second surface of the insulating layer.

[0022] Another aspect of the present disclosure is characterized by a method, comprising: providing a semiconductor structure including a first region and a second region, the first region including a first trench structure, the second region including a second trench structure, wherein the semiconductor structure includes: a first sacrificial film covering the first trench structure, and a second sacrificial film formed on a surface of the second trench structure from an opening of the second trench structure to a bottom of the second trench structure, and wherein the second sacrificial film includes a first portion located on a top surface of the second region and a second portion located on an inner surface of the second trench structure. Changing at least one characteristic of a region of sacrificial material, wherein the region of the sacrificial material includes at least one of the first portion of the second sacrificial film or the first sacrificial film. Etching the second portion of the second sacrificial film from the inner surface of the second trench structure, while at least a portion of the first sacrificial film remains to cover the first trench structure.

[0023] In some embodiments, changing the at least one property of the region of the sacrificial material includes implanting ions into the region of the sacrificial material to change an etch rate of the region of the sacrificial material.

[0024] Embodiments of the present disclosure may provide one or more of the following technical advantages and / or benefits. For example, in some cases, during the etching process, the sacrificial material of the second trench structure may be etched, while the sacrificial material of the first trench structure may be retained or etched slower or less than the sacrificial material of the second trench structure. In some embodiments, the present technology may use a protective layer to cover the sacrificial material of the first trench structure while exposing the sacrificial material of the second trench structure. In some embodiments, the technology described herein can implant ions into the sacrificial material of the first trench structure, thereby reducing the etching rate of the sacrificial material of the first trench structure. Therefore, the sacrificial material of the first trench structure can be retained to a large extent, while the sacrificial material of the second trench structure is etched in the same etching process. Ion implantation-based technology can simplify the manufacturing process (for example, the technology can omit the steps of depositing and removing a dedicated protective layer). Therefore, the present technology can reduce the manufacturing cost of the semiconductor structure. The present technology can also alleviate the problem of oxide residue, which is a typical problem in the sacrificial material etching process. In some embodiments, the present technology can expand the time window for etching the sacrificial material, thereby simplifying the manufacturing process of the semiconductor structure.

[0025] The present technology can be applied to various types of semiconductor devices, volatile memory devices (e.g., DRAM memory devices) or non-volatile memory (NVM) devices, such as NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase change memory (PCM) such as phase change random access memory (PCRAM), spin transfer torque (STT)-magnetoresistive random access memory (MRAM), etc. The present technology can also be applied to charge trapping-based memory devices, such as silicon-oxide-nitride-oxide-silicon (SONOS) memory devices, and to floating gate-based memory devices. The present technology can also be applied to three-dimensional (3D) memory devices. The present technology can be applied to various memory types, such as SCL (single-level cell) devices, MLC (multi-level cell) devices like 2-level cell devices, TLC (three-level cell) devices, QLC (quadruple-level cell) devices, or PLC (five-level cell) devices. Additionally or alternatively, the present technology may be applied to various types of devices and systems, such as a secure digital (SD) card, an embedded multimedia card (eMMC) or a solid-state drive (SSD), an embedded system, and the like.

[0026] The details of one or more embodiments of the subject matter of the present disclosure are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings, which are incorporated herein and form a part of the present disclosure, illustrate various aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and enable one of ordinary skill in the relevant art to make and use the present disclosure.

[0028] Figure 1A is a top view of an exemplary 3D semiconductor structure.

[0029] Figure 1B Depicted along Figure 1A 2. A cross-sectional view of an exemplary 3D semiconductor structure along cut lines AA′ and BB′ shown in FIG.

[0030] Figure 2A-2E Structural cross-sectional views of exemplary semiconductor structures after various stages of the fabrication process are shown.

[0031] Figures 3A-3D Structural cross-sectional views of exemplary semiconductor structures after various stages of the fabrication process are shown.

[0032] Figure 4 is a flow chart of an exemplary process for forming a semiconductor structure.

[0033] Figure 5A block diagram of an exemplary system having one or more semiconductor devices is shown.

[0034] Like reference numbers and designations in the various drawings represent like elements.It is also to be understood that the various exemplary embodiments shown in the figures are merely illustrative representations and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0035] Figure 1A-1B An exemplary 3D semiconductor structure 100 is shown, wherein Figure 1A is a top view of an exemplary 3D semiconductor structure 100, and Figure 1B Depicted along Figure 1A 1 is a cross-sectional view of an exemplary 3D semiconductor structure 100 along cut lines AA′ and BB′ shown in FIG. The 3D semiconductor structure 100 may be used to manufacture a memory device, for example, a 3D NAND memory device.

[0036] In some embodiments, Figure 1A As shown in , the semiconductor structure 100 includes one or more array regions (e.g., array region 100A, array region 100C), and a connection region 100B, the connection region 100B being configured to provide a conductive connection to one or more array regions, for example, coupling the array region to a control circuit. In some examples, the semiconductor structure 100 includes two array regions 100A, 100C, wherein the connection region 100B is between the two array regions along a first horizontal direction (e.g., X direction). Each array region 100A, 100C includes an array of channel structures 140. The channel structure 140 can be used to form a string of memory cells, and the memory cells can be coupled in series along a vertical direction (e.g., Z direction) perpendicular to the first horizontal direction. The memory cell may include at least one vertical transistor. The vertical transistors of the memory cell may be stacked together along a second direction.

[0037] In some embodiments, Figure 1B As shown in , the semiconductor structure 100 includes a substrate 110 and a stack 130 of alternating conductive layers 130A and isolation layers 130B provided above the substrate 110. The substrate 110 can be any suitable semiconductor substrate having any suitable semiconductor material such as a single crystal semiconductor, a polycrystalline semiconductor, or a single crystal semiconductor. For example, the substrate 110 can include silicon, silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), silicon on insulator (SOI), germanium on insulator (GOI), gallium nitride, silicon carbide, III-V compounds, or any combination thereof. A contact structure 160 can be formed within the connection region 100B. The contact structure 160 can be configured to connect a corresponding one of the conductive layers within the array region 100A and / or the array region 100C to, for example, a control circuit.

[0038] The stack 130 may extend in a second horizontal direction (e.g., Y direction) parallel to the top surface of the substrate 110 and perpendicular to the first horizontal direction. The conductive layer 130A and the isolation layer 130B may alternate in a vertical direction (e.g., Z direction) perpendicular to the second horizontal direction. The conductive layers 130A may be the same or different in thickness, for example, their thickness is in the range of 10-500nm, for example, about 35nm. The isolation layers 130B may also be the same or different in thickness, for example, their thickness is in the range of 10-500nm, for example, about 25nm. It should be noted that Figure 1B The number of conductive layers 130A and isolation layers 130B shown in the figure is for illustration only, and any suitable number of conductive layers 130A and isolation layers 130B may be included in the stack 130 of the semiconductor structure 100. The conductive layer 130A may include any suitable conductive material, for example, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), polysilicon, doped silicon, silicide, or any combination thereof. The isolation layer 130B may include a dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the isolation layer 130B may also include a high-k dielectric material, for example, hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, or any combination thereof.

[0039] One or more channel structures may be formed in the stack 130, penetrating the conductive layer 130A and the isolation layer 130B of the stack 130 into the substrate 110. For example, Figure 1BAs shown, the first channel structure 140 is formed within the array region 100A, and the second channel structure 141 is formed within the connection region 100B. In some examples, each of the first channel structure 140 and the second channel structure 141 may have a cylindrical or pillar shape, and may include a high-k layer extending through the conductive layer 130A and the isolation layer 130B of the stack 130, a barrier layer surrounded by the high-k layer, a charge trapping layer (or storage layer) surrounded by the barrier layer, a tunneling layer surrounded by the charge trapping layer, a channel layer surrounded by the tunneling layer, and a core filler layer surrounded by the channel layer, and also includes a channel contact (not shown) formed on the core filler layer and in contact with the channel layer. In some embodiments, the channel layer may include silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon, the tunneling layer may include silicon oxide, silicon nitride, or any combination thereof, the blocking layer may include silicon oxide, silicon nitride, a high-k dielectric, or any combination thereof, and the charge trapping layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some embodiments, the tunneling layer, charge trapping layer, and blocking layer, collectively referred to as a storage film, may include an ONO dielectric (silicon oxide-silicon nitride-silicon oxide).

[0040] Each of the first channel structure 140 and the second channel structure 141 may be formed as follows: one or more channel openings (not shown) extending downwardly into the substrate 110 through the sacrificial layer of the stack 130 and the isolation layer 130B of the stack 130 are then formed by a combination of a photolithography process and an etching process; and a high-k layer, a barrier layer, a charge trapping layer, a tunneling layer, a channel layer, a core filler layer, and a channel contact may then be formed within the channel opening. In some embodiments, the sacrificial layer of the stack 130 within the array region 100A may be replaced with a conductive material (e.g., tungsten (W)) to form a conductive layer 130A of the 3D semiconductor structure 100. The conductive layer 130A may be used to form a stack of transistors of a memory cell, which may form a vertical memory cell string along the first channel structure 140. The first channel structure 140 may be connected to one or more metal layers (not shown) formed above the stack 130. In some embodiments, the second channel structure 141 is a dummy channel structure and is used to support the conductive layer 130A and the isolation layer 130B of the stack 130 within the connection region 100B, and thus no metal layer is connected to the second channel structure 141 .

[0041] One or more first slit structures 150A may be formed in the stack 130 of the array region 100A along a first horizontal direction (e.g., X direction) to divide the semiconductor structure 100 into a plurality of semiconductor blocks. Similarly, one or more second slit structures 150B may be formed in the connection region 100B along the first horizontal direction to divide the semiconductor structure 100 into a plurality of semiconductor blocks. The corresponding first slit structures 150A and second slit structures 150B may be coupled to each other along the first horizontal direction, for example, Figure 1A In some embodiments, along the second horizontal direction (e.g., Figure 1A In the embodiment of the present invention, the width of the first slit structure 150A is smaller than the width of the second slit structure 150B. For example, the width of the second slit structure 150B may be approximately 1.5 to 2 times the width of the first slit structure 150A. Each of the one or more first slit structures 150A and / or the one or more second slit structures 150B may extend through the stack 130 in a vertical direction (e.g., Z direction) perpendicular to the first horizontal direction and the second horizontal direction, for example, as shown in FIG. Figure 1B shown.

[0042] In some embodiments, a tetraethyl orthosilicate (TEOS) hard mask (not shown) may be deposited over the stack 130 in a deposition process (e.g., a chemical vapor deposition (CVD) process). A photoresist layer (not shown) may be applied over the TEOS hard mask and patterned corresponding to the trench locations within the stack 130. The stack 130 may then be etched with the TEOS hard mask formed thereon, whereby a trench structure may be formed within the stack 130 to reveal the substrate 110, and the lateral sides of the sacrificial layer and the isolation layer 130B of the stack 130 are exposed. The trench structure may then be filled with a trench filler material 151 (e.g., polysilicon) to form a first slit structure 150A and / or a second slit structure 150B.

[0043] One or more contact structures 160 may be formed within the connection region 100B to connect the conductive layer 130A of the 3D semiconductor structure 100. In some embodiments, the connection region 100B includes a top end and a bottom end opposite to each other in the Z direction, and each of the one or more contact structures 160 is coupled outwardly to a conductive contact at the top end or the bottom end. In some embodiments, a contact structure opening 161 may be formed to extend from the uppermost isolation layer 130B of the isolation layers 130B into a portion of the stack 130 (which may include one or more conductive layers 130A and / or one or more isolation layers 130B) to reach a corresponding (or target) conductive layer 130A in the conductive layers 130A, thereby exposing the lateral side of the portion of the stack 130. A spacer 162 may be formed to cover the lateral side of the portion of the stack 130 and the top surface of the corresponding conductive layer 130A. Then, for example, the spacer 162 covering the top surface of the desired conductive layer 130A may be removed by etching. A filling material (eg, oxide) 160 a and a conductive material 160 b (eg, metal) may be sequentially deposited through the contact structure opening 161 to form the contact structure 160 .

[0044] The 3D semiconductor structure 100 may include an insulating layer 163 deposited on top of the stack 130. The insulating layer 163 is closer to the end of the second slit structure 150B than the stack 130 along the Z direction. The insulating layer 163 may include a top surface 163A and a bottom surface 163B along the Z direction. The top surface 163A is closer to the end of the second slit structure 150B than the bottom surface 163B along the Z direction. In some cases, ions may be implanted from the top surface 163A of the insulating layer 163 during the manufacturing process of the second slit structure 150B (e.g., as combined with Figures 3A-3D As a result, insulating layer 163 can include ions distributed among the insulating material in insulating layer 163. In some cases, the ions include at least one of nitrogen, argon, carbon, or boron. In some examples, the ion concentration in the insulating material of insulating layer 163 is about 10 -14 cm 3 In some embodiments, since ions are implanted from top surface 163A of insulating layer 163, ion concentration may decrease from top surface 163A to bottom surface 163B along the Z direction. In other words, the concentration of ions adjacent to top surface 163A may be higher than the concentration of ions adjacent to bottom surface 163B.

[0045] In some embodiments, the semiconductor structure 100 includes one or more top select gates (TSG) 164. The semiconductor structure 100 can be formed using the following steps. A stack of alternating dielectric layers 130C and isolation layers 130B is formed. After forming the stack of alternating dielectric layers 130C and isolation layers 130B, an insulating layer (e.g., polysilicon) 163 can be formed over the stack. A first portion of the insulating layer 163 in the connection region 100B is etched away, while a second portion of the insulating layer 163 in the array region 100A remains. Then, one or more TSGs 164 are formed in the array region 100A based on the second portion of the insulating layer 163 in the array region 100A. Thereafter, a dielectric material 165 is deposited on top of the etched insulating layer 163. Figure 1B As shown, since the first portion of the insulating layer 163 is etched away, the layer thickness of the dielectric material 165 in the connection region 100B is greater than the layer thickness of the dielectric material 165 over the TSG 164 in the array region 100A.

[0046] In some embodiments, the semiconductor structure 100 can be used to form a memory device by one or more additional processing steps. For example, on a first side of the semiconductor structure 100, the substrate 110 can be thinned or removed to, for example, expose a conductive material (e.g., polysilicon or metal) in a channel structure (e.g., channel structure 140) and / or a slit structure (e.g., slit structures 150A and 150B). A conductive material (e.g., metal) can be deposited on the exposed conductive material to form a common source layer, wherein the memory cell string and / or the slit structure can be conductively coupled to the common source layer. On a second side of the semiconductor structure 100 opposite to the first side, the semiconductor structure 100 can be integrated with a control structure (e.g., a CMOS wafer or die) including a control circuit. For example, a surface of the second side of the semiconductor structure 100 can be bonded to a surface of the control circuit of the control structure.

[0047] Figure 2A-2E The structure of an exemplary semiconductor structure after various stages of the manufacturing process is shown in FIG. Figure 1A-1B The 3D semiconductor structure 100 or a portion of the 3D semiconductor structure 100 is similar or identical. Figure 2A-2E is with Figure 1B Having similar or same perspective (e.g., along Figure 1A Cross-sectional view along the cutting lines AA′ and BB′ shown.

[0048] Figure 2AThe structure 200a after the first stage of forming the semiconductor structure is shown. The first stage includes, for example, providing a semiconductor structure including a first region 201 and a second region 202, and depositing a protective layer 207 on the semiconductor structure. In some embodiments, the first region 201 includes a first trench structure 203, and the second region includes a second trench structure 204. In some cases, the first region 201 includes an array region (e.g., corresponding to Figure 1A-1B Array region 100A or 100C), and first trench structure 203 is in the array region. In some cases, second region 202 includes a connection region (eg, corresponding to Figure 1A-1B The first trench structure 203 may be used to form a gap structure (eg, Figure 1A-1B The second trench structure 204 may be used to form a slit structure (eg, Figure 1A-1B The second gap structure 150B).

[0049] In some examples, the second region 202 is adjacent to the first region 201 along a first horizontal direction (e.g., X direction) perpendicular to the vertical direction. In some cases, the first trench structure 203 is coupled (e.g., contacts, connects, etc.) to the second trench structure 204. In some cases, along the second horizontal direction (e.g., Y direction), the first trench structure 203 has a smaller width than the second trench structure 204. In some examples, the width of the second trench structure 204 is 1.5 to 2 times greater than the width of the first trench structure.

[0050] In some embodiments, before depositing the protective layer 207, a sacrificial material is deposited over the first trench structure 203 to fill the sacrificial material in the first trench structure 203, thereby forming a first sacrificial film 205A and a filled sacrificial material 205B in the first trench structure 203. The first sacrificial film 205A may cover the filled sacrificial material 205B, and thereby cover the first trench structure 203. An air gap 205c may be formed in the filled sacrificial material 205B inside the first trench structure 203. In addition, a sacrificial material is deposited over the second trench structure 204 to form a second sacrificial film 206, the second sacrificial film 206 having a first portion 206A located on the top surface of the second region 202, a second portion 206B located on the inner surface of the second trench structure 204, and a third portion 206C located at the bottom of the second trench structure 204 ... second trench structure 204 may be provided with a plurality of layers of the first sacrificial film 206, each of which may be provided with a plurality of layers of the first sacrificial Figure 1BThe second sacrificial film 206 is formed on the surface of the second trench structure 204 (in the Z direction shown). The sacrificial material may include any suitable sacrificial material, such as oxide, carbon, polysilicon, or a combination thereof. The first sacrificial film 205A may be coupled (e.g., contacted, connected, etc.) to the second sacrificial film 206. It should be noted that the width of the second trench structure 204 and the width of the first trench structure 203 are configured so that the sacrificial material can fill the opening of the first trench structure 203 to form the filled sacrificial material 205B, but cannot cover the opening of the second trench structure 204.

[0051] As described above, a protective layer 207 may be deposited on the structure 200a. The protective layer 207 may form a layer on the first sacrificial film 205A. In addition, the protective layer 207 can be formed on the first portion 206A of the second sacrificial film 206, while the opening of the second trench structure 204 remains open. For example, in some cases, the protective layer 207 does not cover the second portion 206B and / or the third portion 206C of the second sacrificial film 206. The protective layer 207 may include one or more materials, such as organic titanium.

[0052] The structure 200a may include a stack 208 of alternating sacrificial layers 208A and isolation layers 208B. As described below, the stack 208 may be used to form a stack of alternating conductive layers and isolation layers, for example Figure 1B The sacrificial layer 208A may include a sacrificial material. The sacrificial material may include an insulating material (eg, silicon dioxide, silicon nitride, carbon), a semiconductor material (eg, silicon, gallium arsenide), or other materials.

[0053] In some embodiments, one or more first channel structures 220 (eg, Figure 1A-1B One or more second channel structures 222 (eg, first channel structures 140) penetrating the stack 208 are formed in the second region 202. Figure 1A-1B An insulating layer 213 (eg, Figure 1B insulating layer 163).

[0054] Figure 2BThe structure 200b after the second stage of forming the semiconductor structure is shown. The second stage includes, for example, etching away the second portion 206B of the second sacrificial film 206 from the inner surface of the second trench structure 204, while at least a portion of the first sacrificial film 205A remains to cover the first trench structure 203. The protective layer 207 can be configured to prevent the material below the protective layer 207 from being etched (for example, by preventing the material below the protective layer 207 from contacting the etchant). Therefore, depositing the protective layer 207 over the selective area can selectively remove material, that is, remove the material not covered by the protective layer 207, while largely retaining the material below the protective layer 207. In this case, the protective layer 207 covers the first sacrificial film 205A and the first portion 206A of the second sacrificial film 206, while the protective layer 207 does not cover the second portion 206B and the third portion 206C of the second sacrificial film 206. As a result, the second portion 206B of the second sacrificial film 206 can be etched away, while the first sacrificial film 205A can remain to cover the first trench structure 203. In some cases, the second portion 206B of the second sacrificial film 206 may be etched using, for example, tetramethylammonium hydroxide (TMAH).

[0055] Figure 2C The structure 200c is shown after the third stage of forming the semiconductor structure. The third stage includes, for example, removing the protective layer 207. For example, the protective layer 207 may be removed using an ashing method or other suitable material removal process.

[0056] Figure 2D The structure 200d after the fourth stage of forming the semiconductor structure is shown. The fourth stage includes, for example, removing the third portion 206C of the second sacrificial film 206 at the bottom of the second trench structure 204. The third portion 206C of the second sacrificial film 206 may be etched away using, for example, TMAH.

[0057] Figure 2E The structure 200e after the fifth stage of forming the semiconductor structure is shown. The fifth stage includes, for example, removing the sacrificial material of the sacrificial layer 208A of the stack 208 in the second region 202. In some cases, the sacrificial material can be removed using a material removal process (e.g., a wet method, an ashing method, or other appropriate method). For example, the sacrificial material in the sacrificial layer 208A can be removed through the opening of the second trench structure 204 (e.g., an etchant can be dripped into the second trench structure 204 through the opening of the second trench structure 204). Removing the sacrificial material can generate a cavity (or a recessed portion) in the sacrificial layer 208A. Then, a conductive material (e.g., tungsten) can be filled in the cavity to form a conductive layer (e.g., Figure 1B), thereby generating a stack of alternating conductive layers and isolation layers (e.g., Figure 1B In some examples, portions of the sacrificial material are not removed to provide support for the structure 200e during one or more subsequent manufacturing process steps.

[0058] Figures 3A-3D The structure of an exemplary semiconductor structure after various stages of the manufacturing process is shown in FIG. Figure 1A-1B The 3D semiconductor structure 100 or a portion of the 3D semiconductor structure 100 is similar or identical. Figures 3A-3D is with Figure 1B Having similar or same perspective (e.g., along Figure 1A In some cases, the combination Figures 3A-3D Describe the manufacturing process and bonding Figure 2A-2B The fabrication processes described are two different fabrication processes for fabricating similar semiconductor structures.

[0059] Figure 3A The structure 300a is shown after a first stage of forming a semiconductor structure. In some cases, the structure 300a does not include Figure 2A The first stage includes, for example, providing a semiconductor structure including a first region 301 and a second region 302. In some embodiments, the first region 301 includes a first trench structure 303 (for example, Figure 2A ), and the second region 302 includes a second trench structure 304 (eg, Figure 2A In some cases, the first region 301 includes an array region (eg, corresponding to a Figure 1A-1B Array region 100A or 100C), and first trench structure 303 is in the array region. In some cases, second region 302 includes a connection region (eg, corresponding to Figure 1A-1B The first trench structure 303 may be used to form a gap structure (eg, Figure 1A-1B The second trench structure 304 may be used to form a slit structure in the second region 302 (eg, Figure 1A-1B The second gap structure 150B).

[0060] In some examples, the second region 302 is adjacent to the first region 301 along a first horizontal direction (e.g., X direction) perpendicular to the vertical direction. In some cases, the first trench structure 303 is coupled (e.g., contacts, connects, etc.) to the second trench structure 304. In some cases, along the second horizontal direction (e.g., Y direction), the first trench structure 303 has a smaller width than the second trench structure 304. In some examples, the width of the second trench structure 304 is 1.5 to 2 times greater than the width of the first trench structure.

[0061] In some embodiments, a sacrificial material is deposited over the first trench structure 303 to fill the sacrificial material in the first trench structure 303, thereby forming a first sacrificial film 305A and a filled sacrificial material 305B in the first trench structure 303. The first sacrificial film 305A may cover the filled sacrificial material 305B, and thereby cover the first trench structure 303. An air gap 305c may be formed in the filled sacrificial material 305B inside the first trench structure 303. In addition, a sacrificial material is deposited over the second trench structure 304 to form a second sacrificial film 306, the second sacrificial film 306 having a first portion 306A located on the top surface of the second region 302, and a second portion 306B located on the inner surface (including the bottom) of the second trench structure 304. The second trench structure 304 is provided with a first portion 306A disposed on the top surface of the second region 302, and a second portion 306B disposed ... Figure 1B The second sacrificial film 306 is formed on the surface of the second trench structure 304 (in the Z direction shown). The sacrificial material may include any suitable sacrificial material, such as oxide, carbon, polysilicon, or a combination thereof. The first sacrificial film 305A may be coupled (e.g., contacted, connected, etc.) to the second sacrificial film 306. It should be noted that the width of the second trench structure 304 and the width of the first trench structure 303 are configured so that the sacrificial material can fill the opening of the first trench structure 303 to form the filled sacrificial material 305B, but cannot cover the opening of the second trench structure 304.

[0062] Structure 300a may include a stack 308 of alternating sacrificial layers 308A and isolation layers 308B. As described below, stack 308 may be used to form a stack of alternating conductive layers and isolation layers, such as Figure 1B The sacrificial layer 308A may include a sacrificial material. The sacrificial material may include an insulating material (e.g., silicon dioxide, silicon nitride, or carbon), a semiconductor material (e.g., silicon or gallium arsenide), or other materials. In some embodiments, an insulating layer 313 (e.g., Figure 1B insulating layer 163).

[0063] Figure 3BStructure 300b after a second stage of forming a semiconductor structure is shown. The second stage includes, for example, changing at least one characteristic of a sacrificial material region. The region of sacrificial material may include, for example, at least one of a first sacrificial film 305A or a first portion 306A of a second sacrificial film 306. In some cases, changing at least one characteristic of the region of the sacrificial material includes implanting ions into the region of the sacrificial material to change the etching rate of the region of the sacrificial material. In some embodiments, a first etching rate of the sacrificial material with implanted ions is less than a second etching rate of the sacrificial material without implanted ions. In some examples, the ratio of the first etching rate to the second etching rate is about 1 / 8. The etching rate can determine the speed at which material is removed during the etching process. For example, a higher etching rate can correspond to a higher etching rate, while a lower etching rate can correspond to a lower etching rate. Therefore, the implanted ions in the selective region can be used to selectively remove material, i.e., removing material without implanted ions while largely retaining material with implanted ions.

[0064] In some embodiments, injecting ions into the region of the sacrificial material includes: controlling at least one of ion implantation power, ion implantation angle, or ion implantation density to implant ions into the region of the sacrificial material. In some examples, controlling at least one of ion implantation power, ion implantation angle, or ion implantation density to implant ions into the region of the sacrificial material includes: controlling to implant ions into the region of the sacrificial material without injecting ions into the filled sacrificial material 305B and the second portion 306B of the second sacrificial film. By doing so, the etching rate of the region of the sacrificial material with implanted ions can be different from (e.g., lower than) the etching rate of the sacrificial material in the filled sacrificial material 305B or the second portion 306B of the second sacrificial film 306. By controlling the etching rates in different regions, a certain material or materials can be removed while protecting other materials from being removed. For example, if the etching rate of the region of the sacrificial material having the implanted ions is lower than the etching rate of the sacrificial material in the second portion 306B of the second sacrificial film 306, during the etching process, at least a portion of the region of the sacrificial material having the implanted ions may remain, while the sacrificial material in the second portion 306B of the second sacrificial film 306 may be (e.g., completely) removed.

[0065] The sacrificial material and the ions may include any suitable materials and / or elements. In some examples, the sacrificial material includes at least one of polysilicon or aluminum oxide, and the ions include at least one of nitrogen, argon, carbon, or boron. For example, if the sacrificial material includes polysilicon, ions may be implanted into a region of the sacrificial material to convert the polysilicon in the region of the sacrificial material into non-polysilicon, thereby changing the etching rate of the region of the sacrificial material, wherein the region of the sacrificial material includes a first portion 306A of the second sacrificial film 306 located on the top surface of the second region 302. In some other examples, the sacrificial material includes silicon nitride, and the ions may include nitrogen.

[0066] Figure 3C The structure 300c after the third stage of forming the semiconductor structure is shown. The third stage includes, for example, etching away the second portion 306B of the second sacrificial film 306 from the inner surface of the second trench structure 304, while at least a portion of the first sacrificial film 305A remains to cover the first trench structure 303. As described above, this can be achieved because the second portion 306B of the second sacrificial film 306 has a higher etching rate than the etching rate of the first sacrificial film 305A. In some cases, the first portion 306A of the second sacrificial film 306 can be implanted with ions, and thus when the second portion 306B of the second sacrificial film 306 is etched away, at least a portion of the first portion 306A of the second sacrificial film 306 can also remain.

[0067] Figure 3D The structure 300d after the fourth stage of forming the semiconductor structure is shown. The fourth stage includes, for example, removing the sacrificial material of the sacrificial layer 308A in the second region 302, for example, similar to Figure 2E In some cases, the sacrificial material may be removed using a material removal process (e.g., a wet process, an ashing process, or other suitable process). For example, the sacrificial material in the sacrificial layer 308A may be removed through the opening of the second trench structure 304 (e.g., an etchant may be dripped into the second trench structure 304 through the opening of the second trench structure 304). Removing the sacrificial material may generate a cavity in the sacrificial layer 308A. Then, a conductive material (e.g., tungsten) may be filled in the cavity to form a conductive layer (e.g., Figure 1B ), thereby generating a stack of alternating conductive layers and isolation layers (e.g., Figure 1B In some examples, a portion of the sacrificial material is not removed to provide support for the semiconductor structure 300d during the manufacturing process.

[0068] Figure 4 is a flow chart of an exemplary process 400 for forming a semiconductor structure. The semiconductor structure may be Figure 1A-1B The semiconductor structure 100 or a portion of the semiconductor structure 100 is similar or identical. Figure 1A-1B To describe process 400. Process 400 may include Figure 2A-2E or Figures 3A-3D Process 400 includes steps that can be performed in any suitable order and / or in any combination.

[0069] At step 410, a semiconductor structure including a first region and a second region is provided. The first region (e.g., Figure 2A The first area 201 or Figure 3A The first region 301 may include a first trench structure (eg, Figure 2A The first trench structure 203 or Figure 3A The first trench structure 303), and the second region (eg, Figure 2A The second area 202 or Figure 3A The second region 302 may include a second trench structure (eg, Figure 2A The second trench structure 204 or Figure 3A The semiconductor structure may include a first sacrificial film (eg, a second trench structure 304) covering the first trench structure. Figure 2A Sacrificial film 205A or Figure 3A 305A), and a second sacrificial film (eg, 305A) formed on the surface of the second trench structure from the opening of the second trench structure to the bottom of the second trench structure along a first direction (eg, Z direction) Figure 2A The sacrificial film 206 or Figure 3A 306). In some cases, the first region includes an array region and the second region includes a connection region. The first trench structure is in the array region and the second trench structure is in the connection region. In some embodiments, the first trench structure is coupled to the second trench structure and the first sacrificial film is coupled to the second sacrificial film. In some examples, along a second direction perpendicular to the first direction (e.g., the Y direction), the first trench structure has a width less than the second trench structure.

[0070] In some embodiments, the exemplary process 400 includes depositing a sacrificial material over the first trench structure and the second trench structure to fill the sacrificial material in the first trench structure and to form a layer covering the filled sacrificial material in the first trench structure (eg, Figure 2A 205B or Figure 3A 305B) of the first sacrificial film, and forming a second sacrificial film having a first portion (eg, Figure 2A 206A or Figure 3A 306A) and a second portion (eg, Figure 2A 206B or Figure 3A 306B), for example, Figure 2A or Figure 3A shown.

[0071] In some embodiments, exemplary process 400 includes changing at least one property of a region of sacrificial material, wherein the region of sacrificial material includes a first sacrificial film (eg, Figure 3A 305A) or the first portion of the second sacrificial film (eg, Figure 3A 306A), for example, Figure 3A As shown. In some examples, changing at least one property of the region of the sacrificial material includes implanting ions into the region of the sacrificial material to change an etching rate of the region of the sacrificial material. In some examples, implanting ions into the region of the sacrificial material includes: controlling at least one of ion implantation power, ion implantation angle, or ion implantation density to implant ions into the region of the sacrificial material. In some cases, controlling at least one of ion implantation power, ion implantation angle, or ion implantation density to implant ions into the region of the sacrificial material includes: controlling to implant ions into the region of the sacrificial material without implanting ions into the first trench structure and the second portion of the second sacrificial film.

[0072] In some examples, the ratio of the etch rate of the region of the sacrificial material having the implanted ions to the etch rate of the second portion of the second sacrificial film is approximately 1 / 8. In some embodiments, the sacrificial material comprises at least one of polysilicon or aluminum oxide, and wherein the ions comprise at least one of nitrogen, argon, carbon, or boron. In some embodiments, the sacrificial material comprises polysilicon, and the method further comprises implanting ions into the region of the sacrificial material to convert the polysilicon in the region of the sacrificial material into non-polysilicon, thereby changing the etch rate of the region of the sacrificial material, wherein the region of the sacrificial material comprises a first portion of the second sacrificial film located on the top surface of the second region. In some embodiments, the sacrificial material comprises silicon nitride, and wherein the ions comprise nitrogen.

[0073] In some cases, before etching the second portion of the second sacrificial film, process 400 includes depositing a protective layer on the semiconductor structure, wherein the protective layer forms a layer on the first sacrificial film and an opening of the second trench structure remains open, wherein the protective layer is located on the first portion of the second sacrificial film, e.g., Figure 2A In some embodiments, the protective layer includes organic titanium. In some examples, the exemplary process 400 includes removing the protective layer from the semiconductor structure after etching the second portion of the second sacrificial film.

[0074] At step 420, at least a portion of the second sacrificial film is etched, while at least a portion of the first sacrificial film remains to cover the first trench structure. In some cases, the second sacrificial film includes a first portion located on the top surface of the second region and a second portion located on the inner surface of the second trench structure, and etching at least a portion of the second sacrificial film includes etching the second portion of the second sacrificial film away from the inner surface of the second trench structure, e.g., Figure 2B or Figure 3B In some cases, the second region includes a plurality of alternating sacrificial layers and insulating layers, and the exemplary process 400 may further include: after etching at least a portion of the second sacrificial film, removing the sacrificial layer in the second region through the opening of the second trench structure, for example, as Figure 2E or Figure 3D shown.

[0075] Figure 5 A block diagram of a system 500 having one or more semiconductor devices (e.g., memory devices) according to one or more embodiments of the present disclosure is shown. The system 500 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage component located therein. Figure 5 As shown in , system 500 may include a host device 508 and a memory system 502, the memory system 502 having one or more 3D memory devices 504 and a memory controller 506. The host device 508 may include a processor of an electronic device, such as a central processing unit (CPU), or may include a system on chip (SoC), such as an application processor (AP). The host device 508 may be configured to send data to the one or more 3D memory devices 504, or receive data from the one or more 3D memory devices 504.

[0076] The 3D memory device 504 may be any 3D memory device disclosed herein, for example, Figure 1A-1B The 3D memory device shown in Figure 2A-2E A 3D memory device of a semiconductor structure 200a-200e, or based on Figures 3A-3D3D memory device of semiconductor structure 300a-300d of the present invention. In some embodiments, 3D memory device 504 includes NAND flash memory. Memory controller 506 (also known as controller circuit) is coupled to 3D memory device 504 and host device 508. According to an embodiment of the present disclosure, 3D memory device 504 may include a plurality of conductive interconnects passing through a cover layer, the conductive interconnects contacting a conductive pad in a conductive pad layer, and memory controller 506 may be coupled to 3D memory device 504 through at least one of the plurality of conductive interconnects. Memory controller 506 is configured to control 3D memory device 504. For example, memory controller 506 may be configured to operate a plurality of channel structures through word lines. Memory controller 506 may manage data stored in 3D memory device 504 and communicate with host device 508.

[0077] In some embodiments, the memory controller 506 is designed / configured to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 506 is designed / configured to operate in a high duty cycle environment, such as an enterprise storage array, and an SSD or embedded multimedia card (eMMC), which is used as a data storage component of a mobile device such as a smart phone, a tablet computer, a laptop computer, etc. The memory controller 506 can be configured to control the operation of the 3D memory device 504, such as read, erase, and program (or write) operations. The memory controller 506 can also be configured to manage various functions related to data stored in or to be stored in the 3D memory device 504, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some implementations, the memory controller 506 is further configured to process error correction codes (ECC) associated with data read from or written to the 3D memory device 504. Any other suitable functions may also be performed by the memory controller 506, such as formatting the 3D memory device 504.

[0078] The memory controller 506 may communicate with an external device (e.g., the host device 508) according to a specific communication protocol. For example, the memory controller 506 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0079] The memory controller 506 and the one or more 3D memory devices 504 can be integrated into various types of memory devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 502 can be implemented and packaged into different types of final electronic products. Figure 5 In one example shown, the memory controller 506 and the 3D memory device 504 may be integrated into the memory system 502. The memory system 502 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc.

[0080] The embodiments and actions and operations of the subject matter described in the present disclosure may be implemented in a digital electronic circuit system, in computer software or firmware embodied in a tangible manner, in computer hardware (including the structures disclosed in the present disclosure and their structural equivalents), or in a combination of one or more of the above options. The embodiments of the subject matter described in the present disclosure may be implemented as one or more computer programs, for example, one or more modules of computer program instructions encoded on a computer program carrier, for execution by a data processing device or for controlling the operation of a data processing device. The carrier may be a tangible non-transitory computer storage medium. Alternatively or additionally, the carrier may be an artificially generated propagation signal, for example, a machine-generated electrical signal, optical signal, or electromagnetic signal, which is generated to encode information for transmission to an appropriate receiving device, thereby being executed by a data processing device. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them, or may be a part of a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them. A computer storage medium is not a propagation signal.

[0081] It should be noted that references to "one embodiment", "an embodiment", "an exemplary embodiment", "some embodiments", "implementations", etc. in this disclosure indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment may include the particular feature, structure, or characteristic. Furthermore, such wording does not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it would be within the knowledge of a person skilled in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments, whether explicitly or not explicitly described.

[0082] Typically, a term can be understood at least in part from usage in context. For example, at least in part depending on the context, the word "one or more" used herein can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or characteristics in a plural sense. Similarly, depending at least in part on the context, words such as "one", "a kind of" or "the" can also be understood to express singular usage or to express plural usage. In addition, the word "based on" can be understood to not necessarily be intended to express an exclusive set of factors, and on the contrary, additional factors that may not be explicitly described can be allowed to exist, which also depends at least in part on the context.

[0083] It should be readily understood that the meanings of "on", "over", and "over" in this disclosure should be interpreted in the broadest manner, such that "on" not only means being directly on something, but also includes being on something with intervening features or layers. Furthermore, "on" or "over" not only means being on or over something, but also includes being on or over something without any intervening features or layers (i.e., directly on something).

[0084] Additionally, for ease of description, spatially relative terms (e.g., "below," "under," "below," "above," "on," etc.) may be used herein to describe the relationship of one element or feature to one or more other elements or features as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or process steps in addition to the orientation shown in the figures. The device can be oriented in other ways (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0085] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed, and therefore unless otherwise indicated, semiconductor devices are formed at the top side of the substrate. The bottom surface is opposite to the top surface, and therefore the bottom side of the substrate is opposite to the top side of the substrate. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a wide range of semiconductor materials, for example, silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0086] As used herein, the term "layer" refers to a material portion including an area with thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. The layer can extend over the entire lower or upper structure, or can have a range that is less than the range of the lower or upper structure. In addition, the layer can be a region of a homogeneous or heterogeneous continuous structure, and its thickness is less than the thickness of the continuous structure. For example, the layer can be located between any set of horizontal planes between the top surface and the bottom surface of the continuous structure, or at the top surface and the bottom surface. The layer can extend horizontally, vertically and / or along a tapered surface. The substrate can be a layer, the substrate can contain one or more layers therein, and / or the substrate can have one or more layers located thereon, above and / or below it. The layer can include multiple layers. For example, the interconnect layer can include one or more conductive and contact layers (wherein contact portions, interconnect lines and / or vertical interconnect paths (VIAs) are formed) and one or more dielectric layers.

[0087] As used herein, the term "nominal / nominally" refers to an expected value or target value of a characteristic or parameter of a component or process step set during the design phase of a product or process, together with a range of values ​​above and / or below the expected value. As used herein, the range of values ​​may be due to slight variations in the manufacturing process or tolerances. As used herein, the term "approximately" indicates that the value of a given quantity may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "approximately" may indicate that the value of a given quantity varies within, for example, 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0088] In this disclosure, the words “horizontal / horizontally / lateral / laterally” refer to being nominally parallel to a lateral surface of a substrate, and the words “vertical” or “vertically” refer to being nominally perpendicular to a lateral surface of a substrate.

[0089] As used herein, the term "3D memory" refers to a three-dimensional (3D) semiconductor device having a vertically oriented string of memory cell transistors (referred to herein as a "memory string", e.g., a NAND string) located on a laterally oriented substrate such that the memory string extends in a vertical direction relative to the substrate.

[0090] The present disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are just examples and are not intended to be limiting. For example, forming a first feature above or on a second feature in the following description may include an embodiment in which the first and second features may be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. The purpose of this repetition is for the purpose of simplicity and clarity, and does not in itself indicate the relationship between the various embodiments and / or configurations discussed.

[0091] The above description of the specific embodiments can be easily modified and / or adjusted for various applications. Therefore, based on the teaching and guidance provided herein, it is intended that such adjustments and modifications fall within the meaning and scope of equivalents of the disclosed embodiments.

[0092] Although the present disclosure contains many specific implementation details, these details should not be understood as limiting the scope of the protection claimed, which is defined by the claims themselves, but rather these details should be understood only as descriptions of features that are unique to a particular embodiment of a particular invention. Certain features described in the present disclosure in the context of multiple separate embodiments may also be implemented in combination in a single embodiment. Conversely, the individual features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any appropriate sub-combination. In addition, although multiple features may be described above as functioning in certain combinations and even initially claimed for protection as such, one or more features from the claimed combination may be removed from the combination in some cases, and the claims may relate to sub-combinations or variations of sub-combinations.

[0093] Similarly, although multiple operations are depicted in a specific order in the drawings and multiple operations are recorded in a specific order in the claims, this should not be understood as requiring such multiple operations to be performed in the specific order shown or in a sequential order to obtain the desired result or all illustrated operations must be performed. In some cases, multitasking and parallel processing may be advantageous. In addition, the division of various system modules and components in the embodiments described above should not be understood as requiring such division in all embodiments, and it should be understood that the described program components and systems can generally be integrated together into a single software product or packaged into multiple software products.

[0094] Specific implementations of the subject matter have been described. Other implementations are also within the scope of the appended claims. For example, the actions recited in the claims can be performed in a different order and still achieve the desired results. As an example, the processes shown in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous.

[0095] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A method comprising: A semiconductor structure comprising a first region and a second region is provided, wherein the first region comprises a first trench structure, and the second region comprises a second trench structure, wherein the semiconductor structure comprises: a first sacrificial film covering the first trench structure, and a second sacrificial film formed on a surface of the second trench structure from an opening of the second trench structure to a bottom of the second trench structure along a first direction; and At least a portion of the second sacrificial film is etched, while at least a portion of the first sacrificial film remains to cover the first trench structure.

2. The method according to claim 1, wherein: The first trench structure is coupled to the second trench structure, and wherein the first sacrificial film is coupled to the second sacrificial film.

3. The method according to claim 1 or 2, wherein: Along a second direction perpendicular to the first direction, the first trench structure has a width smaller than that of the second trench structure.

4. The method according to claim 3, further comprising: A sacrificial material is deposited over the first trench structure and the second trench structure to fill the sacrificial material in the first trench structure and form the first sacrificial film covering the filled sacrificial material in the first trench structure, and to form the second sacrificial film having a first portion located on a top surface of the second region and a second portion located on an inner surface of the second trench structure.

5. The method according to any one of claims 1 to 4, wherein: The second sacrificial film includes a first portion located on the top surface of the second region and a second portion located on the inner surface of the second trench structure, and Wherein, etching the at least one portion of the second sacrificial film includes etching away the second portion of the second sacrificial film from the inner surface of the second trench structure.

6. The method according to claim 5, further comprising: At least one property of a region of sacrificial material is changed, wherein the region of the sacrificial material includes at least one of the first portion of the second sacrificial film or the first sacrificial film.

7. The method according to claim 6, wherein: Changing the at least one property of the region of the sacrificial material comprises: Ions are implanted into the region of the sacrificial material to change an etch rate of the region of the sacrificial material.

8. The method according to claim 7, wherein: Implanting the ions into the region of the sacrificial material comprises: At least one of an ion implantation power, an ion implantation angle, or an ion implantation density is controlled to implant the ions into the region of the sacrificial material.

9. The method according to claim 7 or 8, wherein: The sacrificial material includes at least one of polysilicon or aluminum oxide, and wherein the ions include at least one of nitrogen, argon, carbon, or boron.

10. The method according to any one of claims 5 to 9, wherein: The sacrificial material comprises polysilicon, and the method further comprises: Ions are implanted into the region of the sacrificial material to convert the polysilicon in the region of the sacrificial material into non-polysilicon, thereby changing the etching rate of the region of the sacrificial material, wherein the region of the sacrificial material includes the first portion of the second sacrificial film located on the top surface of the second region.

11. The method according to any one of claims 1 to 10, wherein: The second region includes a plurality of alternating sacrificial layers and insulating layers, and The method further includes: after etching the at least one portion of the second sacrificial film, removing the sacrificial layer in the second region through the opening of the second trench structure.

12. A semiconductor device comprising: An array region, the array region comprising a first slit structure extending along a first direction; as well as a connection region, the connection region being adjacent to the array region along a second direction perpendicular to the first direction, The connection region includes a second gap structure, the second gap structure extends along the first direction through the insulating layer extending along the second direction, and The insulating layer includes an insulating material and ions distributed in the insulating material in the insulating layer.

13. The semiconductor device according to claim 12, comprising a stack of conductive layers and isolation layers alternating with each other along the first direction, in, Each of the first and second gap structures extends through the stack of the conductive layer and the isolation layer, and The insulating layer is closer to an end of the second gap structure along the first direction than the stack of the conductive layer and the isolation layer.

14. The semiconductor device according to claim 13, wherein: The connection region includes a plurality of contact structures extending through the stack of conductive and isolating layers, and At least one of the conductive layers is coupled to a corresponding contact structure of the plurality of contact structures.

15. The semiconductor device according to claim 14, wherein: The connection region includes a first end and a second end opposite to each other along the first direction, and Each of the plurality of contact structures is externally coupled to a conductive contact portion at the first end or the second end.

16. The semiconductor device according to any one of claims 13 to 15, wherein: The array region includes a plurality of channel structures extending through the stack of the conductive layer and the isolation layer.

17. The semiconductor device according to any one of claims 12 to 16, wherein: The first slit structure connects the second slit structure along the second direction, and Wherein, along a third direction perpendicular to the first direction and the second direction, the width of the first gap structure is smaller than the width of the second gap structure.

18. The semiconductor device according to any one of claims 13 to 17, wherein: The insulating layer includes a first surface and a second surface along the first direction, the first surface is closer to the end of the second gap structure than the second surface along the first direction, and wherein a first concentration of the ions adjacent to the first surface is higher than a second concentration of the ions adjacent to the second surface of the insulating layer.

19. A method comprising: Providing a semiconductor structure including a first region and a second region, the first region including a first trench structure, the second region including a second trench structure, wherein the semiconductor structure includes: a first sacrificial film covering the first trench structure, and a second sacrificial film formed on a surface of the second trench structure from an opening of the second trench structure to a bottom of the second trench structure, and wherein the second sacrificial film includes a first portion located on a top surface of the second region and a second portion located on an inner surface of the second trench structure; and changing at least one property of a region of sacrificial material, wherein the region of the sacrificial material includes at least one of the first portion of the second sacrificial film or the first sacrificial film; and The second portion of the second sacrificial film is etched away from the inner surface of the second trench structure, while at least a portion of the first sacrificial film remains to cover the first trench structure.

20. The method according to claim 19, wherein: Changing the at least one property of the region of the sacrificial material comprises: Ions are implanted into the region of the sacrificial material to change an etch rate of the region of the sacrificial material.

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