Semiconductor device and manufacturing method thereof

Abstract

The embodiment of the invention provides a semiconductor device and a manufacturing method thereof, the semiconductor device comprises a substrate, a first capacitor structure and a second capacitor structure, a first groove and a second groove are formed in the substrate, the width of the first groove is larger than that of the second groove, and the depth of the first groove is different from that of the second groove; the first capacitor structure comprises a first laminated body arranged on the inner wall of the first groove, and the first laminated body comprises first electrode layers and first dielectric layers which are alternately laminated; the second capacitor structure comprises a second laminated body arranged on the inner wall of the second groove, and the second laminated body comprises a second electrode layer and a second dielectric layer which are alternately laminated.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to semiconductor devices and methods for manufacturing the same. Background Art

[0002] With the development of advanced packaging technology, the demand for high-performance, high-density, and low-thickness capacitors is becoming more and more urgent. Silicon capacitors, as high-end substitutes for MLCC (Multi-Layer Ceramic Capacitor), are currently widely used in power decoupling, high-frequency and high-speed transmission, and other fields. Silicon capacitors are small and thin capacitors made using thin-film semiconductor technology. They have the characteristics of high stability, high capacitance density, and the ability to meet integration requirements, and can better meet the needs of the microelectronics field. Summary of the invention

[0003] Embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same.

[0004] In a first aspect of the present disclosure, a semiconductor device is provided, comprising:

[0005] A substrate, wherein a first groove and a second groove are formed in the substrate, wherein a width of the first groove is greater than a width of the second groove, and a depth of the first groove is different from a depth of the second groove;

[0006] A first capacitor structure includes a first stacked body arranged on an inner wall of the first groove, wherein the first stacked body includes first electrode layers and first dielectric layers alternately stacked;

[0007] The second capacitor structure includes a second stacked body arranged on the inner wall of the second groove, and the second stacked body includes second electrode layers and second dielectric layers stacked alternately.

[0008] According to a second aspect of the present disclosure, there is provided a semiconductor device comprising:

[0009] A substrate, wherein a first groove array and a second groove array isolated from each other are formed in the substrate, wherein the number and / or size of the first grooves in the first groove array are different from the second grooves in the second groove array;

[0010] A first capacitor structure includes a first stack located on the inner wall of each first groove in the first groove array and the top surface of the substrate between adjacent first grooves, wherein the first stack includes alternately stacked first electrode layers and first dielectric layers;

[0011] The second capacitor structure includes a second stack located on the inner wall of each second groove in the second groove array and the top surface of the substrate between adjacent second grooves. The second stack includes alternately stacked second electrode layers and second dielectric layers.

[0012] A third aspect of the present disclosure provides a method for manufacturing a semiconductor device, comprising:

[0013] A patterned buffer layer is formed on a substrate; a first pattern and a second pattern are formed in the patterned buffer layer, and a width of the first pattern is greater than a width of the second pattern;

[0014] Etching the substrate based on the patterned buffer layer to simultaneously form a first groove corresponding to the first pattern and a second groove corresponding to the second pattern; wherein the depth of the first groove is different from the depth of the second groove;

[0015] A first stack is formed on the inner wall of the first groove, and a second stack is formed on the inner wall of the second groove; wherein the first stack includes alternately stacked first electrode layers and first dielectric layers, and the second stack includes alternately stacked second electrode layers and second dielectric layers.

[0016] In the disclosed embodiment, the first groove and the second groove can be formed simultaneously in the same etching process. Specifically, by utilizing the load effect of the etching process, by setting the width of the first groove to be greater than the width of the second groove, it is possible to achieve that the first groove and the second groove formed simultaneously have different depths under the same etching parameters. The different widths of the first groove and the second groove may make the number of layers of the first electrode layer included in the first stack different from the number of layers of the second electrode layer included in the second stack, so that the capacitance density of the first capacitor structure is different from that of the second capacitor structure. The depth of the first groove and the second groove is different, so that the depth of the first stack and the second stack is different, so that the capacitance density of the first capacitor structure and the second capacitor structure is different. The capacitance density of the first capacitor structure and the second capacitor structure is different, which can make the capacitance and / or equivalent inductance of the two different, and then make the resonant frequency different. By combining capacitor structures with different resonant frequencies, different frequency bands can be filtered, so that a capacitor chip can be compatible with multi-frequency band filtering, meeting the filtering requirements of different functional modules inside the same chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of a deep trench capacitor provided by the present disclosure.

[0018] Figure 2 The structure of the semiconductor device provided by the present invention is shown in FIG. Figure 1 .

[0019] Figure 3 The structure of the semiconductor device provided by the present invention is shown in FIG. Figure 2 .

[0020] Figure 4 The structure of the semiconductor device provided by the present invention is shown in FIG. Figure 3 .

[0021] Figure 5 The first schematic top view of the semiconductor device provided by the present invention.

[0022] Figure 6 The second schematic top view of the semiconductor device provided by the present invention.

[0023] Figure 7 The structure of the semiconductor device provided by the present invention is shown in FIG. Figure 4 .

[0024] Figure 8 A schematic flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present disclosure.

[0025] Figure 9a to Figure 9h A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present disclosure.

[0026] Figure 10a to Figure 10b A schematic diagram of the structure of another semiconductor device provided by the present invention during the manufacturing process.

[0027] Fig.11 A design process of a capacitor provided in an embodiment of the present disclosure.

[0028] Fig.12 A schematic diagram of the filtering frequency band of three capacitors connected in parallel provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] In order to facilitate the understanding of the present disclosure, the exemplary embodiments of the present disclosure will be described in more detail below with reference to the relevant drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0030] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In some embodiments, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of the actual embodiment may not be described here, and well-known functions and structures may not be described in detail.

[0031] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "one" or "the" can also be understood to convey singular usage or to convey plural usage, depending at least in part on the context. In addition, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least in part on the context.

[0032] Unless otherwise defined, the purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0033] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0034] Figure 1 A schematic diagram of a deep trench capacitor provided in an embodiment of the present disclosure. A deep trench capacitor (DTC) is a type of silicon capacitor. During the preparation process of a deep trench capacitor, a trench array is first formed, and then an electrode layer and a dielectric layer are deposited in the trench array. Figure 1 As shown, the deep trench capacitor includes a plurality of trench arrays 10 that are isolated from each other and arranged according to a certain rule, and each trench array 10 includes a plurality of trenches 11 arranged side by side. The number and size of the trenches 11 in each trench array 10 and the spacing between adjacent trenches 11 are equal, so that the parameters of the capacitor formed by each trench array are the same. For example, the capacitor formed by each trench array has the same equivalent inductance L, equivalent resistance R and capacitance C, and thus has the same resonant frequency f.

[0035] Deep trench capacitors can be integrated inside the chip. For example, high-density deep trench capacitors can be integrated on a 2.5D silicon adapter. Deep trench capacitors play an important role in the power integrity and signal integrity of products in advanced packaging. With the continuous development of integrated circuits, more functional modules may be integrated inside the same chip, and different functional modules may require filtering in different frequency bands. Deep trench capacitors with a single resonant frequency cannot meet the filtering requirements of multiple frequency bands when integrated in the package.

[0036] In view of this, an embodiment of the present disclosure provides a semiconductor device that can support multi-frequency band filtering in different regions. Figure 2 A schematic diagram of a semiconductor device provided in an embodiment of the present disclosure Figure 1 .like Figure 2 As shown, the semiconductor device includes a substrate 100, a first capacitor structure and a second capacitor structure. Among them, a first trench array 210 and a second trench array 310 isolated from each other are formed in the substrate 100, and the number and / or size of the first trenches in the first trench array 210 are different from the second trenches in the second trench array 310. The first capacitor structure includes a first stack 410, and the first stack 410 is located on the top surface of the substrate between the inner wall of each first trench 211 in the first trench array 210 and the adjacent first trenches 211. The second capacitor structure includes a second stack 510, and the second stack 510 is located on the top surface of the substrate between the inner wall of each second trench 311 in the second trench array 310 and the adjacent second trenches 311.

[0037] By way of example, the base 100 includes a substrate 101. The substrate 101 may be made of silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon on insulator (SOI), germanium on insulator (GOI), III-V compounds (e.g., GaN, GaAs, InAs, etc.), or any other suitable semiconductor material. The substrate 101 may also be made of other materials. In the present embodiment, the substrate 101 is a silicon substrate.

[0038] In some embodiments, the base 100 may further include a protective layer 102, which is located on the top surface of the substrate 101. The protective layer 102 is used to protect the top surface of the substrate 101 during the manufacturing process, and can also isolate the capacitor structure formed on the substrate 101 from the substrate 101 to achieve electrical isolation between the capacitor structure and the substrate 101. By way of example, the material of the protective layer 102 includes insulating materials such as silicon oxide and silicon nitride.

[0039] Continue to see Figure 2, a first groove array 210 and a second groove array 310 are formed in the substrate 100. The first groove array 210 includes a plurality of first grooves 211 arranged side by side at equal intervals. Here and in the following text, the spacing refers to the distance between adjacent sidewalls of adjacent grooves. The equal spacing of the plurality of first grooves 211 means that the spacing S1 between each two adjacent first grooves 211 is equal. The first grooves 211 are arranged in a direction perpendicular to the surface of the substrate 100 (e.g. Figure 1 The Z direction in the figure extends into the substrate 101, but does not penetrate the substrate 101.

[0040] The second groove array 310 includes a plurality of second grooves 311 arranged side by side at equal intervals S2. The second grooves 311 extend into the substrate 101 in a direction perpendicular to the surface of the base 100, but do not penetrate the substrate 101. In the embodiment of the present disclosure, the first groove array 210 and the second groove array 310 are isolated from each other, which means that the plurality of first grooves 211 are arranged continuously without the second grooves 311 interspersed therebetween, and the plurality of second grooves 311 are also arranged continuously without the first grooves 211 interspersed therebetween. That is, the first groove array 210 and the second groove array 310 are independent of each other.

[0041] The size of the first groove 211 may include: the length L1 of the first groove 211 along its extending direction (see Figure 5 ), the width W1 of the first trench 211 perpendicular to its extension direction, and the depth H1 of the first trench 211 into the substrate along the direction perpendicular to the substrate surface. Similarly, the dimensions of the second trench include: the length L2 of the second trench 311 along its extension direction (see Figure 5 ), the width W2 of the second groove 311 perpendicular to its extension direction, and the depth H2 of the second groove 311 into the substrate along the direction perpendicular to the substrate surface. The size of the first groove is different from that of the second groove, which means that at least one of the three parameters L1, W1 and H1 of the first groove is different from the corresponding parameters L2, W2 and H2 of the second groove. It can be understood that the first groove 211 and the second groove 311 are not exactly the same, and there is a difference between the two.

[0042] In some embodiments of the present disclosure, a width W1 of the first trench 211 is greater than a width W2 of the second trench 311 , and a depth H1 of the first trench 211 is different from a depth H2 of the second trench 311 .

[0043] For example, the depth H1 and width W1 of the first groove 211, and the depth H2 and width W2 of the second groove 311 satisfy the same preset correspondence, which refers to the correspondence between the depth and width of the grooves in the substrate under the same etching parameters related to the load effect of the etching process.

[0044] In this embodiment, the first groove 211 and the second groove 311 are formed simultaneously in the same etching step. According to the loading effect of the etching process, the etching depths of the patterns with different opening areas are different. The present disclosure utilizes this loading effect to simultaneously form grooves of different depths. By utilizing the preset correspondence between the depth and width of the grooves in the substrate under the same etching parameters, by setting the width of the first groove to be greater than the width of the second groove, it is possible to simultaneously form the first groove and the second groove of different depths under the same etching parameters, thereby simplifying the manufacturing process of the first groove and the second groove and saving costs.

[0045] For example, the same substrate and etching parameters as those used in manufacturing the product can be used in advance to obtain the preset corresponding relationship between the depth and width of the groove in the substrate through several experiments. Of course, the preset corresponding relationship between the depth and width of the groove in the substrate can also be obtained through a combination of experiments and simulations.

[0046] In this disclosure Figure 2 In the illustrated embodiment, the depth H1 of the first groove 211 is greater than the depth H2 of the second groove 311. That is, the greater the width of the groove, the deeper the depth. In other embodiments, the load effect of other etchants and substrates may also be manifested as the greater the depth of the groove, the shallower the depth, so the depth H1 of the first groove 211 may be less than the depth H2 of the second groove 311. In different embodiments, the depths of the first groove and the second groove may be specifically set according to the target frequency band to be filtered.

[0047] Continue to see Figure 2 The first capacitor structure includes a first stacked body 410 , and the first stacked body 410 includes first electrode layers 411 and first dielectric layers 412 that are alternately stacked.

[0048] The material of the first electrode layer 411 includes, but is not limited to, metal, conductive metal nitride, conductive metal silicide, semiconductor, etc. The metal may be tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), tantalum (Ta), iron (Fe), cobalt (Co), nickel (Ni), platinum (Pt), silver (Ag), gold (Au), etc. The conductive metal nitride may be titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), etc. The semiconductor may be polysilicon, doped polysilicon, etc. The material of the first dielectric layer 412 may include silicon oxide, silicon oxide doped with elements such as nitrogen and carbon, or other high-K dielectric materials, etc.

[0049] The so-called alternating stacking of the first electrode layer 411 and the first dielectric layer 412 means: a first dielectric layer 412 is disposed on a first electrode layer 411, another first electrode layer 411 is disposed on the first dielectric layer 412, and another first dielectric layer 412 is disposed on the first electrode layer 411, and the cycle repeats. In this embodiment, the first stack 410 includes three first electrode layers, and the bottom layer and the top layer are both first electrode layers. Specifically, the first stack 410 includes a bottom first electrode layer, a first first dielectric layer, a middle first electrode layer, a second first dielectric layer, and a top first electrode layer.

[0050] In the first capacitor structure, the first electrode layer 411 serves as an electrode, and the first dielectric layer 412 serves as an insulating isolation layer between the electrodes. For a capacitor structure including only two first electrode layers, the bottom first electrode layer serves as one electrode of the first capacitor structure, and the top first electrode layer serves as another electrode of the first capacitor structure. For a capacitor structure including three or more first electrode layers, the first electrode layers arranged at intervals serve as the same electrode of the first capacitor structure, and the first electrode layers arranged adjacent to each other serve as different electrodes of the capacitor structure. For example, in this embodiment, Figure 2 As shown, the first stack 410 includes three first electrode layers and two first dielectric layers arranged between the first electrode layers, the bottom first electrode layer and the top first electrode layer are arranged at intervals, and the two together serve as one electrode of the first capacitor structure, and the middle first electrode layer is arranged adjacent to the bottom first electrode layer and the top first electrode layer, and serves as another electrode of the first capacitor structure. It can also be understood that the first capacitor formed by the bottom first electrode layer and the middle first electrode layer is connected in parallel with the second capacitor formed by the bottom first electrode layer and the middle first electrode layer.

[0051] For another example, in another embodiment, the first stack includes four first electrode layers and three first dielectric layers arranged between the first electrode layers, then the first first electrode layer (i.e., the bottom electrode layer) and the third first electrode layer are spaced apart, and the two together serve as one electrode of the capacitor structure; the second first electrode layer and the fourth first electrode layer (i.e., the top electrode layer) are spaced apart, and the two together serve as another electrode of the capacitor structure. It can also be understood that: the first capacitor formed by the first electrode layer and the second first electrode layer, the second capacitor formed by the second first electrode layer and the third first electrode layer, and the third capacitor formed by the third first electrode layer and the fourth first electrode layer are connected in parallel.

[0052] Continue to see Figure 2, the bottom first electrode layer extends continuously on the sidewall and bottom of each first groove 211 in the first groove array 210, and the top surface of the substrate 100 between adjacent first grooves 211, so that the whole presents a meandering S shape, wherein the part of the bottom first electrode layer in the first groove 211 has the same contour shape as the first groove 211, for example, both are U-shaped. The middle first electrode layer is arranged relative to each part of the bottom first electrode layer across the first dielectric layer, so that the middle first electrode layer presents a meandering S shape as a whole. The top first electrode layer is arranged relative to each part of the middle first electrode layer across the first dielectric layer, so that the top first electrode layer also presents a meandering S shape as a whole. Such a first electrode layer 411 can increase the electrode area of ​​the first capacitor structure, thereby increasing the capacitance C of the first capacitor structure. The capacitance of the first capacitor structure can be understood as the sum of the capacitances of the first capacitor and the second capacitor connected in parallel.

[0053] The second capacitor structure includes a second stack 510, and the second stack 510 includes alternately arranged second electrode layers 511 and second dielectric layers 512. The understanding of alternate stacking can refer to the above explanation of the first stack 410. In this embodiment, the second stack 510 includes three second electrode layers 511, and the bottom layer and the top layer are both one second electrode layer 511. Specifically, the second stack 510 includes a bottom second electrode layer, a first second dielectric layer, a middle second electrode layer, a second second dielectric layer, and a top second electrode layer.

[0054] The material of the second electrode layer 511 can be selected from the material of the first electrode layer 411, and the material of the second dielectric layer 512 can be selected from the material of the first dielectric layer 412. By way of example, the material of each second electrode layer 511 is the same as that of the first electrode layer 411 at the corresponding position, for example, the material of the bottom second electrode layer is the same as that of the bottom first electrode layer, the material of the middle second electrode layer is the same as that of the middle first electrode layer, and the material of the top second electrode layer is the same as that of the top first electrode layer. By way of example, the material of each second dielectric layer 512 is the same as that of the first dielectric layer 412 at the corresponding position, for example, the material of the first second dielectric layer is the same as that of the first first dielectric layer, and the material of the second second dielectric layer is the same as that of the second first dielectric layer.

[0055] For example, each second electrode layer 511 has the same thickness as the first electrode layer 411 at the corresponding position, and each second dielectric layer 512 has the same thickness as the first dielectric layer 412 at the corresponding position. In some embodiments, each second electrode layer 511 is formed by synchronous deposition with the first electrode layer 411 at the corresponding position in the same deposition process, and each second dielectric layer 512 is formed by synchronous deposition with the first dielectric layer 412 at the corresponding position in the same deposition process.

[0056] Similar to the first stack 410, the bottom second electrode layer in the second stack 510 continuously extends on the sidewall and bottom of each second groove 311 in the second groove array 310, and on the top surface of the substrate 100 between adjacent second grooves 311, so that the whole presents a meandering S shape, wherein the portion of the bottom second electrode layer in the second groove 311 has the same contour shape as the second groove 311, for example, both are U-shaped. The middle second electrode layer is arranged opposite to each part of the bottom second electrode layer across the second dielectric layer, and the top second electrode layer is arranged opposite to each part of the middle second electrode layer across the second dielectric layer, so that the middle second electrode layer and the top second electrode layer both present a meandering S shape. In this way, the electrode area of ​​the second capacitor structure can be increased, thereby increasing the capacitance of the second capacitor structure.

[0057] like Figure 2 As shown, when the depth H1 of the first groove 211 is greater than the depth H2 of the second groove 311, the depth of the first stack 410 attached to the side wall of the first groove 211 is greater than the depth of the second stack 510 attached to the side wall of the second groove 311. In this way, the capacitance density of the first capacitor structure can be greater than the capacitance density of the second capacitor structure, and the capacitance value of the first capacitor structure can be greater than the capacitance value of the second capacitor structure. In addition, since the area of ​​the first electrode layer 411 of the first stack 410 is greater than the area of ​​the second electrode layer 511 of the second stack 510, the equivalent inductance of the first capacitor structure is greater than the equivalent inductance of the second capacitor structure, so that the resonant frequency f1 of the first capacitor structure is less than the resonant frequency f2 of the second capacitor structure. That is, the first capacitor structure and the second capacitor structure obtain different resonant frequencies, and when the first capacitor structure and the second capacitor structure are connected in parallel, the filtering function of a specific frequency band can be realized.

[0058] In some embodiments, the number of first electrode layers 411 in the first stack 410 is greater than the number of second electrode layers 511 in the second stack 510 .

[0059] exist Figure 2 In the embodiment shown, the number of first electrode layers 411 is equal to the number of second electrode layers 511, both of which are three layers. When the second groove 311 is narrowed to a certain extent relative to the first groove 211, the number of second electrode layers 511 that can be accommodated in the second groove 311 will decrease. Figure 3 A schematic diagram of a semiconductor device provided in an embodiment of the present disclosure Figure 2 The structures of the first groove array 210 and the first stack 410 are similar to Figure 2 Same as Figure 2The difference is that the width W2 of the second groove 311 is narrower, so that the second stack 510 includes only two second electrode layers 511. Specifically, the second stack 510 includes a bottom second electrode layer, a first second dielectric layer, an intermediate second electrode layer, and a second second dielectric layer, wherein the second second dielectric layer 512 closes the opening of the second groove 311. One case where the second second dielectric layer 512 closes the opening of the second groove 311 is: Figure 3 The second second dielectric layer 512 shown fills up the remaining space in the second trench 311 . In another case, the second second dielectric layer 512 may close the opening of the second trench 311 , but a gap is naturally formed in the second second dielectric layer 512 .

[0060] Compared to the first stack 410, the second stack 510 has one less electrode layer, and only the bottom second electrode layer and the middle second electrode layer constitute a capacitor. Figure 2 The second capacitor structure shown, Figure 3 The capacitance density of the second capacitor structure is smaller, so that the capacitance value of the second capacitor structure is smaller, thereby Figure 3 The resonant frequency of the second capacitor structure is higher. It can be understood that Figure 2 The first capacitor structure and the second capacitor structure in parallel can achieve filtering of a specific target frequency band, and Figure 3 The first capacitor structure and the second capacitor structure in parallel can achieve filtering of another specific target frequency band. That is, by adjusting the width of the groove, the number of electrode layers in the capacitor structure can be changed, thereby changing the resonant frequency of the capacitor structure to meet the filtering requirements of different target frequency bands.

[0061] In some embodiments, the first stack 410 includes alternately stacked first electrode layers 411 and first dielectric layers 412, and the second stack 510 includes alternately stacked second electrode layers 511 and second dielectric layers 512; wherein the area ratio of the second electrode layer of the top layer to the second electrode layer of the second top layer in the second stack 510 is smaller than the area ratio of the first electrode layer of the top layer to the first electrode layer of the second top layer in the first stack 410.

[0062] Figure 4 A schematic diagram of a semiconductor device provided in an embodiment of the present disclosure Figure 3 , wherein the structures of the first groove array 210 and the first stack 410 are similar to Figure 2 Same as Figure 2The difference is that the width W2 of the second groove 311 is narrower. After the bottom second electrode layer, the first second dielectric layer, the middle second electrode layer and the second second dielectric layer are formed in the second groove 311, the second groove 311 is closed. The top second electrode layer extends continuously along the top surface of the substrate 100. Although the number of second electrode layers 511 in the second stack 510 is equal to the number of first electrode layers 411 in the first stack 410, the top second electrode layer is only arranged relative to the area of ​​the middle second electrode layer (in this embodiment, also the second top second electrode layer) located on the top surface of the substrate, so that the relative area between the top second electrode layer and the middle second electrode layer is smaller than the relative area between the top first electrode layer and the middle first electrode layer (in this embodiment, also the second top first electrode layer), thereby making Figure 4 The capacitance and resonant frequency of the second capacitor structure in the Figure 2 The second capacitor structure in.

[0063] although Figure 3 and Figure 4 The second groove array 310 is the same as that of the second capacitor structure, but it is possible to select whether to set the second electrode layer 511 on the top layer to adjust the capacitance and the resonant frequency of the second capacitor structure to meet the filtering requirements for different target frequency bands.

[0064] In some embodiments, the number of first trenches 211 in the first trench array 210 is different from the number of second trenches 311 in the second trench array 310 .

[0065] like Figure 3 and Figure 4 As shown, the number of the first grooves 211 can be less than the number of the second grooves 311. In another embodiment, the number of the first grooves can also be greater than or equal to the number of the second grooves. In different embodiments, how the number of the first grooves and the number of the second grooves are set depends on the target frequency band. Studies have shown that the fewer the number of grooves, the smaller the area of ​​the stack, which can reduce the capacitance density, thereby reducing the capacitance value and increasing the resonant frequency of the capacitor structure.

[0066] In some embodiments, a length L1 of the first trench 211 along its extending direction is different from a length L2 of the second trench 311 along its extending direction.

[0067] Figure 5 A schematic top view of a semiconductor device provided in an embodiment of the present disclosure Figure 1 .like Figure 5 As shown, the first groove array 210 includes a plurality of first grooves 211 arranged side by side along the first direction (D1 direction), and the second groove array 310 includes a plurality of second grooves 311 arranged side by side along the first direction, wherein the length L1 of the first groove 211 is less than the length L2 of the second groove 311 .

[0068] The research shows that the shorter the length of the groove is, the shorter the length of the stack is, and the smaller the area is, which reduces the equivalent inductance of the capacitor structure, thereby increasing the resonant frequency of the capacitor structure. Figure 5 The length L1 of the first groove 211 is smaller than the length L2 of the second groove 311 , which is beneficial to improving the resonant frequency of the first capacitor structure.

[0069] In another embodiment, the length L1 of the first groove 211 may also be greater than or equal to the length L2 of the second groove 311. In different implementations, how the length of the first groove 211 and the length of the second groove 311 are set depends on the target frequency band.

[0070] In some embodiments, the spacing S1 between adjacent first trenches 211 in the first trench array 210 may also be different from the spacing S2 between adjacent second trenches 311 in the second trench array 310 .

[0071] Figure 6 A schematic top view of a semiconductor device provided in an embodiment of the present disclosure Figure 2 .like Figure 6 As shown, the first groove array 210 includes a plurality of first grooves 211 arranged side by side along a first direction (D1 direction), and the second groove array 310 includes a plurality of second grooves 311 arranged side by side along a second direction (D2), and the second direction is perpendicular to the first direction and parallel to the plane where the substrate is located.

[0072] exist Figure 5 In the embodiment shown, the extending direction of the first grooves 211 in the first groove array 210 is the same as the extending direction of the second grooves 311 in the second groove array 310. Figure 6 In the illustrated embodiment, the extension direction of the first groove 211 in the first groove array 210 and the extension direction of the second groove 311 in the second groove array 310 are perpendicular to each other. This can reduce the relative area of ​​the first stack 410 and the second stack 510, thereby reducing the coupling effect between the first capacitor structure and the second capacitor structure and improving the signal quality.

[0073] In summary, in the embodiments of the present disclosure, a corresponding set of parallel capacitors can be designed according to the target impedance of a specific frequency band, and at least two capacitors in the set of capacitors have different resonant frequencies. Based on the resonant frequency of each capacitor in the selected set of capacitors and the preset corresponding relationship, the number and size of the grooves corresponding to the capacitors, and the number and morphology of the electrode layers (for example, whether to set Figure 4 The top second electrode layer 511).

[0074] The study found that: (1) Reducing the number of grooves can reduce the capacitance density, thereby reducing the capacitance C and increasing the resonant frequency f; (2) Reducing the width of the groove can reduce the number of capacitor layers, thereby reducing the capacitance C and increasing the resonant frequency f; (3) Reducing the depth of the groove can reduce the capacitance density, thereby reducing the equivalent inductive reactance L and increasing the resonant frequency; (4) Reducing the length of the groove can reduce the capacitance density, thereby reducing the equivalent inductive reactance L and increasing the resonant frequency.

[0075] exist Figure 2 In the semiconductor device shown, the depth of the second trench 311 is less than the depth of the first trench 211, so that the second capacitor structure has a higher resonance frequency f than the first capacitor structure, thereby obtaining a capacitor structure with two resonance frequencies. Figure 3 In the semiconductor device shown in FIG. 1 , the number of second electrode layers in the second stack 510 is less than the number of first electrode layers in the first stack 410, and the depth of the second trench 311 is less than the depth of the first trench 211, so that the second capacitor structure has a larger resonant frequency f than the first capacitor structure, thereby obtaining a capacitor structure with two resonant frequencies, and the filtering frequency bands of the first capacitor structure and the second capacitor structure connected in parallel are different from each other. Figure 2 .exist Figure 4 In the semiconductor device shown in FIG. 1 , the area ratio of the top second electrode layer to the second top second electrode layer of the second stack 510 is smaller than the area ratio of the top first electrode layer to the second top first electrode layer of the first stack 410, which can reduce the capacitance density, and the depth of the second groove 311 is smaller than the depth of the first groove 211, which can also reduce the capacitance density, thereby increasing the resonant frequency, and the filtering frequency bands of the first capacitor structure and the second capacitor structure connected in parallel are different from each other. Figure 2 and Figure 3 .

[0076] It should be noted that the semiconductor device provided by the embodiment of the present disclosure may include multiple capacitor structures with different sizes, numbers of layers or morphologies, and the first capacitor structure and the second capacitor structure are only two of them. In different regions of the semiconductor device, different capacitor structure combinations can be set in different regions, so that the capacitor structure combination in each region can filter a specific frequency band, and the capacitor structure combination in different regions can filter different frequency bands, so that one capacitor chip is compatible with multi-frequency band filtering, which can meet the filtering requirements of different functional modules in the same package.

[0077] In some embodiments, the semiconductor device further includes an isolation layer 103, and the isolation layer 103 is located between the first stack 410 and the substrate 100 and between the second stack 510 and the substrate 100. Specifically, in the present embodiment, the isolation layer 103 is disposed on the inner wall of the first groove 211, the inner wall of the second groove 311 and the top surface of the substrate 100, and the bottom first electrode layer of the first stack 410 and the bottom second electrode layer of the second stack 510 are disposed on the isolation layer. The isolation layer 103 is used to isolate the electrode layer in the first stack 410 and the second stack 510 from the substrate (for example, including the semiconductor substrate 101), and as a buffer layer, buffers the stress between the electrode layer and the substrate. In particular, when the electrode layer is made of metal material, it has a large stress, and the isolation layer can buffer the stress between the electrode layer and the substrate, thereby improving the adhesion between the two.

[0078] In some embodiments, the material of the isolation layer 103 includes but is not limited to silicon oxide, silicon oxide doped with nitrogen or carbon, or other insulating oxides. In this embodiment, the material of the isolation layer 103 is silicon dioxide. The thickness of the isolation layer 103 can be determined according to the capacitor design requirements and the material of the isolation layer.

[0079] In some embodiments, Figures 2 to 4 As shown, the semiconductor device also includes: an interconnection structure 610, which is located on the side of the first stack 410 and the second stack 510 away from the substrate 100, and the interconnection structure 610 is coupled to multiple first electrode layers 411 and multiple second electrode layers 511, and connects the first capacitor structure and the second capacitor structure in parallel.

[0080] For example, the interconnect structure 610 includes a plurality of interconnect structures along a direction perpendicular to the plane where the substrate is located ( Figure 2 The wiring layer includes a plurality of conductive lines 612 configured to realize parallel connection of the first capacitor structure and the second capacitor structure.

[0081] For example, the two ends of the first stack 410 that are oppositely arranged along the width direction of the first trench are located on the top surface of the substrate 100, and the two ends can serve as regions electrically connected to the interconnect structure 610. The width direction of the first trench is perpendicular to the extension direction of the first trench. Among them, the two ends of each first electrode layer 411 located on the top surface of the substrate serve as contact regions for electrical connection with the contact plug 611. The contact region is not covered by other first electrode layers to avoid the conductive plug connected to the contact region from being mistakenly connected to other first electrode layers, thereby improving the reliability of the trench capacitor.

[0082] In this embodiment, other first electrode layers above the first electrode layer where the contact region is located do not extend above the contact region, that is, the contact region protrudes from other first electrode layers above the first electrode layer where it is located, so that no other first electrode layers exist above the contact region, thereby achieving a one-to-one connection between the first electrode layer having the contact region and the contact plug. In a specific embodiment, Figure 2 As shown, the two ends of the first stack 410 are arranged in a step structure, and each step includes a first electrode layer. Specifically, from bottom to top, the first step includes the bottom first electrode layer, the second step includes the middle first electrode layer, and the third step includes the top first electrode layer.

[0083] Multiple contact plugs 611 are correspondingly located on the horizontal planes of the multiple steps and are in contact with multiple first electrode layers. In this embodiment, the interconnect structure 610 includes three first contact plugs, the first first contact plug and the third first contact plug are located on the first step and the third step in the step structure at the same end of the first stack 410, and the second contact plug is located on the second step in the step structure at the other end. This arrangement facilitates the first first contact plug and the third first contact plug to be connected to the same conductive line 612, that is, to the same voltage terminal, so that the bottom first electrode layer and the top first electrode layer are coordinated as the same electrode of the first capacitor structure to achieve control.

[0084] It should be noted that Figure 2 In the step structure shown, the first step and the second step reveal the first dielectric layer, and the two contact plugs 611 penetrate the first dielectric layer and are connected to the bottom first electrode layer and the middle first electrode layer respectively. In other embodiments, the first step and the second step can also directly reveal the first electrode layer. But in comparison, Figure 2 In the step structure shown, the first dielectric layer can protect the first electrode layer thereunder during the etching process step, so that the first electrode layer obtains a better morphology and thus obtains higher performance.

[0085] The two ends of the second stack 510 that are oppositely disposed along the width direction of the second groove 311 have the same structure as the two ends of the first stack 410, and can be used as regions electrically connected to the interconnection structure. The understanding of the two end structures of the second stack 510 can refer to the first stack 410, and will not be repeated here.

[0086] exist Figure 2 and Figure 4In the illustrated embodiment, the interconnect structure 610 further includes three second contact plugs, wherein the first second contact plug and the third second contact plug are located on the first step and the third step in the step structure at the same end of the second stack 510, and the second second contact plug is located on the second step in the step structure at the other end. This arrangement facilitates the first second contact plug and the third second contact plug to be connected to the same conductive line 612, that is, to the same voltage terminal, so that the bottom second electrode layer and the top second electrode layer are coordinatedly controlled as the same electrode of the second capacitor structure.

[0087] Furthermore, the second second contact plug and the second first contact plug are respectively arranged on the step structures close to each other in the first stack 410 and the second stack 510, so that the second second contact plug and the second first contact plug are connected to the same conductive line 612, so as to connect the first capacitor structure and the second capacitor structure in parallel.

[0088] In some embodiments, the semiconductor device further includes an interconnect dielectric layer 620, which covers at least the surface exposed by the first stack 410 and the second stack 510, and the surface of the substrate 100 not covered by the first stack 410 and the second stack 510. The interconnect structure 610 is located in the interconnect dielectric layer 620. The material of the interconnect dielectric layer 620 includes but is not limited to silicon oxide, doped silicon oxide, silicon nitride or other insulating materials. In this embodiment, the material of the interconnect dielectric layer 620 is silicon oxide.

[0089] In summary, in the semiconductor device provided by the embodiment of the present disclosure, the multiple capacitor structures can have different sizes, morphologies and numbers of layers, and thus have different resonant frequencies. By selecting several capacitor structures for parallel combination, filtering in different frequency bands can be achieved.

[0090] The present disclosure also provides a semiconductor device, Figure 7 A schematic diagram of a semiconductor device provided in an embodiment of the present disclosure Figure 4 ,like Figure 7 As shown, the semiconductor device includes: a substrate 100, a first capacitor structure and a second capacitor structure. A first trench 211 and a second trench 311 are formed in the substrate, the width W1 of the first trench 211 is greater than the width W2 of the second trench 311, and the depth H1 of the first trench 211 is different from the depth H2 of the second trench 311. The first capacitor structure includes a first stack 410 arranged on the inner wall of the first trench 211, the first stack 410 includes a first electrode layer 411 and a first dielectric layer 412 alternately stacked; the second stack 510 includes a second electrode layer 511 and a second dielectric layer 512 alternately stacked.

[0091] In some embodiments, the depth H1 and width W1 of the first groove 211, and the depth H2 and width W2 of the second groove 311 satisfy a preset correspondence, which refers to the correspondence between the depth and width of the grooves in the substrate under the same etching parameters related to the load effect of the etching process.

[0092] In the disclosed embodiment, the first groove 211 and the second groove 311 are formed simultaneously in the same etching process. Specifically, by utilizing the load effect of the etching process, by setting the width of the first groove to be greater than the width of the second groove, it is possible to achieve that the first groove and the second groove formed simultaneously have different depths under the same etching parameters. The different widths of the first groove and the second groove may make the number of layers of the first electrode layer included in the first stack 410 different from the number of layers of the second electrode layer included in the second stack 510, so that the capacitance density of the first capacitor structure is different from the second capacitor structure. The depth of the second groove and the second groove is different, so that the depth of the first stack and the second stack is different, so that the capacitance density of the first capacitor structure and the second capacitor structure is different. The capacitance density of the first capacitor structure and the second capacitor structure is different, which can make the capacitance value and / or equivalent inductance of the first capacitor structure and the second capacitor structure different, thereby making the resonant frequency f different. By combining capacitor structures with different resonant frequencies, different frequency bands can be filtered, so that a capacitor chip can be compatible with multi-frequency band filtering, meeting the filtering requirements of different functional modules inside the same chip.

[0093] The present disclosure also provides a system, including: a substrate, and one or more semiconductor devices as described in any of the above embodiments of the present disclosure. By way of example, the system is a chip including a silicon adapter board, wherein the silicon adapter board is an embodiment of the substrate. The semiconductor device can be mounted on the silicon adapter board. Alternatively, the semiconductor device can be directly formed on the silicon adapter board, wherein the silicon adapter board is used to form a substrate.

[0094] The present disclosure also provides a method for manufacturing a semiconductor device. Figure 8 A schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 8 , the manufacturing method comprises:

[0095] S100: forming a patterned mask layer on a substrate; a first pattern and a second pattern are formed in the patterned mask layer, and a width of the first pattern is greater than a width of the second pattern;

[0096] S200: etching the substrate based on the patterned mask layer to simultaneously form a first groove corresponding to the first pattern and a second groove corresponding to the second pattern; wherein a depth of the first groove is different from a depth of the second groove;

[0097] S300: forming a first stack on the inner wall of the first groove, and forming a second stack on the inner wall of the second groove; wherein the first stack includes alternately stacked first electrode layers and first dielectric layers, and the second stack includes alternately stacked second electrode layers and second dielectric layers.

[0098] The preparation method provided by the embodiment of the present disclosure can utilize the load effect of the etching process to simultaneously form a first groove and a second groove of different widths and depths on the same substrate, so that the first stack formed in the first groove and the second stack formed in the second groove may have different structural dimensions, morphologies or electrode layers, and thus the first capacitor structure formed by the first stack and the second capacitor structure formed by the second stack may have different capacitances and / or equivalent inductances, and have different resonant frequencies. By combining capacitor structures with different resonant frequencies in parallel, different frequency bands can be filtered, and the use of one capacitor chip compatible with multi-frequency band filtering can be achieved, which can meet the filtering requirements of different functional modules within the same chip.

[0099] In some embodiments, in step S100, the patterned mask layer includes a first graphic set and a second graphic set, the first graphic set includes a plurality of first graphics arranged side by side, and the second graphic set includes a plurality of second graphics arranged side by side. Correspondingly, step S200 specifically includes: etching the substrate based on the patterned mask layer to simultaneously form a first groove array corresponding to the first graphic set and a second groove array corresponding to the second graphic set. Correspondingly, step S300 specifically includes: forming a first stack located between the inner wall of each first groove in the first groove array and the top surface of the substrate between adjacent first grooves, and forming a second stack located between the inner wall of each second groove in the second groove array and the top surface of the substrate between adjacent second grooves.

[0100] Figure 9a to Figure 9h Schematic diagram of the structure of the semiconductor device during the preparation process provided by the embodiment of the present disclosure. Figure 8 , Figure 9a to Figure 9h The method for manufacturing a semiconductor device provided by an embodiment of the present disclosure is described in detail.

[0101] See also Figure 9a , performing step S100 to form a patterned mask layer on the substrate 100 .

[0102] In some embodiments, the base 100 includes a substrate 101 and a protective layer 102 located on the substrate 101. The patterned mask layer can be a patterned photoresist layer 700, and the patterned photoresist layer 700 is located on the protective layer 102. In other embodiments, the protective layer 102 can also be regarded as a mask layer when etching the substrate 101. In some other embodiments, a mask layer can also be provided between the protective layer 102 and the patterned photoresist layer 700. The mask layer in the embodiments of the present disclosure refers to a layer structure located on the substrate and used as a mask when etching the substrate. The present disclosure does not limit the specific material of the mask layer.

[0103] By way of example, the patterned photoresist layer 700 can be formed by a deposition process, a photolithography process, and an etching process. Specifically, the step of forming the patterned photoresist layer 700 includes: depositing a photoresist layer on the top surface of the protective layer 102; exposing the photoresist layer to form a first graphic set 710 and a second graphic set 720 in the photoresist layer, and the photoresist layer formed with the first graphic set 710 and the second graphic set 720 is a patterned photoresist layer 700. The first graphic set 710 corresponds to the first groove array, and by way of example, the top view of the first graphic set 710 is the same as that of the first groove array. The second graphic set 720 corresponds to the second groove array, and by way of example, the top view of the second graphic set 720 is the same as that of the second groove array.

[0104] Based on the above analysis of the number and size of the first groove array and the second groove array, it can be known that the number and / or size of the first graphics in the first graphic set 710 is different from the second graphics in the second graphic set 720. For example, the number of first graphics 711 in the first graphic set 710 may be different from the number of second graphics 721 in the second graphic set 720; and / or the width of the first graphics 711 is different from the width of the second graphics 721; and / or the length of the first graphics 711 is different from the length of the second graphics 721; and / or the spacing between adjacent first graphics 711 is different from the spacing between adjacent second graphics 751. In this embodiment, as Figure 9a As shown, the number of first graphics 711 is different from the number of second graphics 721, wherein the number of first graphics 711 is 4, and the number of second graphics 721 is 5. The width of the first graphics 711 is greater than the width of the second graphics 721, but the length of the first graphics 711 is equal to the length of the second graphics 721 (not shown in the figure).

[0105] See also Figure 9b, perform step S200, use the patterned mask layer 700 as a mask, and etch the protective layer 102 and the substrate 101 in sequence to simultaneously form a first groove array 210 corresponding to the first pattern set 710, and a second groove array 310 corresponding to the second pattern set 720. When etching the substrate 101, the patterned protective layer 102 is used as a mask. The first groove array 210 includes a plurality of first grooves 211 arranged side by side, and the second groove array 310 includes a plurality of second grooves 311 arranged side by side. The first grooves 211 and the second grooves 311 are both arranged in a direction perpendicular to the plane of the substrate (for example, Figure 9a The Z direction in the figure extends into the substrate 101 but does not penetrate the substrate 101.

[0106] For example, the substrate 100 may be etched using a dry etching process to form the first trench array 210 and the second trench array 310 .

[0107] In this embodiment, the width and depth of the first groove and the width and depth of the second groove are designed according to the preset corresponding relationship between the width and depth of the groove in the substrate under the same etching parameters. As mentioned above, there is a load effect in the etching process, that is, the etching depths of patterns of different widths in the same substrate are different. The present disclosure utilizes this load effect to simultaneously form grooves of different depths. The same substrate and etching parameters as those used in manufacturing the product can be used to obtain the corresponding relationship between the depth and width of the groove in the substrate through several experiments. The corresponding relationship between the depth and width of the groove in the substrate can also be obtained by combining experiments and simulations.

[0108] In this etching step, the etching parameters used when determining the above-mentioned preset corresponding relationship can be used to simultaneously etch the substrate based on the first figure and the second figure, so that the first groove and the second groove can be formed synchronously. In this way, the design of the groove structure is combined with the load effect of the etching process, and the first groove and the second groove that can meet the requirements of the final filter frequency band can be formed by etching once, thereby simplifying the manufacturing process and saving costs. Imagine that if the first groove and the second groove cannot be formed at one time, but the first groove and the second groove are formed separately, then multiple masks are required, and photoresist layers must be set multiple times, etc., which will greatly increase the process steps and increase costs. In this embodiment, the load effect of the etching process is used, and the size of the first groove and the second groove is comprehensively designed in combination with the size requirements of the filter frequency band for the groove, so that the first groove and the second groove are formed synchronously, which can shorten the manufacturing time and reduce the manufacturing cost.

[0109] After forming the first trench array and the second trench array, the patterned photoresist layer 700 is removed to facilitate subsequent processes. As an example, in this embodiment, the protective layer 102 on the top surface of the substrate 101 is retained. In other embodiments, the protective layer 102 on the top surface of the substrate can also be removed to expose the top surface of the substrate 101.

[0110] In some embodiments, see Fig.9c , after step S200 and before step S300, the manufacturing method further includes: forming an isolation layer 103 on the inner wall of each first groove 211, the inner wall of each second groove 311 and the top surface of the substrate 100 to isolate the electrode layer of the capacitor structure formed subsequently from the substrate, buffer the stress between the two, and improve the adhesion between the two.

[0111] In some embodiments, the isolation layer 103 may be formed by processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). The material of the isolation layer 103 includes, but is not limited to, silicon oxide, silicon oxide doped with nitrogen, carbon, etc., silicon nitride, or other insulating materials. In other embodiments, if the substrate 101 is a silicon substrate, then in this step, a process such as thermal oxidation may be used to oxidize the sidewalls and bottom of the first trench 211, the sidewalls and bottom of the second trench 311, and the top surface of the substrate 101 to form a silicon oxide layer, and the silicon dioxide layer serves as the isolation layer 103. In this embodiment, the material of the isolation layer 103 is deposited silicon oxide.

[0112] See also Figure 9d to Figure 9f , performing step S300 to form a first stacked body 410 in the first groove array 210 , and forming a second stacked body 510 in the second groove array 310 .

[0113] In some embodiments, the first stack 410 and the second stack 510 are formed simultaneously. The steps of forming the first stack and the second stack include: forming an initial stack on the inner wall of each first groove, the inner wall of each second groove and the top surface of the substrate, the initial stack including alternately stacked electrode material layers and dielectric material layers; patterning the initial stack to simultaneously form the first stack and the second stack isolated from each other, wherein the first stack includes alternately stacked first electrode layers and first dielectric layers, and the second stack includes alternately stacked second electrode layers and second dielectric layers.

[0114] like Figure 9d and Fig.9eAs shown, an electrode material layer 811 is formed on the inner wall of each first groove 211, the inner wall of each second groove 311 and the top surface of the substrate 100, a dielectric material layer 812 is formed on the surface of the electrode material layer 811, and another electrode material layer 811 is formed on the surface of the dielectric material layer 812, and this cycle is repeated to form an initial stack 810 in which the electrode material layers 811 and the dielectric material layers 812 are alternately stacked. For example, in this embodiment, Figure 9d It is shown that a bottom electrode material layer is formed on the surface of the adhesion layer 301, a first dielectric material layer is formed on the surface of the bottom electrode material layer, and an intermediate electrode material layer is formed on the surface of the first dielectric material layer. Fig.9e It is further shown that a second dielectric material layer is formed on the surface of the middle electrode material layer, and a top electrode material layer is formed on the surface of the second dielectric material layer. It is worth noting that since the width of the second groove 311 is small, it is sealed after the second dielectric material layer is formed, so that the top electrode material layer cannot enter the second groove 311 and is only located on the top surface of the substrate 100. The width of the first groove 211 is wide, so all layers can enter the first groove 211, so that the profiles at all locations are basically the same, all presenting an S shape.

[0115] In some embodiments, the electrode material and dielectric material layers can be formed in sequence by chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD) processes. In this embodiment, the electrode material layer 811 is made of a conductive metal or metal compound with good step coverage, such as a titanium nitride film deposited by ALD. The dielectric material layer 812 is made of a high dielectric constant film material with good step coverage, such as silicon nitride, zirconium oxide, aluminum oxide, hafnium oxide or a composite film deposited by ALD or furnace tube.

[0116] In this embodiment, by forming grooves of different widths and depths, capacitor structures of different designs are formed. The depth and number of layers of the capacitor structure will be different, thereby bringing different equivalent inductances and capacitances, thereby obtaining different resonant frequencies.

[0117] See also Figure 9f , patterning the initial stack to form a first stack 410 and a second stack 510 .

[0118] For example, the initial stack can be patterned by multiple photolithography processes and etching processes. In this embodiment, the first stack 410 and the second stack 510 each include two step structures, each step structure has three steps. For example, each step in the four step structures is formed simultaneously.

[0119] In some embodiments, the step of patterning the initial stack includes: patterning the electrode material layer and the dielectric material layer in sequence from the top electrode material layer; or, patterning the electrode material layer and the dielectric material layer in sequence from the bottom electrode material layer. The present disclosure takes patterning the initial stack in sequence from the top electrode material layer as an example for explanation.

[0120] Specifically, the top electrode material layer can be sequentially etched through the first photolithography process and the etching process to simultaneously form the third step in the four-step structure and expose the second dielectric material layer; the second dielectric material layer and the middle electrode material layer can be sequentially etched through the second photolithography process and the etching process to simultaneously form the second step in the four-step structure and expose the first dielectric material layer; the first dielectric material layer and the top electrode material layer can be etched through the third photolithography process and the etching process to simultaneously form the first step in the four-step structure and interrupt the first stack and the second stack. After the step structure is formed, the portion of the initial stack located at the first groove array 210 forms the first stack 410, and the portion located at the second groove array 310 forms the second stack 510, thereby obtaining Figure 4 The semiconductor device shown has a first stacked body 410 and a second stacked body 510 .

[0121] In some embodiments, to form Figure 3 The semiconductor devices shown, such as Fig.10a As shown, in the step of patterning the initial stack, the top electrode material layer at the second groove array 310 can be removed by an etching process. For example, in the first photolithography process and etching process, the top electrode material layer at the first groove array 210 can be etched to form the top first electrode layer 411 of the first stack 410, and the top electrode material layer at the second groove array 310 can be removed at the same time, so that the second second dielectric layer 512 is exposed at the second groove array 310.

[0122] In some embodiments, the manufacturing method also includes: forming an interconnection structure on the side of the first stack and the second stack away from the substrate; the interconnection structure is coupled to multiple first electrode layers and multiple second electrode layers, and the first capacitor structure formed by the first stack and the second capacitor structure formed by the second stack are connected in parallel.

[0123] See also Figure 9g and Fig.10b, an interconnection dielectric layer 620 may be formed on the side of the first stack and the second stack away from the substrate. The interconnection dielectric layer 620 covers the exposed surface of the first stack 410 and the second stack 510, and the exposed surface of the substrate 100 not occupied by the first stack 410 and the second stack 510. In addition, the interconnection dielectric layer 620 may also fill the remaining space in the first trench 211 not occupied by the first stack 410.

[0124] For example, the step of forming the interconnect dielectric layer includes: forming an interconnect dielectric material layer by a deposition process, and flattening the interconnect dielectric material layer to obtain the interconnect dielectric layer. The deposition process includes but is not limited to chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD). In this embodiment, considering that the first groove is a large-sized deep groove, there may still be a certain degree of voids, and a plasma-enhanced chemical vapor deposition interconnect dielectric material layer is used, so that the first groove can be sealed, and the remaining space in the first groove not occupied by the first stack can form a cavity structure, and the air in the cavity structure has a lower dielectric constant than the interconnect dielectric material, so the parasitic capacitance can be reduced. Here, the cavity structure is naturally formed when the interconnect dielectric layer is formed, and no additional steps are required, and the cost will not be increased.

[0125] For example, the interconnect dielectric material layer may be planarized by a chemical mechanical polishing (CMD) process. The material of the interconnect dielectric layer includes but is not limited to silicon oxide or other insulating materials.

[0126] See also Figure 9h and Fig.10b , an interconnection structure 610 is formed in the interconnection dielectric layer 620, and the interconnection structure 610 is connected to each electrode layer in the first stack 410 and the second stack 510 to lead out each electrode layer. The interconnection structure 610 may include a plurality of contact plugs 611 and a wiring layer connecting the plurality of contact plugs, each contact plug 611 is located on a step in the step structure, and passes through the dielectric layer at the step to contact and connect with the electrode layer. Figure 9h In the embodiment shown, three contact plugs 611 are used to lead out the three first electrode layers 411 of the first stack 410, and three contact plugs 611 are used to lead out the three second electrode layers 511 of the second stack 510. Fig.10b In the illustrated embodiment, since the second stacked body 510 includes only two second electrode layers 511 , only two contact plugs 611 are needed to lead out the two second electrode layers 511 .

[0127] The wiring layer includes a plurality of conductive wires 612, and the wiring layer can couple the positive and negative electrodes of different capacitor structures as needed to achieve parallel connection. For example, the material of the conductive wires 612 is metal. The metal can be at least one of the metals provided above, such as tungsten and copper.

[0128] The above provides a process of manufacturing the first capacitor structure and the second capacitor structure after the number and size of the first capacitor structure and the second capacitor structure are designed. In some embodiments, before the manufacturing process, the manufacturing method further includes:

[0129] Determining the resonant frequency of a plurality of capacitors connected in parallel based on a target frequency band corresponding to the target impedance; the plurality of capacitors comprising a first capacitor structure and a second capacitor structure;

[0130] Based on the resonant frequencies of the plurality of capacitors and a preset corresponding relationship, the number and size of the first grooves corresponding to the first capacitor structure and the number and size of the second grooves corresponding to the second capacitor structure are respectively determined; the preset corresponding relationship refers to the corresponding relationship between the depth and width of the grooves in the substrate under the same etching parameters related to the load effect of the etching process;

[0131] The number and size of the first patterns are determined based on the number and size of the first grooves, and the number and size of the second patterns are determined based on the number and size of the second grooves, the size including the width.

[0132] Fig.11 The design process of the first groove array and the second groove array provided in the embodiment of the present disclosure. Fig.11 Shown is the process of determining the parameters of the decoupling capacitors for the power supply terminals.

[0133] Capacitor filtering mainly uses the characteristics of capacitors that block DC and pass AC. By connecting capacitors in parallel to the power supply or signal path, the noise on the power supply or signal path can be bypassed to the ground, leaving only clean power or signal for subsequent circuits. In addition, the closer the frequency of the interference signal is to the resonant frequency of the capacitor, the easier it is to be filtered by the capacitor. This type of capacitor used for filtering is also called a decoupling capacitor or bypass capacitor. Decoupling capacitors play an important role in the power integrity and signal integrity of the product.

[0134] The first step is to establish the target impedance Z of the power supply terminal. T and the maximum frequency f T .

[0135] For example, Where ΔV is the maximum allowable ripple voltage and ΔI is the current fluctuation.

[0136] Step 2: Design and target impedance Z T and the maximum frequency f T The corresponding capacitor combinations are connected in parallel.

[0137] The capacitor combination can include multiple layers of capacitors. For example, it can include bulk capacitors, board capacitors, and even package capacitors, on-chip capacitors, etc. The impedance frequency characteristics of the entire power distribution network (composed of power terminals, wiring, and decoupling circuits) will become the impedance frequency curve of the capacitor combination. Each layer of capacitors covers a frequency region (that is, a specific frequency band) to meet the overall target impedance.

[0138] For example, Among them, L power It is the power inductance determined by the position of the power module relative to the bulk capacitor.

[0139] For example, Among them, L bilk is the wiring inductance from the bulk capacitor to the board capacitor.

[0140] In addition, the wiring length L between the board capacitor and the functional module can be established max .

[0141] For example, Among them, ESL is the residual inductance of the plate capacitor, w is the width of the wiring section, and h is the distance between the wiring and the ground layer.

[0142] A layer in the capacitor combination may include multiple capacitors with different resonant frequencies to filter a target frequency band together. Multiple capacitors with different resonant frequencies may be integrated on the same capacitor chip and manufactured by the semiconductor device manufacturing method disclosed above.

[0143] In the third step, based on the multiple capacitors with different resonant frequencies f selected in the second step, combined with the preset corresponding relationship related to the load effect of the etching process, the groove size, morphology and number of layers of the stacked body corresponding to each capacitor structure are determined. Among them, each capacitor selected in the second step corresponds to a capacitor structure.

[0144] The fourth step is to prepare a capacitor chip. Different regions of the capacitor chip may include multiple decoupling capacitors corresponding to different circuits or modules. That is, the decoupling capacitor of the power supply terminal determined above is only located in one region of the capacitor chip.

[0145] The fifth step is to select capacitors of different capacitance values ​​and different resonant frequencies in parallel after forming the capacitor chip based on the combination in the second step to realize the filtering function of the target frequency band.

[0146] Fig.12 The figure shows the filtering frequency band when three capacitors are connected in parallel. Fig.12As shown, capacitors C1 and C2 are connected in parallel to filter the target frequency band F1, while capacitors C1, C2 and C3 are connected in parallel to filter the target frequency band F2. Each of capacitors C1, C2 and C3 may correspond to a capacitance structure.

[0147] The disclosed embodiment proposes: based on the actual working requirements of the chip, a parallel combination of different capacitors is selected to achieve filtering. And through structural design, a capacitor formation process with different resonant frequencies under the same set of process flows is established, that is, the capacitor structure, morphology, number of layers, etc. are changed to achieve the change of the capacitor resonant frequency, so that a single capacitor chip has a filtering function, and can support multi-frequency band filtering in different regions, thereby improving the integration of the capacitor chip.

[0148] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: A substrate, wherein a first groove and a second groove are formed in the substrate, wherein a width of the first groove is greater than a width of the second groove, and a depth of the first groove is different from a depth of the second groove; A first capacitor structure includes a first stacked body arranged on an inner wall of the first groove, wherein the first stacked body includes first electrode layers and first dielectric layers alternately stacked; The second capacitor structure includes a second stacked body arranged on the inner wall of the second groove, and the second stacked body includes second electrode layers and second dielectric layers stacked alternately.

2. The semiconductor device according to claim 1, wherein: The depth and width of the first groove, and the depth and width of the second groove both satisfy a preset corresponding relationship; The preset corresponding relationship refers to the corresponding relationship between the depth and width of the groove in the substrate under the same etching parameters related to the load effect of the etching process.

3. The semiconductor device according to claim 1, wherein: A first groove array is formed in the substrate, the first groove array comprising a plurality of first grooves arranged side by side; wherein the first stack is located on the inner wall of each first groove in the first groove array and the top surface of the substrate between adjacent first grooves; A second groove array is formed in the substrate, and the second groove array includes a plurality of second grooves arranged side by side; wherein the second stack is located on the inner wall of each second groove in the second groove array and the top surface of the substrate between adjacent second grooves.

4. The semiconductor device according to claim 1 or 3, characterized in that: The number of the first electrode layers in the first stack is greater than the number of the second electrode layers in the second stack.

5. The semiconductor device according to claim 3, characterized in that The area ratio of the second electrode layer in the top layer to the second electrode layer in the second stack is smaller than the area ratio of the first electrode layer in the top layer to the first electrode layer in the first stack.

6. The semiconductor device according to claim 1 or 3, characterized in that: A length of the first groove along its extending direction is different from a length of the second groove along its extending direction.

7. The semiconductor device according to claim 3, characterized in that The number of first grooves in the first groove array is different from the number of second grooves in the second groove array.

8. The semiconductor device according to claim 1 or 3, characterized in that: The semiconductor device further comprises: An interconnection structure is located on a side of the first stack and the second stack away from the substrate, the interconnection structure is coupled to the first electrode layers and the second electrode layers, and connects the first capacitor structure and the second capacitor structure in parallel.

9. A semiconductor device, characterized in that: include: A substrate, wherein a first groove array and a second groove array isolated from each other are formed in the substrate, wherein the number and / or size of the first grooves in the first groove array are different from the second grooves in the second groove array; A first capacitor structure includes a first stack located on the inner wall of each first groove in the first groove array and the top surface of the substrate between adjacent first grooves, wherein the first stack includes alternately stacked first electrode layers and first dielectric layers; The second capacitor structure includes a second stack located on the inner wall of each second groove in the second groove array and the top surface of the substrate between adjacent second grooves. The second stack includes alternately stacked second electrode layers and second dielectric layers.

10. The semiconductor device according to claim 9, characterized in that The depth and width of the first groove, and the depth and width of the second groove both satisfy a preset corresponding relationship; The preset corresponding relationship refers to the corresponding relationship between the depth and width of the groove in the substrate under the same etching parameters related to the load effect of the etching process.

11. A system, characterized in that: include: substrate; One or more semiconductor devices according to any one of claims 1 to 10 are arranged on the substrate.

12. A method for manufacturing a semiconductor device, characterized in that: include: forming a patterned mask layer on a substrate; A first figure and a second figure are formed in the patterned mask layer, and a width of the first figure is greater than a width of the second figure; Etching the substrate based on the patterned mask layer to simultaneously form a first groove corresponding to the first pattern and a second groove corresponding to the second pattern; wherein the depth of the first groove is different from the depth of the second groove; A first stack is formed on the inner wall of the first groove, and a second stack is formed on the inner wall of the second groove; wherein the first stack includes alternately stacked first electrode layers and first dielectric layers, and the second stack includes alternately stacked second electrode layers and second dielectric layers.

13. The method for manufacturing a semiconductor device according to claim 12, wherein: The patterned mask layer includes a first graphic set and a second graphic set, wherein the first graphic set includes a plurality of the first graphics arranged side by side, and the second graphic set includes a plurality of the second graphics arranged side by side; The etching of the substrate based on the patterned mask layer to simultaneously form a first groove corresponding to the first pattern and a second groove corresponding to the second pattern comprises: Etching the substrate based on the patterned mask layer to simultaneously form a first groove array corresponding to the first pattern set and a second groove array corresponding to the second pattern set; The forming of the first stacked body on the inner wall of the first groove and the forming of the second stacked body on the inner wall of the second groove comprises: The first stack forms the top surface of the substrate between the inner wall of each first groove in the first groove array and the adjacent first grooves, and the second stack forms the top surface of the substrate between the inner wall of each second groove in the second groove array and the adjacent second grooves.

14. The method for manufacturing a semiconductor device according to claim 12 or 13, characterized in that: The manufacturing method further comprises: Determining the resonant frequency of a plurality of capacitors connected in parallel based on a target frequency band corresponding to the target impedance; the plurality of capacitors comprising a first capacitor structure and a second capacitor structure; Based on the resonant frequencies of the plurality of capacitors and a preset corresponding relationship, the number and size of the first grooves corresponding to the first capacitor structure and the number and size of the second grooves corresponding to the second capacitor structure are respectively determined; the preset corresponding relationship refers to the corresponding relationship between the depth and width of the grooves in the substrate under the same etching parameters related to the load effect of the etching process; The number and size of the first patterns are determined based on the number and size of the first grooves, and the number and size of the second patterns are determined based on the number and size of the second grooves, the size including the width.

15. The method for manufacturing a semiconductor device according to claim 13, wherein: The forming of the first stack and the second stack comprises: forming an initial stack covering the inner wall of each of the first grooves, the inner wall of each of the second grooves and the top surface of the substrate, wherein the initial stack comprises alternately stacked electrode material layers and dielectric material layers; The initial stack is patterned to simultaneously form the first stack and the second stack isolated from each other.

16. The method for manufacturing a semiconductor device according to claim 12 or 13, characterized in that: The manufacturing method further comprises: An interconnection structure is formed on the side of the first stack and the second stack away from the substrate; the interconnection structure is coupled to multiple first electrode layers and multiple second electrode layers, and connects a first capacitor structure formed by the first stack and a second capacitor structure formed by the second stack in parallel.

Images