Bidirectional silicon-controlled electrostatic protection device structure with NBL segmentation and manufacturing method of bidirectional silicon-controlled electrostatic protection device structure

Abstract

The invention discloses an NBL segmented bidirectional silicon controlled electrostatic protection device structure. The structure comprises a substrate P-Sub; first to fifth NBL regions are arranged in the substrate P-Sub; a high-voltage N-type low-doped NWHT region is arranged above the NBL region; a first high-voltage P-type low-doped PWHT region and a second high-voltage P-type low-doped PWHT region are arranged in the NWHT region; a first PW region is arranged above the first PWHT region; a second PW region is arranged above the second PWHT region; a first NW region is arranged between the first PW region and the second PW region; a first P + region, a first N + region and a second P + region are sequentially arranged in the first PW region from left to right; a second N + region and a third N + region are sequentially arranged in the first NW region from left to right; and a third P + region, a fourth N + region and a fourth P + region are sequentially arranged in the second PW region from left to right. According to the bidirectional silicon controlled rectifier structure with the segmented NBL, the NBL below the NWHT area is segmented, the current path of the longitudinal parasitic NPN triode is lengthened, the parasitic resistance and the voltage drop on the silicon controlled rectifier path are increased, and therefore the purpose of improving the maintaining voltage of a device is achieved.

Description

Technical Field

[0001] The invention relates to the field of electrostatic protection of semiconductor devices, and in particular to a bidirectional thyristor electrostatic protection device structure with NBL segmentation and a manufacturing method thereof. Background Art

[0002] With the continuous advancement of semiconductor process technology, integrated circuits have been widely used in various fields of modern society. However, the thickness of the gate oxide layer of transistors has become thinner and thinner, and electrostatic discharge (ESD) has become one of the main causes of integrated circuit failure. Electrostatic discharge is one of the most common phenomena in nature. It refers to the transfer of charge caused by objects with different potentials approaching or directly contacting each other, and each transfer of electrostatic charge will pose a serious threat to the reliability of integrated circuits. Therefore, more and more engineers and scholars have focused their attention on highly robust ESD electrostatic protection semiconductor devices. According to statistics on chip failure data related to the semiconductor industry, electronic system failures, chip function abnormalities, and circuit damage caused by electrostatic discharge have led to hundreds of billions of economic losses. This data fully illustrates the importance of electrostatic discharge protection design in the field of integrated circuits. Designing small-area, highly robust ESD devices is of great significance to improving integrated circuit performance and reducing costs.

[0003] At present, there are many problems in the practical application of traditional bidirectional silicon-controlled rectifiers (DDSCR). When the ESD pulse reaches the anode of the traditional DDSCR, the device forms a latch-like positive feedback loop composed of parasitic PNP and parasitic NPN under the action of the avalanche effect, which is used to release the electrostatic current. However, the holding voltage of this type of structure is usually very low. In the high-voltage field, due to the high operating voltage of the chip, the low holding voltage of the traditional DDSCR can easily cause the latch effect to burn the entire chip. Therefore, a large number of studies have focused on improving the holding voltage of the DDSCR, and the holding voltage of the device is increased by lengthening the distance between the cathode and the anode and segmenting the emitter. However, the method of lengthening the distance between the cathode and the anode increases the R&D cost of the device and requires a large layout area. The method of segmenting the emitter can significantly reduce the failure current of the device.

[0004] The structure and equivalent circuit of the traditional bidirectional thyristor rectifier are as follows Figure 1 When the anode of the device is hit by ESD, an avalanche breakdown effect occurs between its NW and cathode PW, generating a large number of avalanche carriers that enter the cathode PW of the device and P1A voltage drop is generated on the cathode. This turns on the parasitic NPN1 transistor composed of the cathode N+, PW, and NW. When NW and PW are in reverse bias, the parasitic PNP transistor composed of the anode P+, ​​anode PW, NW, and cathode PW works in the saturation region. When the NPN1 and PNP parasitic transistors enter the saturation region, the DDSCR is fully turned on, forming a low-resistance PNPN path to release the electrostatic current. However, the device's maintenance voltage is usually low. When the normal operating voltage of the protected chip is higher than the device's maintenance voltage, it is very easy to cause a latch effect and burn the chip. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides a bidirectional thyristor electrostatic protection device structure with NBL segmentation based on the study of the positive feedback mechanism of the device, which has a simple structure, small occupied area, high holding voltage, and provides a manufacturing method thereof.

[0006] The technical solution of the present invention to solve the above problems is: a bidirectional thyristor electrostatic protection device structure with NBL segmentation, characterized in that: a bidirectional thyristor electrostatic protection device structure with NBL segmentation, characterized in that: it includes a substrate P-Sub; a first NBL area, a second NBL area, a third NBL area, a fourth NBL area and a fifth NBL area are provided in the substrate P-Sub; a first NWHT area is provided above the NBL area; a first PWHT area, a second PWHT area, a first PW area, a first NW area, a second PW area, a first field oxygen isolation area, a first P+ injection area, a second field oxygen isolation area, a first N+ injection area, a third field oxygen isolation area are provided in the NWHT area from bottom to top and from left to right. region, a second P+ implantation region, a fourth field oxygen isolation region, a second N+ implantation region, a fifth field oxygen isolation region, a third N+ implantation region, a sixth field oxygen isolation region, a third P+ implantation region, a seventh field oxygen isolation region, a fourth N+ implantation region, an eighth field oxygen isolation region, a fourth P+ implantation region, and a ninth field oxygen isolation region; the first P+ implantation region, the first N+ implantation region, and the second P+ implantation region are arranged in the first PW region; the second N+ implantation region and the third N+ implantation region are arranged in the first NW region; the third P+ implantation region, the fourth N+ implantation region, and the fourth P+ implantation region are arranged in the second PW region; the first P+ implantation region is connected to the first N+ implantation region as a cathode of the device; the fourth P+ implantation region is connected to the fourth N+ implantation region as an anode of the device;

[0007] In the above-mentioned bidirectional thyristor electrostatic protection device structure with NBL segmentation, when ESD stress reaches the device anode and the device cathode is grounded, the first NW region, the first NWHT region and the first PW region undergo avalanche breakdown, and then the parasitic PNP transistor composed of the first PW region, the first NW region, the first NWHT region and the second PW region is turned on; the parasitic NPN transistor composed of the first N+ injection region, the first PW region, the first NWHT region and the first NW region L1 Transistor; parasitic NPN composed of the first N+ injection region, the first PW region, the first PWHT region, the first NWHT region, the first NBL region, the second NBL region, the third NBL region, and the first NW region V1 Transistor, NPN L1 The base region of the transistor and the NPN V1 The base region of the transistor passes through the parasitic resistance R p1 Connected to the first P+ injection region, and led from the first P+ injection region to the cathode, the emitter region of the PNP transistor is connected through the parasitic resistor R p2 Connected to the fourth P+ injection region, and led out from the fourth P+ injection region to the anode, V1 The collector region of the transistor and the base region of the PNP transistor are connected through a parasitic resistor R n1 and R n2 connected; thereby forming a bidirectional thyristor structure with NBL segmentation, lengthening the longitudinal NPN current path inside the device and the parasitic resistance through which the current flows, increasing the voltage drop, and achieving the purpose of increasing the device holding voltage.

[0008] A method for manufacturing a bidirectional thyristor electrostatic protection device structure with NBL segmentation comprises the following steps:

[0009] Step 1: forming an NBL region and an NWHT region in the substrate P-Sub;

[0010] Step 2: Forming the first to ninth field oxygen isolation regions on the substrate P-Sub by photolithography;

[0011] Step 3: forming a first PWHT region and a second PWHT region in the wrapping region of the NWHT region by photolithography;

[0012] Step 4: forming a first PW region in the first PWHT region and forming a second PW region in the second PWHT region by photolithography;

[0013] Step 5: forming a first NW region between the first PW region and the second PW region by photolithography;

[0014] Step 6: Forming a first P+ injection region and a second P+ injection region in the first PW region, and forming a third P+ injection region and a fourth P+ injection region in the second PW region by photolithography;

[0015] Step 7: By photolithography, a first N+ implantation region is formed in the first PW region, a second N+ implantation region and a third N+ implantation region are formed in the first NW region, and a fourth N+ implantation region is formed in the second PW region.

[0016] The technical solution of the present invention to solve the above problems is:

[0017] 1. The present invention constitutes a bidirectional thyristor structure with NBL segmentation, which can further lengthen the length of the internal current path, that is, the NBL layer is segmented, thereby V1 Two parasitic resistors are connected in series on the path connecting the collector region of the transistor and the base region of the PNP transistor; thereby lengthening the length of the internal current path, increasing the voltage drop on the device's thyristor current path, and achieving the purpose of increasing the device's holding voltage.

[0018] 2. The present invention uses NBL segmentation to increase the holding voltage of the device. Based on the above mechanism, the holding voltage of the device can be significantly increased without lengthening the distance between the anode and cathode of the device. Therefore, the device can significantly increase the holding voltage of the device without occupying additional chip area. In addition, the NBL segmentation method does not require emitter segmentation to increase the holding voltage of the device, and does not require reducing the width of the device current discharge path. Therefore, the device will not reduce the failure current of the device while increasing the holding voltage.

[0019] 3. The present invention does not use any special process level and is completely applicable to the standard BCD process. It can effectively protect the core chip under higher voltage operation without the risk of latch-up, and can significantly improve its reliability and stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a cross-sectional view and equivalent circuit diagram of the traditional bidirectional thyristor structure.

[0021] Figure 2 1 is a cross-section and circuit connection diagram of a bidirectional thyristor structure with NBL segmentation in an embodiment of the present invention.

[0022] Figure 3 Schematic diagram of a three-dimensional parasitic structure of a bidirectional thyristor structure with NBL segmentation in an embodiment of the present invention.

[0023] Figure 4 It is an equivalent circuit of a bidirectional thyristor structure with NBL segmentation for ESD protection in an embodiment of the present invention, namely, an ESD current release path.

[0024] Figure 5 FIG. 4 is a top view of a bidirectional thyristor structure with NBL segments in an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0026] like Figure 1-Figure 5 As shown, a bidirectional thyristor structure with NBL segmentation is characterized by:

[0027] The invention comprises a substrate P-Sub101; a first NBL region 201, a second NBL region 202, a third NBL region 203, a fourth NBL region 204 and a fifth NBL region 205 are arranged in the substrate P-Sub101; a first NWHT region 301 is arranged above the NBL region; a first PWHT region 401, a second PWHT region 402, a first PW region 501, a first NW region 601, a second PW region 502, a first field oxygen isolation region 901, a first P+ implantation region 701, a second field oxygen isolation region 902, a first N+ implantation region 801, a third field oxygen isolation region 903, a second P+ implantation region 702, a fourth field oxygen isolation region 904, a first N+ implantation region 805, a second N+ implantation region 806, a third field oxygen isolation region 907, a second P+ implantation region 708, a fourth field oxygen isolation region 909, a first N+ implantation region 810, a second N+ implantation region 811, a third field oxygen isolation region 909, a second P+ implantation region 709, a fourth field oxygen isolation region 901, a first PWHT region 401, a second PWHT region 402, a first PW region 501, a first NW region 601, a second PW region 502, a first field oxygen isolation region 901, a first P+ implantation region 701, a second field oxygen isolation region 902, a first N+ implantation region 812, a third field oxygen isolation region 903, a second P+ implantation region 702, a fourth field oxygen isolation region 904, a first N+ implantation region 813, a second N+ implantation region 814, a third field oxygen isolation region 904, a second P+ implant The first P+ injection region 701, the first N+ injection region 801 and the second P+ injection region 702 are arranged in the first PW region 501; the second N+ injection region 802 and the third N+ injection region 803 are arranged in the first NW region 601; the third P+ injection region 703, the fourth N+ injection region 804 and the fourth P+ injection region 704 are arranged in the second PW region 502.

[0028] The first P+ injection region 701 is connected to the first metal layer 1001 of metal layer 1 through a contact hole, the first N+ injection region 801 is connected to the second metal layer 1002 of metal layer 1 through a contact hole, a metal through hole 1201 is provided on the first metal layer 1101 of metal layer 2, the first metal layer 1001 and the second metal layer 1002 of metal layer 1 are connected to the first metal layer 1101 of metal layer 2 through the metal through hole 1201, and are used as the cathode of the device.

[0029] The fourth N+ injection region 804 is connected to the third metal layer 1003 of metal layer 1 through a contact hole, the fourth P+ injection region 704 is connected to the fourth metal layer 1004 of metal layer 1 through a contact hole, a metal through hole 1202 is provided on the second metal layer 1102 of metal layer 2, the third metal layer 1003 and the fourth metal layer 1004 of metal layer 1 are connected to the second metal layer 1102 of metal layer 2 through the metal through hole 1202, and are used as the anode of the device.

[0030] A method for manufacturing a bidirectional thyristor electrostatic protection device structure with NBL segmentation comprises the following steps:

[0031] Step 1: forming a first NBL region 201, a second NBL region 202, a third NBL region 203, a fourth NBL region 204, a fifth NBL region 205, and a first NWHT region 301 in the substrate P-Sub101; specifically:

[0032] The first NBL region 201, the second NBL region 202, the third NBL region 203, the fourth NBL region 204, the fifth NBL region 205, and the first NWHT region 301 are formed on the surface of the substrate P-Sub101, and then a layer of silicon dioxide film is formed by thermal oxidation to alleviate the stress damage caused by silicon nitride formed in subsequent process steps. A layer of silicon nitride is deposited by chemical vapor deposition (LPCVD) technology as a stop layer for CMP in subsequent process steps.

[0033] The photoresist is evenly applied on the wafer, and the photoresist is exposed and developed. This step is used to define the shallow trench isolation (STI). Then the silicon nitride, silicon dioxide and isolation shallow trench are etched to remove the photoresist layer, and a layer of silicon dioxide is deposited by chemical vapor deposition (LPCVD). After that, chemical mechanical polishing is performed until the silicon nitride film layer is reached, and the silicon nitride film layer is removed by hot phosphoric acid wet etching.

[0034] Step 2: By photolithography, a first field oxygen isolation region 901, a second field oxygen isolation region 902, a third field oxygen isolation region 903, a fourth field oxygen isolation region 904, a fifth field oxygen isolation region 905, a sixth field oxygen isolation region 906, a seventh field oxygen isolation region 907, an eighth field oxygen isolation region 908, and a ninth field oxygen isolation region 909 are formed on the substrate P-Sub101. Specifically:

[0035] Using field oxygen (LOCOS) isolation technology, a silicon dioxide film layer is grown by thermal oxidation as a buffer layer, and then silicon nitride is deposited by chemical vapor deposition (LPCVD) technology, and photoresist is applied on the wafer, and photolithography technology is used to define the first field oxygen isolation region 901, the second field oxygen isolation region 902, the third field oxygen isolation region 903, the fourth field oxygen isolation region 904, the fifth field oxygen isolation region 905, the sixth field oxygen isolation region 906, the seventh field oxygen isolation region 907, the eighth field oxygen isolation region 908, and the ninth field oxygen isolation region 909. Then, the reactive ions will etch away the silicon nitride on the first field oxygen isolation region 901, the second field oxygen isolation region 902, the third field oxygen isolation region 903, the fourth field oxygen isolation region 904, the fifth field oxygen isolation region 905, the sixth field oxygen isolation region 906, the seventh field oxygen isolation region 907, the eighth field oxygen isolation region 908, and the ninth field oxygen isolation region 909, and then field region implantation is performed to prevent the field region from being opened.

[0036] Step 3: Form the first PWHT region 401 and the second PWHT region 402 in the first NWHT region 301 by photolithography. Specifically:

[0037] A photoresist is coated on the wafer to define the first PWHT region 401 and the second PWHT region 402 , and then high-energy boron ions are implanted to form a local P-type region, and the photoresist layer is removed.

[0038] The first PWHT region 401 and the second PWHT region 402 are annealed to repair the crystal damage on the silicon surface caused by ion implantation, activate the implanted impurities, and eliminate further diffusion of the impurities by using the RTP process.

[0039] Step 4: forming a first NW region 601 in the first NWHT region 301 by photolithography.

[0040] Step 5: forming a first PW region 501 in the first PWHT region 401 and forming a second PW region 502 in the second PWHT region 402. Specifically:

[0041] A photoresist is coated on the wafer to define the first NW region 601 , and then high-energy phosphorus ions are implanted to form a local N-type region, and the photoresist layer is removed.

[0042] A photoresist is coated on the wafer to define the first PW region 501 and the second PW region 502, and then high-energy boron ions are implanted to form a local P-type region, and the photoresist is removed.

[0043] The first NW region 601, the first PW region 501, and the second PW region 502 are annealed to repair the crystal damage on the silicon surface caused by ion implantation, activate the implanted impurities, and eliminate further diffusion of impurities using the RTP process.

[0044] Step 6: By photolithography, a first P+ injection region and a second P+ injection region are formed in the first PW region, and a third P+ injection region and a fourth P+ injection region are formed in the second PW region; specifically:

[0045] Photoresist forming is used to control ion implantation, shallow depth, heavily doped boron ion implantation, remove the photoresist layer, and form the first P+ implantation area 701, the second P+ implantation area 702, the third P+ implantation area 703, and the fourth P+ implantation area 704.

[0046] Step 7: By photolithography, a first N+ implantation region is formed in the first PW region, a second N+ implantation region and a third N+ implantation region are formed in the first NW region, and a fourth N+ implantation region is formed in the second PW region. Specifically:

[0047] Photoresist forming is used to control ion implantation, shallow depth, heavily doped arsenic ion implantation, and remove the photoresist layer to form the first N+ implantation area 801, the second N+ implantation area 802, the third N+ implantation area 803, and the fourth N+ implantation area 804.

[0048] The present invention constitutes a bidirectional thyristor structure with NBL segmentation, which can further lengthen the length of the internal current path of the device, that is, the internal NBL layer is segmented, such as Figure 2 and Figure 3 As shown. Thus, a bidirectional thyristor rectifier with NBL segmentation is formed, which increases the voltage drop on the current path inside the device and achieves the purpose of increasing the device holding voltage. The present invention adopts a bidirectional thyristor structure with NBL segmentation, and its equivalent circuit and top view are shown in Figure 4 and Figure 5 Specifically:

[0049] When the ESD stress reaches the anode of the device and the cathode of the device is grounded, the first NW region 601, the first NWHT region 301 and the first PW region 501 undergo avalanche breakdown, and then the parasitic PNP transistor composed of the first PW region 501, the first NW region 601, the first NWHT region 301 and the second PW region 502 is turned on; the parasitic NPN transistor composed of the first N+ injection region 801, the first PW region 501, the first NWHT region 301 and the first NW region 601 is turned on. L1 The first N+ injection region 801, the first PW region 501, the first PWHT region 401, the first NWHT region 301, the first NBL region 201, the second NBL region 202, the third NBL region 203, and the first NW region 601 constitute a parasitic NPN V1 Transistor, NPN L1 The base region of the transistor and the NPN V1 The base region of the transistor passes through the parasitic resistance R p1Connected to the first P+ injection region, and led from the first P+ injection region 701 to the cathode, the emitter region of the PNP transistor is connected to the first P+ injection region 701 through the parasitic resistor R p2 Connected to the fourth P+ injection region, and led out from the fourth P+ injection region 804 to the anode, V1 The collector region of the transistor and the base region of the PNP transistor are connected through a parasitic resistor R n1 and R n2 Thus, a bidirectional thyristor structure with NBL segmentation is formed, which lengthens the current path inside the device, increases the parasitic resistance and voltage drop on the path, and achieves the purpose of increasing the device holding voltage.

[0050] In summary, the present invention provides a bidirectional thyristor electrostatic protection device structure with NBL segmentation and a manufacturing method thereof, which has a simple structure and standardized process. The bidirectional thyristor electrostatic protection device structure with NBL segmentation is fully compatible with the standard BCD process, and does not use masks other than the standard process, so that the bidirectional thyristor electrostatic protection device has a larger holding voltage, which can effectively protect the core chip under higher voltage operation, and there is no risk of latch-up, with high reliability and high stability.

Claims

1. A bidirectional thyristor electrostatic protection device structure with NBL segmentation, characterized in that: include: Substrate P-Sub; The substrate P-Sub is provided with a first NBL region, a second NBL region, a third NBL region, a fourth NBL region and a fifth NBL region; a first NWHT region is provided above the NBL region; The NWHT region is provided with a first PWHT region and a second PWHT region from left to right in sequence; above the first PWHT region and the second PWHT region, a first PW region, a first NW region, and a second PW region are provided in sequence from left to right; above the first PW region, the first NW region, and the second PW region, a first field oxygen isolation region, a first P+ implantation region, a second field oxygen isolation region, a first N+ implantation region, a third field oxygen isolation region, a second P+ implantation region, a fourth field oxygen isolation region, a second N+ implantation region, a fifth field oxygen isolation region, a third N+ implantation region, a sixth field oxygen isolation region, a third P+ implantation region, a seventh field oxygen isolation region, a fourth N+ implantation region, an eighth field oxygen isolation region, a fourth P+ implantation region, and a ninth field oxygen isolation region are provided in sequence from left to right; The first P+ implantation region, the first N+ implantation region and the second P+ implantation region are arranged in the first PW region; The second N+ implantation region and the third N+ implantation region are arranged in the first NW region; The third P+ injection region, the fourth N+ injection region and the fourth P+ injection region are arranged in the second PW region; The first P+ implantation region is connected to the first N+ implantation region as a cathode of the device; The fourth P+ implantation region is connected to the fourth N+ implantation region as an anode of the device.

2. The bidirectional thyristor electrostatic protection device structure with NBL segmentation according to claim 1 is characterized in that: When the ESD stress reaches the anode of the device and the cathode of the device is grounded, the first NW region, the first NWHT region and the first PW region undergo avalanche breakdown, and then the parasitic PNP transistor composed of the first PW region, the first NW region, the first NWHT region and the second PW region is turned on; the parasitic NPN transistor composed of the first N+ injection region, the first PW region, the first NWHT region and the first NW region is turned on. L1 Transistor; parasitic NPN composed of the first N+ injection region, the first PW region, the first PWHT region, the first NWHT region, the first NBL region, the second NBL region, the third NBL region, and the first NW region V1 Transistor, NPN L1 The base region of the transistor and the NPN V1 The base region of the transistor passes through the parasitic resistance R P1 Connected to the first P+ injection region, and led from the first P+ injection region to the cathode, the emitter region of the PNP transistor is connected through the parasitic resistor R P2 Connected to the fourth P+ injection region, and led out from the fourth P+ injection region to the anode, V1 The collector region of the transistor and the base region of the PNP transistor are connected through a parasitic resistor R n1 and R n2 connected; thereby forming a bidirectional thyristor structure with NBL segments.

3. The bidirectional thyristor electrostatic protection device structure with NBL segmentation according to claim 1, characterized in that: Also includes: Metal layer 1 and metal layer 2; The first P+ injection region is connected to the first metal layer of metal layer 1 through a contact hole, the first N+ injection region is connected to the second metal layer of metal layer 1 through a contact hole, a metal through hole is provided on the first metal layer of metal layer 2, the first metal layer and the second metal layer of metal layer 1 are connected to the first metal layer of metal layer 2 through the metal through hole, and are used as the cathode of the device.

4. The bidirectional thyristor electrostatic protection device structure with NBL segmentation according to claim 1, characterized in that: Also includes: Metal layer 1 and metal layer 2; the fourth N+ injection region is connected to the third metal layer of metal layer 1 through a contact hole, the fourth P+ injection region is connected to the fourth metal layer of metal layer 1 through a contact hole, a metal through hole is provided on the second metal layer of metal layer 2, the third metal layer of metal layer 1 and the fourth metal layer 1004 are connected to the second metal layer of metal layer 2 through the metal through hole, and are used as the anode of the device.

5. A method for manufacturing a bidirectional thyristor electrostatic protection device structure with NBL segmentation according to any one of claims 1 to 4, characterized in that: The following steps are involved: Step 1: forming an NBL region and an NWHT region in the substrate P-Sub; Step 2: Forming the first to ninth field oxygen isolation regions on the substrate P-Sub by photolithography; Step 3: forming a first PWHT region and a second PWHT region in the wrapping region of the NWHT region by photolithography; Step 4: forming a first PW region in the first PWHT region and forming a second PW region in the second PWHT region by photolithography; Step 5: forming a first NW region between the first PW region and the second PW region by photolithography; Step 6: Forming a first P+ injection region and a second P+ injection region in the first PW region, and forming a third P+ injection region and a fourth P+ injection region in the second PW region by photolithography; Step 7: By photolithography, a first N+ implantation region is formed in the first PW region, a second N+ implantation region and a third N+ implantation region are formed in the first NW region, and a fourth N+ implantation region is formed in the second PW region.

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