Grid-control enhanced asymmetric bidirectional silicon-controlled electrostatic protection device and manufacturing method thereof

Abstract

The invention discloses a grid-control enhanced asymmetric bidirectional silicon-controlled electrostatic protection device and a manufacturing method thereof. A first NBL region is arranged in the substrate P-Sub; a first annular HVNW region, a first P-Epi region and a second P-Epi region are arranged above the NBL region; first to fourth PW regions and first to third NW regions are arranged above the HVNW region and the P-Epi region; a first P + injection region is arranged in the first PW region; a first strip-shaped polysilicon gate, a second P + injection region, a second trapezoidal polysilicon gate, a first N + injection region and a third P + injection region are arranged in the second PW region; a second N + injection region is arranged in the second NW region; a third strip-shaped polysilicon gate, a fourth P + injection region, a fourth trapezoidal polysilicon gate, a third N + injection region and a fifth P + injection region are arranged in the third PW region; a fourth N + injection region is arranged in the third NW region; and a sixth P + injection region is arranged in the fourth PW. According to the grid-control enhanced asymmetric bidirectional silicon controlled rectifier, the polysilicon gate is embedded in the N + injection region, so that the grid-control effect is enhanced, the emission efficiency of parasitic NPN is reduced, and the maintaining voltage is improved.

Description

Technical Field

[0001] The present invention relates to the field of electrostatic protection of semiconductor devices, and in particular to a gate-controlled enhanced asymmetric bidirectional thyristor electrostatic protection device and a manufacturing method thereof. Background Art

[0002] With the continuous progress of society and the continuous improvement of scientific and technological levels, the development of integrated circuits (ICs) has developed from submicron to deep submicron and has entered the nanometer level. With the continuous development of semiconductor technology, chip size has gradually decreased, and the number of transistors that can be integrated per unit chip area has continued to increase, which makes the chip more sensitive to electrostatic discharge (ESD). The accumulation of electrostatic charge is ubiquitous and widely present in all areas of daily life. Therefore, more and more IC designers have begun to focus on ESD protection of semiconductors. Relevant data show that in the application of integrated circuits and microelectronic products, failures caused by ESD will cause hundreds of billions of economic losses each year, which reflects the importance of ESD protection in electronic product design. In the field of high voltage, this problem is particularly prominent. High operating voltage brings a series of troubles to ESD design, which requires ESD protection devices to have fast turn-on speed, high holding voltage and high failure current.

[0003] At present, there are many problems with the actual use of traditional silicon controlled rectifiers (SCRs). When the ESD pulse reaches the anode of the traditional SCR, the device forms a positive feedback loop composed of parasitic PNP and parasitic NPN under the action of the avalanche effect to release the electrostatic current, which makes the traditional SCR have a lower holding voltage. However, in the high-voltage field, due to the high operating voltage of the chip, the low holding voltage of the traditional SCR is prone to cause a latch effect and burn the entire chip. In addition, since the reverse path of the traditional SCR is equivalent to a forward-biased diode, it cannot be applied to a bidirectional port. The above shortcomings make the traditional SCR unable to effectively protect the internal core circuit of the chip.

[0004] The structure and equivalent circuit of traditional silicon controlled rectifier are as follows Figure 1 When the anode of the device is hit by ESD, an avalanche breakdown effect occurs between the anode NW and the cathode PW, generating a large number of avalanche carriers that enter the cathode PW of the device and P1A voltage drop is generated on the cathode. This turns on the parasitic NPN transistor composed of the cathode N+, PW, and NW. When NW and PW are in reverse bias, the parasitic PNP transistor composed of the anode P+, ​​anode PW, and cathode PW operates in the saturation region. When the NPN and PNP parasitic transistors enter the saturation region, the traditional SCR is fully turned on, forming a low-resistance PNPN path to release the electrostatic current, and the thyristor path is fully turned on. At this time, the traditional SCR produces a negative resistance phenomenon, and the current continues to increase while the voltage decreases. However, the maintenance voltage of the device is usually low. When the normal operating voltage of the protected chip is higher than the device maintenance voltage, it is very easy to cause a latch effect and burn the chip. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides a gate-controlled enhanced asymmetric bidirectional thyristor electrostatic protection device with simple structure, high failure current and high holding voltage based on the research on asymmetric bidirectional thyristor, and provides a manufacturing method thereof.

[0006] The technical solution of the present invention to solve the above problems is: a gate-controlled enhanced asymmetric bidirectional thyristor electrostatic protection device, characterized in that: it includes a substrate P-Sub; a first NBL area is provided in the substrate P-Sub; a first annular HVNW area and first to second P-Epi areas are provided above the NBL area. The HVNW region and P-Epi are provided with a first PW region, a first NW region, a second PW region, a second NW region, a third PW region, a third NW region, a fourth PW region, a first field oxygen isolation region, a first P+ injection region, a second field oxygen isolation region, a first multi-strip crystalline silicon gate, a second P+ injection region, a second trapezoidal polysilicon gate, a first N+ injection region, a third P+ injection region, a third field oxygen isolation region, a second N+ injection region, a fourth field oxygen isolation region, a third strip polysilicon gate, a fourth P+ injection region, a fourth trapezoidal polysilicon gate, a third N+ injection region, a fifth P+ injection region, a fifth field oxygen isolation region, a fourth N+ injection region, a sixth field oxygen isolation region, a sixth P+ injection region and a seventh field oxygen isolation region in sequence from bottom to top and from left to right. The first P+ injection region is arranged in the first PW region; the first strip-shaped polysilicon gate, the second P+ injection region, the second trapezoidal polysilicon gate, the first N+ injection region, and the third P+ injection region are arranged in the second PW region; the second N+ injection region is arranged in the second NW region; the third strip-shaped polysilicon gate, the fourth P+ injection region, the fourth trapezoidal polysilicon gate, the third N+ injection region, and the fifth P+ injection region are arranged in the third PW region; the fourth N+ injection region is arranged in the third NW region; the sixth P+ injection region is arranged in the fourth PW region. The first P+ injection region, the first strip-shaped polysilicon gate, the second P+ injection region, the second trapezoidal polysilicon gate, the first N+ injection region, and the sixth P+ injection region are connected as the cathode of the device; the third strip-shaped polysilicon gate, the fourth P+ injection region, the fourth trapezoidal polysilicon gate, and the third N+ injection region are connected as the anode of the device;

[0007] In the above-mentioned gate-controlled enhanced asymmetric bidirectional thyristor electrostatic protection device, when the ESD stress reaches the anode of the device and the cathode of the device is grounded, the second NW region, the first HVNW region, the second PW region, and the first P-Epi region undergo avalanche breakdown, and then the parasitic PNP1 transistor composed of the second PW region, the first P-Epi region, the second NW region, the first HVNW region, the third PW region, and the second P-Epi region is turned on; the parasitic NPN1 transistor composed of the first N+ injection region, the second PW region, the first P-Epi region, the first HVNW region, the second NW region, the first HVNW region, the second NW region, the first N+ injection region, the second PW region, the first P-Epi region, the first HVNW region, and the second NW region is turned on; the base region of the NPN1 transistor is connected through the parasitic resistor R P1 Connected to the second P+ injection area, and led to the cathode by the second P+ injection area. When the ESD stress reaches the cathode of the device and the anode of the device is grounded, the third NW area, the first HVNW area, the third PW area, and the second P-Epi area undergo avalanche breakdown, and then the parasitic PNP2 transistor composed of the third PW area, the second P-Epi area, the third NW area, the first HVNW area, and the fourth PW area is turned on; the parasitic NPN2 transistor composed of the third N+ injection area, the third PW area, the second P-Epi area, the third NW area, and the first HVNW area is turned on; the base area of ​​the NPN2 transistor is connected to the cathode of the device and the anode of the device is grounded. P2 Connected to the fourth P+ injection area, and led to the anode by the fourth P+ injection area. Thus, a gate-controlled enhanced asymmetric bidirectional thyristor electrostatic protection device is formed. By segmenting the first N+ injection area and the third N+ injection area and embedding the polysilicon gate, a trapezoidal polysilicon gate is formed, thereby enhancing the gate control effect, using the gate electric field to drive the current to a deeper path, and improving the robustness of the device. In addition, the segmentation of the emitter N+ injection area reduces the emission efficiency of the parasitic NPN and improves the holding voltage of the device.

[0008] A method for manufacturing a gate-controlled enhanced asymmetric bidirectional thyristor electrostatic protection device comprises the following steps:

[0009] Step 1: forming an NBL region, a P-Epi region and an annular HVNW region in the substrate P-Sub;

[0010] Step 2: Forming the first to seventh field oxygen isolation regions on the substrate P-Sub by photolithography;

[0011] Step 3: sequentially forming the first to third NW regions in the first HVNW region by photolithography;

[0012] Step 4: Forming the first to fourth PW regions in P-Sub and P-Epi in sequence by photolithography;

[0013] Step 5: forming a first strip-shaped polysilicon gate and a second trapezoidal polysilicon gate in the second PW region, and forming a third strip-shaped polysilicon gate and a fourth trapezoidal polysilicon gate in the third PW region.

[0014] Step six: By photolithography, a first P+ injection region is formed in the first PW region, second and third P+ injection regions are formed in the second PW region, fourth and fifth P+ injection regions are formed in the third PW region, and a sixth P+ injection region is formed in the fourth PW region.

[0015] Step seven: by photolithography, a first N+ implantation region is formed in the first PW region, a second N+ implantation region is formed in the second NW region, a third N+ implantation region is formed in the third PW region, and a fourth N+ implantation region is formed in the third NW region.

[0016] The technical solution of the present invention to solve the above problems is:

[0017] 1. The present invention constitutes a gate-controlled enhanced asymmetric bidirectional thyristor electrostatic protection device, which segments the emitter N+ injection region of the forward thyristor path and the reverse thyristor path, thereby reducing the area of ​​the emitter N+ injection region and the emission efficiency of the parasitic NPN transistor, thereby suppressing the positive feedback effect of the thyristor. This method does not require additional chip area and the introduction of special layers, and is fully compatible with traditional CMOS processes, and can effectively improve the device holding voltage.

[0018] 2. The present invention segments the emitter N+ injection region of the forward thyristor and the reverse thyristor and embeds the polysilicon gate, thereby enhancing the gate's ability to control the thyristor current, and aggregates the surface parasitic current path with the main thyristor current path, thereby extending the SCR current path and effectively increasing the device's holding voltage. In addition, since there is an electric field with the same direction as the current path under the gate, the SCR current flows to a deeper path, thereby increasing the current release capacity per unit area, effectively improving the device's robustness and failure current.

[0019] 3. The process level used in the present invention is simple, no additional special level is required, and the implementation process is simple. The operation of segmenting the emitter N+ injection area and embedding the gate can be implemented through EDA software without breaking the design rules in the process file. In addition, the structure can modulate the segment ratio of the emitter N+ injection area according to the requirements of different voltage domains to meet the requirements of the maintenance voltage, thereby effectively protecting the core chip from the impact of external electrostatic discharge. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a cross-sectional view and equivalent circuit diagram of the traditional thyristor structure.

[0021] Figure 2The cross section and circuit connection diagram of the gate control effect enhanced asymmetric bidirectional thyristor structure in the embodiment of the present invention.

[0022] Figure 3 It is a schematic diagram of the three-dimensional structure of an asymmetric bidirectional thyristor structure with enhanced gate control effect in an embodiment of the present invention.

[0023] Figure 4 It is an equivalent circuit of an asymmetric bidirectional thyristor structure of gate-controlled effect enhancement type for ESD protection in an embodiment of the present invention, namely, an ESD current release path.

[0024] Figure 5 It is a top view of an asymmetric bidirectional thyristor structure with enhanced gate control effect in an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0026] like Figure 1-Figure 5 As shown, a gate-controlled effect enhanced asymmetric bidirectional thyristor structure is characterized by:

[0027] The invention comprises a substrate P-Sub101; a first NBL region 201 is provided in the substrate P-Sub101; a first annular HVNW region 301 and a first P-Epi region 401 and a second P-Epi region 402 are provided above the NBL region; a first PW region 501, a second PW region 502, a third PW region 503, a fourth PW region 504, a first NW region 601, a second NW region 602 and a third NW region 603 are provided above the HVNW region and the P-Epi region; a first P+ injection region 701 is provided in the first PW region 501; a first P+ injection region 702 is provided in the second PW region 502; a first P+ injection region 703 is provided in the second PW region 502; a first P+ injection region 704 is provided in the first PW region 501; a first P+ injection region 705 is provided in the second PW region 502; a first P+ injection region 706 is provided in the second PW region 502; a first P+ injection region 707 is provided in the first PW region 501; a first P+ injection region 708 is provided in the second PW region 502; a first P+ injection region 709 is provided in the first PW region 501; a first P+ injection region 709 is provided in the second PW region 502; a first P+ injection region 709 is provided in the first PW region 501; a first P+ injection region 701 is provided in the second PW region 502; a first P+ injection region 709 is provided in the first PW region 501; a first P+ injection region 709 is provided in the second PW region 502; a first P+ injection region 701 is provided in the first PW region 501; a From left to right, there are successively provided with a first strip-shaped polysilicon gate 1001, a second P+ injection region 702, a second trapezoidal polysilicon gate 1002, a first N+ injection region 801 and a third P+ injection region 703; a second N+ injection region 802 is provided in the second NW region 602; a third strip-shaped polysilicon gate 1003, a fourth P+ injection region 704, a fourth trapezoidal polysilicon gate 1003 and a third N+ injection region 803; a fourth N+ injection region 804 is provided in the third NW region 603; a sixth P+ injection region 706 is provided in the fourth PW504.

[0028] The first P+ injection region 701 is connected to the first metal layer 1101 of the metal layer 1 through a contact hole, the first strip-shaped polysilicon gate 1001 is connected to the second metal layer 1102 of the metal layer 1 through a contact hole, the second P+ injection region 702 is connected to the third metal layer 1103 of the metal layer 1 through a contact hole, the second trapezoidal polysilicon gate 1002 is connected to the fourth metal layer 1104 of the metal layer 1 through a contact hole, and the first N+ injection region 801 is connected to the fourth metal layer 1104 of the metal layer 1 through a contact hole. The fifth metal layer 1105 of the metal layer 1 is connected, and the sixth P+ injection region 706 is connected to the tenth metal layer 1110 of the metal layer 1 through a contact hole. The first metal layer 1101, the second metal layer 1102, the third metal layer 1103, the fourth metal layer 1104, the fifth metal layer 1105, and the tenth metal layer 1110 of the metal layer 1 are connected to the first metal layer 1301 of the metal layer 2 through the metal through hole 1201, and are used as the anode of the device.

[0029] The third strip-shaped polysilicon gate 1003 is connected to the sixth metal layer 1106 of the metal layer 1 through a contact hole, the fourth P+ injection region 803 is connected to the seventh metal layer 1107 of the metal layer 1 through a contact hole, the fourth trapezoidal polysilicon gate 1004 is connected to the eighth metal layer 1108 of the metal layer 1 through a contact hole, the third N+ injection region 803 is connected to the ninth metal layer 1109 of the metal layer 1 through a contact hole, the sixth metal layer 1106, the seventh metal layer 1107, the eighth metal layer 1108 and the ninth metal layer 1109 of the metal layer 1 are connected to the second metal layer 1302 of the metal layer 2 through the metal through hole 1202, and are used as the cathode of the device.

[0030] A method for manufacturing a gate-controlled enhanced asymmetric bidirectional thyristor electrostatic protection device comprises the following steps:

[0031] Step 1: forming a first NBL region 201, a first annular HVNW region 301, a first P-Epi region 401, and a second P-Epi region 402 in the substrate P-Sub101. Specifically:

[0032] The first NBL region 201, the first annular HVNW region 301, the first P-Epi region 401, and the second P-Epi region 402 are formed on the surface of the substrate P-Sub101. Then, a layer of silicon dioxide film is formed by thermal oxidation to alleviate the stress damage caused by silicon nitride formed in the subsequent process steps. A layer of silicon nitride is deposited by chemical vapor deposition (LPCVD) technology as a stop layer for CMP in the subsequent process steps.

[0033] The photoresist is evenly applied on the wafer, and the photoresist is exposed and developed. This step is used to define the shallow trench isolation (STI). Then the silicon nitride, silicon dioxide and isolation shallow trench are etched to remove the photoresist layer, and a layer of silicon dioxide is deposited by chemical vapor deposition (LPCVD). After that, chemical mechanical polishing is performed until the silicon nitride film layer is reached, and the silicon nitride film layer is removed by hot phosphoric acid wet etching.

[0034] Step 2: By photolithography, a first field oxygen isolation region 901, a second field oxygen isolation region 902, a third field oxygen isolation region 903, a fourth field oxygen isolation region 904, a fifth field oxygen isolation region 905, a sixth field oxygen isolation region 906, and a seventh field oxygen isolation region 907 are formed on the substrate P-Sub101. Specifically:

[0035] Using field oxygen (LOCOS) isolation technology, a silicon dioxide film layer is grown by thermal oxidation as a buffer layer, and then silicon nitride is deposited by chemical vapor deposition (LPCVD) technology, and photoresist is applied on the wafer, and photolithography technology is used to define the first field oxygen isolation region 901, the second field oxygen isolation region 902, the third field oxygen isolation region 903, the fourth field oxygen isolation region 904, the fifth field oxygen isolation region 905, the sixth field oxygen isolation region 906, and the seventh field oxygen isolation region 907. Then, the reactive ions will etch away the silicon nitride on the first field oxygen isolation region 901, the second field oxygen isolation region 902, the third field oxygen isolation region 903, the fourth field oxygen isolation region 904, the fifth field oxygen isolation region 905, the sixth field oxygen isolation region 906, the seventh field oxygen isolation region 907, the eighth field oxygen isolation region 908, and the ninth field oxygen isolation region 909, and then field region injection is performed to prevent the field region from being turned on.

[0036] Step 3: By photolithography, a first PW region 501 and a fourth PW region 504 are formed on the substrate P-Sub101, a second PW region 502 and a third PW region 503 are sequentially formed in the first P-Epi region 401 and the second P-Epi region 402, and a first NW region 601, a second NW region 602 and a third NW region 603 are sequentially formed in the first annular HVNW301. Specifically:

[0037] A photoresist is coated on the wafer to define the first PW region 501, the second PW region 502, the third PW region 503 and the fourth PW region 504, and then high-energy boron ions are implanted to form a lightly doped P-type region, and the photoresist layer is removed.

[0038] A photoresist is coated on the wafer to define the first NW region 601 , the second NW region 602 and the third NW region 603 , and then high-energy phosphorus ions are implanted to form a local N-type region, and the photoresist layer is removed.

[0039] The first PW region 501, the second PW region 502, the third PW region 503, the fourth PW region 504, the first NW region 601, the second NW region 602 and the third NW region 603 are annealed to repair the crystal damage on the silicon surface caused by ion implantation, activate the implanted impurities, and eliminate further diffusion of impurities using the RTP process.

[0040] Step 4: forming a first strip-shaped polysilicon gate 1001 and a second trapezoidal polysilicon gate 1002 in the second P-Well region 502, and forming a third strip-shaped polysilicon gate 1003 and a fourth trapezoidal polysilicon gate 1004 in the third P-Well region 503. Specifically:

[0041] The growth of the sacrificial oxide layer is used to capture defects on the silicon surface. The gate oxide layer is grown and used as the gate insulating layer of the transistor. The first strip-shaped polysilicon gate 1001, the second trapezoidal polysilicon gate 1002, the third strip-shaped polysilicon gate 1003 and the fourth trapezoidal polysilicon gate 1004 are deposited by chemical vapor deposition (LPCVD). Photoresist molding and polysilicon etching are required to accurately obtain the specific shape of polysilicon from the photoresist and remove the photoresist layer. Polysilicon oxidation is used to buffer the isolation polysilicon and the silicon nitride formed in the subsequent steps. A layer of silicon nitride is deposited by chemical vapor deposition (LPCVD), and the silicon nitride is etched to leave the isolation sidewalls, and the ion implantation of the source and drain regions of the transistor is accurately positioned.

[0042] Step 5: By photolithography, a first P+ injection region 701 is formed in the first PW region 501, a second P+ injection region 702 and a third P+ injection region 703 are formed in the second PW region 502, a fourth P+ injection region 704 and a fifth P+ injection region 705 are formed in the third PW region 503, and a sixth P+ injection region 706 is formed in the fourth PW region 504. Specifically:

[0043] Photoresist forming is used to control ion injection, shallow depth, heavily doped boron ion injection, remove the photoresist layer, and form the first P+ injection area 701, the second P+ injection area 702, the third P+ injection area 703, the fourth P+ injection area 704, the fifth P+ injection area 705 and the sixth P+ injection area 706.

[0044] Step 6: By photolithography, a first N+ implantation region 801 is formed in the second PW region 502, a second N+ implantation region 802 is formed in the second NW region 602, a third N+ implantation region 803 is formed in the third PW region 503, and a fourth N+ implantation region 804 is formed in the third NW region 603. Specifically:

[0045] Photoresist forming is used to control ion implantation, shallow depth, heavily doped arsenic ion implantation, and remove the photoresist layer to form the first N+ implantation area 801, the second N+ implantation area 802, the third N+ implantation area 803 and the fourth N+ implantation area 804.

[0046] The present invention constitutes an asymmetric bidirectional thyristor structure with enhanced gate control effect, which can reduce the emitter efficiency and enhance the gate control effect by segmenting the emitter N+ injection area and embedding the gate. Figure 2 and Figure 3 As shown. Thus, a gate-controlled enhanced asymmetric bidirectional thyristor rectifier is formed, which suppresses the positive feedback effect of the thyristor and achieves the purpose of increasing the device holding voltage; because there is an electric field with the same direction as the current path under the gate, the SCR current flows to a deeper path, which improves the robustness and failure current of the device. The present invention adopts a gate-controlled enhanced asymmetric bidirectional thyristor structure, such as Figure 4 and Figure 5 Specifically:

[0047] When the ESD stress reaches the anode of the device and the cathode of the device is at the ground potential, the second NW region 602, the first HVNW region 301, the second PW region 502, and the first P-Epi region 401 undergo avalanche breakdown, and then the parasitic PNP1 transistor composed of the second PW region 502, the first P-Epi region 401, the second NW region 602, the first HVNW region 301, the third PW region 503, and the second P-Epi region 402 is turned on; the parasitic NPN1 transistor composed of the first N+ injection region 801, the second PW region 502, the first P-Epi region 401, the first HVNW region 301, and the second NW region 602 is turned on; the base region of the NPN1 transistor is connected through the parasitic resistor R P1 Connected to the second P+ injection region 702, and led to the cathode by the second P+ injection region 702. When the ESD stress reaches the cathode of the device and the anode of the device is grounded, the third NW region 603, the first HVNW region 301, the third PW region 503, and the second P-Epi region 402 undergo avalanche breakdown, and then the parasitic PNP2 transistor composed of the third PW region 503, the second P-Epi region 402, the third NW region 603, the first HVNW region 301, and the fourth PW region 504 is turned on; the parasitic NPN2 transistor composed of the third N+ injection region 803, the third PW region 503, the second P-Epi region 402, the third NW region 603, and the first HVNW region 301; the base region of the NPN2 transistor is connected to the cathode of the device and the anode of the device is grounded. P2Connected to the fourth P+ injection region 704, and led to the anode by the fourth P+ injection region 704. Thus, a gate-controlled enhanced asymmetric bidirectional thyristor electrostatic protection device is formed. By segmenting the first N+ injection region 801 and the third N+ injection region 803 and embedding the polysilicon gate, a trapezoidal polysilicon gate is formed, thereby enhancing the gate control effect, using the gate electric field to drive the current to a deeper path, and improving the robustness of the device. In addition, the segmentation of the emitter N+ reduces the emission efficiency of the parasitic NPN and improves the holding voltage of the device.

[0048] In summary, the present invention provides a gate-controlled enhanced asymmetric bidirectional thyristor electrostatic protection device and a manufacturing method, which is simple in structure and does not require breaking the process design rules. The manufactured gate-controlled enhanced asymmetric bidirectional thyristor electrostatic protection device is fully compatible with the standard CMOS process and does not use masks other than the standard process, so that the bidirectional thyristor electrostatic protection device has a larger holding voltage and a larger failure current, which can effectively protect the core chip under higher voltage operation, and there is no risk of latch-up, with high reliability and high stability.

Claims

1. A gate-controlled enhanced asymmetric bidirectional thyristor electrostatic protection device, characterized in that: include: Substrate P-Sub; A first NBL region is provided in the substrate P-Sub; A first annular HVNW region, a first P-Epi region, and a second P-Epi region are disposed above the NBL region; The first PW region, the first NW region, the second PW region, the second NW region, the third PW region, the third NW region, and the fourth PW region are arranged from left to right above the HVNW region, the first P-Epi region, and the second P-Epi region; the first field oxygen isolation region, the first P+ implantation region, the second field oxygen isolation region, the first strip-shaped polysilicon gate, the second P+ implantation region, the second trapezoidal polysilicon gate, the first N+ implantation region, the third P+ implantation region, the third field oxygen isolation region, the second N+ implantation region, the fourth field oxygen isolation region, the third strip-shaped polysilicon gate, the fourth P+ implantation region, the fourth trapezoidal polysilicon gate, the third N+ implantation region, the fifth P+ implantation region, the fifth field oxygen isolation region, the fourth N+ implantation region, the sixth field oxygen isolation region, the sixth P+ implantation region, and the seventh field oxygen isolation region are arranged from left to right above the first PW region; The first P+ implantation region is arranged in the first PW region; the first strip-shaped polysilicon gate, the second P+ implantation region, the second trapezoidal polysilicon gate, the first N+ implantation region, and the third P+ implantation region are arranged in the second PW region; the second N+ implantation region is arranged in the second NW region; the third strip-shaped polysilicon gate, the fourth P+ implantation region, the fourth trapezoidal polysilicon gate, the third N+ implantation region, and the fifth P+ implantation region are arranged in the third PW region; the fourth N+ implantation region is arranged in the third NW region; the sixth P+ implantation region is arranged in the fourth PW region; The first P+ implantation region, the first strip-shaped polysilicon gate, the second P+ implantation region, the second trapezoidal polysilicon gate, the first N+ implantation region and the sixth P+ implantation region are connected to serve as the cathode of the device; The third strip-shaped polysilicon gate, the fourth P+ implantation region, the fourth trapezoidal polysilicon gate and the third N+ implantation region are connected to serve as the anode of the device.

2. A gate-controlled enhanced asymmetric bidirectional thyristor electrostatic protection device according to claim 1, characterized in that: When the ESD stress reaches the anode of the device and the cathode of the device is at the ground potential, the second NW region, the first HVNW region, the second PW region, and the first P-Epi region undergo avalanche breakdown, and then the parasitic PNP1 transistor composed of the second PW region, the first P-Epi region, the second NW region, the first HVNW region, the third PW region, and the second P-Epi region is turned on; the parasitic NPN1 transistor composed of the first N+ injection region, the second PW region, the first P-Epi region, the first HVNW region, the second NW region is turned on; the base region of the NPN1 transistor is connected through the parasitic resistor R P1 The device is connected to the second P+ injection region and is led out to the cathode by the second P+ injection region; when the ESD stress reaches the cathode of the device and the anode of the device is grounded, the third NW region, the first HVNW region, the third PW region, and the second P-Epi region undergo avalanche breakdown, and then the parasitic PNP2 transistor composed of the third PW region, the second P-Epi region, the third NW region, the first HVNW region, and the fourth PW region is turned on; the parasitic NPN2 transistor composed of the third N+ injection region, the third PW region, the second P-Epi region, the first HVNW region, and the third NW region is turned on; the base region of the NPN2 transistor is connected to the cathode of the device and the anode of the device is grounded ... P2 Connected to the fourth P+ injection region and led out to the anode from the fourth P+ injection region.

3. A gate-controlled enhanced asymmetric bidirectional thyristor electrostatic protection device according to claim 1, characterized in that: The first P+ injection region is connected to the first metal layer of metal layer 1 through a contact hole, the first strip-shaped polysilicon gate is connected to the second metal layer of metal layer 1 through a contact hole, the second P+ injection region is connected to the third metal layer of metal layer 1 through a contact hole, the second trapezoidal polysilicon gate is connected to the fourth metal layer of metal layer 1 through a contact hole, the first N+ injection region is connected to the fifth metal layer of metal layer 1 through a contact hole, the sixth P+ injection region is connected to the tenth metal layer of metal layer 1 through a contact hole, the first metal layer, the second metal layer, the third metal layer, the fourth metal layer, the fifth metal layer, and the tenth metal layer of metal layer 1 are connected to the first metal layer of metal layer 2 through the metal through hole and serve as the anode of the device.

4. A gate-controlled enhanced asymmetric bidirectional thyristor electrostatic protection device according to claim 1, characterized in that: The third strip-shaped polysilicon gate is connected to the sixth metal layer of metal layer 1 through a contact hole, the fourth P+ injection area is connected to the seventh metal layer of metal layer 1 through a contact hole, the fourth trapezoidal polysilicon gate is connected to the eighth metal layer of metal layer 1 through a contact hole, the third N+ injection area is connected to the ninth metal layer of metal layer 1 through a contact hole, the sixth metal layer, the seventh metal layer, the eighth metal layer and the ninth metal layer of metal layer 1 are connected to the second metal layer of metal layer 2 through the metal through hole and serve as the cathode of the device.

5. A method for manufacturing a gate-controlled enhanced asymmetric bidirectional thyristor electrostatic protection device according to any one of claims 1 to 4, comprising the following steps: Step 1: forming an NBL region, a P-Epi region and an annular HVNW region in the substrate P-Sub; Step 2: Forming the first to seventh field oxygen isolation regions on the substrate P-Epi by photolithography; Step 3: sequentially forming the first to third NW regions in the first HVNW region by photolithography; Step 4: Forming the first to fourth PW regions in P-Sub and P-Epi in sequence by photolithography; Step 5: forming a first strip-shaped polysilicon gate and a second trapezoidal polysilicon gate in the second PW region, and forming a third strip-shaped polysilicon gate and a fourth trapezoidal polysilicon gate in the third PW region; Step six: By photolithography, a first P+ injection region is formed in the first PW region, second and third P+ injection regions are formed in the second PW region, fourth and fifth P+ injection regions are formed in the third PW region, and a sixth P+ injection region is formed in the fourth PW region. Step seven: by photolithography, a first N+ implantation region is formed in the first PW region, a second N+ implantation region is formed in the second NW region, a third N+ implantation region is formed in the third PW region, and a fourth N+ implantation region is formed in the third NW region.

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