Enhanced high electron mobility transistor based on ScAlN and preparation method thereof

Abstract

The invention provides an enhanced high electron mobility transistor based on ScAlN and a preparation method thereof. The prepared transistor comprises an AllnN gradient layer, an ScAlN barrier layer, a cap layer and a GaN channel layer. The preparation method comprises the following steps: depositing an epitaxial wafer on a standby substrate; etching is carried out on the bonding body; and preparing an electrode of the transistor and obtaining a preparation result. The wide-band-gap ScAlN cap layer grown on the channel layer of the N-polarity GaN / ScAlN heterojunction can induce enough negative polarization charges to form a potential well below the grid electrode, so that the concentration of 2DEG in the channel layer is favorably consumed to improve the threshold voltage of the transistor; the ScAlN wide band gap material has a stronger polarization effect, and is beneficial to forming a higher 2DEG concentration at a heterogeneous interface, thereby improving the current density of the device; the N-polarity GaN material has better interface quality, and the energy consumption of the Ga-polarity GaN material during working can be reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and relates to an enhanced high electron mobility transistor and a preparation method thereof, and specifically relates to an enhanced high electron mobility transistor based on ScAlN and a preparation method thereof, which can be used as a microwave power device and a power electronic device. Background Art

[0002] High electron mobility transistors usually use traditional GaN / AlGaN heterojunctions, in which the carrier concentration and mobility of the two-dimensional electron gas (2DEG) are limited by material properties, resulting in limited carrier concentration and mobility. This is particularly evident in high-frequency and high-power applications, as these applications require higher current density and faster switching speeds. Traditional Ga-polar GaN materials form a high density of polarization charges at the interface during growth, resulting in a high interface state density. The high interface state density not only increases the leakage current of the device, but also reduces its reliability and electrical performance. In contrast, the surface of N-polar GaN materials has a lower polarization charge density, which can significantly reduce the interface state density and leakage current, and improve the reliability and performance of the device.

[0003] An enhanced high electron mobility transistor is a transistor that starts to conduct when a positive gate voltage is applied. The main ways to realize an enhanced high electron mobility transistor are P-GaN, thin barrier, recessed gate, fluorine ion implantation, and cascode. The thin barrier structure reduces the 2DEG concentration in the channel by thinning the barrier layer, but it will increase the on-resistance of the device; the recessed gate technology is similar to the thin barrier, and the principle is to only etch the barrier layer in the area under the gate. When the barrier layer under the gate is thin to a certain extent, the 2DEG concentration in the channel under the gate can be ignored and a normally-off device is formed, but this structure reduces the concentration of the two-dimensional electron gas under the gate; it is impossible to increase the threshold voltage while increasing the 2DEG concentration in the on state of the device.

[0004] The main indicators that affect the performance of enhanced high electron mobility transistors include breakdown voltage, switching speed, conduction loss, on-state current, off-state leakage current, and threshold voltage. In order to improve the threshold voltage, for example, the patent document with application publication number CN118800795A and titled "A dual-channel enhanced gallium nitride HEMT device and its preparation method" discloses a dual-channel enhanced gallium nitride HEMT device and its preparation method that can effectively improve the threshold voltage. The invention uses a dual-channel structure to make the currents of the two channels converge at the drain, thereby obtaining a larger saturation current. The p-type GaN (gallium nitride) back barrier layer of the device has an auxiliary depletion effect on the 2DEG (two-dimensional electron gas) in the first channel. The back barrier layer is combined with the MIS gate or the p-GaN gate inserted above the barrier layer to achieve the depletion effect on the 2DEG under the gate. The two together realize the device enhancement mode; combined with the field plate and the gate field plate, the electric field between the gate and the drain is modulated. This invention improves the threshold voltage of the enhancement-mode gallium nitride HEMT device by optimizing the electric field distribution between the gate and the drain. However, due to the existence of interface states at the interface of the semiconductor layer that lead to current leakage, the threshold voltage is still low. In addition, the use of a P-type GaN back barrier layer affects the increase in the peak electric field at the gate edge, which in turn leads to a poor 2DEG concentration when the enhancement-mode high electron mobility transistor is in the on state. Summary of the invention

[0005] The purpose of the present invention is to overcome the defects of the above-mentioned prior art and propose an enhanced high electron mobility transistor based on ScAlN and a preparation method thereof, which are used to solve the technical problems of low transistor threshold voltage and low current density in the on state in the prior art.

[0006] To achieve the above object, the technical solution adopted by the present invention is:

[0007] An enhanced high electron mobility transistor based on ScAlN, comprising a substrate, a buffer layer, a gradient layer, a barrier layer, a nucleation layer and a channel layer stacked in sequence from bottom to top, and a drain electrode D and a source electrode S arranged on the channel layer, a cap layer arranged between the drain electrode D and the source electrode S, and a gate electrode G arranged on the cap layer;

[0008] Preferably, the gradient layer uses lnAlN with an Al composition of 0 to 0.38 and a thickness of 20 nm to 30 nm; the barrier layer uses ScAlN with an Sc composition of 0.16 to 0.18 and a thickness of 5 nm to 10 nm; the channel layer uses N-polar GaN material with a thickness of 10 nm to 15 nm; the cap layer uses ScAlN with a thickness of 10 nm to 30 nm.

[0009] Preferably, the substrate, buffer layer, nucleation layer and passivation layer are: the substrate is made of Si or sapphire with a thickness of 300μm to 600μm; the buffer layer is made of GaN with a thickness of 1μm to 1.5μm; the nucleation layer is made of AlN with a thickness of 2nm to 4nm; and the passivation layer is made of SiO2 or Si3N4 with a thickness of 0.1μm to 1μm.

[0010] Preferably, the drain D and source S of the channel layer are made of Ti / Al / Ni / Au with a thickness of 10-80nm / 70-200nm / 30-50nm / 40-70nm; the gate G is made of Ni / Au with a thickness of 20-80nm / 60-300nm.

[0011] A method for preparing an enhanced high electron mobility transistor comprises the following steps:

[0012] (1) Depositing epitaxial wafer on a spare substrate:

[0013] Depositing AlN, GaN, N-polar GaN, AlN, ScAlN, lnAlN, and GaN on the upper surface of the spare substrate in sequence from bottom to top to form a composite structure including the spare substrate and an epitaxial wafer stacked by an AlN nucleation layer, a GaN buffer layer, an N-polar GaN channel layer, an AlN nucleation layer, a ScAlN barrier layer, an lnAlN gradient layer, and a GaN bonding cap layer;

[0014] (2) Etching after heterogeneous bonding of the composite structure and the substrate:

[0015] Heterogeneously bonding the composite structure to the substrate, etching the spare substrate and the GaN buffer layer in the bonded body after the heterogeneous bonding, and then annealing the etched bonded body to obtain a bonded body with the surface of the GaN channel layer exposed;

[0016] (3) Preparation of electrodes for enhanced high electron mobility transistors:

[0017] After depositing a layer of ScAIN on the surface of the channel layer of the bonded body obtained in step (2), selective etching is performed on the bonded body, and a drain D, a source S and a gate G of an enhanced high electron mobility transistor are prepared on the bonded body on which the ScAIN cap layer is deposited, so as to obtain a basic device structure with an N-polar GaN channel layer surface exposed;

[0018] (4) Obtaining the preparation results of enhanced high electron mobility transistor:

[0019] A SiO2 or Si3N4 passivation layer is deposited on the exposed portion of the N-polar GaN surface of the basic device structure obtained in step (2) to obtain an enhanced high electron mobility transistor.

[0020] Compared with the prior art, the present invention has the following advantages:

[0021] 1) The wide bandgap ScAlN cap layer grown on the channel layer of the N-polar GaN / ScAlN heterojunction of the present invention can induce sufficient negative polarization charges to form a potential well below the gate, effectively depleting the concentration of 2DEG in the channel layer, thereby increasing the threshold voltage of the transistor. Compared with the prior art, the stability and reliability of the transistor in the off state are effectively improved.

[0022] 2) The ScAlN wide bandgap material used in the barrier layer of the present invention has a stronger polarization effect, which helps to form a higher 2DEG concentration at the heterogeneous interface, thereby improving the current density of the device.

[0023] 3) The N-polar GaN material used in the channel layer of the present invention has better interface quality, can reduce the interface state density, reduce the scattering of carriers, improve the carrier mobility, and lower the square resistance of the channel layer, thus avoiding the defect of high energy consumption of the Ga-polar GaN material used in the prior art during operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a schematic diagram of the structure of the enhanced high electron mobility transistor of the present invention.

[0025] Figure 2 The figure is a schematic diagram of the realization of the method for preparing the enhanced high electron mobility transistor of the present invention.

[0026] Figure 3 The present invention is a flowchart of the method for preparing an enhanced high electron mobility transistor. DETAILED DESCRIPTION

[0027] The present invention is further described in detail below in conjunction with the accompanying drawings and specific examples, but the present invention is not limited thereto. The experimental methods described in the following examples are conventional methods unless otherwise specified; the reagents and materials described are commercially available unless otherwise specified.

[0028] Embodiment 1:

[0029] Reference Figure 1 The enhanced high electron mobility transistor of the present invention comprises a substrate, a buffer layer, a gradient layer, a barrier layer, a nucleation layer and a channel layer stacked in sequence from bottom to top, and a drain electrode D and a source electrode S arranged on the channel layer, a cap layer is arranged between the drain electrode D and the source electrode S, and a gate electrode G is arranged on the cap layer;

[0030] The gradient layer is made of 25nm thick lnAlN, which is used to make the top peak of the valence band at the heterojunction disappear and the hole potential well be pulled down. However, the top of the valence band is still close to and clamped at the Fermi level, and the gradient back barrier induces the generation of three-dimensional hole gas in the entire barrier layer;

[0031] The barrier layer is made of ScAlN with a Sc component of 0.17 and a thickness of 8 nm, which has a stronger polarization effect and helps to form a higher 2DEG concentration at the heterogeneous interface, thereby improving the current density of the device;

[0032] The channel layer adopts N-polar GaN material with a thickness of 12 nm, which has better interface quality, can reduce interface state density, reduce carrier scattering, improve carrier mobility, and have lower sheet resistance of the channel layer, thus avoiding the defect of high energy consumption of Ga-polar GaN material used in the prior art during operation;

[0033] The cap layer, which uses a 20nm thick ScAlN cap layer, can induce sufficient negative polarization charges to form a potential well under the gate, effectively deplete the concentration of 2DEG in the channel layer, thereby increasing the threshold voltage of the transistor and effectively improving the stability and reliability of the transistor in the off state.

[0034] The substrate is made of Si with a size of 4 inches, a thickness of 600 μm, and a crystal orientation of

[111] , which improves the electrical properties and growth performance of the material;

[0035] The buffer layer is made of GaN with a thickness of 1.5 μm, and the nucleation layer is made of AlN with a thickness of 3 nm;

[0036] The passivation layer is made of Si3N with a thickness of 0.5 μm. 4， To suppress the current collapse phenomenon.

[0037] The channel layer, wherein the drain D and the source S are made of Ti / Al / Ni / Au with a thickness of 20nm / 120nm / 40nm / 50nm; the gate G is made of Ni / Au with a thickness of 40nm / 100nm.

[0038] Reference Figure 2 and 3 The method for preparing an enhanced high electron mobility transistor of the present invention comprises the following steps:

[0039] Step 1) Depositing an epitaxial wafer on a spare substrate:

[0040] 1a) Deposition of GaN buffer layer:

[0041] Using metal organic chemical vapor deposition (MOCVD) technology, a GaN buffer layer with a thickness of 1.5 μm was epitaxially grown on a Si substrate under the process conditions of a flow rate ratio of NH3 to TMGa of 2000, a temperature of 900°C, and a chamber pressure of 150 mbar.

[0042] 1b) Deposition of GaN channel layer:

[0043] Using metal organic chemical vapor deposition (MOCVD) technology, a GaN channel layer with a thickness of 12nm was epitaxially grown on the GaN buffer layer under the process conditions of a flow rate ratio of NH3 to TMGa of 1500, a temperature of 900°C, and a growth pressure of 50mbar.

[0044] 1c) depositing an AlN nucleation layer;

[0045] Using metal organic chemical vapor deposition (MOCVD) technology, under the process conditions of NH3 and TMAl flow rate ratio of 1000, temperature of 450°C, and growth pressure of 50mbar, an AlN nucleation layer with a thickness of 3nm was epitaxially grown on the Ga polar surface of the GaN channel layer;

[0046] 1d) Deposition of ScAlN graded layer and barrier layer:

[0047] Using molecular beam epitaxy (MBE) technology, the cleaned and dried GaN substrate was placed in the MBE equipment and grown at a vacuum pressure of 2×10 -8 Pa pressure condition, the Sc source is 3×10 -8 Torr flow rate, N source is 7.8×10 -8 Torr flow rate, Al source is 2×10 -8 Under the nitrogen-rich mode process conditions of 100 Torr flow rate, a ScAlN barrier layer with a thickness of 10 nm and a Sc composition of 0.18 is grown on the N-polar GaN channel layer. The Sc source is changed to a ln source with a value of 4×10 -8 Torr flow rate to generate lnAlN graded layer with thickness of 25nm;

[0048] 1e) Deposition of GaN buffer layer:

[0049] Using metal organic chemical vapor deposition (MOCVD) technology, a GaN buffer layer with a thickness of 1.5 μm was epitaxially grown on the ScAlN barrier layer under the process conditions of a flow rate ratio of NH3 to TMGa of 2000, a temperature of 900°C, and a growth pressure of 150 mbar.

[0050] Step 2) After heterogeneously bonding the composite structure to the substrate, etching is performed:

[0051] 2a) Surface pretreatment of the composite structure and the Si substrate: to remove organic dirt, the composite structure and the Si substrate were placed in an acetone solution for ultrasonic cleaning for 10 minutes, the composite structure and the Si substrate were taken out, and they were rinsed with deionized water; to remove stubborn organic residues, the composite structure and the Si substrate were immersed in a H2SO4:H2O2=7:3 solution for 15 minutes, the composite structure and the Si substrate were taken out, and they were fully rinsed with deionized water; to remove the thin layer of oxide on the surface of the silicon wafer and form a new oxide film at the same time, the composite structure and the Si substrate were immersed in a H2O:H2O2:NH4OH=5:1:1 solution for 15 minutes, the composite structure and the Si substrate were taken out, and they were fully rinsed with a large amount of deionized water to ensure that all chemical residues were completely removed; the composite structure and the substrate were blown dry with nitrogen to ensure that their surfaces were completely dry;

[0052] 2b) Pre-deposit 50-100 nm SiO grown at 300°C on the composite structure and Si substrate 2， Then, a coating machine is used to spin coat SOG on the composite structure and the Si substrate at a speed of 4000-5000 r / min;

[0053] 2c) aligning the composite structure and the substrate face to face and pressing them, and completing heterogeneous bonding using a bonding machine;

[0054] 2d) using a plasma etching ICP method with an SF6 flow rate of 300 sccm, a radio frequency RF power of 60 W, an ICP etching power of 2000 W, and a pressure of 95 mTorr as etching conditions, the spare substrate is initially etched, and the spare substrate having a thickness of 30 μm after the initial etching is etched again with an SF6 flow rate of 150 sccm, a radio frequency RF power of 30 W, an ICP etching power of 1000 W, and a pressure of 95 mTorr as etching conditions to obtain a bonded body that does not contain the spare substrate;

[0055] 2e) using a plasma etching ICP method with flow rates of BCl3, Cl2 and O2 of 4 sccm, 25 sccm and 4 sccm, a radio frequency RF power of 60 W, an ICP etching power of 350 W, and an etching chamber pressure of 20 mTorr as etching conditions, the GaN buffer layer in the bonded body not including the spare substrate is etched to obtain a bonded body with the surface of the GaN channel layer exposed;

[0056] 2f) The exposed N-polar GaN channel layer after etching is subjected to a thermal annealing process, that is, annealing in an annealing furnace at 500° C. for 10 minutes to repair the surface damage caused by etching.

[0057] Step 3) preparing an electrode of an enhanced high electron mobility transistor:

[0058] 3a) The surface of the N-polar GaN channel layer after annealing is cleaned, that is, the substrate surface is ultrasonically cleaned with acetone and isopropanol solutions for 5 minutes, and then the residual organic solvent on the surface is cleaned with deionized water for 3 minutes, and then it is cleaned with BOE (7:1) for 30 seconds to remove the thin layer of oxide on the surface of the bond body exposed on the surface of the GaN channel layer, and finally rinsed with deionized water and dried with N2 to expose the bond body on the surface of the GaN channel layer; the substrate is placed in the injection chamber and baked at 160° C. for 30 minutes, and then transferred to the preparation room, and degassed at 400° C. for 30 minutes to remove moisture and contamination on the surface of the substrate;

[0059] 3b) The cleaned and dried bonded body is placed in a molecular beam epitaxial growth MBE device under a vacuum pressure of 2×10 - 8 Pa pressure condition, the Sc source is 3×10 -8 Torr flow rate, N source is 7.8×10 -8 Torr flow rate, Al source is 2×10 - 8 Under the process condition of nitrogen-rich mode with a flow rate of 100 Torr, a ScAlN layer with a thickness of 5 nm and a Sc composition of 0.18 is grown on the exposed N-polarity GaN channel layer to form a bonded body after the deposition of ScAIN;

[0060] 3c) etching both ends of the ScAIN layer to expose the GaN channel layer below, and leaving a ScAIN cap layer at the center of the surface of the GaN channel layer;

[0061] 3d) Ti metal with a thickness of 20 nm, Al metal with a thickness of 120 nm, Ni metal with a thickness of 40 nm, and Au metal with a thickness of 50 nm are sequentially deposited at both ends of the GaN channel layer using electron beam evaporation technology to form a Ti / Al / Ni / Au four-layer metal electrode, and rapid annealing is performed in a N2 atmosphere at a temperature of 800° C. for 25 seconds to complete the preparation of the drain D and the source S;

[0062] 3e) Ni metal with a thickness of 40 nm and Au metal with a thickness of 100 nm are sequentially deposited on the ScAlN barrier layer using electron beam evaporation technology on the ScAlN cap layer formed at the center position on the surface of the GaN channel layer to form a Ni / Au double-layer metal electrode, and then rapidly annealed in a N2 atmosphere at a temperature of 650°C for 25 seconds to complete the fabrication of the gate.

[0063] Step 4) Obtaining the preparation result of the enhanced high electron mobility transistor:

[0064] 4a) using a PECVD device, setting its power to 100 W, the reaction chamber temperature to 250° C., the reaction chamber pressure to 50 Torr, and simultaneously introducing two gases, SiH4 and NH3, as the silicon source and nitrogen source, respectively, with the gas flow ratio set to SiH4:NH3=2:1, to grow a Si3N4 passivation layer with a thickness of 200 nm on the ScAlN barrier layer to protect the underlying material, reduce surface defects and improve the reliability of the device;

[0065] 4b) Photolithography is performed on the passivation layer using a standard photolithography process, and the basic device structure of the deposited passivation layer after photolithography is placed in the reaction chamber of the RIE equipment. The equipment power is set to 200 W, the reaction chamber pressure is set to 5 Torr, and two gases, CF4 with a flow rate of 20 sccm and O2 with a flow rate of 5 sccm, are introduced at the same time. The etching time is set to 180 s, and the Si3N4 passivation layer on the source, drain, and gate is etched away to complete the production of the high electron mobility transistor.

[0066] Embodiment 2: The implementation process and structure of this embodiment are the same as those of Embodiment 1, and only some parameters are adjusted. In this embodiment, the thickness of lnAlN is 20nm, the barrier layer adopts ScAlN with an Sc composition of 0.16 and a thickness of 5nm, the channel layer adopts an N-polar GaN material with a thickness of 10nm, the cap layer adopts a ScAlN cap layer with a thickness of 10nm, the substrate adopts Si with a thickness of 300μm, the buffer layer adopts GaN with a thickness of 1μm, the nucleation layer adopts AlN with a thickness of 2nm, the passivation layer adopts SiO2 with a thickness of 0.1μm, the drain D and the source S adopt Ti / Al / Ni / Au with a thickness of 10nm / 70nm / 30nm / 40nm, and the gate G adopts Ni / Au with a thickness of 20nm / 60nm;

[0067] The flow rate ratio of NH3 and TMAl for AlN deposition was 500, the temperature was 400°C, and the chamber pressure was 50 mbar;

[0068] The flow rate ratio of NH3 and TMGa for GaN deposition was 1500, the chamber temperature was 800°C, and the chamber pressure was 50 mbar;

[0069] The chamber temperature of SiH4 and NH3 for depositing Si3N4 was 200°C, and the chamber pressure was maintained at 50 mbar.

[0070] Embodiment 3, the implementation process and structure of this embodiment are the same as those of embodiment 1, only some parameters are adjusted, this embodiment is the implementation process and structure of this embodiment are the same as those of embodiment 1, only some parameters are adjusted, this embodiment is, lnAlN thickness is 30nm, the barrier layer adopts ScAlN with Sc component of 0.18 and thickness of 10nm, the channel layer adopts N-polar GaN material with thickness of 15nm, the cap layer adopts ScAlN cap layer with thickness of 30nm, the substrate adopts Si with thickness of 600μm, the buffer layer adopts GaN with thickness of 1.5μm, the nucleation layer adopts AlN with thickness of 4nm, the passivation layer adopts SiO2 with thickness of 1μm, the drain D and the source S adopt Ti / Al / Ni / Au with thickness of 80nm / 200nm / 50nm / 70nm, and the gate G adopts Ni / Au with thickness of 60nm / 300nm;

[0071] The flow rate ratio of NH3 and TMAl for AlN deposition was 1000, the temperature was 500°C, and the chamber pressure was 100 mbar;

[0072] The flow rate ratio of NH3 and TMGa for GaN deposition was 2500, the chamber temperature was 100°C, and the chamber pressure was 250 mbar;

[0073] The chamber temperature of SiH4 and NH3 for depositing Si3N4 was 300°C, and the chamber pressure was maintained at 250 mbar.

Claims

1. An enhanced high electron mobility transistor based on ScAlN, comprising a substrate, a buffer layer, a gradient layer, a barrier layer, a nucleation layer and a channel layer stacked in sequence from bottom to top, and a drain D and a source S arranged on the channel layer, a cap layer is arranged between the drain D and the source S, and a gate G is arranged on the cap layer; characterized in that, The gradient layer uses AlAlN with an Al component of 0 to 0.38 and a thickness of 20 nm to 30 nm; the barrier layer uses ScAlN with an Sc component of 0.16 to 0.18 and a thickness of 5 nm to 10 nm; the channel layer uses N-polar GaN material with a thickness of 10 nm to 15 nm; and the cap layer uses ScAlN with a thickness of 10 nm to 30 nm.

2. The enhanced high electron mobility transistor according to claim 1, characterized in that: The substrate, buffer layer, nucleation layer and passivation layer are as follows: the substrate is made of Si or sapphire with a thickness of 300μm to 600μm; the buffer layer is made of GaN with a thickness of 1μm to 1.5μm; the nucleation layer is made of AlN with a thickness of 2nm to 4nm; and the passivation layer is made of SiO2 or Si3N4 with a thickness of 0.1μm to 1μm.

3. The enhanced high electron mobility transistor according to claim 1, characterized in that: The channel layer, wherein the drain D and the source S are made of Ti / Al / Ni / Au with a thickness of 10-80nm / 70-200nm / 30-50nm / 40-70nm; the gate G is made of Ni / Au with a thickness of 20-80nm / 60-300nm.

4. A method for preparing an enhanced high electron mobility transistor according to claim 1, characterized in that: The steps include: (1) Depositing epitaxial wafer on a spare substrate: Depositing AlN, GaN, N-polar GaN, AlN, ScAlN, AllnN, and GaN sequentially from bottom to top on the upper surface of the spare substrate to form a composite structure including the spare substrate and an epitaxial wafer stacked by an AlN nucleation layer, a GaN buffer layer, an N-polar GaN channel layer, an AlN nucleation layer, a ScAlN barrier layer, an AllnN gradient layer, and a GaN bonding cap layer; (2) Etching after heterogeneous bonding of the composite structure and the substrate: Heterogeneously bonding the composite structure to the substrate, etching the spare substrate and the GaN buffer layer in the bonded body after the heterogeneous bonding, and then annealing the etched bonded body to obtain a bonded body with the surface of the GaN channel layer exposed; (3) Preparation of electrodes for enhanced high electron mobility transistors: After depositing a layer of ScAIN on the surface of the channel layer of the bonded body obtained in step (2), selective etching is performed on the bonded body, and a drain D, a source S and a gate G of an enhanced high electron mobility transistor are prepared on the bonded body on which the ScAIN cap layer is deposited, so as to obtain a basic device structure with an N-polar GaN channel layer surface exposed; (4) Obtaining the preparation results of enhanced high electron mobility transistor: A SiO2 or Si3N4 passivation layer is deposited on the exposed portion of the N-polar GaN surface of the basic device structure obtained in step (2) to obtain an enhanced high electron mobility transistor.

5. The preparation method according to claim 4, characterized in that: In step (1), AlN, GaN, N-polar GaN, AlN, ScAlN, AllnN, and GaN are sequentially deposited on the upper surface of the spare substrate from bottom to top, wherein the AlN, GaN, N-polar GaN, and GaN are deposited by a metal organic chemical vapor MOCVD method, and by filling NH 3、 The cavity of TMAl and TMGa is realized as follows: The flow rate ratio of NH3 and TMAl for depositing AlN is 500-1000, the temperature is 400℃-500℃, and the chamber pressure is 50mbar-100mbar; The flow rate ratio of NH3 and TMGa for depositing GaN is 1500-2500, the chamber temperature is 800℃-1000℃, and the chamber pressure is 50mbar-250mbar; The flow rate ratio of NH3 and TMGa for depositing N-polar GaN is 1000-2000, the chamber temperature is 800°C-1000°C, and the chamber pressure is 50mbar-250mbar.

6. The preparation method according to claim 4, characterized in that: The step (1) of depositing AlN, GaN, N-polar GaN, AlN, ScAlN, AllnN, and GaN on the upper surface of the spare substrate in sequence from bottom to top, wherein the deposition of InAlN and ScAlN is achieved by using a molecular beam epitaxy MBE method and by filling a cavity with Sc source, N source, Al source, and In source, specifically: The Sc source flow rate for depositing ScAlN is 3×10 -8 Torr, N source flow rate is 7.8×10 -8 Torr, Al source flow rate is 2×10 - 8 Torr, the chamber pressure is 2×10 -8 Pa; The source flow rate of deposited lnAlNSc is 3×10 -8 Torr, N source flow rate is 7.8×10 -8 Torr, ln source flow rate is 4×10 - 8 Torr, the chamber pressure is 2×10 -8 Pa.

7. The preparation method according to claim 4, characterized in that: In step (2), the composite structure and the substrate are heterogeneously bonded. Before bonding, SOG is applied to the bonding cap layer and the substrate in the composite structure respectively to achieve reliable bonding between the composite structure and the substrate.

8. The preparation method according to claim 4, characterized in that: The etching of the spare substrate and the GaN buffer layer in the bonded body after heterogeneous bonding described in step (2) is carried out by using a plasma etching ICP method and by filling a cavity with SF6, BCl3, Cl2 and O2, and the implementation steps are as follows: (2a) The spare substrate is initially etched under the etching conditions of SF6 flow rate of 300 sccm, RF power of 60 W, ICP etching power of 2000 W, and pressure of 95 mTorr, and the spare substrate having a thickness of 30 μm to 40 μm after the initial etching is etched again under the etching conditions of SF6 flow rate of 150 sccm, RF power of 30 W, ICP etching power of 1000 W, and pressure of 95 mTorr to obtain a bonded body without the spare substrate; (2b) With the flow rates of BCl3, Cl2 and O2 being 4 sccm, 25 sccm and 4 sccm, the RF power being 60 W, the ICP etching power being 350 W to 400 W, and the etching chamber pressure being 20 mTorr as the etching conditions, the GaN buffer layer in the bonded body excluding the spare substrate is etched to obtain a bonded body with the surface of the GaN channel layer exposed.

9. The method according to claim 4, characterized in that The step (3) of preparing the electrode of the enhanced high electron mobility transistor is implemented by: (3a) depositing a layer of ScAIN on the surface of the channel layer of the bonded body where the surface of the GaN channel layer is exposed, and etching both ends of the ScAIN to obtain a GaN channel layer exposed below and a ScAIN cap layer left at the center of the surface; (3b) Ti / Al / Ni / Au is deposited at both ends of the GaN channel layer, and Ni / Au is deposited on the ScAIN cap layer. The deposited layers at both ends of the GaN channel layer and the deposited layers on the ScAIN cap layer are used as the drain D and source S, and the gate G of the enhanced high electron mobility transistor, respectively. (4) Obtaining the preparation results of enhanced high electron mobility transistor: A SiO2 or Si3N4 passivation layer is deposited on the exposed portion of the N-polar GaN surface of the basic device structure obtained in step (2) to obtain an enhanced high electron mobility transistor.

10. The method according to claim 4, characterized in that The passivation layer described in step (4), wherein the deposition of Si3N4 is achieved by plasma enhanced chemical vapor deposition (PECVD) method and by filling the cavity with SiH4 and NH3, is achieved under the following conditions: The gas flow ratio of SiH4 and NH3 is 2:1, the chamber temperature is 200℃~300℃, the equipment power is 100w, and the chamber pressure is 50mbar~250mbar.

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