Semiconductor device and preparation method and equipment thereof

Abstract

The invention relates to a semiconductor device and a preparation method and equipment thereof. The method comprises the following steps: providing a substrate; the top surface of the substrate comprises a hard mask layer, and a first region and a second region which are arranged along a first direction parallel to the top surface of the substrate; wherein the first region is used for forming a BCD device, and the second region is used for forming a device; forming a first groove and a second groove which are arranged along the first direction in the substrate in the second area; forming a shielding electrode in the first groove; after the shielding electrode is etched back, filling a sacrificial layer in the first groove; after removing part of the hard mask layer along the first direction, forming a patterned barrier layer on the top surface of the first oxide layer in the first region; forming a BCD oxidation isolation layer in the substrate of the first region based on the patterned barrier layer; and forming an interlayer dielectric layer and a grid electrode which are sequentially arranged along the direction deviating from the substrate in the first groove, thereby effectively solving the compatibility problem of Trench MOS (Metal Oxide Semiconductor) and BCD (Bipolar Compact Disc) processes.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a preparation method and equipment thereof. Background Art

[0002] As a key and advanced power integrated circuit manufacturing technology, the Bipolar-CMOS-DMOS (BCD) process is a relatively mature chip processing technology type on the market. It can simultaneously prepare bipolar junction transistors (BJT), complementary metal oxide semiconductor field effect transistors (CMOS) and double-diffused metal oxide semiconductor field effect transistors (DMOS) on a single IC. It uses bipolar devices and CMOS devices as low-voltage control and DMOS as power devices, combining the strengths of the three devices. Therefore, it has a wide range of application scenarios.

[0003] Among the three devices, the DMOS device, as a power device, usually occupies more than half of the circuit board area and is the focus of design in the BCD process. It is mainly divided into lateral DMOS (Lateral Double diffused MOSFET, LDMOS) devices and vertical DMOS (Vertical Double-diffused, VDMOS) devices. Among them, compared with planar gate VDMOS devices or LDMOS devices, vertical trench MOS devices are less compatible with traditional CMOS planar processes, and have higher investment costs and process difficulties. Therefore, how to improve the compatibility of vertical trench MOS devices and traditional BCD processes has become an urgent problem for researchers to solve. Summary of the invention

[0004] Based on this, it is necessary to provide a semiconductor device and a method for preparing the same, and an electronic device to address the technical problems in the prior art, which can at least realize the simultaneous preparation of trench MOS devices and BCD devices.

[0005] In a first aspect, the present application provides a method for preparing a semiconductor device, comprising: providing a substrate; the top surface of the substrate comprises a hard mask layer, and a first region and a second region arranged along a first direction parallel to the top surface of the substrate; wherein the first region is used to form a BCD device, and the second region is used to form a trench MOS device; forming a first groove and a second groove arranged along a first direction in the substrate of the second region; forming a shielding electrode in the first groove; after etching back the shielding electrode, filling a sacrificial layer in the first groove; after removing part of the hard mask layer along the first direction, forming a patterned barrier layer on the top surface of the first oxide layer in the first region; based on the patterned barrier layer, forming a BCD oxidation isolation layer in the substrate of the first region; forming an interlayer dielectric layer and a gate arranged in sequence along a direction away from the substrate in the first groove.

[0006] In the above-mentioned semiconductor device preparation method, in the preparation method, a hard mask layer is used to block the first area where the BCD device is formed, and a gate oxide layer and a shielding electrode of the device are formed in the second area by combining photolithography, oxidation and deposition processes, and then a barrier layer is set to isolate the second area, and a BCD oxidation isolation layer is formed in the first area. Finally, a second polysilicon gate process is performed in the second area to complete the preparation of the interlayer dielectric layer and the gate of the trench MOS device. The method successfully realizes the integration of the BCD device and the trench MOS device by reasonably changing the original process steps, while adding as few process levels as possible and without affecting the BCD device, thereby effectively improving the compatibility of the trench MOS device and the traditional BCD process.

[0007] In some embodiments, during the process of forming the shielding electrode in the first trench, an isolation structure is formed in the second trench;

[0008] The formation of the shielding electrode and the isolation structure includes: patterning the hard mask layer on the top surface of the substrate in the second area; forming a first trench and a second trench based on the patterned hard mask layer; forming a gate oxide layer on the inner surface of the first trench and the second trench; filling the first trench and the second trench with polysilicon, and simultaneously forming a shielding electrode located in the first trench and an isolation structure located in the second trench.

[0009] In some embodiments, the hard mask layer includes a first oxide layer, a nitride layer, and a second oxide layer stacked in sequence in a direction away from the substrate;

[0010] Removing part of the hard mask layer along the first direction includes: removing the second oxide layer and part of the nitride layer; and the remaining nitride layer is used to form a grinding stop layer.

[0011] In some embodiments, the grinding stop layer is removed and the first oxide layer is retained; and a barrier layer covering a top surface of the first oxide layer is formed.

[0012] In some embodiments, the thickness of the grinding stop layer is adjusted; the adjusted grinding stop layer is used to form a barrier layer covering the top surface of the first oxide layer.

[0013] In some embodiments, a BCD oxidation isolation layer is formed in the first region based on a patterned barrier layer, and further includes: based on a photoresist layer, patterning the barrier layer on the top surface of the first oxide layer in the first region to expose a portion of the first oxide layer; performing a furnace tube thermal oxidation process on the substrate to form a BCD oxidation isolation layer at the exposed top surface of the first oxide layer.

[0014] In some embodiments, forming an interlayer dielectric layer and a gate also includes: sequentially removing a patterned barrier layer and a sacrificial layer in the first trench; forming an interlayer dielectric layer in the first trench using thermal growth; filling the first trench with polysilicon; and removing the polysilicon outside the first trench, at which point the remaining polysilicon in the first trench is used to form a gate.

[0015] In some embodiments, the preparation method also includes: performing an ion implantation process on the substrate in the first region and the second region to form a well region; removing the first oxide layer; forming a BCD gate oxide layer covering the top surface of the BCD device in the first region and the trench MOS device in the second region; and forming a BCD control gate on the top surface of the BCD gate oxide layer in the first region.

[0016] In a second aspect, the present application also provides a semiconductor device, which is prepared using the preparation method in any of the above embodiments.

[0017] In the above-mentioned semiconductor device, on the one hand, the trench MOS device in which the current flows in the direction perpendicular to the substrate effectively cooperates with the LDMOS device, optimizing the current distribution in the semiconductor device and making it more uniform, thereby enhancing the current handling capacity of the semiconductor device. On the other hand, since the reverse withstand voltage of the LDMOS device depends on the adjustment of the lateral drift length, in order to increase the breakdown voltage, it is often necessary to increase the width of the drift region. Excessive drift length will cause the on-resistance to rise, affecting the driving ability of the device. In the above-mentioned semiconductor device, the MOS structure with a shielded gate structure introduces a longitudinal field plate in the semiconductor device, so that the depletion capacity of the drift region carriers is further enhanced, while ensuring a lower impedance, the breakdown voltage of the device is effectively increased. Under the same output conditions, the lateral area occupied by the trench MOS device is small. Therefore, the semiconductor device can achieve a dual improvement in technical performance and economic benefits while increasing the cell density.

[0018] In a third aspect, the present application also provides an electronic device, which is a semiconductor device prepared by the preparation method in any of the above embodiments; or includes the semiconductor device in the above embodiments.

[0019] Equipment equipped with semiconductor devices can be widely used in power tools, drones, automobiles, medical equipment and other fields.

[0020] Unexpected technical effects of this application:

[0021] In the semiconductor device and its preparation method and equipment provided in the above embodiments, by adjusting the original process flow, the BCD device and the trench MOS device are successfully integrated on the same chip while minimizing process interference and introducing additional process steps, further reducing the on-resistance of the semiconductor device and reducing the layout area, which can meet the development needs of the BCD process of high voltage, high power and high density, and lay the foundation for pushing the performance limit of power integration and achieving higher performance and integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 is a flow chart of a method for preparing a semiconductor device provided in an embodiment;

[0024] Figure 2 It is a schematic cross-sectional view of a structure obtained after providing a substrate in step S102 in a method for preparing a semiconductor device provided in an embodiment;

[0025] Figure 3 It is a schematic cross-sectional view of a structure obtained after forming a first trench and a second trench in step S1044 in a method for preparing a semiconductor device provided in an embodiment;

[0026] Figure 4 It is a schematic cross-sectional view of a structure obtained after a gate oxide layer is formed in step S1062 in a method for preparing a semiconductor device provided in an embodiment;

[0027] Figure 5 A schematic cross-sectional view of a structure obtained by forming a shielding electrode and an isolation structure in step S1064 in a method for preparing a semiconductor device provided in an embodiment;

[0028] Figure 6 It is a schematic cross-sectional view of a structure obtained after etching back the shielding gate in step S1082 in the method for preparing a semiconductor device provided in an embodiment;

[0029] Figure 7It is a schematic cross-sectional view of a structure obtained after forming a sacrificial layer 13 in step S1084 in a method for preparing a semiconductor device provided in an embodiment;

[0030] Figure 8 It is a schematic cross-sectional view of a structure obtained after a grinding stop layer is formed in step S1102 in a method for preparing a semiconductor device provided in an embodiment;

[0031] Fig. 9 It is a schematic cross-sectional view of a structure obtained after the grinding stop layer is removed in step S1104 in the method for preparing a semiconductor device provided in an embodiment;

[0032] Fig.10 It is a schematic cross-sectional view of a structure obtained after a barrier layer is formed in step S1106 in a method for preparing a semiconductor device in an embodiment;

[0033] Fig.11 It is a schematic cross-sectional view of a structure obtained after the blocking layer is patterned in step S1122 in the method for preparing a semiconductor device in one embodiment;

[0034] Fig.12 It is a schematic cross-sectional view of a structure obtained after a BCD isolation oxide layer is formed in step S1124 in a method for preparing a semiconductor device in an embodiment;

[0035] Fig.13 It is a schematic cross-sectional view of a structure obtained after an interlayer dielectric layer is formed in step S1142 in a method for preparing a semiconductor device in an embodiment;

[0036] Fig.14 It is a schematic cross-sectional view of a structure obtained after the gate 18 is formed in step S1144 in the method for preparing a semiconductor device in one embodiment;

[0037] Fig.15 It is a schematic cross-sectional view of a structure obtained after forming a BCD control gate 30 in a method for preparing a semiconductor device in an embodiment;

[0038] Fig.16 Schematic diagram of a cross-sectional structure of a semiconductor device manufacturing method in an embodiment in which a BCD oxidation isolation layer 16 is formed by using an optimized process.

[0039] Description of reference numerals:

[0040] 10. Substrate; 101. First conductive type base; 1011. Second conductive type buried layer; 1012. First well region; 1013. Second well region; 1014. First conductive type buried layer; 1015. Third well region; 102. First conductive type epitaxial layer; 1021. First epitaxial layer; 1022. Second epitaxial layer; 11. Hard mask layer; 111. First oxide layer; 112. Nitride layer; 113. Second oxide layer; 12. Gate oxide layer; 13. Sacrificial layer; 14. Grinding stop layer; 15. Blocking layer; 16. BCD oxidation isolation layer; 17. Interlayer dielectric layer; 18. Gate; 19. BCD gate oxide layer; 201. First trench; 202. Second trench; 21. Shielding electrode; 22. Isolation structure; 30. BCD control gate. DETAILED DESCRIPTION

[0041] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0043] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0044] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0045] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0046] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the present application, so that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present application.

[0047] In an embodiment of the present application, the substrate may include a first surface located on the front side, and a back side opposite to the front side, i.e., a second surface. Ignoring the flatness of the first surface and the second surface, a first direction parallel to the first surface is defined, and the direction toward the substrate includes a second direction perpendicular to the first surface of the substrate. For example, the direction parallel to the top surface of the substrate is the first direction, and the direction toward the substrate is the second direction. The first direction and the second direction are perpendicular to each other. In an embodiment of the present application, the first direction is defined as the Y-axis direction, and the second direction is defined as the X-axis direction. At the same time, the first area is defined as area A, and the second area is defined as area B.

[0048] See also Figure 1 The present application provides a method for preparing a semiconductor structure, including: step S102-step S110.

[0049] Step S102: providing a substrate 10; the top surface of the substrate 10 includes a hard mask layer 11, and a first region A and a second region B arranged along an OY direction parallel to the top surface of the substrate; wherein the first region A is used to form a BCD device, and the second region B is used to form a trench MOS device.

[0050] See also Figure 2 Specifically, the substrate 10 includes a first conductive type base 101 and a first conductive type epitaxial layer 102 arranged along the XO direction; wherein the first conductive type epitaxial layer 102 also includes a first epitaxial layer 1021 and a second epitaxial layer 1022 arranged along the XO direction, and a second conductive type buried layer 1011 and a first conductive type buried layer 1014 located at the junction of the first epitaxial layer 1021 and the second epitaxial layer 1022 and spaced apart along the OY direction. The positional relationship between the first conductive type epitaxial layer 102, the second conductive type buried layer 1011, and the first conductive type buried layer 1014 mentioned in this embodiment is a well-known technology in the art, and thus will not be elaborated on.

[0051] The first epitaxial layer 1021 also includes a first well region 1012 and a second well region 1013 alternately arranged along the OY direction in the first region A, and a third well region 1015 located in the second region B. The first well region 1012 and the third well region 1015 have the same conductivity type, which is opposite to the second well region 1013. The third well region 1015 is in contact with the first conductive type buried layer 1014 in the OY direction, and has the same size along the OX direction. The third well region 1015 and the first conductive type buried layer 1014 are used to form a drift region of a trench MOS device. By adjusting the doping concentration of the first conductive type buried layer 1014, its on-resistance can be effectively reduced.

[0052] Furthermore, the first conductive type substrate 101 is used for mechanical support and for setting the drain lead-out terminal of the trench MOS device. The first conductive type epitaxial layer 102 has a thickness ranging from 4um to 10um. Figure 2 The first region A of the semiconductor device only shows the original LDMOS device. When the first conductivity type in the present application is N-type, the second conductivity type is P-type, and vice versa.

[0053] Specifically, the hard mask layer 11 includes a first oxide layer 111, a nitride layer 112, and a second oxide layer 113, forming an oxide-nitride-oxide (Oxide-Nitride-Oxide, ONO) structure, the material of the first oxide layer 111 includes but is not limited to silicon oxide (Si2O), and its thickness is 135Å; the material of the nitride layer 112 includes but is not limited to silicon nitride (Si3N4), and its thickness is 1800Å; the material of the second oxide layer 113 includes but is not limited to tetraethyl orthosilicate (TEOs), and its thickness is 3000Å.

[0054] Step S104 : forming a first trench 201 and a second trench 202 arranged along the OY direction in the substrate 10 in the second region B.

[0055] Specifically, the cross-sectional shape of the first groove 201 and the second groove 202 along the OY direction may include a regular trapezoid, an inverted trapezoid, a rectangle, etc., which is not specifically limited here.

[0056] Step S106 : forming a shielding electrode 21 in the first trench 201 .

[0057] Specifically, the material of the shielding electrode 21 includes but is not limited to heavily doped polysilicon, which is used to connect to the source potential, laterally deplete the drift region, and adjust the internal electric field distribution; wherein the heavily doped polysilicon can be of the same type of doping or of multiple types of alternating doping, for example, single N-type doping or NPN alternating doping.

[0058] Step S108 : After etching back the shielding electrode 21 , a sacrificial layer 13 is filled in the first trench 201 .

[0059] Specifically, the material of the sacrificial layer 13 is consistent with the material of the first oxide layer 111 .

[0060] Step S110 : After removing a portion of the hard mask layer 11 along the first direction, a patterned barrier layer 15 is formed on the top surface of the first oxide layer 111 in the first region A.

[0061] Specifically, the material of the barrier layer 15 may be consistent with the material of the nitride layer 112 , both including silicon nitride (Si 3 N 4 ).

[0062] Step S112 : forming a BCD oxidation isolation layer 16 in the substrate 10 in the first region A based on the patterned barrier layer 15 .

[0063] Specifically, the BCD oxide isolation layer 16 here represents the LOCOS field oxide grown after performing the Local Oxidation of Silicon (LOCOS) process, and is used to improve the parasitic field effect transistor and the latch effect.

[0064] Step S114 : forming an interlayer dielectric layer 17 and a gate 18 arranged along the XO direction in the first trench 201 .

[0065] Specifically, the interlayer dielectric layer 17 includes but is not limited to silicon dioxide (SiO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), and is used to isolate the shielding electrode and the gate. The material of the gate 18 includes but is not limited to heavily doped polysilicon, which is used to connect the gate potential. Compared with the U-shaped trench MOS device, the trench MOS device with a shielded gate deep trench (Split Gate Trench, SGT) structure can effectively reduce the gate-drain capacitance and has lower switching loss.

[0066] The semiconductor structure obtained after steps S102-S114 can be referred to Fig.15 In order to facilitate understanding of this application, Figures 3 to 15 is a schematic diagram of each step of an exemplary method for preparing a semiconductor device provided in an embodiment of the present application, wherein: Fig.15 This is an example of a semiconductor device prepared by the preparation method of the present application. There may be other suitable examples of semiconductor devices prepared by the present application, and the present application does not limit them. Figures 3 to 15 The semiconductor device manufacturing method provided in the embodiment of the present application is described in detail.

[0067] See also Figure 3In some embodiments, step S104 also includes: steps S1042 to S1044.

[0068] Step S1042 : patterning the hard mask layer 11 on the top surface of the substrate 10 in the second region B.

[0069] For example, see Figure 3 , a photoresist is coated on the hard mask layer, and after a series of steps such as exposure and development, a patterned photoresist layer is realized by a self-aligned double patterning (SADP) process or a self-aligned quadruple patterning (SAQP) process to define the position and shape of the subsequent first trench 201 and the second trench 202.

[0070] Step S1044 : forming a first trench 201 and a second trench 202 based on the patterned hard mask layer 11 .

[0071] For example, please continue to see Figure 3 Either dry etching or wet etching can be used to form a first trench 201 in the third well region 1015 and a second trench 202 in the second epitaxial layer 1022. The size of the first trench 201 and the second trench 202 along the OY direction ranges from 4um to 8um.

[0072] See also Figure 4-Figure 5 In some embodiments, step S106 further includes: forming an isolation structure 22 in the second trench 202 during the process of forming the shielding electrode 21 in the first trench 201 , specifically including steps S1062 to S1064 .

[0073] Step S1062 : forming a gate oxide layer 12 on the inner surfaces of the first trench 201 and the second trench 202 .

[0074] For example, see Figure 4 The gate oxide layer 12 can be formed on the inner surface of the first trench 201 and the second trench 202 by, but not limited to, a thermal growth process. The thickness of the gate oxide layer 12 is in the range of 2000Å-5000Å, and the specific data can be adjusted according to the breakdown voltage of the semiconductor device, and is not specifically limited here.

[0075] Step S1064 : filling the first trench 201 and the second trench 202 with polysilicon, and simultaneously forming a shielding electrode 21 in the first trench 201 and an isolation structure 22 in the second trench 202 .

[0076] Specifically, see Figure 5The isolation structure 22 and the shielding electrode 21 can be prepared simultaneously by one or more deposition processes such as but not limited to chemical vapor deposition (CVD), atomic layer deposition (ALD), and high density plasma deposition (HDP). In this case, the gate oxide layer 12 is used to form the oxide layer of the isolation structure 22. Compared with the traditional reverse bias PN junction isolation technology, the isolation structure 22 has a stronger withstand voltage capability.

[0077] See also Figure 6-Figure 7 In some embodiments, step S108 further includes:

[0078] Step S1082 : removing part of the polysilicon in the shielding electrode 21 .

[0079] Specifically, see Figure 6 The chemical mechanical polishing process and the etching process can be combined to etch back the polysilicon in the first trench 201 and the second trench 202 to obtain an isolation structure 22 whose top surface is flush with the top surface of the second epitaxial layer 1022 and a shielding electrode 21 whose top surface is not higher than the second epitaxial layer 1022.

[0080] Step S1084 : forming a sacrificial layer 13 in the first trench 201 , the sacrificial layer 13 having a top surface not lower than the hard mask layer 11 .

[0081] For example, see Figure 7 The above structure can also be formed by any deposition process such as CVD process, ALD process and HDP process. Since the sacrificial layer 13 fills the gaps between the first trench 201 and the second trench 202 and the hard mask layer 11, the integrity of the shielding electrode 21 and the isolation structure 22 can be protected during the subsequent formation of the BCD oxidation isolation layer 16.

[0082] See also Figure 8-9 In some embodiments, step S110 further includes:

[0083] Step S1102 : removing the second oxide layer 113 and part of the nitride layer 112 ; the remaining nitride layer 112 is used to form a grinding stop layer 14 .

[0084] Specifically, see Figure 8 The structure can be formed by chemical mechanical polishing process. During the polishing process, part of the sacrificial layer 13 and the second oxide layer 113 are removed simultaneously, and the top surface of the remaining sacrificial layer 13 is not higher than the polishing stop layer 14. The thickness of the polishing stop layer 14 ranges from 1450Å to 1550Å.

[0085] Step S1104 : removing the grinding stop layer 14 and retaining the first oxide layer 111 .

[0086] For example, see Fig. 9 , any one or more of the planarization processes may be used to form the above structure.

[0087] Step S1106 : forming a barrier layer 15 covering the top surface of the first oxide layer 111 .

[0088] For example, see Fig.10 A deposition process is used to form a barrier layer 15 on the top surface of the first oxide layer 111 and the sacrificial layer 13. The thickness of the barrier layer 15 is in the range of 1400Å-1700Å.

[0089] See also Figure 11-Figure 12 In some embodiments, step S112 further includes:

[0090] Step S1122 : patterning the barrier layer 15 on the top surface of the first oxide layer 111 in the first region A based on the photoresist layer to expose a portion of the first oxide layer 111 .

[0091] Step S1124 : performing a furnace thermal oxidation process on the substrate 10 to form a BCD oxidation isolation layer 16 on the exposed top surface of the first oxide layer 111 .

[0092] Specifically, Fig.11 As shown, a patterned barrier layer 15 is formed in the first region A by photolithography to expose the oxygen field region. Fig.12 The substrate 10 is subjected to a furnace thermal oxidation process to form a BCD oxidation isolation layer 16 in the field oxide region as an oxide for LOCOS isolation. The barrier layer 15 acts as a mask to block the diffusion of oxidants, so that the area covered by the barrier layer 15 is not oxidized.

[0093] See also Figure 13-14 In some embodiments, step S114 further includes:

[0094] Step S1142 : sequentially removing the patterned barrier layer 15 and the sacrificial layer 13 located in the first trench 201 .

[0095] Step S1144 : forming an interlayer dielectric layer 17 in the first trench 201 by thermal growth.

[0096] Step S1146 : filling polysilicon into the first trench 201 .

[0097] Step S1148 : removing the polysilicon outside the first trench 201 . At this time, the remaining polysilicon in the first trench 201 is used to form the gate 18 .

[0098] For example, a wet etching process may be used to remove the barrier layer 15 and the sacrificial layer 13 located in the first trench 201 to obtain: Fig.13 The structure shown in FIG. is then formed by a thermal growth process to form an interlayer dielectric layer 17 with a thickness ranging from 500Å to 800Å. In this embodiment, the material of the interlayer dielectric layer 17 includes silicon dioxide (SiO2). A gate 18 is formed in the first trench 201 by combining a deposition process and an etching back process. The resulting structure is shown in FIG. Fig.14 shown.

[0099] See also Fig.15 In some embodiments, the semiconductor device manufacturing method further includes: performing an ion implantation process on the substrate 10 in the first region A and the second region B to form a well region; removing the first oxide layer 111; forming a BCD gate oxide layer 19 covering the top surface of the BCD device in the first region A and the trench MOS device in the second region B; and forming a BCD control gate 30 on the top surface of the BCD gate oxide layer 19 in the first region.

[0100] Specifically, the photolithography process, the deposition process, the backside thinning process and the ion implantation process may be combined, and then the remaining steps in the BCD process may be performed to sequentially complete the preparation of structures such as doped regions, electrodes and the like in each region.

[0101] In some other embodiments, step S1104 to step S1106 are optimized to: adjust the thickness of the grinding stop layer 14 , and the adjusted grinding stop layer 14 is used to form a barrier layer 15 covering the top surface of the first oxide layer 111 .

[0102] In the above embodiment, by adjusting the deposition thickness of the grinding stop layer 14, after the planarization process is performed, it is directly used as the barrier layer 15 of the LOCOS process to achieve the selective oxidation of silicon. The resulting structural schematic diagram is as follows: Figure 8 Then, continue to perform step S1122-step S1124, in the second region B, use the sacrificial layer 13 to replace the barrier layer 15 in the original step, and use it as a protective layer for the shielding electrode 21 and the isolation structure 22 in the second region B in the LOCOS process. The resulting structure is as shown in FIG. Fig.16 Based on the above structure, step S114 is repeated to obtain Fig.15 After the process adjustment, under the premise of ensuring that the structure of the trench MOS device is not affected, the steps of removing the grinding stop layer 14 and regrowing the barrier layer 15 in the original process are omitted, thereby effectively optimizing the process flow, significantly improving its efficiency and reducing material consumption.

[0103] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: providing a substrate; The top surface of the substrate includes a hard mask layer, and a first region and a second region arranged along a first direction parallel to the top surface of the substrate; wherein the first region is used to form a BCD device, and the second region is used to form a trench MOS device; forming a first trench and a second trench arranged along the first direction in the substrate of the second region; forming a shielding electrode in the first trench; After etching back the shielding electrode, a sacrificial layer is filled in the first trench; After removing a portion of the hard mask layer along the first direction, a patterned barrier layer is formed on the top surface of the first oxide layer in the first region; Based on the patterned barrier layer, forming a BCD oxidation isolation layer in the substrate of the first region; An interlayer dielectric layer and a gate are formed in the first trench and are arranged in sequence along a direction away from the substrate.

2. The preparation method according to claim 1, characterized in that: forming an isolation structure in the second trench during the process of forming the shielding electrode in the first trench; Forming the shielding electrode and the isolation structure includes: patterning the hard mask layer on the top surface of the substrate in the second region; Based on the patterned hard mask layer, forming the first trench and the second trench; forming a gate oxide layer on inner surfaces of the first trench and the second trench; Polysilicon is filled into the first trench and the second trench, and the shielding electrode located in the first trench and the isolation structure located in the second trench are simultaneously formed.

3. The preparation method according to claim 1, characterized in that: The hard mask layer includes a first oxide layer, a nitride layer, and a second oxide layer stacked in sequence in a direction away from the substrate; Removing a portion of the hard mask layer along a first direction includes: removing the second oxide layer and a portion of the nitride layer; The remaining nitride layer is used to form a grinding stop layer.

4. The preparation method according to claim 3, characterized in that: removing the grinding stop layer and retaining the first oxide layer; A barrier layer is formed to cover a top surface of the first oxide layer.

5. The preparation method according to claim 3, characterized in that: The thickness of the grinding stop layer is adjusted; the adjusted grinding stop layer is used to form a blocking layer covering the top surface of the first oxide layer.

6. The preparation method according to claim 1, characterized in that: Based on the patterned barrier layer, the BCD oxidation isolation layer is formed in the first region, further comprising: Based on the photoresist layer, patterning the barrier layer on the top surface of the first oxide layer in the first region to expose a portion of the first oxide layer; A furnace thermal oxidation process is performed on the substrate to form the BCD oxidation isolation layer at the first oxide layer on the exposed top surface.

7. The preparation method according to claim 1, characterized in that: The interlayer dielectric layer and the gate are formed, and further comprising: removing the patterned barrier layer and the sacrificial layer located in the first trench in sequence; forming an interlayer dielectric layer in the first trench by thermal growth; filling polysilicon into the first trench; The polysilicon outside the first trench is removed, and the remaining polysilicon in the first trench is used to form the gate.

8. The preparation method according to any one of claims 1 to 7, characterized in that: Also includes: Performing an ion implantation process on the substrate in the first region and the second region to form a well region; removing the first oxide layer; forming a BCD gate oxide layer covering the top surface of the BCD device in the first region and the trench MOS device in the second region; A BCD control gate is formed on the top surface of the BCD gate oxide layer in the first region.

9. A semiconductor device, characterized in that: The invention is prepared by the preparation method according to any one of claims 1 to 8.

10. An electronic device, characterized in that: A semiconductor device manufactured by the manufacturing method according to any one of claims 1 to 8; or A semiconductor device comprising the semiconductor device according to claim 9.

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