Transistor and manufacturing method thereof

Abstract

The invention provides a transistor and a manufacturing method thereof, and belongs to the field of semiconductor devices. The transistor comprises a first channel layer, a first barrier layer, a second channel layer, a second barrier layer, a dielectric layer, a source electrode and a drain electrode, the first barrier layer, the second channel layer and the second barrier layer are sequentially stacked on the first channel layer, and the first barrier layer, the second channel layer and the second barrier layer are provided with a source electrode groove and a drain electrode groove which extend to the first channel layer; the source electrode is located in the source electrode groove and connected with the first channel layer, the drain electrode is located in the drain electrode groove and connected with the first channel layer, and the dielectric layer is located between the source electrode and the inner wall of the source electrode groove.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor devices, and in particular to a transistor and a method for manufacturing the same. Background Art

[0002] GaN-based transistors are candidates for next-generation power switching applications due to their superior device properties (low specific on-resistance, low switching losses, and high breakdown voltage).

[0003] In many power switching circuits, such as DC-AC inverters and boost converters, it is necessary for transistors to be able to conduct in the reverse direction with low losses to provide a freewheeling current path so that the inductive load current is not disturbed and to suppress high voltage peaks.

[0004] At present, the conventional structure of GaN high electron mobility transistor (HEMT) can be reverse-conducted, and the reverse conduction voltage V RT Depends on the gate-source bias V GS and threshold voltage V th , V RT =|V th -V GS |. In actual power switching circuit applications, negative gate-source bias V is usually used. GS To prevent false start-up and improve noise immunity, V RT In order to obtain lower reverse conduction loss, an external anti-parallel Schottky barrier diode is usually used, but this will introduce additional parasitic parameters and increase the total cost. Summary of the invention

[0005] The embodiment of the present disclosure provides a transistor and a method for manufacturing the same, which can achieve low reverse conduction voltage through the structure of the transistor itself. The technical solution is as follows:

[0006] In one aspect, a transistor is provided, the transistor comprising: a first channel layer, a first barrier layer, a second channel layer, a second barrier layer, a dielectric layer, a source electrode, and a drain electrode;

[0007] The first barrier layer, the second channel layer and the second barrier layer are sequentially stacked on the first channel layer, and the first barrier layer, the second channel layer and the second barrier layer are provided with a source groove and a drain groove extending to the first channel layer;

[0008] The source electrode is located in the source groove and connected to the first channel layer, the drain electrode is located in the drain groove and connected to the first channel layer, and the dielectric layer is located between the source electrode and an inner wall of the source groove.

[0009] Optionally, the thicknesses of the first channel layer, the first barrier layer, the second channel layer and the second barrier layer are 400-500 nm, 20-25 nm, 250-300 nm and 20-25 nm respectively.

[0010] Optionally, the dielectric layer is a HfO2 dielectric layer.

[0011] Optionally, the transistor further includes a buffer layer, the buffer layer includes an AlGaN buffer layer and a superlattice buffer layer, and the superlattice buffer layer is located between the AlGaN buffer layer and the first channel layer.

[0012] Optionally, the transistor further includes a carbon-doped GaN layer, wherein the carbon-doped GaN layer is located between the superlattice buffer layer and the first channel layer.

[0013] In another aspect, a method for manufacturing a transistor is provided, the method comprising:

[0014] Manufacturing a first channel layer, a first barrier layer, a second channel layer and a second barrier layer stacked in sequence;

[0015] Opening a source groove and a drain groove extending to the first channel layer on the first barrier layer, the second channel layer and the second barrier layer;

[0016] fabricating a dielectric layer;

[0017] A source and a drain are manufactured, wherein the source is located in the source groove and connected to the first channel layer, the drain is located in the drain groove and connected to the first channel layer, and the dielectric layer is located between the source and the inner wall of the source groove.

[0018] Optionally, the step of manufacturing a first channel layer, a first barrier layer, a second channel layer, and a second barrier layer stacked in sequence comprises:

[0019] In an environment where the reaction chamber temperature is 1000-1100° C., the reaction chamber pressure is 190-210 mbar, the NH3 flow rate is 9000-11000 sccm, and the TMGa flow rate is 190-210 sccm, growing the first channel layer with a thickness of 400-500 nm;

[0020] In an environment where the reaction chamber temperature is 1010-1110° C., the reaction chamber pressure is 190-210 mbar, the NH3 flow rate is 4900-5100 sccm, the TMGa flow rate is 190-210 sccm, and the TMAl flow rate is 40-60 sccm, growing the first barrier layer with a thickness of 20-25 nm on the first channel layer;

[0021] In an environment where the reaction chamber temperature is 1000-1100° C., the reaction chamber pressure is 190-210 mbar, the NH3 flow rate is 9000-11000 sccm, and the TMGa flow rate is 190-210 sccm, growing the second channel layer with a thickness of 250-300 nm on the first barrier layer;

[0022] In an environment where the reaction chamber temperature is 1010-1110°C, the reaction chamber pressure is 190-210 mbar, the NH3 flow rate is 4900-5100 sccm, the TMGa flow rate is 190-210 sccm, and the TMAl flow rate is 40-60 sccm, the second barrier layer with a thickness of 20-25 nm is grown on the second channel layer.

[0023] Optionally, the manufacturing of the dielectric layer includes:

[0024] Depositing a HfO2 dielectric film in the source groove;

[0025] The HfO2 dielectric film is patterned to obtain a HfO2 dielectric layer.

[0026] Optionally, the method further comprises:

[0027] A buffer layer is manufactured, wherein the buffer layer comprises an AlGaN buffer layer and a superlattice buffer layer, and the superlattice buffer layer is located between the AlGaN buffer layer and the first channel layer.

[0028] Optionally, the method further comprises:

[0029] A carbon-doped GaN layer is fabricated, wherein the carbon-doped GaN layer is located between the superlattice buffer layer and the first channel layer.

[0030] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects:

[0031] In the transistor, a double heterojunction composed of a first channel layer, a first barrier layer, a second channel layer, and a second barrier layer forms a double two-dimensional electron gas (2DEG) channel, and the double 2DEG channel serves as a first path and a second path for reverse conduction. The source electrode, the dielectric layer, and the first channel layer in the source groove form a metal oxide semiconductor (MOS) channel diode (MCD). The MCD acts as a switch to control the first path, which is composed of a metal-insulator-semiconductor structure. The first path will be opened before the second path. Due to the introduction of the first path, the transistor has an additional reverse conduction channel, which helps to enhance the reverse conduction performance, provide an additional reverse current path, significantly improve the reverse current capability, while maintaining high conduction and blocking performance, and reduce reverse conduction losses in power switch applications. Compared with traditional external anti-parallel Schottky barrier diodes, no additional parasitic parameters are introduced, the total cost is not increased, and the breakdown voltage is not reduced due to sacrificing the forward conduction area. In addition, compared with the HEMT in the related art, the transistor provided by the embodiment of the present disclosure can obtain a lower reverse conduction voltage (V RT ), while its V RT and gate-source bias (V GS ), the forward conduction capability and blocking characteristics remain almost unchanged. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 is a schematic structural diagram of a transistor provided by an embodiment of the present disclosure;

[0034] Figure 2 is a schematic diagram of an equivalent circuit of a diode provided in an embodiment of the present disclosure;

[0035] Figure 3 is a schematic diagram of the operation of a transistor provided by an embodiment of the present disclosure in a working environment;

[0036] Figure 4 The embodiment of the present disclosure provides Figure 3 Equivalent circuit diagram of

[0037] Figure 5 is a schematic diagram of the operation of a transistor provided by an embodiment of the present disclosure in a working environment;

[0038] Figure 6 The embodiment of the present disclosure provides Figure 5 Equivalent circuit diagram of

[0039] Figure 7 is a schematic diagram of the operation of a transistor provided by an embodiment of the present disclosure under a working stage;

[0040] Figure 8 The embodiment of the present disclosure provides Figure 7 Equivalent circuit diagram of

[0041] Fig. 9 is a flow chart of a method for manufacturing a transistor provided by an embodiment of the present disclosure;

[0042] Fig.10 It is a flow chart of another method for manufacturing a transistor provided in an embodiment of the present disclosure.

[0043] Reference numerals

[0044] 100: substrate; 101: first channel layer; 102: first barrier layer; 103: second channel layer; 104: second barrier layer; 105: dielectric layer; 106: source; 107: drain; 108: buffer layer; 181: AlGaN buffer layer; 182: superlattice buffer layer; 109: carbon-doped GaN layer; 110: P-GaN layer; 111: passivation layer; 112: gate; 113: nucleation layer; 200: MCD; 1001: source groove; 1002: drain groove. DETAILED DESCRIPTION

[0045] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0046] Figure 1 A schematic diagram of a transistor structure provided by an embodiment of the present disclosure. Figure 1 The transistor includes: a first channel layer 101 , a first barrier layer 102 , a second channel layer 103 , a second barrier layer 104 , a dielectric layer 105 , a source 106 and a drain 107 .

[0047] The first barrier layer 102 , the second channel layer 103 and the second barrier layer 104 are sequentially stacked on the first channel layer 101 , and the first barrier layer 102 , the second channel layer 103 and the second barrier layer 104 are provided with a source groove 1001 and a drain groove 1002 extending to the first channel layer 101 .

[0048] The source 106 is located in the source groove 1001 and connected to the first channel layer 101 , the drain 107 is located in the drain groove 1002 and connected to the first channel layer 101 , and the dielectric layer 105 is located between the source 106 and the inner wall of the source groove 1001 .

[0049] The embodiments of the present disclosure provide a double channel reverse conducting (DCRC) HEMT.

[0050] In the disclosed embodiment, in the transistor, the double heterojunction composed of the first channel layer, the first barrier layer, the second channel layer, and the second barrier layer forms a double 2DEG channel, and the double 2DEG channel serves as a first path and a second path for reverse conduction. The source electrode, the dielectric layer, and the first channel layer in the source groove form an MCD ( Figure 1 200). The MCD acts as a switch to control the first path, which is composed of a metal-insulator-semiconductor structure. The first path will be opened before the second path. Due to the introduction of the first path, the transistor has an additional reverse conduction channel, which helps to enhance the reverse conduction performance, provide an additional reverse current path, significantly improve the reverse current capability, while maintaining high conduction and blocking performance, and reduce reverse conduction losses in power switch applications. Compared with the traditional external anti-parallel Schottky barrier diode, no additional parasitic parameters are introduced, the total cost is not increased, and the breakdown voltage is not reduced due to sacrificing the forward conduction area. In addition, compared with the HEMT in the related art, the transistor provided by the embodiment of the present disclosure can obtain a lower reverse conduction voltage (V RT ), while its V RT and gate-source bias (V GS ), the forward conduction capability and blocking characteristics remain almost unchanged.

[0051] In the embodiment of the present disclosure, the first channel layer 101 and the second channel layer 103 are GaN channel layers.

[0052] The thickness of the first channel layer 101 is 400-500 nm, for example, 450 nm. The thickness of the second channel layer 103 is 250-300 nm, for example, 270 nm.

[0053] In the embodiment of the present disclosure, the first barrier layer 102 and the second barrier layer 104 may be a single layer or a composite layer.

[0054] For example, the first barrier layer 102 and the second barrier layer 104 are AlGaN layers, such as Al 0.25 Ga 0.75 N layers.

[0055] The thickness of the first barrier layer 102 is 20-25 nm, for example, 23 nm. The thickness of the second barrier layer 104 is 20-25 nm, for example, 23 nm.

[0056] In the present embodiment, the channel layer and the barrier layer having the above-mentioned thickness are used to ensure the double 2DEG channel and its reverse conduction function, while not causing the size of the entire transistor to be too large.

[0057] In other implementations, the first barrier layer 102 and the second barrier layer 104 may also be InAlGaN layers.

[0058] In the embodiment of the present disclosure, the dielectric layer 105 is an oxide dielectric layer, such as a HfO 2 dielectric layer.

[0059] In the disclosed embodiment, HfO2 is a high-K dielectric material, a good insulator, and has low leakage current.

[0060] In other implementations, the dielectric layer 105 may also be a ZrO 2 or SiO 2 layer.

[0061] Figure 2 is a schematic diagram of an equivalent circuit of a diode provided in an embodiment of the present disclosure. Figure 2 , M represents metal, i.e., source; I represents insulator, i.e., HfO2 dielectric layer; S represents semiconductor, i.e., first channel layer. The source, HfO2 dielectric layer, and first channel layer constitute a MOS channel diode, acting as a switch to control the first path, which is composed of a metal-insulator-semiconductor structure. The thicker the HfO2 dielectric layer, the weaker the electron accumulation effect along the channel in the MCD. The thinner the HfO2 dielectric layer, the short channel effect will lead to premature breakdown.

[0062] In the embodiment of the present disclosure, the thickness of the HfO2 dielectric layer can be 15-20 nm. The above thickness can balance the above two situations and ensure the reliability of the transistor.

[0063] In the embodiment of the present disclosure, the length of the HfO2 dielectric layer may be 0.25 μm. The length here refers to the extension length of the HfO2 dielectric layer from the top and sidewall to the bottom of the groove.

[0064] In the embodiment of the present disclosure, the HfO2 dielectric layer can be manufactured by an atomic layer deposition (ALD) process.

[0065] See again Figure 1 The transistor further includes a buffer layer 108 , wherein the buffer layer 108 includes an AlGaN buffer layer 181 and a superlattice buffer layer 182 , and the superlattice buffer layer 182 is located between the AlGaN buffer layer 181 and the first channel layer 101 .

[0066] like Figure 1 As shown, the transistor further includes a carbon-doped GaN layer 109 , and the carbon-doped GaN layer 109 is located between the superlattice buffer layer 182 and the first channel layer 101 .

[0067] like Figure 1 As shown, the transistor further includes a substrate 100 , in which a buffer layer 108 and a carbon-doped GaN layer 109 are stacked.

[0068] like Figure 1 As shown, the transistor further includes a nucleation layer 113 , and the nucleation layer 113 is located between the substrate 100 and the buffer layer 108 .

[0069] In the embodiment of the present disclosure, the AlGaN buffer layer 181 in the buffer layer 108 is a stress buffer layer, and the superlattice buffer layer 182 is used for matching between the substrate and the channel layer. The carbon-doped GaN layer 109 serves as a high resistance layer.

[0070] In the embodiment of the present disclosure, the substrate 100 is a Si substrate, a silicon carbide substrate or a sapphire substrate.

[0071] Exemplarily, the substrate 100 is a Si substrate.

[0072] In the embodiment of the present disclosure, the thickness of the AlGaN buffer layer 181 is 80-120 nm, for example, 100 nm.

[0073] In the embodiment of the present disclosure, the superlattice buffer layer 182 includes a superlattice structure composed of an AlN layer and an AlGaN layer.

[0074] In this implementation, by providing a buffer layer of a superlattice structure composed of an AlN layer and an AlGaN layer, the growth quality of the channel layer of the transistor is improved.

[0075] In the disclosed embodiment, the thickness of the AlN layer is 4-6 nm, and the thickness of the AlGaN layer is 20-30 nm.

[0076] Exemplarily, the thickness of the AlN layer is 5 nm, and the thickness of the AlGaN layer is 25 nm.

[0077] In the embodiment of the present disclosure, the number of periods of the superlattice structure in the buffer layer 108 is 40-60.

[0078] By way of example, the number of periods of the superlattice structure in the buffer layer 108 is 50.

[0079] In the embodiment of the present disclosure, the thickness of the carbon-doped GaN layer 109 is 900-1200 nm.

[0080] Exemplarily, the thickness of the carbon-doped GaN layer is 1000 nm.

[0081] In the embodiment of the present disclosure, the nucleation layer 113 is an AlN nucleation layer. The thickness of the AlN nucleation layer may be 150-200 nm, for example, 170 nm.

[0082] See again Figure 1 The transistor also includes a P-GaN layer 110, a passivation layer 111 and a gate 112. The P-GaN layer 110 is located on the second barrier layer 104. The passivation layer 111 covers the second barrier layer 104 and the P-GaN layer 110. The gate 112 passes through the passivation layer 111 and is connected to the second barrier layer 104.

[0083] In the embodiment of the present disclosure, the thickness of the P-GaN layer 110 is 100-150 nm.

[0084] Exemplarily, the thickness of the P-GaN layer 110 is 120 nm.

[0085] In the embodiment of the present disclosure, the thickness of the passivation layer 111 is 350-450 nm.

[0086] Exemplarily, the thickness of the passivation layer 111 is 400 nm.

[0087] By way of example, the passivation layer 112 may be a SiN passivation layer.

[0088] In the disclosed embodiments, a novel normally-off DCRC HEMT is proposed, which has an integrated MOS channel diode to achieve low reverse conduction voltage. In addition, the thickness of each film layer in the transistor is optimized to maintain good forward conduction capability and blocking characteristics.

[0089] Figure 3 It is a schematic diagram of the operation of a transistor provided by an embodiment of the present disclosure under a working stage. Figure 4 yes Figure 3 Equivalent circuit diagram of . Figure 3 and Figure 4 , in the reverse conduction state, when V GS ≤0V, V RT <|V DS |≤|V th -V GS |, in the case of the accumulation layer below the source recess, the MOS channel diode is turned on. V DS Is the voltage between the source and drain. Among them, the charge accumulation can be realized on both sides of the insulating layer, and a thin layer with greatly increased HfO2 carrier concentration is called the accumulation layer.

[0090] Figure 5It is a schematic diagram of the operation of a transistor provided by an embodiment of the present disclosure under a working stage. Figure 6 yes Figure 5 Equivalent circuit diagram of . Figure 5 and Figure 6 , in the reverse conduction state, when V GS ≤0V,|V DS |>|V th -V GS |, the 2DEG under the P-GaN layer in the second path is depleted, opening the second path. Therefore, both paths participate in reverse conduction and improve the reverse current capacity.

[0091] Figure 7 It is a schematic diagram of the operation of a transistor provided by an embodiment of the present disclosure under a working stage. Figure 8 yes Figure 7 Equivalent circuit diagram of . Figure 7 and Figure 8 , in the on state, when V GS >V th , V DS When >0V, only the second path is turned on and the MOS channel diode is pinched off. Therefore, the forward conduction characteristics will not be affected by the MOS channel diode.

[0092] Compared with the HEMT in the related art, the DCRC-HEMT provided in the embodiment of the present disclosure can obtain a lower reverse conduction voltage (V RT ), while V RT and gate-source bias (V GS ) has nothing to do with the V RT is 0.62V. At V GS = 0V and -1V, the V RT Compared with the V RT The forward conduction capability and blocking characteristics of DCRC HEMTs remained almost unchanged.

[0093] Fig. 9 is a flow chart of a method for manufacturing a transistor provided by an embodiment of the present disclosure. Fig. 9 The method steps include:

[0094] 301. Fabricate a first channel layer, a first barrier layer, a second channel layer, and a second barrier layer that are stacked in sequence.

[0095] 302. Open a source groove and a drain groove extending to the first channel layer on the first barrier layer, the second channel layer and the second barrier layer.

[0096] 303. Fabricate a dielectric layer.

[0097] 304. Make a source and a drain, wherein the source is located in the source groove and connected to the first channel layer, the drain is located in the drain groove and connected to the first channel layer, and the dielectric layer is located between the source and the inner wall of the source groove.

[0098] In the disclosed embodiment, in the transistor, a double heterojunction composed of a first channel layer, a first barrier layer, a second channel layer, and a second barrier layer forms a double 2DEG channel, and the double 2DEG channel serves as a first path and a second path for reverse conduction. The source, dielectric layer, and first channel layer in the source groove form an MCD. The MCD acts as a switch to control the first path, which is composed of a metal-insulator-semiconductor structure. The first path will be opened before the second path. Due to the introduction of the first path, the transistor has an additional reverse conduction channel, which helps to enhance the reverse conduction performance, provide an additional reverse current path, significantly improve the reverse current capability, while maintaining high conduction and blocking performance, and reduce reverse conduction losses in power switch applications. Compared with traditional external anti-parallel Schottky barrier diodes, no additional parasitic parameters are introduced, the total cost is not increased, and the breakdown voltage is not reduced due to sacrificing the forward conduction area.

[0099] Fig.10 A flow chart of a method for manufacturing a transistor provided in an embodiment of the present disclosure, see Fig.10 , the method flow chart includes:

[0100] 401. Provide a substrate.

[0101] In the embodiment of the present disclosure, the substrate 100 is a Si substrate, a silicon carbide substrate or a sapphire substrate.

[0102] Exemplarily, the substrate 100 is a Si substrate.

[0103] Optionally, the method may further include:

[0104] The substrate is placed in a metal-organic chemical vapor deposition (MOCVD) reaction chamber for nitride epitaxy, hydrogen is introduced as a carrier gas and the substrate temperature is raised to 1000° C. to 1110° C. to decompose the oxide on the substrate surface at high temperature to obtain a clean surface.

[0105] For example, a silicon substrate is placed in MOCVD, the substrate temperature is raised to 1050°C, and treated in a H2 atmosphere for 10 minutes to obtain a clean silicon surface.

[0106] In the embodiments of the present disclosure, the subsequent insulating and semiconductor film layers may be manufactured using the MOCVD process unless otherwise specified.

[0107] 402. Fabricate a buffer layer on the substrate, wherein the buffer layer includes an AlGaN buffer layer and a superlattice buffer layer.

[0108] In the embodiment of the present disclosure, the AlGaN buffer layer 181 in the buffer layer 108 is a stress buffer layer, and the superlattice buffer layer 182 is used for matching between the substrate and the channel layer. The carbon-doped GaN layer 109 serves as a high resistance layer.

[0109] In the embodiment of the present disclosure, the thickness of the AlGaN buffer layer 181 is 80-120 nm, for example, 100 nm.

[0110] In the embodiment of the present disclosure, the superlattice buffer layer 182 includes a superlattice structure composed of an AlN layer and an AlGaN layer.

[0111] In this implementation, by providing a buffer layer of a superlattice structure composed of an AlN layer and an AlGaN layer, the growth quality of the channel layer of the transistor is improved.

[0112] In the embodiment of the present disclosure, the thickness of the AlN layer is 4-6 nm, and the thickness of the AlGaN layer is 20-25 nm.

[0113] Exemplarily, the thickness of the AlN layer is 5 nm, and the thickness of the AlGaN layer is 25 nm.

[0114] In the embodiment of the present disclosure, the number of periods of the superlattice structure in the buffer layer 108 is 40-60.

[0115] By way of example, the number of periods of the superlattice structure in the buffer layer 108 is 50.

[0116] In the embodiment of the present disclosure, step 402 may include:

[0117] In the first step, a 40-60nm AlGaN buffer layer is grown under the conditions of a reaction chamber temperature of 1030-1130°C, a reaction chamber pressure of 40-60mbar, an NH3 flow rate of 3000-5000sccm, a TMGa flow rate of 400-500sccm, and a TMAl flow rate of 140-160sccm; the TMAl flow rate is doubled to continue growing a 40-60nm AlGaN buffer layer.

[0118] For example, a 50nm AlGaN buffer layer is grown under the conditions of a reaction chamber temperature of 1080°C, a reaction chamber pressure of 50mbar, an NH3 flow rate of 4000sccm, a TMGa flow rate of 450sccm, and a TMAl flow rate of 150sccm; the TMAl flow rate is doubled and a 50nm AlGaN buffer layer is continued to be grown.

[0119] In the second step, a superlattice buffer layer is grown under the conditions of a reaction chamber temperature of 1090-1190° C., a reaction chamber pressure of 40-60 mbar, an NH3 flow rate of 4000-6000 sccm, a TMGa flow rate of 150-250 sccm, and a TMAl flow rate of 40-60 sccm.

[0120] Exemplarily, the superlattice buffer layer is grown in an environment where the reaction chamber temperature is 1140° C., the reaction chamber pressure is 50 mbar, the NH 3 flow rate is 5000 sccm, the TMGa flow rate is 200 sccm, and the TMAl flow rate is 40 sccm.

[0121] Optionally, the method further comprises:

[0122] Before step 402 , an AlN nucleation layer is grown on the substrate. The thickness of the AlN nucleation layer may be 150-200 nm, for example, 170 nm.

[0123] 403. Fabricate a carbon-doped GaN layer on the buffer layer.

[0124] In the embodiment of the present disclosure, the thickness of the carbon-doped GaN layer 109 is 900-1200 nm.

[0125] Exemplarily, the thickness of the carbon-doped GaN layer is 1000 nm.

[0126] In the embodiment of the present disclosure, step 403 may include:

[0127] A carbon-doped GaN layer is formed under an environment in which the reaction chamber temperature is 1000-1100°C, the reaction chamber pressure is 150-250 mbar, the NH3 flow rate is 4000-6000 sccm, the TMGa flow rate is 300-500 sccm, the carbon doping source C2H4 flow rate is 150-250 sccm, and the growth time is 15-30 minutes.

[0128] Exemplarily, a carbon-doped GaN layer is formed with a growth time of 20 minutes under an environment of a reaction chamber temperature of 1050° C., a reaction chamber pressure of 200 mbar, an NH 3 flow rate of 5000 sccm, a TMGa flow rate of 400 sccm, and a carbon doping source C 2 H 4 flow rate of 200 sccm.

[0129] 404. Fabricate a first channel layer, a first barrier layer, a second channel layer, and a second barrier layer stacked in sequence on the carbon-doped GaN layer.

[0130] In the embodiment of the present disclosure, the first channel layer 101 and the second channel layer 103 are GaN channel layers.

[0131] The thickness of the first channel layer 101 is 400-500 nm, for example, 450 nm. The thickness of the second channel layer 103 is 250-300 nm, for example, 270 nm.

[0132] In the embodiment of the present disclosure, the first barrier layer 102 and the second barrier layer 104 may be a single layer or a composite layer.

[0133] For example, the first barrier layer 102 and the second barrier layer 104 are AlGaN layers, such as Al 0.25 Ga 0.75 N layers.

[0134] The thickness of the first barrier layer 102 is 20-25 nm, for example, 23 nm. The thickness of the second barrier layer 104 is 20-25 nm, for example, 23 nm.

[0135] In the present embodiment, the channel layer and the barrier layer having the above-mentioned thickness are used to ensure the double 2DEG channel and its reverse conduction function, while not causing the size of the entire transistor to be too large.

[0136] In other implementations, the first barrier layer 102 and the second barrier layer 104 may also be InAlGaN layers.

[0137] In the embodiment of the present disclosure, step 404 may include:

[0138] In the first step, the first channel layer with a thickness of 400-500 nm is grown under the conditions of a reaction chamber temperature of 1000-1100° C., a reaction chamber pressure of 190-210 mbar, an NH3 flow rate of 9000-11000 sccm, and a TMGa flow rate of 190-210 sccm.

[0139] Exemplarily, the first channel layer with a thickness of 450 nm is grown under an environment where the reaction chamber temperature is 1050° C., the reaction chamber pressure is 200 mbar, the NH 3 flow rate is 10000 sccm, and the TMGa flow rate is 200 sccm.

[0140] In the second step, under the environment of reaction chamber temperature of 1010-1110°C, reaction chamber pressure of 190-210mbar, NH3 flow rate of 4900-5100sccm, TMGa flow rate of 190-210sccm, and TMAl flow rate of 40-60sccm, the first barrier layer with a thickness of 20-25nm is grown on the first channel layer.

[0141] Exemplarily, under an environment where the reaction chamber temperature is 1060° C., the reaction chamber pressure is 200 mbar, the NH 3 flow rate is 5000 sccm, the TMGa flow rate is 200 sccm, and the TMAl flow rate is 50 sccm, the first barrier layer with a thickness of 23 nm is grown on the first channel layer.

[0142] The third step is to grow the second channel layer with a thickness of 250 to 300 nm on the first barrier layer under an environment in which the reaction chamber temperature is 1000 to 1100° C., the reaction chamber pressure is 190 to 210 mbar, the NH3 flow rate is 9000 to 11000 sccm, and the TMGa flow rate is 190 to 210 sccm.

[0143] Exemplarily, in an environment where the reaction chamber temperature is 1050° C., the reaction chamber pressure is 200 mbar, the NH 3 flow rate is 10000 sccm, and the TMGa flow rate is 200 sccm, the second channel layer with a thickness of 270 nm is grown on the first barrier layer.

[0144] The fourth step is to grow the second barrier layer with a thickness of 20 to 25 nm on the second channel layer under an environment where the reaction chamber temperature is 1010 to 1110°C, the reaction chamber pressure is 190 to 210 mbar, the NH3 flow rate is 4900 to 5100 sccm, the TMGa flow rate is 190 to 210 sccm, and the TMAl flow rate is 40 to 60 sccm.

[0145] Exemplarily, the second barrier layer with a thickness of 23 nm is grown on the second channel layer under an environment of a reaction chamber temperature of 1060° C., a reaction chamber pressure of 200 mbar, an NH 3 flow rate of 5000 sccm, a TMGa flow rate of 200 sccm, and a TMAl flow rate of 50 sccm.

[0146] The above growth process is used to manufacture the first semiconductor layer to the second barrier layer, which can ensure the double 2DEG channel and its reverse conduction effect.

[0147] 405 . Fabricate a P-GaN layer and a passivation layer on the second barrier layer, wherein the passivation layer covers the second barrier layer and the P-GaN layer.

[0148] In the embodiment of the present disclosure, the thickness of the P-GaN layer 110 is 100-150 nm.

[0149] Exemplarily, the thickness of the P-GaN layer 110 is 120 nm.

[0150] In the embodiment of the present disclosure, the thickness of the passivation layer 111 is 350-450 nm.

[0151] Exemplarily, the thickness of the passivation layer 111 is 400 nm.

[0152] By way of example, the passivation layer 112 may be a SiN passivation layer.

[0153] In the embodiment of the present disclosure, the P-GaN layer 110 is a Mg-doped P-GaN layer, and the Mg doping concentration is 1E19 cm -3 When the P-GaN layer 110 is grown, the temperature of the reaction chamber is 900° C., the pressure of the reaction chamber is 200 mbar, the flow rate of NH 3 is 5000 sccm, and the flow rate of TMGa is 200 sccm.

[0154] In the embodiment of the present disclosure, the pattern of the P-GaN layer 110 is obtained by inductively coupled plasma etching based on Cl2 / BCl3.

[0155] In the embodiment of the present disclosure, the passivation layer 112 is made by a low pressure chemical vapor deposition process.

[0156] 406. Open a source groove and a drain groove extending to the first channel layer on the first barrier layer, the second channel layer and the second barrier layer.

[0157] In the disclosed embodiment, the source groove and the drain groove are made by using processes such as inductively coupled plasma etching, plasma oxidation and wet etching.

[0158] 407. Fabricate a dielectric layer.

[0159] In the embodiment of the present disclosure, the dielectric layer 105 is an oxide dielectric layer, such as a HfO 2 dielectric layer.

[0160] In other implementations, the dielectric layer 105 may also be a ZrO 2 or SiO 2 layer.

[0161] In the embodiment of the present disclosure, step 407 may include:

[0162] A HfO2 dielectric film is deposited in the source groove.

[0163] The HfO2 dielectric film is patterned to obtain a HfO2 dielectric layer.

[0164] 408. Fabricate a source and a drain, wherein the source is located in the source groove and connected to the first channel layer, the drain is located in the drain groove and connected to the first channel layer, and the dielectric layer is located between the source and the inner wall of the source groove.

[0165] In the embodiment of the present disclosure, a low temperature ohmic process may be used to deposit a Ti / Al / Ni / Au metal stack, and then patterning may be performed to form a source and a drain.

[0166] 409. Make a gate, and the gate passes through the passivation layer and is connected to the P-GaN layer.

[0167] Optionally, this step may include: etching the passivation layer to form a groove connected to the P-GaN layer; and then making a gate covering the groove, so that the gate passes through the passivation layer and is connected to the P-GaN layer.

[0168] In the disclosed embodiment, after selectively removing a portion of the passivation layer by reactive ion etching, the gate is formed by electron beam evaporation and lift-off process.

[0169] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A transistor, characterized in that: The transistor comprises: a first channel layer (101), a first barrier layer (102), a second channel layer (103), a second barrier layer (104), a dielectric layer (105), a source electrode (106) and a drain electrode (107); The first barrier layer (102), the second channel layer (103) and the second barrier layer (104) are sequentially stacked on the first channel layer (101); the first barrier layer (102), the second channel layer (103) and the second barrier layer (104) are provided with a source groove (1001) and a drain groove (1002) extending to the first channel layer (101); The source electrode (106) is located in the source electrode groove (1001) and is connected to the first channel layer (101); the drain electrode (107) is located in the drain electrode groove (1002) and is connected to the first channel layer (101); and the dielectric layer (105) is located between the source electrode (106) and the inner wall of the source electrode groove (1001).

2. The transistor according to claim 1, characterized in that The thicknesses of the first channel layer (101), the first barrier layer (102), the second channel layer (103) and the second barrier layer (104) are 400-500 nm, 20-25 nm, 250-300 nm and 20-25 nm respectively.

3. The transistor according to claim 1 or 2, characterized in that: The dielectric layer (105) is a HfO2 dielectric layer.

4. The transistor according to claim 1 or 2, characterized in that: The transistor further comprises a buffer layer (108), wherein the buffer layer (108) comprises an AlGaN buffer layer (181) and a superlattice buffer layer (182), wherein the superlattice buffer layer (182) is located between the AlGaN buffer layer (181) and the first channel layer (101).

5. The transistor according to claim 4, characterized in that The transistor further comprises a carbon-doped GaN layer (109), wherein the carbon-doped GaN layer (109) is located between the superlattice buffer layer (182) and the first channel layer (101).

6. A method for manufacturing a transistor, characterized in that: The method comprises: Manufacturing a first channel layer, a first barrier layer, a second channel layer and a second barrier layer stacked in sequence; Opening a source groove and a drain groove extending to the first channel layer on the first barrier layer, the second channel layer and the second barrier layer; fabricating a dielectric layer; A source and a drain are manufactured, wherein the source is located in the source groove and connected to the first channel layer, the drain is located in the drain groove and connected to the first channel layer, and the dielectric layer is located between the source and the inner wall of the source groove.

7. The method according to claim 6, characterized in that The method of manufacturing a first channel layer, a first barrier layer, a second channel layer and a second barrier layer stacked in sequence comprises: In an environment where the reaction chamber temperature is 1000-1100° C., the reaction chamber pressure is 190-210 mbar, the NH3 flow rate is 9000-11000 sccm, and the TMGa flow rate is 190-210 sccm, growing the first channel layer with a thickness of 400-500 nm; In an environment where the reaction chamber temperature is 1010-1110° C., the reaction chamber pressure is 190-210 mbar, the NH3 flow rate is 4900-5100 sccm, the TMGa flow rate is 190-210 sccm, and the TMAl flow rate is 40-60 sccm, growing the first barrier layer with a thickness of 20-25 nm on the first channel layer; In an environment where the reaction chamber temperature is 1000-1100° C., the reaction chamber pressure is 190-210 mbar, the NH3 flow rate is 9000-11000 sccm, and the TMGa flow rate is 190-210 sccm, growing the second channel layer with a thickness of 250-300 nm on the first barrier layer; In an environment where the reaction chamber temperature is 1010-1110°C, the reaction chamber pressure is 190-210 mbar, the NH3 flow rate is 4900-5100 sccm, the TMGa flow rate is 190-210 sccm, and the TMAl flow rate is 40-60 sccm, the second barrier layer with a thickness of 20-25 nm is grown on the second channel layer.

8. The method according to claim 6 or 7, characterized in that: The method of manufacturing the dielectric layer comprises: Depositing a HfO2 dielectric film in the source electrode groove; The HfO2 dielectric film is patterned to obtain a HfO2 dielectric layer.

9. The method according to claim 6 or 7, characterized in that: The method further comprises: A buffer layer is manufactured, wherein the buffer layer comprises an AlGaN buffer layer and a superlattice buffer layer, and the superlattice buffer layer is located between the AlGaN buffer layer and the first channel layer.

10. The method according to claim 9, characterized in that The method further comprises: A carbon-doped GaN layer is fabricated, wherein the carbon-doped GaN layer is located between the superlattice buffer layer and the first channel layer.

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